JP2003158143A - Molding method of thin semiconductor device and molding die therefor - Google Patents
Molding method of thin semiconductor device and molding die thereforInfo
- Publication number
- JP2003158143A JP2003158143A JP2001358278A JP2001358278A JP2003158143A JP 2003158143 A JP2003158143 A JP 2003158143A JP 2001358278 A JP2001358278 A JP 2001358278A JP 2001358278 A JP2001358278 A JP 2001358278A JP 2003158143 A JP2003158143 A JP 2003158143A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- molding
- package
- mold
- thin semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 111
- 238000000465 moulding Methods 0.000 title claims abstract description 62
- 238000000034 method Methods 0.000 title claims abstract description 20
- 229920005989 resin Polymers 0.000 claims abstract description 41
- 239000011347 resin Substances 0.000 claims abstract description 41
- 229920001187 thermosetting polymer Polymers 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 abstract description 18
- 239000002184 metal Substances 0.000 abstract 2
- 230000008602 contraction Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000012790 adhesive layer Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- 102100033040 Carbonic anhydrase 12 Human genes 0.000 description 1
- 101000867855 Homo sapiens Carbonic anhydrase 12 Proteins 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
Landscapes
- Injection Moulding Of Plastics Or The Like (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体素子とその
半導体素子が実装された配線基板の一面に樹脂製パッケ
ージが形成された薄型半導体装置のモールド方法及びそ
のモールド金型にに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for molding a thin semiconductor device in which a resin package is formed on one surface of a semiconductor element and a wiring board on which the semiconductor element is mounted, and a molding die thereof.
【0002】[0002]
【従来の技術】先ず、従来技術の薄型半導体装置につい
て説明する。2. Description of the Related Art First, a conventional thin semiconductor device will be described.
【0003】図4は従来技術の薄型半導体装置の製造方
法を説明するための主製造工程図、図5は従来技術の薄
型半導体装置の樹脂パッケージに用いるモールド金型の
一部断面図、図6は図5に示したモールド金型を用いて
モールドしている状態を示す一部断面図、図7は従来技
術の薄型半導体装置をマザー基板に実装する状態を示し
た断面図、図8は従来技術の他のモールド金型の構造を
示した断面図、図9は図8に示したモールド金型を用い
てプリント基板に実装されている各種部品をモールドす
る状態を示した断面図、そして図10は図8に示したモ
ールド金型でモールドされた従来技術の薄型半導体装置
の断面図である。FIG. 4 is a main manufacturing process diagram for explaining a conventional method of manufacturing a thin semiconductor device, FIG. 5 is a partial sectional view of a molding die used for a resin package of a conventional thin semiconductor device, and FIG. Is a partial cross-sectional view showing a state of molding using the molding die shown in FIG. 5, FIG. 7 is a cross-sectional view showing a state of mounting a conventional thin semiconductor device on a mother substrate, and FIG. FIG. 9 is a cross-sectional view showing the structure of another mold die of the technology, FIG. 9 is a cross-sectional view showing a state in which various parts mounted on a printed circuit board are molded using the mold die shown in FIG. 10 is a sectional view of a conventional thin semiconductor device molded by the molding die shown in FIG.
【0004】従来技術の薄型半導体装置のパッケージ
(封止)形態の一つとして、配線基板に薄型半導体素子
を組み込み、一面から樹脂でパッケージ(封止)したい
わゆるAmkor社などが製品化しているetCSPな
どが知られている。As one of the package (sealing) forms of the conventional thin semiconductor device, a so-called Amkor company or the like which has a thin semiconductor element incorporated in a wiring board and is packaged (sealed) with resin from one side is commercialized. Are known.
【0005】このような薄型半導体装置は、図4に示し
たような主工程を経て得ることができる。即ち、先ず、
図4Aに示したダイボンド工程で、配線基板10に薄型
半導体素子Sを固定する。配線基板10には薄型半導体
素子Sを組み込むための空洞部11が、そしてその周辺
に搭載しようとする薄型半導体素子Sの電極に対応する
回路配線12などが形成されており、また、薄型配線基
板10の裏面に、予め、粘着層を備えた仮固定テープ2
0が貼り付けられている。半導体素子Sはその空洞部1
1に露出している仮固定テープ20ヘその粘着層を利用
してダイボンドされる。Such a thin semiconductor device can be obtained through the main steps as shown in FIG. That is, first,
In the die bonding step shown in FIG. 4A, the thin semiconductor element S is fixed to the wiring board 10. The wiring board 10 is provided with a cavity 11 for incorporating the thin semiconductor element S, and circuit wirings 12 and the like corresponding to the electrodes of the thin semiconductor element S to be mounted on the periphery thereof. Temporary fixing tape 2 provided with an adhesive layer on the back surface of 10 in advance
0 is pasted. The semiconductor element S has a cavity 1
Die-bonding to the temporary fixing tape 20 exposed at No. 1 using the adhesive layer.
【0006】次に、図4Bに示すワイヤボンド工程で、
薄型半導体素子Sの電極部と配線基板1の回路配線12
とを、例えば、金線などのワイヤーWを用いて接続す
る。Next, in the wire bonding process shown in FIG. 4B,
Circuit parts 12 of the thin semiconductor element S and the wiring board 1
And are connected using a wire W such as a gold wire.
【0007】そして次に、図4Cに示したモールド工程
で、金型(不図示)を用いて、前記配線基板10の表
面、薄型半導体素子S、ワイヤーWを、それらが存在す
る側から樹脂Rで覆い、パッケージ30をモールド(成
型)する。Then, in a molding step shown in FIG. 4C, a resin (not shown) is used to mold the surface of the wiring substrate 10, the thin semiconductor element S, and the wire W from the side where they are present to the resin R. Then, the package 30 is molded.
【0008】そして次に、図4Dに示したテープ剥離工
程で、モールドされた配線基板10から仮固定テープ2
0を剥離、除去する。Then, in the tape peeling step shown in FIG. 4D, the temporary fixing tape 2 is removed from the molded wiring board 10.
0 is peeled off and removed.
【0009】次に、図4Eに示した半田ボール形成工程
で、回路配線12と導通し、配線基板10の裏面に貫通
しているバイアホール13の表面に半田ボール14を形
成する。半田ボール14はセットのマザー基板(不図
示)への実装の信頼性を向上させるための有効な構造で
あるが、特に小型パッケージに於いては安定した実装平
面が確保できることから、ボール付けしない場合もあ
る。Next, in a solder ball forming step shown in FIG. 4E, a solder ball 14 is formed on the surface of the via hole 13 which is electrically connected to the circuit wiring 12 and penetrates the back surface of the wiring substrate 10. The solder ball 14 is an effective structure for improving the reliability of mounting the set on a mother board (not shown). However, in a small package, a stable mounting plane can be secured. There is also.
【0010】最後に、図4Fに示したシングレーション
工程で、大判の配線基板から複数の最終的な薄型半導体
装置1Bを切り出す。これが従来技術の薄型半導体装置
1Bである。通常、生産性の向上を目的として、1枚の
大判の配線基板に複数個の半導体装置1Bが形成される
形態になっている。このような薄型半導体装置1Bの厚
みは約300μm或いはそれ以下である。Finally, in the thinning step shown in FIG. 4F, a plurality of final thin semiconductor devices 1B are cut out from a large-sized wiring board. This is the conventional thin semiconductor device 1B. Usually, in order to improve productivity, a plurality of semiconductor devices 1B are formed on one large-sized wiring board. The thickness of such a thin semiconductor device 1B is about 300 μm or less.
【0011】図4Cのモールドは図5に示したようなモ
ールド金型を用いて行われる。The molding of FIG. 4C is performed using a molding die as shown in FIG.
【0012】このモールド金型40は下金型41と上金
型42とから構成されている。下金型41は、そのキャ
ビティ面に配線基板10或いは半導体素子Sと仮固定テ
ープ20とが重ねられた厚みとそれら半導体素子Sを覆
い、ワイヤーWが接続されている回路配線12の一部分
がモールドされなければならない部分の配線基板10の
面積に相当する窪みのキャビティ411が形成されてい
る。The molding die 40 is composed of a lower die 41 and an upper die 42. The lower die 41 covers the semiconductor substrate S or the semiconductor element S and the temporary fixing tape 20 on the cavity surface of the cavity substrate, and covers the semiconductor element S. A part of the circuit wiring 12 to which the wire W is connected is molded. A hollow cavity 411 corresponding to the area of the wiring substrate 10 that must be formed is formed.
【0013】上金型42は、そのキャビティ面に、少な
くともワイヤーWの高さより若干高く、そしてワイヤー
Wが配線基板10上の配線回路12に接続されている部
分を含む面積のキャビティ421が形成されている。更
に、溶融樹脂Rを注入するゲート422が形成されてい
る。The upper mold 42 has a cavity 421 formed on the cavity surface thereof at least slightly higher than the height of the wire W and having an area including the portion where the wire W is connected to the wiring circuit 12 on the wiring board 10. ing. Further, a gate 422 for injecting the molten resin R is formed.
【0014】このような構造のモールド金型40を用
い、図6に示したように、図4Bに示した仮固定テープ
20に固定されているワイヤーボンド済み半導体素子S
と配線基板10とを下金型41のキャビティ411内に
載置し、この上に上金型42を被せ、クランプし、その
状態でゲート422から熱硬化性の溶融樹脂Rを注入
し、配線基板10の一面に半導体素子S、ワイヤーWを
覆い、硬化させると、パッケージ30が形成され、薄型
半導体装置1Bが得られる。Using the molding die 40 having such a structure, as shown in FIG. 6, the wire-bonded semiconductor element S fixed to the temporary fixing tape 20 shown in FIG. 4B.
The wiring board 10 and the wiring board 10 are placed in the cavity 411 of the lower mold 41, the upper mold 42 is covered and clamped thereon, and in that state, the thermosetting molten resin R is injected from the gate 422, and wiring is performed. When the semiconductor element S and the wire W are covered on one surface of the substrate 10 and cured, the package 30 is formed and the thin semiconductor device 1B is obtained.
【0015】このモールド方法は、一般に、トランスフ
ァーモールド方式と称され、モールド金型40を180
℃前後に加熱した状態で熱硬化性樹脂Rを注入し、モー
ルドする方式である。このような配線基板10の一面
に、トランスファーモールド法によって樹脂Rからなる
パッケージ30を形成するパッケージング技術において
は、モールド時は、配線基板10、半導体素子Sなどが
180℃前後の高温状態で熱硬化性樹脂Rにより固めら
れるため、硬化後、モールド金型40から取り出されて
常温になった時には、図7に示したように、配線基板1
0、半導体素子S(シリコン)、熱硬化性樹脂R(例え
ば、工ポキシレジン)のそれぞれの熱膨張係数の違いや
熱硬化性樹脂Rそのものの硬化収縮により、パッケージ
30を中心に薄型半導体装置1Bが反ってしてしまうと
いう問題が生じる。This molding method is generally called a transfer molding method, and the molding die 40 is
This is a method of injecting a thermosetting resin R in a state of being heated to around 0 ° C. and molding. In the packaging technology in which the package 30 made of the resin R is formed on one surface of the wiring board 10 by the transfer molding method, the wiring board 10, the semiconductor element S, and the like are heated at a high temperature of about 180 ° C. during molding. Since it is hardened by the curable resin R, after being cured, when it is taken out from the molding die 40 and reaches room temperature, as shown in FIG.
0, the semiconductor element S (silicon), and the thermosetting resin R (for example, epoxy resin) have different thermal expansion coefficients and the thermosetting resin R itself cures and shrinks, so that the thin semiconductor device 1B centering on the package 30 is provided. The problem of warping arises.
【0016】それ故、このモールド工程で発生した反り
は、その後の工程でハンドリングミスを誘発し、生産性
の低下にもつながるが、最大の問題は図7に示したよう
に電子機器側のマザー基板50に実装する際に、薄型半
導体装置1Bの反りにより、接続不良が多発してしまう
という問題である。Therefore, the warp generated in this molding process causes a handling error in the subsequent process, which leads to a decrease in productivity, but the biggest problem is that the mother on the electronic equipment side as shown in FIG. The problem is that when the semiconductor device 1B is mounted on the substrate 50, the thin semiconductor device 1B is warped, resulting in frequent connection failures.
【0017】パッケージ30の反り量は被モールド体で
ある半導体素子Sが大型化すればするほど、また薄型化
すればするほど大きくなる。このような大型化、薄型化
された薄型半導体装置1Bに顕著に発生する反りは、電
子機器のマザー基板50への実装時に、マザー基板50
の電極端子への接続、信頼性をより著しく低下させる原
因となる。The amount of warpage of the package 30 increases as the size of the semiconductor element S, which is the object to be molded, increases and as it decreases in thickness. The warp that remarkably occurs in such a large-sized and thinned thin semiconductor device 1B is caused when the mother board 50 is mounted on the mother board 50 of the electronic device.
Connection to the electrode terminals, and significantly lower the reliability.
【0018】また、前記のような反りは、図10に示し
たように、プリント基板61上にLSIチップ62、I
Cチップ63、チップコンデンサ64などを実装し、樹
脂モールドされたLCC(リードレスチップキャリヤ
ー)のような半導体装置1Cを得る場合にも生じるとさ
れている。このような場合の反りを修正するための技術
は、特開平8−213418に開示されている。図8及
び図9に、そのためのモールド金型を再掲した。ただ
し、これらの図面に付した符号は公報に掲載されている
図面に付された符号と異なっていることを予め断ってお
く。As shown in FIG. 10, the warp as described above is caused by the LSI chips 62, I on the printed circuit board 61.
It is said that this also occurs when a semiconductor device 1C such as a resin-molded LCC (leadless chip carrier) is obtained by mounting a C chip 63, a chip capacitor 64 and the like. A technique for correcting the warp in such a case is disclosed in JP-A-8-213418. The mold for that purpose is shown again in FIGS. 8 and 9. However, it should be noted in advance that the reference numerals attached to these drawings are different from the reference numerals attached to the drawings disclosed in the publication.
【0019】図8に示したように、このモールド金型7
0も、下金型71と上金型72とから構成されている。As shown in FIG. 8, this molding die 7
0 is also composed of a lower mold 71 and an upper mold 72.
【0020】その下金型71は、モールドしようとする
LSIチップ62、ICチップ63、チップコンデンサ
64などの部品が実装されたプリント基板61部分が載
置されるキャビティ711を形成する面が突起台座71
2に形成されている構造のものである。The lower die 71 has a protrusion pedestal on the surface forming a cavity 711 in which the printed circuit board 61 portion on which components such as the LSI chip 62, the IC chip 63, and the chip capacitor 64 to be molded are mounted. 71
2 has a structure formed.
【0021】一方の上金型72は、前記の各種部品に対
応したキャビティ面に、前記の各種部品及びプリント基
板61の厚みの約2倍ほどの深さのキャビティ721が
形成されている構造のものである。上金型72にはキャ
ビティ721に通じるゲート722及びゲート722へ
通じるランナー723も形成されている。One upper mold 72 has a structure in which a cavity 721 having a depth about twice the thickness of the various components and the printed circuit board 61 is formed on the cavity surface corresponding to the various components. It is a thing. The upper mold 72 is also formed with a gate 722 leading to the cavity 721 and a runner 723 leading to the gate 722.
【0022】このような構造の下金型71の前記キャビ
ティ711の突起台座712に、図9に示したように、
前記の各種部品が実装されているプリント基板61部分
を載置し、その上から上金型721を被せてクランプし
た後、ランナー723及びゲート722を通じて溶融さ
れた熱硬化性樹脂Rをキャビティに注入し、その後、モ
ールド金型70などが冷却した後、そのモールド金型7
0から被モールド物体を取り出すと、図5に示したモー
ルド金型40を用いてモールドした場合に通常生じる反
りとは逆方向にプリント基板61が台形状に反った半導
体装置1Cを得ている。As shown in FIG. 9, the projection pedestal 712 of the cavity 711 of the lower mold 71 having the above structure is
The printed circuit board 61 portion on which the above-mentioned various components are mounted is placed, and the upper mold 721 is placed thereon to be clamped, and then the molten thermosetting resin R is injected into the cavity through the runner 723 and the gate 722. Then, after the mold die 70 and the like are cooled, the mold die 7 is cooled.
When the object to be molded is taken out from 0, a semiconductor device 1C is obtained in which the printed circuit board 61 has a trapezoidal warp in the direction opposite to the warp that normally occurs when molding is performed using the molding die 40 shown in FIG.
【0023】そしてこのようにプリント基板61が台形
状に反った半導体装置1Cのパッケージ65の熱硬化性
樹脂Rが硬化収縮することによりプリント基板61が反
っても、プリント基板61が予め逆に反り返った形状と
なっていることから、前記の硬化収縮による反りによっ
てプリント基板61がほぼ平坦になるとされている。In this way, even if the printed circuit board 61 warps due to the thermosetting resin R of the package 65 of the semiconductor device 1C in which the printed circuit board 61 warps in a trapezoidal shape, the printed circuit board 61 warps back in advance. Since it has a different shape, the printed circuit board 61 is said to be substantially flat due to the warp due to the curing shrinkage.
【0024】[0024]
【発明が解決しようとする課題】しかし、図に示した構
造から明らかなように、従来技術の半導体装置1Cは、
1.各種部品(62、63、64)がプリント基板61
の上に実装されていること
2.各種部品が実装された部分のプリント基板61のみ
が反るというよりも台形に変形された構造で成形されて
いること
3.各種部品の上方を覆うパッケージ65の厚みが各種
部品の高さの2倍に近い厚みであること
4.各種部品の上方を覆うパッケージ65が断面台形の
構造でモールドされていること
などから、従来の熱硬化性樹脂Rの硬化収縮による前記
プリント基板61部分の反りを、この公開された発明の
技術による反り返し構造で平坦化することは非常に難し
い。However, as is clear from the structure shown in the figure, the semiconductor device 1C of the prior art has: Various parts (62, 63, 64) are printed circuit boards 61
It is implemented on 2. 2. Only the printed circuit board 61 in which the various components are mounted is formed in a trapezoidally deformed structure rather than being warped. 3. The thickness of the package 65 that covers the tops of the various components is approximately twice the height of the various components. Since the package 65 that covers the tops of various components is molded in a trapezoidal cross-section, the warpage of the printed circuit board 61 portion due to the curing shrinkage of the conventional thermosetting resin R is prevented by the disclosed technology of the present invention. It is very difficult to flatten with a warped structure.
【0025】従って、本発明はこのような課題を解決し
ようとするものであって、熱硬化性樹脂でモールドされ
たパッケージが形成される薄型半導体装置であっても、
反り返ろうとする薄型半導体装置を確実に平坦化してモ
ールドできる薄型半導体装置のモールド方法及びそのモ
ールド金型を得ることを目的とするものである。Therefore, the present invention is intended to solve such a problem, and even in a thin semiconductor device in which a package molded with a thermosetting resin is formed,
An object of the present invention is to obtain a molding method for a thin semiconductor device and a molding die for the thin semiconductor device, which can surely flatten and mold a thin semiconductor device that is going to warp.
【0026】[0026]
【課題を解決するための手段】それ故、本発明の薄型半
導体装置のモールド方法では、半導体素子とその半導体
素子を実装しようとする配線基板とがほぼ同一面を形成
するように配設され、その半導体素子の電極が接続され
た配線基板の一面に樹脂製パッケージが形成された薄型
半導体装置のモールド方法において、前記半導体素子と
前記配線基板とを熱硬化性樹脂でモールドしてパッケー
ジを形成する場合に、そのモールドした熱硬化性樹脂を
硬化させた時に硬化収縮によって生じる前記パッケージ
の反りを予め見込んで、前記半導体素子と前記配線基板
とを前記反りと同等の逆反りで反り返した状態て樹脂モ
ールドする方法を採って、前記課題を解決している。Therefore, in the molding method for a thin semiconductor device of the present invention, the semiconductor element and the wiring board on which the semiconductor element is to be mounted are arranged so as to form substantially the same surface, In a method for molding a thin semiconductor device in which a resin package is formed on one surface of a wiring board to which electrodes of the semiconductor element are connected, a package is formed by molding the semiconductor element and the wiring board with a thermosetting resin. In this case, the warpage of the package caused by curing shrinkage when the molded thermosetting resin is cured is expected in advance, and the semiconductor element and the wiring board are warped with the same warpage as the warpage. The above problem is solved by adopting a resin molding method.
【0027】また、本発明の薄型半導体装置用モールド
金型では、下金型と上金型との間に、半導体素子とその
半導体素子を実装しようとする配線基板とがほぼ同一面
を形成するように配設され、その半導体素子の電極が接
続された配線基板の一面に樹脂製パッケージを形成する
ための薄型半導体装置用モールド金型において、前記下
金型のキャビティ面が所定の曲率で凸型湾曲面に形成さ
れており、前記上金型のキャビティ面が前記所定の深さ
で前記凸型湾曲面の全面に対向し、そして前記凸型湾曲
面の曲率と同一の曲率で凹型湾曲面に形成されている構
造を採って、前記課題を解決している。Further, in the mold die for a thin semiconductor device of the present invention, the semiconductor element and the wiring board on which the semiconductor element is to be mounted form substantially the same surface between the lower die and the upper die. In a mold die for a thin semiconductor device for forming a resin package on one surface of a wiring board to which electrodes of semiconductor elements are connected, the cavity surface of the lower die is convex with a predetermined curvature. The cavity surface of the upper mold faces the entire surface of the convex curved surface at the predetermined depth, and the concave curved surface has the same curvature as that of the convex curved surface. The above problem is solved by adopting the structure formed in the above.
【0028】このモールド金型の場合の前記凸型湾曲面
及び凹型湾曲面の曲率は、前記半導体素子と前記配線基
板とを樹脂でモールドしてパッケージを形成する場合
に、そのモールドした樹脂を硬化させた時に硬化収縮に
よって生じる前記パッケージの反りと同等の逆反りでモ
ールドできる曲率であることが望ましい。The curvature of the convex curved surface and the concave curved surface in the case of this molding die is such that when the semiconductor element and the wiring board are molded with resin to form a package, the molded resin is cured. It is desirable that the curvature is such that the mold can be molded with a reverse warp equivalent to the warp of the package caused by the shrinkage upon curing.
【0029】従って、本発明の薄型半導体装置のモール
ド方法によれば、少なくとも半導体素子がモールドされ
ているパッケージを均一な厚さでモールドでき、そのモ
ールド後、常温に戻ったときに、パッケージの反りを容
易に逆に反り返すことができ、そのパッケージを、そし
てその中にモールドされている半導体素子をほぼ平坦に
維持させることができる。Therefore, according to the method for molding a thin semiconductor device of the present invention, at least a package in which a semiconductor element is molded can be molded with a uniform thickness, and when the temperature returns to room temperature after the molding, the package warps. Can be easily turned back and the package, and the semiconductor device molded therein, can be maintained substantially flat.
【0030】また、本発明の薄型半導体装置用モールド
金型によれば、少なくとも半導体素子部分を覆うパッケ
ージを薄い均一な厚さでモールドすることができ、しか
も、そのモールド後、常温に戻ったときに、そのパッケ
ージの反りを容易に逆に反り返えすことができる曲率で
モールドすることができる。Further, according to the molding die for a thin semiconductor device of the present invention, the package covering at least the semiconductor element portion can be molded with a thin and uniform thickness, and when the temperature returns to room temperature after the molding. In addition, it is possible to mold the package with a curvature that can easily reverse the warp of the package.
【0031】[0031]
【発明の実施の形態】以下、図1乃至図3を用いて、本
発明の一実施形態の薄型半導体装置のモールド方法及び
そのモールド金型を説明する。BEST MODE FOR CARRYING OUT THE INVENTION A molding method for a thin semiconductor device and a molding die thereof according to an embodiment of the present invention will be described below with reference to FIGS. 1 to 3.
【0032】図1は本発明の一実施形態の薄型半導体装
置用モールド金型の構造を示した一部断面図、図2は図
1に示したモールド金型を用いて薄型半導体装置をモー
ルドしている状態を示したそのモールド金型と薄型半導
体装置との一部断面図、そして図3は図1のモールド金
型を用いてモールドされた薄型半導体装置をマザー基板
に実装する状態を示す薄型半導体装置とマザー基板との
断面図である。FIG. 1 is a partial cross-sectional view showing the structure of a molding die for a thin semiconductor device according to an embodiment of the present invention, and FIG. 2 is a plan view of a thin semiconductor device molded using the molding die shown in FIG. FIG. 3 is a partial cross-sectional view of the molding die and the thin semiconductor device showing the state in which the molding die and the thin semiconductor device molded using the molding die of FIG. 1 are mounted on the mother substrate. It is a sectional view of a semiconductor device and a mother substrate.
【0033】先ず初めに、図1を用いて本発明の一実施
形態の薄型半導体装置用モールド金型の構造及び構成を
説明する。First, the structure and construction of a thin mold semiconductor device mold according to an embodiment of the present invention will be described with reference to FIG.
【0034】符号80は本発明の一実施形態の薄型半導
体装置用モールド金型を指す。このモールド金型80は
下金型81と上金型82とから構成されている。Reference numeral 80 indicates a molding die for a thin semiconductor device according to an embodiment of the present invention. The molding die 80 is composed of a lower die 81 and an upper die 82.
【0035】下金型81は、そのキャビティ811が所
定の曲率で凸型湾曲面812に形成されており、上金型
82は、そのキャビティ821が所定の深さで前記凸型
湾曲面811の全面に対向し、そしてその凸型湾曲面8
11の曲率と同一の曲率で凹型湾曲面822に形成され
た構造のものである。また、上金型82にはキャビティ
821に通じるゲート823とこのゲート823に通じ
るランナー824も形成されている。The lower die 81 has a cavity 811 formed in a convex curved surface 812 with a predetermined curvature, and the upper die 82 has a cavity 821 having a predetermined depth in the convex curved surface 811. The convex curved surface 8 facing the entire surface and
It has a structure formed on the concave curved surface 822 with the same curvature as that of No. 11. The upper mold 82 is also formed with a gate 823 communicating with the cavity 821 and a runner 824 communicating with the gate 823.
【0036】この下金型81の凸型湾曲面812及び凹
型湾曲面822の曲率は、モールドしようとする半導体
素子Sと配線基板10とを樹脂Rでモールドしてパッケ
ージ30を形成する場合に、そのモールドした樹脂Rを
硬化させた時に硬化収縮によって生じるパッケージ30
の反りと同等の逆反りでモールドできる曲率とする。The curvatures of the convex curved surface 812 and the concave curved surface 822 of the lower die 81 are the same when the semiconductor element S to be molded and the wiring substrate 10 are molded with the resin R to form the package 30. Package 30 which is produced by curing shrinkage when the molded resin R is cured
The curvature should be such that it can be molded with a reverse warpage equivalent to that of.
【0037】本発明の薄型半導体装置のモールド方法は
このようなモールド金型80を用いて行う。即ち、図2
に示したように、モールド金型80の下金型81の凸型
湾曲面812に、図4Bに示した半導体素子Sとその半
導体素子Sを実装しようとする配線基板10とがほぼ同
一面を形成するように配設され、仮固定テープ20で固
定され、ワイヤーボンドされたそれら半導体素子Sと配
線基板10とを載置し、その上から上金型82を、その
凹型湾曲面822が凸型湾曲面812に一致して対向す
るように載せ、両金型をクランプする。The molding method of the thin semiconductor device of the present invention is performed using such a molding die 80. That is, FIG.
As shown in FIG. 5, the semiconductor chip S shown in FIG. 4B and the wiring board 10 on which the semiconductor chip S is mounted are substantially flush with each other on the convex curved surface 812 of the lower mold 81 of the molding die 80. The semiconductor element S and the wiring board 10 which are arranged so as to be formed, fixed by the temporary fixing tape 20 and wire-bonded are placed, and the upper die 82 and the concave curved surface 822 thereof are convex from above. Both molds are clamped by placing them so as to match the mold curved surface 812 and face each other.
【0038】次に、図2に示したように、下金型81と
上金型82とをクランプした後、ランナー824からゲ
ート823を通じてキャビティ内に熱硬化性の溶融樹脂
Rを注入する。その溶融樹脂Rが配線基板10、半導体
素子Sの一面及びワイヤーWを覆う。Next, as shown in FIG. 2, after the lower die 81 and the upper die 82 are clamped, a thermosetting molten resin R is injected into the cavity from the runner 824 through the gate 823. The molten resin R covers the wiring substrate 10, one surface of the semiconductor element S and the wire W.
【0039】その溶融樹脂Rを硬化させると、樹脂製パ
ッケージ30Aは少なくともワイヤーボンドされている
範囲内のモールド部分がそのワイヤーWの膨らみ部分を
覆う薄い厚さで均一に成形され、極めて薄いパッケージ
30の半製品の薄型半導体装置が得られる。When the molten resin R is cured, the resin package 30A is uniformly molded with a thin thickness so that the mold portion at least within the range of wire bonding covers the bulging portion of the wire W, and the package 30A is extremely thin. The semi-finished thin semiconductor device can be obtained.
【0040】しかもそのパッケージ30Aは、前記凸型
湾曲面812及び前記凹型湾曲面822が前記熱硬化性
樹脂を硬化させた時に硬化収縮によって通常生じるパッ
ケージ30の反りを予め見込んで、モールドされたパッ
ケージ30(或いは、半導体素子Sと配線基板10)を
前記反りと同等の逆反りで反り返した状態でモールドさ
れていることから、クランプが解かれた下金型81と上
金型82とから取り出した前記逆反り状態の半製品の薄
型半導体装置は、そのパッケージ30の温度が常温に戻
った後は、ほぼ平坦になる。Moreover, the package 30A is a molded package in which the warp of the package 30 which is usually caused by the curing shrinkage when the convex curved surface 812 and the concave curved surface 822 cure the thermosetting resin is preformed. Since 30 (or the semiconductor element S and the wiring substrate 10) is molded in a warped state with a warp equivalent to the above-mentioned warpage, the clamp is released from the lower mold 81 and the upper mold 82. Further, the semi-finished thin semiconductor device in the reverse warpage state becomes substantially flat after the temperature of the package 30 returns to room temperature.
【0041】その後、図4Dの仮固定テープ剥離工程、
図4Eの半田ボール形成工程、図Fのシングレーション
工程などの加工工程を経て、図3に示したように、目的
とする良好な平坦性のある薄型半導体装置1Aを得るこ
とができる。Thereafter, the temporary fixing tape peeling step of FIG. 4D,
As shown in FIG. 3, the desired thin semiconductor device 1A having good flatness can be obtained through the processing steps such as the solder ball forming step of FIG. 4E and the singulation step of FIG.
【0042】従って、図3に示したように、この薄型半
導体装置1Aを電子機器側のマザー基板50へ実装する
時に、接続不良の少ない安定した実装が可能となる。Therefore, as shown in FIG. 3, when the thin semiconductor device 1A is mounted on the mother board 50 on the electronic equipment side, stable mounting with few connection failures can be performed.
【0043】[0043]
【発明の効果】以上説明したように、本発明によれば、
パッケージが極めて薄い厚さであるにも係わら、そして
反りのない平坦な薄型半導体装置を得ることができる。As described above, according to the present invention,
It is possible to obtain a flat thin semiconductor device having no warp even though the package has an extremely thin thickness.
【0044】従って、生産工程においては良好なハンド
リングができ、高い生産性を維持することができる。ま
た、この薄型半導体装置は平坦であることから電子機器
側のマザー基板へ高い信頼性をもって実装することがで
きる。Therefore, good handling can be performed in the production process, and high productivity can be maintained. Further, since this thin semiconductor device is flat, it can be mounted on the mother board on the electronic device side with high reliability.
【図1】 本発明の一実施形態の薄型半導体装置用モー
ルド金型の構造を示した一部断面図である。FIG. 1 is a partial cross-sectional view showing the structure of a mold die for a thin semiconductor device according to an embodiment of the present invention.
【図2】 図1に示したモールド金型を用いて薄型半導
体装置をモールドしている状態を示したそのモールド金
型と薄型半導体装置との一部断面図である。FIG. 2 is a partial cross-sectional view of a thin mold semiconductor device and a thin mold semiconductor device showing a state where a thin mold semiconductor device is molded using the mold mold shown in FIG.
【図3】 図1のモールド金型を用いてモールドされた
薄型半導体装置をマザー基板に実装する状態を示す薄型
半導体装置とマザー基板との断面図である。FIG. 3 is a cross-sectional view of the thin semiconductor device and the mother substrate showing a state in which the thin semiconductor device molded by using the molding die of FIG. 1 is mounted on the mother substrate.
【図4】 従来技術の薄型半導体装置の製造方法を説明
するための主製造工程図である。FIG. 4 is a main manufacturing process diagram for explaining a conventional method for manufacturing a thin semiconductor device.
【図5】 従来技術の薄型半導体装置の樹脂パッケージ
に用いるモールド金型の一部断面図である。FIG. 5 is a partial cross-sectional view of a molding die used for a resin package of a conventional thin semiconductor device.
【図6】 図5に示したモールド金型を用いてモールド
している状態を示す一部断面図である。FIG. 6 is a partial cross-sectional view showing a state of molding using the molding die shown in FIG.
【図7】 従来技術の薄型半導体装置をマザー基板に実
装する状態を示した断面図である。FIG. 7 is a cross-sectional view showing a state in which a conventional thin semiconductor device is mounted on a mother substrate.
【図8】 従来技術の他のモールド金型の構造を示した
断面図である。FIG. 8 is a cross-sectional view showing the structure of another conventional molding die.
【図9】 図8に示したモールド金型を用いてプリント
基板に実装されている各種部品をモールドする状態を示
した断面図である。9 is a cross-sectional view showing a state in which various parts mounted on a printed board are molded using the molding die shown in FIG.
【図10】 図8に示したモールド金型でモールドされ
た従来技術の薄型半導体装置の断面図である。10 is a cross-sectional view of a conventional thin semiconductor device molded by the molding die shown in FIG.
10…配線基板、11…空洞部、12…回路配線、13
…バイアホール、14…半田ボール、20…仮固定テー
プ、50…マザー基板、80…本発明のモールド金型、
81…下金型、811…キャビティ、812…凸型湾曲
面、82…上金型、821…キャビティ、822…凹型
湾曲面、823…ゲート、824…ランナー、S…半導
体素子、W…ワイヤー、R…(溶融)樹脂10 ... Wiring board, 11 ... Hollow part, 12 ... Circuit wiring, 13
... via holes, 14 ... solder balls, 20 ... temporary fixing tape, 50 ... mother substrate, 80 ... molding die of the present invention,
81 ... Lower mold, 811 ... Cavity, 812 ... Convex curved surface, 82 ... Upper mold, 821 ... Cavity, 822 ... Recessed curved surface, 823 ... Gate, 824 ... Runner, S ... Semiconductor element, W ... Wire, R ... (molten) resin
フロントページの続き Fターム(参考) 4F202 AA36 AH37 AM35 CA12 CB01 CB12 CB17 CK12 4F206 AA36 AH37 AM35 JA02 JB12 JB17 5F061 AA01 BA03 CA21 DA06 Continued front page F-term (reference) 4F202 AA36 AH37 AM35 CA12 CB01 CB12 CB17 CK12 4F206 AA36 AH37 AM35 JA02 JB12 JB17 5F061 AA01 BA03 CA21 DA06
Claims (3)
とする配線基板とがほぼ同一面を形成するように配設さ
れ、該半導体素子の電極が接続された配線基板の一面に
樹脂製パッケージが形成された薄型半導体装置のモール
ド方法において、 前記半導体素子と前記配線基板とを熱硬化性樹脂でモー
ルドしてパッケージを形成する場合に、該モールドした
熱硬化性樹脂を硬化させた時に硬化収縮によって生じる
前記パッケージの反りを予め見込んで、前記半導体素子
と前記配線基板とを前記反りと同等の逆反りで反り返し
た状態て樹脂モールドすることを特徴とする薄型半導体
装置のモールド方法。1. A semiconductor element and a wiring board on which the semiconductor element is to be mounted are arranged so as to form substantially the same surface, and a resin package is provided on one surface of the wiring board to which the electrodes of the semiconductor element are connected. In the method of molding a formed thin semiconductor device, when the semiconductor element and the wiring board are molded with a thermosetting resin to form a package, curing shrinkage occurs when the molded thermosetting resin is cured. A method for molding a thin semiconductor device, characterized in that the semiconductor chip and the wiring board are resin-molded in a state in which they are warped by an opposite warpage that is the same as the warpage, in consideration of the warpage of the package that occurs.
該半導体素子を実装しようとする配線基板とがほぼ同一
面を形成するように配設され、該半導体素子の電極が接
続された配線基板の一面に樹脂製パッケージを形成する
ための薄型半導体装置用モールド金型において、 前記下金型のキャビティ面が所定の曲率で凸型湾曲面に
形成されており、 前記上金型のキャビティ面が前記所定の深さで前記凸型
湾曲面の全面に対向し、そして前記凸型湾曲面の曲率と
同一の曲率で凹型湾曲面に形成されていることを特徴と
する薄型半導体装置用モールド金型。2. A semiconductor element and a wiring board on which the semiconductor element is to be mounted are arranged between the lower mold and the upper mold so as to form substantially the same surface, and the electrodes of the semiconductor element are arranged. In a mold die for a thin semiconductor device for forming a resin package on one surface of a connected wiring board, a cavity surface of the lower die is formed into a convex curved surface with a predetermined curvature, and the upper die is formed. A thin semiconductor, wherein a cavity surface of the mold faces the entire surface of the convex curved surface at the predetermined depth, and is formed as a concave curved surface with the same curvature as that of the convex curved surface. Mold for equipment.
は、前記半導体素子と前記配線基板とを熱硬化性樹脂で
モールドしてパッケージを形成する場合に、該モールド
した熱硬化性樹脂を硬化させた時に硬化収縮によって生
じる前記パッケージの反りと同等の逆反りでモールドで
きる曲率であることを特徴とする請求項2に記載の薄型
半導体装置用モールド金型。3. The curvatures of the convex curved surface and the concave curved surface are determined by molding the thermosetting resin when the semiconductor element and the wiring board are molded with a thermosetting resin to form a package. The mold die for a thin semiconductor device according to claim 2, wherein the mold has a curvature capable of being molded with a reverse warp equivalent to that of the package caused by curing shrinkage when cured.
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