JP2003151289A - Nonvolatile semiconductor memory and its writing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory and its writing method in which an additional writing is conducted without conducting an erroneous writing even though there exists a memory cell to which data are written into its drain side while supplying a writing non-selective voltage using a local selfboost system. SOLUTION: When a local selfboost is to be conducted, electric charges obtained while boosting the potential of the channel section of a memory cell are supplied to a memory cell close to a source of a NAND string from not only a bit line BL but also from a source line SL. Since a writing non-selective voltage is boosted while supplying electric charges from the line SL also (a STEP3), a sufficient voltage is obtained to inhibit writing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory and a writing method thereof, and more particularly to an NA.
The present invention relates to a write inhibit voltage generation method for a device that supplies a write inhibit voltage using a local self-boost method in an ND type flash memory.

[0002]

2. Description of the Related Art FIGS. 3 and 4 are each for explaining a NAND type flash memory. FIG. 3 is a block diagram showing a schematic structure of a main portion, and FIG. 4 is a circuit diagram showing a memory cell structure. . As shown in FIG. 3, NAND memory cells are arranged in a matrix in the main body memory cell array 11.
A row decoder 12, a column decoder 13, a data latch / sense amplifier 14, etc. are connected to 1. The row decoder 12 decodes a row address signal to select a word line and a select gate line provided in the main body memory cell array 11. Further, the column decoder 13 decodes a column address signal to select a bit line provided in the main body memory cell array 11. The data latch / sense amplifier 14 latches write data or read data, and
Sense and amplify. Further, a redundant portion memory cell array 15 is provided adjacent to the main body memory cell array 11 so as to share the row decoder 12. The redundant portion memory cell array 15 is the main memory cell array 1
When a defect occurs in the memory cell in No. 1, the memory cell is replaced by a block unit for relief, and basically has the same configuration as the main body memory cell array 11. A redundant section column decoder 16, a redundant section data latch / sense amplifier 17, etc. are connected to the redundant section memory cell array 15, and when replacement for defect repair is performed, The same writing or reading as in the main body memory cell array 11 can be performed.

The memory cell of the NAND flash memory is constructed as shown in FIG. The current paths of a plurality (typically 16) of memory cells MC0 to MC15 are connected in series to form a NAND string. Bit line (drain) of this NAND string
Select gates S1 and S2 are connected to the end and the source line (source) end, respectively, so that the NAND string can be separated from the bit lines BLn and BLn + 1 and the source line SL as needed.

The above-mentioned NAND flash memory is basically based on serial operation, and typically, writing and reading are performed in units of a page composed of 512 bytes. Write / read data is a data latch (sense amplifier / data latch 14) connected to each bit line.
Temporarily held in.

In the NAND flash memory, a unit composed of one NAND string constitutes an erase block. When rewriting the data, first erase the data in the block and set all the data in the memory cells to "1" (D-type state where the threshold voltage is 0 V or less), and write the data in page units. Accordingly, the memory cell is selectively "0" (threshold voltage is 0
The state of E-type higher than V) is written. When writing, first set 1 in the data load cycle.
The write data for the page is transferred to the data register. In the subsequent write phase, the write voltage is applied to the word line, and the latched data is written in the memory cell.

FIGS. 5A and 5B show the relationship of voltages applied to the memory cells during writing. Since the memory cells on the same page are physically connected to the same word line, a write voltage (Vpgm, for example, 20V) is applied to the control gates all at once. In the case of the memory cell MC in which "0" is written as shown in (a), 0 V is applied to the drain from the bit line, a tunnel current is generated by a high electric field between the floating gate and the substrate, and electrons are injected into the floating gate. By doing so, "0" data is written. In the case of the write inhibit shown in FIG. 6B, that is, in the case of the memory cell MC holding “1” data in the erased state, the potential of the channel portion of the memory cell is set to the write inhibit voltage of about 10 V by the voltage from the bit line. Set, weaken the electric field between the floating gate and the substrate, and prohibit writing.

Local self-boosting is known as one of the methods for generating the write inhibit voltage. For local self-boosting, see "ISSCC Digest of Technical Papers, pp. 32-33, Feb.,
In 1996 ", Tae-Sung Jung et al. Announced. In the local self-boosting, as shown in Figure 4 of this reference, the selected word line is applied with the write voltage Vpgm (for example, 2
0V), and the word lines on both sides of the selected word line have 0V
To A pass voltage Vpass (for example, 11V) is applied to the other word lines. The power supply voltage Vcc is applied from the data latch circuit to the bit line of the write inhibit cell.
Here, when the non-selected word line is raised from 0V to the pass voltage Vpass, the channel potential of the memory cell rises due to capacitive coupling with the floating gate. On this occasion,
Since the voltage relationship of the drain side select gate is gate = drain = Vcc, when the source is raised to "Vcc- (Vth of select gate)" together with the channel of the memory cell, the drain side select gate is cut off. The channel of the memory cell finally rises to about 7V.

A memory cell adjacent to the selected memory cell is in an erased state and is in D-type (conducting even if the gate is 0V), but the voltage on the drain side is capacitively coupled to the non-selected memory cell. Since it has been raised to about 7V by this, it is cut off by this back gate bias, and the potential of the channel of the selected memory cell rises to about 10V due to capacitive coupling with the floating gate. As a result, the electric field between the floating gate and the channel portion is weakened, and the injection of electrons into the floating gate is suppressed. That is, the memory cell can maintain the erased state.

In order to realize the local self-boost as described above, the memory cell connected to the side closer to the bit line than the memory cell of the page to be written is Dt.
It is desired to be in the ype, that is, the erased state. In this case, the memory cells on the source side must always be written in order. However, in the NAND flash memory, as shown in FIG. 3, in addition to the 512-byte main body area (data area, that is, the main body memory cell array) 11, a 16-32-byte redundant area (management area, that is, redundant part memory) is used. A cell array) 15 is prepared. The body region 11 and the redundant region 15 are physically connected to the same word line.

There are several methods of controlling the write data by an external controller, but as one general example, after writing the data of one block unit to the main body,
Consider a method of writing a management flag in the redundant area of each page according to the state of the written data.
In this case, when writing the flag in the redundant region 15, the memory cell on the drain side of the body region 11 may be written.

Now, consider the state shown in FIGS. 6 and 7. FIG. 6 shows a state in which erroneous writing occurs during additional writing using local self boost. Figure 7
FIG. 7 is a cross-sectional view of the state shown in FIG. 6 above. That is,
This is a case where the memory cell MC2 connected to the word line WL2 is in the erased state and the flag is written in the redundant region 15 connected to this word line WL2. Word line W
Since the main body memory cell MC2 on L2 is in the write non-selected state, it must hold the erased state. It is assumed that "0" data is written in the memory cell MC3 which is only one on the drain side from the selected page, and the memory cell MC1 which is adjacent to the side closer to the source is in the erased state ("1"). At the time of writing, each word line WL0 to WL
15 indicates WL2 = Vpgm, WL as shown in FIG.
1 = WL3 = 0V, WL0 = WL4, ... = WL15 = V
It becomes a pass.

Since the memory cell MC1 is in the erased state,
Even if the gate voltage is 0V, it is in a conductive state. Since this memory cell MC1 is D-type, the channel potential of the memory cell MC0 must be raised sufficiently high in order to cut it off. However, here, the channel of the memory cell MC0 must be lifted by only one word line WL0 having the pass voltage Vpass. Furthermore, the word line WL0 must also raise the diffusion layer capacitance forming the drain of the source side select gate S2 and the diffusion layer capacitance between the memory cells MC0 and MC1. Moreover, since the diffusion layer capacitance on the select gate S2 side is suppressed to 0 V by the gate voltage, the parasitic capacitance is large.

FIG. 8 shows temporal changes in the channel potential of the memory cell MC2 when "0" is written in the memory cell MC0 and when "1" is written. If the normal order of writing from the memory cell on the source side is kept, the memory cell MC3 on the drain side is
Is always in the erased state, charge can be supplied from the drain side and the channel potential can be sufficiently increased even if the word line WL3 is at 0V. However, in the case of the state shown in FIG. 6, the charge from the bit line BL is blocked by the memory cell MC3, so that the efficiency of raising the potential of the channel decreases. As a result, the memory cell MC2 cannot be write-protected, and data is erroneously written in the memory cell MC2.

The selected word lines are WL3, WL4, ...
As the number of gates with respect to the diffusion layer capacitance increases, the erroneous writing is less likely to occur. The above-mentioned defects are caused by word lines WL1 and WL2.
It's time to write more.

[0015]

As described above, in the conventional nonvolatile semiconductor memory and the writing method thereof, when the write inhibit voltage is supplied by using the local self-boosting method, the data is already written on the drain side of the memory cell to be written. When there is a memory cell in which there is a memory cell, the charge supply from the bit line is stopped when the potential of the channel portion of the memory cell is raised, so that the write-inhibit voltage cannot be sufficiently obtained, which causes erroneous write failure. There was a problem.

The present invention has been made in view of the above circumstances. An object of the present invention is to write data on the drain side when a write non-selection voltage is supplied by using the local self-boosting method. A non-volatile semiconductor memory capable of performing additional writing without erroneous writing even if there is a memory cell in a state and a writing method thereof.

[0017]

The nonvolatile semiconductor memory of the present invention is an NA for writing data in page units.
An ND type non-volatile semiconductor memory is characterized in that a write non-select voltage is generated while supplying charges from a source line.

Further, the nonvolatile semiconductor memory of the present invention is an NA for performing writing in page units and generating a write non-selection voltage by the local self-boosting method.
In an ND type flash memory, during local self-boost, when an arbitrary number of word lines near the drain of the NAND string are selected, the drain side select gate is turned on, and the remaining number of word lines near the source is turned on. When it is selected, it is characterized by booting while turning on the select gate on the source side.

Further, the non-volatile semiconductor memory of the present invention is a NAND-type non-volatile semiconductor memory that writes data in page units, and the write non-selection voltage of the channel portion of the memory cell does not depend on the write data. The feature is that the channel potential is selectively used as a write voltage for a memory cell in which data is in a write state after being generated by capacitive coupling with a line.

Furthermore, the non-volatile semiconductor memory of the present invention is a NAND-type non-volatile semiconductor memory that writes data in page units, and the current path of a plurality of non-volatile memory cells is connected in series. A string, a word line connected to the control gate of each memory cell, a bit line arranged to intersect with the word line, and one end of a current path is connected to one end of the NAND string. A first select gate having the other end connected to the bit line and a gate connected to the first select gate line, a source line, and one end of a current path connected to the other end of the NAND string The other end of is connected to the source line and the gate is connected to the second
When a write non-select voltage is applied to the second select gate connected to the select gate line and the memory cell located on the side of the source line in the NAND string, the source line is higher than the ground potential and the write voltage is higher than the ground voltage. And a source line voltage generating circuit for giving a predetermined pass voltage lower than the above.

The non-volatile semiconductor memory of the present invention is a NAND flash memory that performs writing in page units and generates a write non-selection voltage by a local self-boosting method, in which the current paths of a plurality of non-volatile memory cells are connected in series. Connected to the memory cell, a word line connected to the control gate of each memory cell, a bit line arranged to intersect the word line, and one end of a current path connected to one end of the NAND string. A first select gate having the other end of the current path connected to the bit line and a gate connected to the first select gate line; a source line; and one end of the current path to the other end of the NAND string. Connected, the other end of the current path is connected to the source line, and the gate is connected to the second select gate line. And a source line voltage generation circuit for applying a predetermined intermediate voltage higher than the ground potential and lower than the write voltage to the source line, and the drain of the NAND string during local self-boosting. When the word line connected to the side memory cell is selected, the first select gate is turned on to boot, and when the word line connected to the source side of the NAND string is selected, the second select gate is selected. It is characterized in that the gate is turned on and booting is performed while applying an intermediate voltage from the source line voltage generating circuit.

The non-volatile semiconductor memory of the present invention is a NAND type non-volatile semiconductor memory that writes data in page units, and is a NAND string in which the current paths of a plurality of non-volatile memory cells are connected in series. A word line connected to the control gate of each memory cell, a bit line crossing the word line, and one end of the current path connected to one end of the NAND string. A first select gate having an end connected to the bit line and a gate connected to a first select gate line, a source line, and one end of a current path connected to the other end of the NAND string A second select gate having the other end connected to the source line and a gate connected to a second select gate line; Write non-selection voltage generated when the write non-selection voltage is applied to the memory cell located on the side of the source line in the memory cell by capacitive coupling with the word line regardless of write data. And a voltage generation circuit,
After the write non-select voltage is generated by the write non-select voltage generation circuit, the channel potential is selectively set to the write voltage for the memory cell in which the data is in the write state.

Furthermore, the non-volatile semiconductor memory writing method of the present invention is a data writing method for a NAND flash memory in which writing is performed in page units and a write non-selection voltage is generated by a local self-boosting method. A step of inputting a command to load data, a step of increasing the potential of the channel portion of the nonvolatile memory cell while injecting charges from the source line, and a step of receiving a write command and writing to the nonvolatile memory cell It is characterized by having and.

According to the above-described structure and method, for the memory cell near the source line of the NAND string at the time of local self-boost, when boosting the potential of the channel portion of the memory cell, Since the write non-selection voltage is raised while supplying the charges, it is possible to obtain a voltage sufficient to inhibit the write.

Therefore, when the write inhibit voltage is supplied by using the local self-boosting method, a sufficient write inhibit voltage can be obtained even if there is a memory cell in the state of being written on the drain side, and the erroneous write operation cannot be performed. It is possible to perform additional writing without writing.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. The basic configuration of the nonvolatile semiconductor memory according to the embodiment of the present invention is the same as that of FIGS. 3 and 4, but a write inhibit voltage (write non-select voltage) is applied to the memory cell on the source line side in the NAND string. At the time of writing, a source line voltage generation circuit is provided for applying a predetermined intermediate voltage (eg, power supply voltage Vdd) higher than the ground potential and lower than the write voltage Vpgm to the source line SL. This source line voltage generating circuit may be provided with a dedicated circuit, or the output voltage of another voltage generating circuit may be used.

That is, in the write sequence of the nonvolatile semiconductor memory according to the embodiment of the present invention, the NAN
Memory cells MC connected to a word line (eg, word lines WL0 to WL3) from the source line SL in the D string
When writing to 0 to MC3, select gate line SGS
To turn on the select gate S2 on the source side, the source line S
While injecting charge from L, the potential of the channel is sufficiently increased. After that, the select gate line SGD is selected, the select gate S1 on the drain side is turned on, and the bit line B
The channel of the memory cell for writing data in which L is 0V draws out electric charges toward the bit line BL to 0.
Set to V. On the other hand, writing to the memory cells MC4 to MC15 connected to the word lines WL4 to WL15 uses the same method as the conventional one.

FIGS. 1 and 2 are for explaining the nonvolatile semiconductor memory and the writing method thereof according to the embodiment of the present invention in more detail. FIG. 1 is a flowchart and FIG. 2 is a timing chart. .

As shown in the flow chart of FIG. 1, at the time of writing, a data load command is first input to perform data latch (sense amplifier / data latch 14 in FIG. 3).
The loading of data into the memory is started (STEP 1). At the start of this data loading, the internal timer is started (STEP 2). Next, the power supply voltage Vdd is applied to the source line SL regardless of the write data, and the source line SL
Memory cells MC0, MC1, M while injecting charges from
Sufficiently raise the potential of the C2 channel (STEP
3). After that, the write command is confirmed (STE
P4), it is determined whether the internal timer has reached the set time (STEP 5). At this time, when the number of data is small, the channel section of the memory cells MC0, MC1, MC2 is raised to a sufficient voltage by waiting for the time defined by the internal timer. Then, when the write command is confirmed and it is determined that the internal timer has reached the set time, the write command is received to start writing to the memory cell (STEP 6). After writing, write verify is performed (STEP 7) to determine whether the writing is sufficient. When the writing is sufficient (verify pass), the writing is ended, and when the writing is insufficient, it is determined whether or not the number of times of writing PC has reached a predetermined number of times max (STEP 9). When the writing is insufficient and the number of times of writing PC has not reached the predetermined number of times max (PC <max), the process returns to STEP 6 to perform additional writing to the memory cell. The same operation is repeated, and when it is determined that the writing has been sufficiently performed, the writing operation ends. Also, the number of writings PC is a predetermined number of times max.
If sufficient writing is not performed despite reaching (for example, 10 times) (PC ≧ max), it is determined that writing has failed, and the writing operation is also ended (ST.
EP10).

The timing chart shown in FIG. 2 starts from the timing (STEP 3) when the loading of the write data into the data latch is completed and the write command for writing into the memory cell is input. Source line SL
Is supplied with a power supply voltage Vcc. In the conventional write method, the select gate S2 on the source side is turned off, but the power supply voltage Vcc is applied to prevent punch through of the select gate S2 due to miniaturization.

In the example of FIG. 2, the source line SL is set to the power supply voltage Vcc during data loading in order to speed up writing. After the write command is input, the select gate line SGS is first selected and the select gate S2 on the source line SL side is turned on (t0). Then, the pass voltage Vpass is applied to the unselected word line WL (unselect) (t1),
In consideration of the timing when the potential Vchannel of the channel portion of the non-selected memory cell rises to some extent, the selected word line WL
Increase n (select) to the write voltage Vpgm (t
2). Since the memory cell on the source side of the selected memory cell can be booted while supplying the charge from the source line SL, the channel potential can be sufficiently raised. With respect to the non-selected memory cell on the drain side, since the number of word lines with respect to the parasitic capacitance is large, the channel potential can be sufficiently increased also here. After waiting for a sufficient time to increase the channel potential Vchannel of the memory cell (t3), the source side select gate S2 is cut off and a high level is applied to the drain side select gate S1 (t4). When the write-inhibit data is loaded and the bit line BL is at the power supply voltage Vcc, the channel of the memory cell portion has risen to a high potential of about 7V, so the drain side select gate S1 is turned on. Without doing so, the write protected state can be maintained.

On the other hand, when the write data is loaded, the select gate S1 is turned on and the potential Vchannel of the channel portion is lowered to 0V. As a result, the potential Vchannel of the channel portion of the memory cell is controlled according to the write data, and writing can be performed as in the conventional case. After that, the select gate line SGD, the selected word line WLn (select), and the non-selected word line WL (unselect) are set to the low level (t5).

Since the operation of raising the potential of the channel portion of the memory cell while supplying the electric charge from the source line SL as described above does not depend on the write data, it can be performed in parallel during the data load cycle. It doesn't lengthen the time.

According to the above configuration and method, in the local self-boost, for the memory cells MC0, MC1 and MC2 close to the source line SL of the NAND string, the channel portions of the memory cells MC0, MC1 and MC2 are provided. Since the write inhibit voltage (non-selection voltage) is increased while supplying the electric charges for boosting the potential of 1 from the source line SL, a voltage sufficient to inhibit the write can be obtained.

In addition, the memory cell MC using the internal timer
Since the potentials of the channel portions of 0, MC1 and MC2 are raised, a sufficient voltage can be obtained even when the number of data is small.

Furthermore, even if the prescribed number of times of writing has been reached, if sufficient writing has not been performed, it is determined that the writing is defective and the writing operation is terminated, so that useless writing operation is not repeated.

Therefore, when the write inhibit voltage is supplied by using the local self-boosting method, a sufficient write inhibit voltage can be obtained even if there is a memory cell in the state of being written on the drain side, and the erroneous write operation is prevented. It is possible to perform additional writing without writing.

Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above-mentioned embodiments, and various modifications may be made without departing from the scope of the invention at the implementation stage. It is possible. In addition, the embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all constituent elements shown in the embodiment, at least one of the problems described in the section of the problem to be solved by the invention can be solved, and it is described in the section of the effect of the invention. When at least one of the effects described above is obtained, a configuration in which this constituent element is deleted can be extracted as an invention.

[0039]

As described above, according to the present invention, even when there is a memory cell which is written on the drain side when the write non-selection voltage is supplied by using the local self boost, A non-volatile semiconductor memory capable of performing additional writing without erroneous writing and a writing method thereof can be obtained.

[Brief description of drawings]

FIG. 1 is a flowchart for explaining a nonvolatile semiconductor memory and a writing method thereof according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining a nonvolatile semiconductor memory according to an embodiment of the present invention and a writing method thereof.

FIG. 3 is a NAND according to the related art and an embodiment of the present invention.
Block diagram showing a schematic configuration of a flash memory.

FIG. 4 is a NAND according to the related art and an embodiment of the present invention.
Diagram showing the memory cell configuration of the flash memory.

5A and 5B are for explaining a voltage relationship applied to a memory cell at the time of writing. FIG. 5A is a memory cell in which "0" is written, and FIG. 5B is a write-inhibited state, that is, an erased state. The figure which shows each case in the case of a memory cell holding 1 "data.

FIG. 6 is a circuit diagram for explaining a state of a memory cell in which erroneous writing occurs at the time of conventional additional writing using local self boost.

7 is a cross-sectional configuration diagram of the circuit shown in FIG.

FIG. 8 is a diagram for explaining a time lapse of booting a write non-selected state in a state where an erroneous write failure occurs, in the case where the memory cell MC0 is “0” and the memory cell MC is “1”. FIG. 11 is a diagram showing a temporal change in the channel potential of the memory cell MC2.

[Explanation of symbols]

11 ... Main body memory cell array (main body area) 12 ... Row decoder 13 ... Column decoder 14 ... Data latch / sense amplifier 15 ... Redundant memory cell array (redundant area) 16 ... Redundant column decoder 17 ... Redundant data latch / sense amplifier MC0 to MC15 ... Memory cells S1 ... Select gate (first select gate) S2 ... Select gate (second select gate) WL0 to WL15 ... Word line WLn (select) ... Selected word line WL (unselect) ... Unselected word line SGD ... Select gate line SGS ... Select gate line BL, BLn, BLn + 1 ... Bit line SL ... Source line Vcc, Vdd ... Power supply voltage Vpgm ... programming voltage Vpass ... pass voltage Vchannel ... Channel potential

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/788 H01L 27/10 434 29/792 29/78 371 F term (reference) 5B025 AC01 AD04 AD09 AE00 5F083 EP02 EP23 EP33 EP34 EP76 ER03 ER09 ER22 ER23 GA15 5F101 BA01 BB05 BC01 BD22 BD34 BE05 BE07

Claims (11)

[Claims] 1. N for writing data in page units
An AND-type non-volatile semiconductor memory, wherein a non-writing voltage for writing is generated while supplying charges from a source line. 2. A NAND flash memory that performs writing in page units and generates a write non-selection voltage by a local self-boosting method, wherein at the time of local self-boosting, an arbitrary number of word lines near the drain of a NAND string are Non-volatile semiconductor memory characterized in that when selected, the select gate on the drain side is turned on, and when the remaining number of word lines close to the source is selected, the select gate on the source side is turned on to boot. . 3. N for writing data in page units
An AND type non-volatile semiconductor memory, in which a write non-select voltage of a channel portion of a memory cell is generated by capacitive coupling with a word line regardless of write data, and then data is written to a memory cell Is a nonvolatile semiconductor memory characterized in that a channel potential is selectively used as a write voltage. 4. N for writing data in page units
An AND-type non-volatile semiconductor memory, wherein a NAND string in which current paths of a plurality of non-volatile memory cells are connected in series, a word line connected to a control gate of each memory cell, and the word line A bit line that is arranged to intersect with one another, one end of the current path is connected to one end of the NAND string, the other end of the current path is connected to the bit line, and the gate is connected to the first select gate line. One select gate, a source line, and one end of the current path is connected to the other end of the NAND string, the other end of the current path is connected to the source line, and the gate is connected to the second select gate line. When a write non-select voltage is applied to the second select gate and the memory cell located on the source line side in the NAND string, A non-volatile semiconductor memory, comprising: a source line voltage generation circuit for applying a predetermined intermediate voltage higher than a ground potential and lower than a write voltage to the source line. 5. A NAND flash memory that performs writing in page units and generates a write non-selection voltage by a local self-boosting method, and a NAND string in which current paths of a plurality of nonvolatile memory cells are connected in series. A word line connected to the control gate of each of the memory cells, a bit line arranged to intersect the word line, one end of the current path connected to one end of the NAND string, and the other end of the current path Is connected to the bit line, the gate is connected to the first select gate line, the first select gate, the source line, and one end of the current path is connected to the other end of the NAND string. A second select gate whose end is connected to the source line and whose gate is connected to a second select gate line; A word line connected to the memory cell on the drain side of the NAND string at the time of local self-boosting, the source line voltage generating circuit applying a predetermined intermediate voltage higher than the ground potential and lower than the write voltage to the source line. When the line is selected, the first select gate is turned on to boot, and when the word line connected to the memory cell on the source side of the NAND string is selected, the second select gate is turned on, and A non-volatile semiconductor memory, which boots while applying an intermediate voltage from the source line voltage generating circuit. 6. N for writing data in page units
An AND-type non-volatile semiconductor memory, wherein a NAND string in which current paths of a plurality of non-volatile memory cells are connected in series, a word line connected to a control gate of each memory cell, and the word line A bit line that is arranged to intersect with one another, one end of the current path is connected to one end of the NAND string, the other end of the current path is connected to the bit line, and the gate is connected to the first select gate line. One select gate, a source line, and one end of the current path is connected to the other end of the NAND string, the other end of the current path is connected to the source line, and the gate is connected to the second select gate line. When a write non-select voltage is applied to the second select gate and the memory cell located on the source line side in the NAND string, And a write non-selection voltage generation circuit for generating a write non-selection voltage of the channel portion of the memory cell by capacitive coupling with the word line regardless of write data, and the write non-selection voltage generation circuit generates the write non-selection voltage. A non-volatile semiconductor memory characterized by selectively setting a channel potential as a write voltage with respect to a memory cell in which data is in a written state. 7. A data writing method for a NAND flash memory, which performs writing in page units and generates a write non-selection voltage by a local self-boosting method, comprising the step of inputting a data load command and loading data. A non-volatile semiconductor comprising: a step of increasing a potential of a channel portion of a non-volatile memory cell while injecting charges from a source line; and a step of receiving a write command and writing to the non-volatile memory cell. How to write memory. 8. The step of raising the potential of the channel portion of the non-volatile memory cell, when a word line connected to a memory cell near the source line is selected, turning on a select gate on the source line side, 8. The nonvolatile memory according to claim 7, wherein the non-selected word line is provided with an intermediate voltage, and the write voltage is applied to the selected word line at a timing when the potential of the channel portion of the non-selected memory cell rises by a predetermined value. Writing method for flexible semiconductor memory. 9. The method according to claim 7, wherein in the step of loading the data, a timer is started at the start of loading the data, and the time of the step of raising the potential of the channel portion of the memory cell is defined. A method for writing to a non-volatile semiconductor memory according to item 1. 10. After the step of performing the writing,
10. The non-volatile semiconductor according to claim 7, further comprising a write verify step, wherein when the write is insufficient, the additional write is performed by returning to the write step. How to write memory. 11. The method according to claim 7, wherein in the step of performing the write verification, the number of times of writing is counted, and when the number of times of writing reaches a prescribed number and writing is insufficient, the writing ends as a writing failure. The method for writing to a nonvolatile semiconductor memory according to any one of the items.