JP2003150662A - Test bench for logic verification - Google Patents

Abstract

PROBLEM TO BE SOLVED: To more efficiently and easily verify a design of a large-scale ASIC. SOLUTION: The test bench for verification capable of easily switching an actual circuit to a dummy circuit for respective function modules on the ASIC is fabricated. Thus, at the time of verifying a certain module, by turning the other modules to the dummy circuits and verifying it, generation of an event at the time of a simulation is suppressed and the simulation is accelerated. Also, since only one test bench is prepared and it is not required to prepare the test benches for checking the respective modules, the test bench is easily maintained and managed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to LSI development, and particularly to a logic verification test bench.

[0002]

2. Description of the Related Art Conventionally, when verifying a large-scale LSI, a test bench is prepared for each module, a rough operation verification is performed, and then a test bench for the entire chip in which the modules are actually connected is used. A method of preparing and performing operation verification, or connecting all modules from the beginning and verifying the entire chip in which everything operates has been adopted.

As a conventional example, FIG. 6 shows a test bench for the entire chip in which each module is connected. In FIG. 6, 10 indicates the entire chip to be verified, and 11, 1
Reference numerals 2, 13, 14, and 15 indicate logic modules. 16 sigAtoBE is a signal connecting the module A to the module B and the module E. Next, FIG. 7 shows a test bench for each module. Here, is shown.

[0004]

However, in a large-scale logic circuit, when all the modules are connected to each other for verification, each module needs to be completed to some extent or the operation of the module to be verified. There are problems that it is necessary to make detailed settings for other modules, the number of events that occur increases, the simulation time is lengthened, and verification takes time before the occurrence of.

For example, in the example of FIG. 6 showing a case where all modules are connected and verified, 12 modules B are used.
In the case of attempting to verify the above, the module 11 is connected to the module B, and is an input to the modules A and C of the module 11 and 13 and the interface of the module 14 to the outside.
If the 15 modules D and E, that is, the logic circuit of the entire chip does not exist, the module B cannot be verified. Moreover, in order to actually operate the module B, if the settings of the modules A, C, D, and E are not performed,
Module B cannot operate. Further, since all of them operate, the simulation time becomes longer than that of verifying the module alone.

On the other hand, when using a plurality of test benches,
It is necessary to prepare a test bench for each module,
Larger circuits require more modules and more testbenches.

Further, it is necessary to change the test bench by changing the module, the test pattern, and the like, which has a drawback that the work becomes complicated.

For example, when the module B is updated, it is necessary to update the test bench of the entire chip shown in FIG. 6 and the test bench 18 of the module B alone shown in FIG. Furthermore, it is the signal sigAtoBE that connects between module A and modules B and E. 1
6 has been changed, 17, 18 and 18 in FIG. 6 and FIG.
It will be necessary to update 19 test benches.

The present invention has been made by paying attention to the above points. By reducing the simulation time when verifying each module alone and maintaining and maintaining the test bench, it is possible to achieve a large scale. The time spent for LSI verification can be reduced, which contributes to shortening the development period.

Further, even when a part of the entire chip is cut out and reused and a new chip is manufactured, it is not necessary to create a new test bench, and the logic verification test bench can be made efficient. The purpose is to provide.

[0011]

First, a test bench is prepared in which only one module is connected to all modules.

Next, a plurality of logic circuits are prepared for each module. One is a logic circuit that actually operates,
One is a logic circuit that does not perform any operation, and the other is a logic circuit that performs a pseudo operation instead of an actual operation.

And for each module,
The configuration of the test bench is changed by selectively specifying which logic circuit is used.

As a result, by realizing various configurations with one test bench, a test bench for each module is prepared, or a test bench for verifying a part or the whole of the chip is prepared. .

That is, the technical contents of the present invention can solve the above-mentioned problems by providing the following constitutions.

The present invention can solve the above problems by having the following configurations.

(1) For logic verification, in a hardware description language capable of owning a plurality of types of logic circuits for one logic module, each logic module has a plurality of types of logic description Test bench.

(2) The test bench for logic verification according to (1), wherein one of a plurality of logic circuits for one logic module is an actual logic description.

(3) The logic verification test bench according to (1), wherein one of the plurality of logic circuits for one logic module has a logic description that does not operate.

(4) The logic verification test according to claim 1, wherein one of a plurality of logic circuits for one logic module is a logic description that operates in a pseudo manner instead of an actual logic. bench.

(5) The logic verification test bench according to the above (1), further comprising means for selecting one from a plurality of logic circuits for each logic module.

[0022]

According to the present invention, first, the test bench may be prepared by connecting only all the modules.
It is easier to maintain and manage the test bench when each module is changed or updated, compared to maintaining and managing multiple test benches.

When verifying each module,
Since each module can be selectively operated or replaced with one that does not operate, by disabling modules that are not related to the verification target, the number of events that occur is reduced and the entire chip is connected. The time for simulation can be reduced.

Further, by connecting a pseudo-intentionally operating module to the module to be connected to the verification target, the verification target module can be directly operated, and when the entire chip is connected and used. It is possible to reduce the setting work until the operation for the module is started, and it is easy to verify the module itself.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIGS. 1 to 3 show a test bench using the present invention for the conventional example FIGS.

First, when trying to verify 12 modules B, as shown in FIG.
Is set to a pseudo logical description that only transfers data to the 12th module B in the next stage, and the 13th module C is set to a pseudo logical description that only receives data from the 12th module B in the previous stage. Modules D and E of 14 and 15 that are not directly related to the setting and verification of the module B of 12
In contrast, by setting a logical description that does not operate at all, the verification of 12 modules B can be performed more efficiently than in the case of operating all modules, in a short time, and without using a dedicated test bench. It can be carried out.

Next, as shown in FIG. 2, when the modules A, B, and C of 11, 12, and 13 are completed, but the modules D and E of 14 and 15 are not yet completed, the chip In order to verify the signal flow from the input pin to the output pin of the module, if the verification is performed by connecting the modules A, B, and C of 11, 12, and 13, the output of the module E of 15 to the module C of 13 Even if is fixed, if it operates for the time being, by selecting a logic circuit that does not operate with respect to the modules D and E of 14 and 15, even if the modules D and E of the actual 14 and 15 are not present. , The purpose verification can be performed. Also, the simulation time is shorter than that of operating the entire chip. Finally, as shown in FIG. 3, by converting all modules into logic circuits that actually operate,
The entire chip can be verified without changing the test bench.

FIGS. 4 and 5 show examples of actual description for realizing the test bench described with reference to FIG.

FIG. 4 shows an example of description in Verilog HDL, and FIG. 5 shows an example of description in VHDL. Both show the description for each module first, and then the testbench for connecting them, that is, the description of the whole chip. Finally, the description for setting the selection of the logic circuit of each module of this test bench is shown. In FIGS. 4 and 5, description of ports of each module and description of logic are omitted for simplification of description.

Here, in the Verilog HDL description,
Using the fdef compiler directive, in each module,
Describe the actual logic circuit, the logic circuit that does not operate, and the logic circuit that operates in a pseudo manner, and select the logic circuit of each module of the test bench by setting the `define compiler directive. By changing this `define compiler directive, the logic circuit for each module can be easily switched.

In the VHDL description, an architecture in which an actual logic circuit, a logic circuit that does not operate, and a logic circuit that performs a pseudo operation are described for one entity is prepared.
Use onfiguration declaration to select the logic circuit for each module. The logic circuit for each module can be easily switched by changing the configuration declaration.

[0032]

As described above, according to the present invention, 1
By switching the internal configuration using only one test bench, verification of each module can be performed more easily and faster than verification of the entire chip. Also, if there is a change in the connection signal between modules, 1
It is only necessary to change one test bench, and it is possible to save the troublesome work such as changing the test bench for verifying each module, and it is possible to eliminate the contradiction of operation and verification due to forgetting to change each test bench.

Therefore, by shortening the simulation time when verifying each module alone, and reducing the time spent for maintaining and managing the test bench, it is possible to reduce the time spent for verifying a large-scale LSI, and Contribute to shortening.

Also, when a new chip is manufactured by cutting out a part of the entire chip and reusing it, it is not necessary to create a new test bench, and the work efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a logic diagram in which a module B is an actual logic description, modules A and C are pseudo logic descriptions, and modules D and E are not logic in a test bench in which all modules in a chip are connected. Diagram showing the test bench when described

FIG. 2 is a diagram showing a test bench in which the modules A, B, and C are the actual logic descriptions and the modules D and E are the non-operating logic descriptions in the test bench in which all the modules in the chip are connected.

FIG. 3 is a diagram showing a test bench in which all modules in a chip are connected to each other, and all modules are actually described in logic.

FIG. 4 Verilo a test bench for realizing FIG.
Described in g

[FIG. 5] A test bench for realizing FIG. 1 described in VHDL.

FIG. 6 is a diagram showing a test bench in which all modules in a chip are connected together.

FIG. 7 is a diagram showing a test bench created for each module in the chip.

[Explanation of symbols]

10 Whole chip to be verified 11 Module A 12 Module B 13 Module C 14 Module D 15 Module E 16 sigAtoBE 17 Module A test bench 18 Test Bench for Module B 19 Module E test bench

Claims (5)

[Claims] 1. A logic verification test, characterized in that, in a hardware description language capable of owning a plurality of types of logic circuits for one logic module, each logic module has a plurality of types of logic description. bench. 2. The logic verification test bench according to claim 1, wherein one of a plurality of logic circuits for one logic module is an actual logic description. 3. The logic verification test bench according to claim 1, wherein one of a plurality of logic circuits for one logic module is a logic description that does not operate. 4. The test bench for logic verification according to claim 1, wherein one of a plurality of logic circuits for one logic module is a logic description that operates in a pseudo manner instead of an actual logic. . 5. The logic verification test bench according to claim 1, further comprising means for selecting one from a plurality of logic circuits for each logic module.