JP2003140966A - Cache memory control method for computer system - Google Patents

Abstract

(57) [Abstract] The object of the present invention is to provide a high-speed cache memory and the same contents of a main storage device in a redundant computer system. An address conversion table for holding a set of physical addresses, information of a cache non-target, and information of a write access right in correspondence with a plurality of logical addresses existing in a logical address space.
0 and when writing to the area specified by the logical address 301, the cache non-target and the write access right information corresponding to the logical address are referred to and directly written to either the cache memory or the main storage device. And a memory write selection unit that performs writing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory control system for a computer system, and more particularly to a cache memory control system for a duplicated computer system.

[0002]

2. Description of the Related Art A computer system that requires high reliability, such as a switching system, generally has a duplicated computer system configuration. That is, a central processing unit, a main storage device, a cache memory, a control device, and an input / output device are provided for each two.
A high-reliability system was constructed by installing two computers to configure two computer systems and connecting the two systems in parallel.

In such a computer system, one of the two parallel computer systems is called an active system and the other is called a standby system. In the active system, for example, when performing call processing, the standby system transfers data via the signal line connected between the active system and the standby system, and the same content as the main storage device of the active system is obtained. Is being processed.

When a failure occurs in the active system due to a software or hardware failure, the active system switches from the active system to the standby system to continue the process. In such a case, the processing can be continued by using the main storage device of the backup system which is matched with the active system.

By the way, the cache memory of the conventional main memory device often employs either of the following two types of control methods. A write-through method in which writing to main memory is performed immediately.

Although there is no improvement in the performance of writing to the main memory, there is an advantage that the contents of the main memory of the active system and the content of the main memory of the standby system can be matched. A copy-back method in which writing to main memory is not performed immediately.

Although there is an advantage that the writing performance to the main storage device is improved, there is a disadvantage that the contents of the main storage device of the active system and the main storage device of the standby system do not match. Therefore, it is necessary to switch the system after writing back the contents of the cache memory to the main storage device.

[0008]

From the above, it is possible to quickly recover from a failure or software failure by duplicating the main storage device by the exchange system or the like. However, in a system that guarantees continuation of service, there is a problem that the copyback method that enables high-speed processing and the content of the main storage device at the time of system switching are incompatible.

The present invention has been made in view of the above circumstances.
It is an object of the present invention to provide high-speed cache memory and main memory unity in a duplicated computer system.

[0010]

In order to achieve the above object, a cache memory control method for a computer system according to the present invention is directed to a set of physical addresses for a plurality of logical addresses, cache non-target information and write access. Address conversion table that holds the information on the right to be associated with each other, and when writing to the area specified by the logical address, the cache non-target and the information on the write access right corresponding to the logical address are referred to and cached. It is characterized in that it is provided with a memory write selection unit that directly writes data into either the memory or the main storage device.

Further, a write access detection unit is provided, the write access detection unit detects writing to an area designated by the logical address, and the memory write selection unit,
One of the cache memory and the main memory is selected upon detection of writing to the area specified by the logical address.

Further, a memory writing unit for writing data in the main memory device and a confirmation unit for confirming the content data written in the main memory device are provided, and the content data written in the main memory device is read to confirm the identity. It is characterized in that the read data is reflected in the cache memory while being confirmed.

In the present specification, "non-cache target"
Means that when a program writes in a logical space at a logical address, it writes directly in the main memory.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment in which the cache control system according to the present invention is applied to a computer system.
In the figure, reference numeral 10 indicates a logical space, and 11 indicates a data area existing at a specific address in the logical space. Reference numeral 20 is a write access detection unit that detects writing to a write-protected data area.

Reference numeral 30 is a write access right setting unit for setting a write access right to the data area of the logical space. Four
0 is management data that defines the logical space address of each cache non-target area and its length. Reference numeral 50 is a cache non-target area management unit that sets whether or not the address translation TBL is a cache non-target area.

Reference numeral 60 denotes a memory write selection unit which determines whether or not the detected write access data is a non-cache target area. Reference numeral 70 denotes a memory writing unit that writes to a cache memory according to an instruction from the memory writing selection unit 60, or writes to a main storage device (physical memory) without passing through the cache memory. Reference numeral 80 is a confirmation unit for confirming the normality of the contents written in the memory.

Reference numeral 90 denotes a data area of a physical memory mounted on the computer system, which corresponds to the data 11. 10
0 is a data area of the cache memory and corresponds to the data 11. 200 accesses the logical space 10 (read / writ
e) The program to do. Reference numeral 300 denotes an address translation lookaside buffer (Translation Lookaside Buffer, hereinafter referred to as TLB).

In FIG. 1, when the operating system or application of the computer system is started, the memory write selection unit 60 requests the cache non-target area management unit 50 to set the address translation table 300. The cache non-target area management unit 50 reads out the information about the cache non-target area definition (each target area start address and its length) from the management data 40,
The cache non-target 303 is set while associating the logical space address 301 and the physical address 302 with the address translation TLB 300.

For example, if the cache is not a target, "1" is set, and the write access right for prohibiting the write access is also set. When write access is prohibited, the write access right 304 is set to "1" and the cache non-target is set to "0".

In this way, it is set in the address translation TBL 300 that the data area 11 of the logical space 10 is a non-cache area and that write access is prohibited. This data area 11 is the logical space 1
There may be two or more on 0.

That is, the data area 11 of the logical space 10
The program 200 sets the data area 1 by the combination of the write access right 304 set in the address conversion TBL 300 and the setting information of the cache non-target 303.
Cache control when writing to 1 is performed.

The combination of the value of the write access right 304 and the value of the cache non-target 303 and the processing are shown below. It should be noted that, as the respective values, the values already exemplified are adopted, and hereinafter, description will be given using these values. The write access right 304 (“0”) & cache non-target 303 (“0”) is writable in the data area 11 and is processed as a cache target access. The write access right 304 (“0”) & cache non-target 303 (“1”) is writable in the data area 11 and is processed as a cache target access. The write access right 304 (“1”) & non-cache target 303 (“0”) is a process in which an interrupt is generated as a logical error because writing is performed even though the data area 11 is set as a write-protected area. Is done. Further, it is processed as a cache target access. The write access right 304 (“1”) & cache non-target 303 (“1”) is writable and is processed as a cache non-target access.

As described above, since the data can be written in the data area 11 and is processed as a non-cache area in the above, the contents of the main storage device and the cache memory always match in the setting of. Will work as you would.

Therefore, if the call control management information of the switching system or the like is stored in the data area 11 in the state of, the information of the cache memory and the information of the main storage device are always the same, and the system may be affected by a failure or the like. Even if the switch is switched, it is not necessary to match the contents of the cache memory with the contents of the main storage device.

Now that each value of the address conversion TBL 300 has been described, the flow of processing triggered by the writing of the program 200 will be described next.

Before that, the setting condition of the address conversion TBL 300 which is the center of the operating environment of the present invention will be described.

In the logical space address 301 of the address conversion TBL 300, the start address of the data area 11 (usually,
The start address of the page) is set, while the start address of the data area 90 is set in the physical memory address 302. Then, it is assumed that the cache non-target 303 is set to "1" indicating the cache non-target, and the write access right 304 is also set to "1" indicating the write protection (write disabled).

Under such an environment, first, the program 2
00 writes data in the data area 11 of the logical space 10. This write is detected by the write access detection unit 20 as a write protection violation. In the conventional process, a process of generating an interrupt as a logic error of the program 200 is performed, but in the present invention, the address conversion TBL is further added.
By referring to the corresponding part of 200, it is confirmed whether the value of the cache non-target 303 is "1".

If the value of the non-cache target 303 is "0", the process of generating an interrupt as a logic error of the program 200 is performed as usual. However, if the value is "1", it is not treated as a logic error and is processed as a cache non-target.

Since the value of the non-cache target 303 is "1", it is also written in the physical memory 90. By this writing, the contents of the cache memory and the main memory are kept the same.

Next, the contents written in the physical memory 90 are further read out, and the confirmation unit 80 confirms that the contents are correctly written. Then, the data area 11 records the read content at a corresponding address on the cache memory 100.

With the above configuration, the contents of the cache memory and the contents of the main storage device can be consistently matched only in a specific data area. Further, when reading from the main memory, even if the data area 11 is used, the cache effect can exhibit the same performance as in the past.

FIG. 2 is a processing flow chart of an embodiment in which the cache control system according to the present invention is applied to a main storage device.
In particular, it shows a processing flow when the program 200 is written as a non-cache target when the writing to the data area 11 is triggered.

First, in step S1, the program 20
0 writes to the data area 11 of the logical space 10.

In step S2, when writing to the data area 11 of the logical space 10, the logical space address of the data area 11 is converted into an address of the physical memory through the address conversion TBL300. At that time,
The logical access address 301 of the data area 11 is associated with the physical address 302 of the data area 90 on the physical memory on the address conversion TBL 300, and the write access right 304 is referenced.

In step S3, at this time, as described with reference to FIG. 1, write-protection is set as the write access right 304 corresponding to the data area 11.
Writing to the data area 11 by the program 200 causes the write access detection unit 20 to generate an interrupt (memory protection exception) as a logic error.

In step S4, however, in the present invention, the cache non-target 303 of the corresponding address translation TBL 300 is further cache non-target ("1").
Is set, the data area 11 can be written as a non-cache target instead of the write protection. Therefore, it is determined that writing to the data area 11 is possible. That is, the memory write selection unit 60
Sends an instruction to the memory writing unit 70 to write the data area 90 of the physical memory corresponding to the data area 11 of the logical space address.

In step S5, the memory writing unit 70 writes in the data area 90 on the physical memory according to the instruction from the memory writing selection unit 60.

In steps S6 to S8, the confirmation unit 80 reads the data written in the main memory (physical memory) and confirms the contents. Then, the reading is to write the contents into the data 100 corresponding to the cache memory.

[0040]

As described above, according to the present invention,
Even if the copy-back method is used to control the cache memory, the cache memory can be controlled in the same way as the write-through method for only the data area existing in the logical space as a non-cache target.

[Brief description of drawings]

FIG. 1 shows an embodiment in which a cache control system according to the present invention is applied to a computer system.

FIG. 2 is a process flow diagram of an embodiment in which a cache control method according to the present invention is applied to a main storage device.

[Explanation of symbols]

10 logical space 11 data area 20 write access detector 30 Write Access Right Setting Section 40 management data 50 Non-cache management unit 60 Memory write selection section 70 Memory writing unit 80 Confirmation Department 90 data areas 100 data areas 200 programs 300 address conversion table 301 Logical space address 302 Physical memory address 303 Cache non-target 304 Write access right

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Claims (3)

[Claims] 1. An address conversion table that holds a plurality of logical addresses in association with a set of physical addresses, cache non-target information, and write access right information, and writes in an area specified by logical addresses. And a memory write selection unit that directly writes data to either the cache memory or the main storage device by referring to the information about the cache non-target and the write access right corresponding to the logical address. Characteristic computer system cache memory control method. 2. The memory device according to claim 1, further comprising a write access detection unit, wherein the write access detection unit detects writing to an area designated by the logical address, and the memory write selection unit. Is a cache memory control method for a computer system, which selects one of the cache memory and the main storage device upon detection of writing to an area specified by the logical address. 3. The content written in the main storage device according to claim 1, further comprising a memory writing unit that writes in the main storage device and a confirmation unit that confirms the content written in the main storage device. A cache memory control method for a computer system, which is characterized by reading the data to confirm the identity and reflecting the read data in the cache memory.