JP2003131625A - Driving device for display device and module of the display device using the same driving device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To further reduce a chip area in accordance with a plurality of lines of data bus lines in a piece of a D/A converter circuit and to realize the cost reduction attendant on it. SOLUTION: This driving device is provided with a plurality of changeover switching circuits SWin1a to an SWin3a which transmit display data to a D/A converter circuit, a plurality of changeover switching circuits SWout1a to an SWout3a which transmit voltage for gradation display to output circuits 137 and a switch changeover signal generating circuit which successively selects a pair of changeover switching circuits corresponding to the respective output terminals of a liquid crystal panel in a time-divisional manner and repeats these selections during one horizontal period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device driving device and a display device module for reducing the circuit scale, reducing the power consumption of the circuit, and reducing the cost.

[0002]

2. Description of the Related Art A TFT (thin film transistor) type liquid crystal display device, which is a typical example of an active matrix type, has been conventionally known. This liquid crystal display device is shown in FIG.
As shown in 0, it comprises a liquid crystal display unit (display device) and a liquid crystal drive circuit (liquid crystal drive device) for driving it.

As shown in FIG. 10, the liquid crystal display section has the following structure.
A TFT type liquid crystal panel 901 is provided. A liquid crystal display element (not shown) and a counter electrode (common electrode) 906 described later are provided in the liquid crystal panel 901.

On the other hand, each of the liquid crystal drive circuits has an IC.
Source driver 902 consisting of (Integrated Circuit)
And a gate driver 903, a controller 904,
A liquid crystal drive power source 905 is provided.

The controller 904 inputs the display data D and the control signal S1 to the source driver 902 and the control signal S2 to the gate driver 903.

As a result, the controller 904 is
A vertical synchronizing signal is input to the gate driver 903 as one of the control signals, and a horizontal synchronizing signal is input to the source driver 902 and the gate driver 903 as one of the control signals.

Display data input from the outside is sent as display data D to the source driver 902 as a digital signal via the controller 904.

The source driver 902 latches the input display data D internally in a time division manner, and then performs D / A conversion in synchronization with the horizontal synchronizing signal received from the controller 904.

This D / A conversion is performed by displaying display data from a plurality of gradation display analog voltages generated by a reference voltage generating circuit (described later) in the source driver 902 based on a reference voltage VR from a liquid crystal drive power source 905. It is performed by selecting one according to D.

An analog voltage for gradation display (for gradation display) obtained by D / A conversion is supplied from a liquid crystal drive voltage output terminal to a source signal line 1004 (see FIG. 11) described later.
Liquid crystal display element (not shown) in the liquid crystal panel 901 corresponding to the liquid crystal drive voltage output terminal.
Sent to each.

FIG. 11 shows the structure of the liquid crystal panel 901. A pixel electrode 1001, a pixel capacitor 1002, and a TFT 100 as an element for turning on / off a voltage application to a pixel.
3, the source signal line 1004, the gate signal line 1005, and the counter electrode 1006 are provided.

In FIG. 11, the area indicated by A corresponds to a liquid crystal display element for one pixel. The source signal line 1004
, A gradation display voltage according to the brightness of the pixel to be displayed is applied from the source driver 902. A scanning signal is applied to the gate line signal 1005 from the gate driver 903 so that the TFTs 1003 arranged in parallel in the vertical direction are sequentially turned on.

The pixel electrode 100 connected to the drain of the TFT 1003 through the TFT 1003 in the ON state
1 is applied with the voltage of the source signal line 1004 and accumulated in the pixel capacitor 1002 between the counter electrode 1006 and
When the TFT 1003 is turned off, the applied voltage is held. As a result, the light transmittance of the liquid crystal changes, and desired display is performed.

12 and 13 show examples of liquid crystal drive waveforms. Reference numerals 1101 and 1201 denote output drive waveforms from the source driver 902, and reference numeral 110
Reference numerals 2 and 1202 denote output drive waveforms (scanning signals) from the gate driver 903. Further, reference numerals 1103 and 1203 denote voltage levels of the counter electrodes, and reference numeral 11
Reference numerals 04 and 1204 denote voltage waveform levels of the pixel electrode.
The voltage applied to the liquid crystal material is equal to the potential difference between the pixel electrode 1001 and the counter electrode 1006, and is indicated by diagonal lines in the figure.

For example, FIG. 12 shows a gate driver 903.
When the drive waveform 1102 of the
03 is turned on, and the difference between the output drive waveform 1101 from the source driver 902 and the voltage level 1103 of the counter electrode is applied to the pixel electrode 1001. After that, the output drive waveform 1102 from the gate and the driver becomes low level, and the TFT 1003 is turned off. At this time, since the pixel capacitor 1002 exists in the pixel, the above voltage is maintained. The same applies to the case of FIG.

12 and 13 show the case where the voltages applied to the liquid crystal material are different, and in the case of FIG. 12, the applied voltage is larger than that in the case of FIG. In this way, by changing the voltage applied to the liquid crystal as an analog voltage, the light transmittance of the liquid crystal is changed in an analog manner,
Realizes multi-gradation display. The number of gray scales that can be displayed is determined by the number of options for the analog voltage applied to the liquid crystal.

FIG. 14 is a block diagram showing an example of the source driver 902. The display data of the input digital signal has display data DR, DG, and DB of R (red), G (green), and B (blue) (for example, in the case of 64 gradations, each has 6-bit configuration). It has become. The display data is once input to the input latch circuit 1301, and is then shifted when the start pulse SP and the clock CK are input, and the shift register 1
In accordance with the operation of 302, the data is stored in the sampling memory 1303 in a time division manner, and then collectively transferred to the hold memory 1304 based on a horizontal synchronizing signal (not shown). In the figure, S represents a cascade output.

The reference voltage generating circuit 1309 has a reference voltage V
It is provided to generate a reference voltage of each level based on R.

The data in the hold memory 1304 is
Via the level shift circuit 1305, D / A (digital /
It is sent to the (analog) conversion unit 1306, and one analog voltage is selected from the reference voltages of each level from the reference voltage generation circuit 1309 according to the digital display data D and converted into an analog voltage. Then, the output circuit 1307 outputs a gray scale display voltage from the liquid crystal drive voltage output terminal 1308 to each liquid crystal display element (A in FIG. 11).
Refer to) source signal line.

As described above, the reference voltage generating circuit 130 is provided.
9, the D / A converter 1306, and the output circuit 13
07 configures a D / A conversion unit and an output unit. Then, in the liquid crystal display device, the liquid crystal drive circuit is configured as described above by using the D / A conversion unit and the output unit, whereby the liquid crystal panel 90 is provided as described above.
Digital data to be displayed on 1 (display data DR, DG,
DB) is D / A converted and applied to each liquid crystal display element through the output circuit 1307.

FIGS. 15 and 16 show details of an example of a D / A conversion unit and an output unit which are used in the above liquid crystal driving device and which convert display data given as a digital signal into an analog voltage and output it. Shows the configuration.

FIG. 15 shows a reference voltage generation circuit 1401 (reference voltage generation circuit 1309 of FIG. 14) which generates a plurality of (64 in this example) reference voltages as gradation display voltages.
Equivalent to. ) Shows a circuit configuration example.

FIG. 16 shows a selection circuit 1402 (D in FIG. 14).
A / A conversion unit 1306) and a voltage follower circuit 1403 (corresponding to the output circuit 1307 in FIG. 14). The example shown in FIG. 16 is a 6-bit digital signal (bit 5 (Bit5) to bit 0 (Bit0)).
2 shows a configuration of a D / A conversion circuit used in a liquid crystal drive circuit with 64 gradations, which outputs 64 analog voltages corresponding to.

The selection circuit 1402 selects and outputs one of a plurality of reference voltages according to the display data D, and the switch circuit section is composed of a MOS transistor.

The voltage follower circuit 1403 is
The voltage selected by the selection circuit 1402 is converted into a low impedance output, and the liquid crystal drive voltage output terminal (see FIG.
(Corresponding to the liquid crystal driving voltage output terminal 1308 of 1)).

The reference voltage generating circuit 1401 is usually
One source driver IC chip is provided for each and is commonly used for a plurality of liquid crystal drive voltage output terminals. On the other hand, in the selection circuit 1402 and the voltage follower circuit 1403, one circuit is used for each liquid crystal drive voltage output terminal.

In the case of color display, the liquid crystal drive voltage output terminal is used for each color. In this case, as the selection circuit 1402 and the voltage follower circuit 1403, one circuit is used for each color for each pixel. That is, if the total number of pixels in the liquid crystal panel 901 is N, the liquid crystal drive voltage output terminals for each color of red, green, and blue are added to R, G, and B, respectively, with subscripts n (n = 1, 2,
, N), the liquid crystal drive voltage output terminals are R1, G1, B1, R2, G2, B2,
, RN, GN, BN exist, and therefore, N selection circuits 1402 and voltage follower circuits 1403 are required.

Then, 3N selection circuits 1402 and output circuits (voltage follower circuits as buffer circuits) are arranged in the source driver 902. For example, when m source drivers are connected, each source driver has (3N / m) circuits.

The reference voltage generating circuit 1401 shown in FIG.
As shown in (1), the resistor element is usually connected in series to output the voltage between the resistors. As a reference voltage VR input terminal input from the liquid crystal drive power source 905, V
0, V8, V16, V24, V32, V40, V48,
Nine terminals of V56 and V64 (generally V0 and V6
In many cases, the reference voltage is input to No. 4 and no voltage is input (not used) to the other intermediate voltage input terminals. )have.

Resistors R0 to R7 are connected in series between the terminals V0 to V64, respectively, as shown in FIG. The resistance ratios of the resistors R0 to R7 are set and the resistance values thereof are determined so that γ correction is performed.

A plurality of resistance elements are further connected in series between the terminals V0 and V8 so that the voltage between the terminals V0 and V8 is divided into eight equal parts. Similarly, between the terminals V8 and V16, between the terminals V16 and V24, between the terminals V24 and V32, between the terminals V32 and V40, between the terminals V40 and V48, between the terminals V48 and V56, and between the terminals V56 and V64. A plurality of resistance elements are further connected in series between the terminals, so that the voltage between the terminals is divided into eight equal parts. As described above, the reference voltage generation circuit 1401 generates a total of 64 levels (V′0 to V′63) of voltage, and the selection circuit 1402 (D / A conversion unit).
Is being supplied to.

In order to perform natural gradation display in accordance with the optical characteristics of the liquid crystal material, the source driver 902 incorporates a resistance ratio called γ correction to give the liquid crystal drive output voltage a polygonal line characteristic. By correcting the optical characteristics of the liquid crystal material by this ratio, more natural gradation display is realized. Here, the source driver 9
FIG. 17 shows an example of the gradation voltage characteristics of No. 02.

The 64 voltages generated by the reference voltage generation circuit 1401 are supplied to the selection circuit 1402.
Sent to. In the selection circuit 1402, one of the 64 input voltages is selected and output according to the display data formed of a 6-bit digital signal.
The above-mentioned switch made of a MOS transistor is provided.

In this example, the MOS transistor as the switch circuit is turned on or off according to the value of each bit of the 6-bit digital display data [bit 5 (MSB) ... Bit 0 (LSB)], and the above One of the 64 levels (V'0 to V'63) input from the reference voltage generation circuit 1401 is selected and output according to the digital display data.

For example, digital display data [00000
0] selects and outputs level V′0, digital display data [000001] selects and outputs level V′1, and digital display data [000010] selects and outputs level V′2. In the digital display data [111110], the level V′62 is selected and output, and in the digital display data [111111], the level V′63 is selected and output.

The voltage follower circuit 1403 is
The same voltage as the analog voltage output from the selection circuit 1402 is made into a lower output impedance and output as a liquid crystal drive signal from the liquid crystal drive voltage output terminal.
It plays a role of charging the picture element and wiring capacity of the liquid crystal panel, and increasing the speed of reaching the target voltage.

However, in order to meet the demands for high quality of liquid crystal display panels such as large size, high definition, multi-gradation display, etc. from the user at present, the number of pixels and the number of digital display bits are increased. Expansion is required.

The increase in the number of pixels leads to the increase in the number of gate signal lines and the number of source signal lines, and in particular, the number of source signal lines is required to correspond to each of R, G and B as described above. Therefore, the number of output terminals of the source driver increases. This increases the circuit area of the D / A conversion circuit (selection circuit) and the output circuit section arranged for each output terminal, and thus increases the area of the source driver IC chip. Furthermore, the expansion of the digital display bit number further increases the circuit area of the D / A conversion circuit (selection circuit).

For example, as shown in FIG. 16, if the number of R, G, and B display bits is 6 bits and each is a 64 gradation display, a switch circuit (here) is provided in the D / A conversion circuit (selection circuit). Then, the number of MOS transistors is 126.

In order to perform a multi-gradation display, R,
If each of the G and B display bits has 8 bits and 256 gradations are displayed, the switch circuit (here, MOS transistor) in the D / A conversion circuit (selection circuit) is composed of 510 pieces. .

Further, if the number of R, G, and B display bits is 10 bits and each is 1024 gradation display, the switch circuit (here, MOS) in the D / A conversion circuit (selection circuit) is used.
The number of transistors is 2046. In this way, for the display bit number of k (k: natural number) bits, the number of switch circuits (here, MOS transistors) in the D / A conversion circuit (selection circuit) is (2 ^{k + 1} −2). Therefore, the number of circuits will increase. As a result, in order to deal with the multi-gradation display, the area of the D / A conversion circuit (selection circuit) is increased and the area of the source driver IC chip is increased.

Since the number of source signal line outputs is large,
An increase in the area of the D / A conversion circuit (selection circuit) arranged for each output terminal and having a large number of circuits directly leads to an increase in the area of the source driver IC chip, and the source driver IC
Will increase the cost.

Further, in order to reduce the cost of the liquid crystal display device module, the number of mounted ICs is reduced as much as possible, and the number of output terminals per source driver is further increased. Therefore, as mentioned above,
The reduction of the D / A conversion circuit (selection circuit) provided in one circuit at the output terminal has become a major issue.

As a technique for improving this point, Japanese Patent Laid-Open No.
The technique disclosed in Japanese Laid-Open Patent Publication No. 260661 is known. This conventional technique will be described below with reference to FIG.

FIG. 18 is a circuit diagram showing a schematic electrical configuration of the above-mentioned prior art. The liquid crystal panel 31 uses the liquid crystal drive circuit 32 to scan the scan bus lines 110, 111, ...
A data bus line 120 provided so as to intersect with
At the intersection with 121, ...
It is called a TFT. , 130, 131, ..., The liquid crystal display pixels VC1, VC2 ,.

In the TFTs 130, 131, ...
The gate is connected to each of the scan bus lines 110, 111, ... And the drain is connected to the data bus line 12
0, 121, ... Are respectively connected. Each scan bus line 110, 111, ... Has one frame display cycle.
As a cycle, scanning signals Gj, Gj + 1, ... Are sequentially applied from the liquid crystal gate circuit. Two data bus lines 1
20 and 121 are switched and driven by the output side changeover switch 140. The data bus lines 120 and 121 are provided with auxiliary capacitors 150 and 151, respectively.

In the liquid crystal drive circuit 32, one drive circuit 190 is provided for every two data bus lines (for example, 120 and 121). Each drive circuit 190
Includes a shift register 200, an input side changeover switch 220 which is an analog switch for changing over the sampling latches 210A and 210B of two systems, and a D / A.
A conversion circuit 230 is provided.

The shift register 200 uses two sampling latches 21 according to the sampling clock signal.
A clock signal for fetching gradation display data is generated in each of 0A and 210B. The input side changeover switch 20 for switching the sampling latches 210A and 210B is controlled by an externally supplied control signal.
Before and after one horizontal period (1H), for example, control is performed so as to switch to the A system shown by the solid line in the first half of 1H and the B system shown in the broken line in the second half of 1H.

The D / A conversion circuit 230 converts the n-bit grayscale display data into a grayscale display analog voltage level based on the outputs of the sampling latches 210A and 210B switched by the input side changeover switch 220. It is possible to derive gradation display voltages for the data bus lines 120 and 121 that are different between the first half and the 1H second half.

An output side changeover switch 140 is provided on the output side of the D / A conversion circuit 230, and is switched to the data bus line 120 side in the first half of 1H, while it is changed to 1H.
In the latter half, it is switched to the data bus line 121 side.
Therefore, the two data bus lines 120 and 121 are connected to one D / A conversion circuit 2 during one horizontal scanning period 1H.
It can be driven by the output from 30.

In the first half of one horizontal period, the grayscale display data latched by the A system of the sampling latch 210A is stored in the pixel capacitance VC1 via the analog switch 140A formed on the liquid crystal panel 31. Applied,
In the latter half of one horizontal period, the gray scale display data latched by the B system of the sampling latch 210B is formed on the liquid crystal panel 31 of the analog switch 14 in the latter half period.
It is applied to the pixel capacitor VC2 via 0B.

As a result, one liquid crystal signal output terminal OS
Thus, it becomes possible to drive the display pixels for two colors. As described above, according to the above conventional technique, it is possible to switch and drive two data bus lines with one terminal of the liquid crystal signal output circuit, and it is possible to reduce the number of outputs to half. As a result, it is possible to reduce the chip area of the liquid crystal drive circuit 32 and reduce the cost.

Further, the above-mentioned conventional technique (Japanese Patent Laid-Open No. 10-26)
No. 0661), another example is disclosed. However, according to this, the drive capability for charging and discharging the pixel capacitance of the liquid crystal panel becomes a problem without providing the voltage follower circuit as the low impedance conversion means.

Further, the above conventional technique (Japanese Patent Laid-Open No. 10-26)
Still another example is disclosed in Japanese Patent Publication No. 0661). According to this, the output side switching means is provided between the voltage follower circuit and the terminal of the liquid crystal panel.

In this case, the gate width of the analog switch, which is the output side switching means, must be increased so that the impedance is low even with a large current for charging and discharging the pixel capacitance of the liquid crystal panel. Will become bigger.

Since the resistance of the analog switch circuit is inserted in series with the output of the voltage follower circuit as the low impedance conversion means, a voltage drop occurs due to this resistance and the supplied voltage becomes unstable. turn into.

Further, the above conventional technique (Japanese Patent Laid-Open No. 10-26)
Still another example is disclosed in Japanese Patent Publication No. 0661). According to this, the auxiliary capacitance is separately provided between the output side switching means and the low impedance conversion means.

In this case, since it is necessary to separately provide the auxiliary capacitance, the area is increased accordingly.

[0059]

However, the above-mentioned conventional technique shown in FIG. 18 has the following problems.

That is, according to the above-mentioned conventional technique, the sampling latch 2 is provided in the first half period of one horizontal period.
An analog switch 140A in which gradation display data latched in the A system of 10A is formed on the liquid crystal panel 31.
Is applied to the pixel capacitor VC1 via
In the latter half period of 2, the gradation display data latched in the B system of the sampling latch 210B is switched and applied to the pixel capacitance VC2 via the analog switch 140B formed on the liquid crystal panel 31.

The analog switches 140A and 140
The changeover control of B (input side changeover switch 220) is performed before and after one horizontal period by a control signal supplied from the outside.
For example, the control is switched to the A system in the first half of 1H and to the B system in the second half of 1H. As described above, in the above-described conventional technique, it is not assumed that the control signal is generated in the liquid crystal drive circuit, and when one drive circuit corresponds to three or more data bus lines, There is no disclosure or suggestion as to how to perform switching control.

That is, the above-mentioned conventional technique only discloses that one drive circuit corresponds to two data bus lines on the basis of a control signal supplied from the outside. What kind of switching control circuit is provided,
It is unknown at all how this drive control circuit handles a plurality of data bus lines with a single drive circuit.
This is supported by the fact that there is no disclosure or suggestion as to how the switching control is specifically performed when one drive circuit corresponds to three or more data bus lines.

The present invention has been made in view of the above-mentioned conventional problems, and an object thereof is to increase the number of terminals (the number of D / A conversion circuits) in response to a demand for further size increase and high definition of a liquid crystal panel. Increase) and an increase in the number of elements in the D / A conversion circuit associated with multi-gradation display, further reducing the chip area corresponding to a plurality of data bus lines in one D / A conversion circuit. And to realize the cost reduction accompanying it.

[0064]

In order to solve the above-mentioned problems, a display device driving apparatus according to the present invention receives display data and selects one from a plurality of gradation display voltages according to the display data. The following measures are taken in the drive device of the display device including the gradation display voltage selecting means and the low impedance conversion means that lowers the impedance of the selected gradation display voltage and outputs it to each terminal of the display device. It is characterized by that.

That is, the driving device of the display device comprises a plurality of input side switching means for sending the display data to the gradation display voltage selecting means, and a plurality of input side switching means for sending the gradation display voltage to the low impedance converting means. Output side switching means, and a pair of input side switching means and output side switching means corresponding to each output terminal of the display device are sequentially selected in a time division manner, and switching control means for repeating these selections for one horizontal period. It is characterized by further provision.

According to the above invention, when the display data is input, one of the plurality of grayscale display voltages is selected by the grayscale display voltage selecting means according to the display data. The gradation display voltage selected in this way is sent to the low impedance conversion means, where it is made into a low impedance, and then output to each terminal of the display device. As a result, the display device displays the display data.

At this time, the pair of input side switching means and output side switching means corresponding to the respective output terminals of the display device are sequentially selected in a time division manner by the switching control means provided in the drive device. One of a plurality of gradation display voltages is selected by the gradation display voltage selection means in accordance with the display data input via the selected input side switching means,
It is sent to the low impedance conversion means via the output side switching means selected at the same time as the input side switching means. The selection relating to the pair of input side switching means and output side switching means is repeated during one horizontal period.

As described above, since one gradation display voltage selecting means is shared by a plurality of pairs of switching means each including a plurality of input side switching means and a plurality of output side switching means, the display device is further improved. It is possible to cope with the increase in the number of terminals (increase in the number of gradation display voltage selection means) due to the demand for larger size and higher definition and the increase in the number of elements in the gradation display voltage selection means accompanying multi-gradation display. Further, it is possible to further reduce the chip area and reduce the cost accordingly.

It is preferable that the switching control means is composed of a shift register circuit, and the input side switching means and the output side switching means are selected in a time division manner based on the output signal of each stage of the shift register circuit. In this case, the switching control means can be realized with a simple structure.

The switching control means selects the input side switching means and the output side switching means in a time division manner so that the two input side switching means and the two output side switching means are not selected at the same time. Is preferred.

In this case, the switching control means simultaneously operates two switches.
Switching control is performed so that one input side switching means and two output side switching means are not selected at the same time. This gives 2
It is possible to reliably prevent current from flowing back between the switching means when switching is performed between the input side switching means and between the two output side switching means, and to reliably reduce switching noise. You can

The switching control means comprises a shift register circuit and an overlap prevention circuit. This overlap prevention circuit is
An AND operation of the output signal of each stage of the shift register circuit and a delayed version of this output signal is performed, and the input side switching means and the output side switching means can be selected in time division based on the operation result. preferable. In this case, the switching control means can be realized with a simple structure.

The output signal of the low impedance conversion means is sent to the switch means provided on the display device through a common output terminal, and the switch means corresponds to each output terminal of the display device. It is preferable that a plurality of switch circuits are provided, and the opening and closing of these switch circuits are sequentially controlled in a time division manner in synchronization with the pair of corresponding input side switching means and output side switching means.

In this case, a pair of input side switching means and output side switching means and a switch circuit corresponding to each output terminal of the display device are selected in synchronization. Accordingly, one output terminal in the drive device is shared by the plurality of low impedance conversion means, so that the number of output terminals in the drive device can be reduced more reliably. Therefore, it becomes possible to narrow the pitch for further enlargement and high definition of the display device,
It becomes possible to obtain high reliability.

The display device module is preferably constructed by using the drive device for the display device. This allows
It is possible to surely realize a display device module having a narrow pitch and high reliability with respect to the size and high definition of the display device.

[0076]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS.

The structure of the liquid crystal display device (liquid crystal display module) having the liquid crystal drive circuit according to the present embodiment, the structure of the liquid crystal panel of the liquid crystal display device, and the liquid crystal drive waveform thereof are shown in FIG. Since it is the same as the one described above, detailed description is omitted here.

The liquid crystal display module (display device module) according to the present embodiment is basically the same as that of FIG. 10, but is different in the following points. That is, in FIG. 10, as the control signal S1 from the controller 904 to each source driver, the switching control signal DA of the switching means provided on the input side and the output side of the D / A conversion circuit.
This is different from the configuration of FIG. 10 in that a SW is newly added.

FIG. 2 is a block diagram showing a configuration example of the source driver 92 according to this embodiment. The display data of the input digital signal is the display data DR, DG, and DB of R (red), G (green), and B (blue), and this display data is once input latch circuit 131. To the sampling memory 133 in time division in accordance with the operation of the shift register 132 that shifts when the start pulse SP and the clock CK are input. ), And is collectively transferred to the hold memory 134. In the figure, S represents a cascade output. Also, in FIG.
The switch switching signal generation circuit 139 causes the source driver 92
However, the present invention is not limited to this, and the switch switching signal generation circuit 139 is not limited to this.
May be provided in an external controller or the like, and a switching signal may be input to the source driver 92.

The reference voltage generating circuit 138 is operated by the reference voltage VR.
It is provided to generate the reference voltage of each level based on the.

The data in the hold memory 134 has a signal level boosted to the voltage level applied to the liquid crystal panel via the level shift circuit 135, and the data including the switch circuit D
It is sent to the / A (digital / analog) converter 136.

The D / A converter 136 is composed of a switching element (switch circuit) and a D / A converter circuit, and one D / A converter circuit outputs a plurality (N) of outputs. The switching elements are driven in a time division manner so that they can be shared.

Further, the source driver 92 has a switching control signal (for example, FIGS. 1 and 3) for controlling ON / OFF of the switching elements arranged at the input stage and the output stage of the D / A conversion circuit. Further, a switch switching signal generating circuit 139 (switching control means) for outputting the switching control signals t1 to t3) is further provided.

This switch switching signal generation circuit 139
A switching control signal DASW (for example, DASW1) of the switching means from the controller 904 (see FIG. 10).
And DASW2. ) In response to the switching control signals (for example, the switching control signals t1 to t in FIGS. 1 and 3).
3)).

The switch switching signal generating circuit 139 is
For example, it is configured by a shift register circuit (three-stage cascade configuration in FIG. 1), the DASW1 is input as a start pulse signal, the DASW2 is used as a transfer clock, the DASW1 is transferred in the shift register circuit 2, and each output is output. The output signal from the stage is, for example, the switching control signal t
It can be easily constructed by taking out as 1 to t3.

Further, the switch switching signal generating circuit 13
9 is not in the source driver, but the controller 9
It is also possible to provide a switching control signal (t1 to t3) from the controller 904 and input it to each source driver.

Further, the D / A conversion section 136 converts the reference voltage of each level from the reference voltage generation circuit 138 into an analog voltage.

Then, via the output circuit 137 (low impedance conversion circuit, voltage follower circuit in this case), from the liquid crystal drive voltage output terminal 140 to each liquid crystal display element (see reference numeral A in FIG. 11) as a gradation display voltage. Is output.

A level shifter circuit 135 in one example of a block diagram of the source driver 92, a D / A converter (digital / analog converter) 136 including a switch circuit,
FIG. 1 shows a more detailed configuration example of the output circuit 137 (low impedance conversion circuit, here a voltage follower circuit). The operation of FIG. 1 will be briefly described below with reference to the timing of FIG. In the configuration example of FIG. 1, one D / A conversion circuit is shared for every three output terminals to share a plurality of outputs, but the present invention is not limited to this. Alternatively, a plurality of output numbers may be shared by one D / A conversion circuit for each of four or more output terminals.

One source driver IC (one D / A
D / A conversion circuits 136a, 13
6b, ..., 136N (in FIG. 1, for convenience of explanation,
Only the D / A conversion circuits 136a and 136N are shown. ) Is provided. Here, for convenience of description, the D / A conversion circuit 136a will be described as an example, but other D / A conversion circuits 1 will be described.
Since 36b to 136N have the same configuration, the same operation is performed.

A changeover switch circuit SWin1a is provided between the input side of the D / A conversion circuit 136a and the level shifter circuit 135-1a, and the D / A conversion circuit 13 is provided.
A changeover switch circuit SWin2a is provided between the input side of 6a and the level shifter circuit 135-2a.
Input side of the / A conversion circuit 136a and the level shifter circuit 13
A changeover switch circuit SWin3a is provided between the switch 5in and 5-3a.

Further, between the output side of the D / A conversion circuit 136a and the voltage follower circuit 137-1a,
A changeover switch circuit SWout1a is provided, and the D /
A changeover switch circuit SWout is provided between the output side of the A conversion circuit 136a and the voltage follower circuit 137-2a.
2a is provided, and a changeover switch circuit SWout3a is provided between the output side of the D / A conversion circuit 136a and the voltage follower circuit 137-3a.

The changeover switch circuit SWin1a and the changeover switch circuit SWout1a are circuits relating to the generation of the gradation display voltage output from the output terminal O1.
The switching control signal t1 is supplied to the control terminal. ON / OFF of the pair of changeover switch circuits SWin1a and SWout1a is controlled based on the changeover control signal t1.

A pair of changeover switch circuits SWin2a
The changeover switch circuit SWout2a is a circuit related to generation of a gradation display voltage output from the output terminal O2, and a changeover control signal t2 is supplied to these control terminals. The changeover switch circuit SWin2a and the changeover switch circuit SWout2a are connected to the changeover control signal t2.
ON / OFF is controlled based on

A pair of changeover switch circuits SWin3a
The changeover switch circuit SWout3a is a circuit related to generation of a gradation display voltage output from the output terminal O3, and a changeover control signal t3 is supplied to these control terminals. The changeover switch circuit SWin3a and the changeover switch circuit SWout3a have the changeover control signal t3.
ON / OFF is controlled based on

The pair of changeover switch circuits are
It corresponds to each output terminal of the liquid crystal panel. Further, although omitted in FIG. 1, the input side changeover switch circuit SWin
1a to SWin3a are respectively provided according to digital display data (bits). For example, in the case of 64-bit display and 6-bit digital display data, each changeover switch circuit is provided with 6 circuits for each bit.

Here, the switching control of the above-mentioned changeover switch circuit will be described below with reference to FIG.

During one horizontal period, first, when the changeover control signal t1 becomes high level, the changeover switch circuit SWin1a.
(For example, 6 circuits) are turned on and become conductive. At this time, the changeover switch circuits SWin2a, SWout2a,
Both SWin3a and SWout3a are off and in a non-conducting state.

As a result, the level shifter circuit 135-1
Digital display data boosted by a (for example, 6
(Bit) is sent to the D / A conversion circuit 136a via the changeover switch circuit SWin1a. In the D / A conversion circuit 136a, the level shifter circuit 135-
According to the digital display data boosted by 1a, a plurality of voltages (for example, from the reference voltage generating circuit 138) (for example,
One gradation display voltage is selected from 64 levels).

The gradation display voltage thus selected is supplied to the voltage follower 137-1a via the changeover switch circuit SWout1a which is turned on by the changeover control signal t1 and is in a conductive state. The impedance is reduced and the output terminal O1 outputs the source line of the liquid crystal panel.

After a certain time T, the changeover control signal t1 changes from the high level to the low level (at this time, the changeover control signal t2 changes from the low level to the high level). The changeover switch circuit SWin1a And SW
All out1a are turned off and become non-conductive.

When the changeover control signal t2 changes from the low level to the high level, both of the changeover switch circuits SWin2a and SWout2a are turned on to be in the conductive state.
As a result, the digital display data (for example, 6 bits) boosted by the level shifter circuit 135-2a is sent to the D / A conversion circuit 136a via the changeover switch circuit SWin2a. In the D / A conversion circuit 136a, a plurality of voltages (for example, 64 levels) from the reference voltage generation circuit 138 are output according to the digital display data boosted by the level shifter circuit 135-2a.
One gradation display voltage is selected from the above.

The gradation display voltage thus selected is supplied to the voltage follower 137-2a via the changeover switch circuit SWout2a which is turned on by the changeover control signal t2 and is in a conductive state. The impedance is reduced and the output terminal O2 outputs the source line to the liquid crystal panel.

After a certain time T, the changeover control signal t2 changes from the high level to the low level (at this time, the changeover control signal t3 changes from the low level to the high level.) The changeover switch circuit SWin2a. And SW
Both out2a are turned off and become non-conductive.

When the changeover control signal t3 changes from the low level to the high level, both of the changeover switch circuits SWin3a and SWout3a are turned on to be in the conductive state.
As a result, the digital display data (for example, 6 bits) boosted by the level shifter circuit 135-3a is sent to the D / A conversion circuit 136a via the changeover switch circuit SWin3a. In the D / A conversion circuit 136a, a plurality of voltages (for example, 64 levels) from the reference voltage generation circuit 138 are output according to the digital display data boosted by the level shifter circuit 135-3a.
One gradation display voltage is selected from the above.

The gradation display voltage thus selected is supplied to the voltage follower 137-3a via the changeover switch circuit SWout3a which is turned on by the changeover control signal t3 and is in a conductive state. The impedance is reduced and the output terminal O3 outputs the source line of the liquid crystal panel.

After a certain time T, the changeover control signal t3 changes from the high level to the low level (at this time, the changeover control signal t1 changes from the low level to the high level.) The changeover switch circuit SWin3a. And SW
All out3a are turned off and become non-conductive. When the switching control signal t1 changes from low level to high level,
The operation described above is repeated within one horizontal period.

Here, the time width of the non-conduction time T '(see FIG. 3) is set by setting the stray capacitance of the output stage of the changeover switch circuit SWout1a, the stray capacitance of the input stage of the voltage follower 135-1a, and the interval therebetween. It may be set within a time period in which the voltage level is sufficiently maintained by the stray capacitance of the wiring. On the other hand, the conduction time T is set to a time in which the voltage level is sufficiently stabilized by charging / discharging the pixel capacitance. As described above, by setting the non-conduction time T ′ and the conduction time T, it is determined how many D / A conversion circuits can be shared.

In the case of FIGS. 1 and 3, the gradation display voltage is output from the D / A conversion circuit at the same timing from the N output terminals of the 3N output terminals, and the remaining 2N output terminals are output. The gradation display voltage is held by the floating capacitance. Then, in the circuit block sharing the D / A conversion circuit, the circuits are sequentially selected by time division, and the selection operation is repeated a plurality of times in one horizontal period. The changeover switch circuit may be any analog switch circuit, and can be easily configured by, for example, a MOS transistor or a transmission gate.

An example of the switch switching signal generating circuit 139 is shown in FIG. The switch switching signal generation circuit 139
Can be easily configured by, for example, a shift register circuit configured by a D type flip-flop (DF / F).

In this case, the D type flip-flop 13
9a to 139c are connected in a cascade. In the D type flip-flop 139a, the switching control signal DASW1 is supplied to the data input terminal D, and the output terminal Q is connected to the data input terminal D of the D type flip-flop 139b. The output terminal Q of the D-type flip-flop 139b is connected to the data input terminal D of the D-type flip-flop 139c. The D-type flip-flop 139a-
The switching control signal DASW2 is supplied to each clock input terminal CK of 139c.

With the above structure, the switching control signals t1 to t3 are output from the output terminals Q of the D type flip-flops 139a to 139c, respectively. FIG. 5 shows the waveform of the main part in the case of the configuration of FIG.

As the D / A conversion circuit, the same structure as the conventional one can be used. The sharing of the D / A conversion circuit according to the present invention can reduce the size of a drive circuit in a display device that performs gradation display by selecting from a plurality of voltage levels, such as a plasma display device or an electroluminescence display device. It is valid. In particular, it is effective in coping with the future increase in the number of output terminals due to the increase in screen size and miniaturization, and the increase in the circuit scale of the D / A conversion unit due to multi-gradation display accompanying high quality.

Here, an example in which the above switching control signals t1 to t3 are prevented from overlapping each other will be described with reference to FIG.

In order to prevent the switching control signals t1 to t3 from overlapping with each other (see FIG. 6) (at the same time, not to be at a high level), the switch switching signal generating circuit 139 is, for example, as shown in FIG. It is necessary to have the circuit configuration shown. It should be noted that members having the same functions as those in FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the circuit configuration of FIG. 7, instead of the signals at the output terminals Q of the D type flip-flops 139a to 139c being directly output as the switching control signals t1 to t3, respectively, the D type flip flops 139a to 139a.
The signal of each output terminal Q of 39c is overlap prevention circuit 139.
The circuit configuration is different from that of FIG. 4 in that the switching control signals t1 to t3 are respectively output via d to 139f.

The overlap prevention circuits 139d to 139f described above.
Are the D-type flip-flops 139a to 139c.
Signal t1 "to t3" at the output terminal Q of the input terminal Q, and is obtained, for example, through a plurality (even number) of inverters (the input terminals of NAND gates may be connected to each other). t1 ′ to t3 ′ and the signal t1 ″
.About.t3 "are output as switching control signals t1 to t3 respectively. FIG. 8 shows the signal waveform of the main part of FIG.

The overlapping prevention circuits 139d-1 to 139d-1
In 39f, the case where the signals t1 ′ to t3 ′ are obtained through a plurality of (even number) inverters has been described, but the present invention is not limited to this, and the signals t1 ″ to t3 ″ are not limited to this. Any configuration may be used as long as it is delayed without being inverted. For example, a buffer (for example, one in which the input terminals of AND gates are cascade-connected to each other (in this case, the number of cascades may be even or odd), etc., or an RC delay circuit may be used.

By using the switching control signals t1 to t3 shown in FIG. 6, a time period during which the switching control is non-conducting between the adjacent switching switch circuits is secured (two switching switch circuits at the same time). Is not selected), it is possible to surely prevent the current from flowing back between the changeover switch circuits temporally adjacent to each other when the changeover switch circuit is changed over, and surely reduce the changeover noise. it can.

A level shifter circuit 135 in an example of a block diagram of the source driver 92, a D / A converter (digital / analog converter) 136 including a switch circuit,
Another more detailed configuration example of the output circuit 137 (low impedance conversion circuit, here, voltage follower circuit) will be described below with reference to FIG.

In FIG. 9, members having the same functions as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. Further, although the configuration example of FIG. 9 illustrates the case where the output terminals of the three voltage follower circuits are connected to each other, the present invention is not limited to this, and four or more voltage follower circuits. The output terminals may be connected to each other.

One source driver IC (one D / A
D / A conversion circuits 136a, 13
, 136N (only the D / A conversion circuit 136a is shown in FIG. 1). here,
For convenience of description, the D / A conversion circuit 136a will be described as an example, but the other D / A conversion circuits 136b to 136N have the same configuration, and therefore the same operation is performed.

A changeover switch circuit SWin1a is provided between the input side of the D / A conversion circuit 136a and the level shifter circuit 135-1a, and the D / A conversion circuit 13 is provided.
A changeover switch circuit SWin2a is provided between the input side of 6a and the level shifter circuit 135-2a.
Input side of the / A conversion circuit 136a and the level shifter circuit 13
A changeover switch circuit SWin3a is provided between the switch 5in and 5-3a.

Further, between the output side of the D / A conversion circuit 136a and the voltage follower circuit 137-1a,
A changeover switch circuit SWout1a is provided, and the D /
A changeover switch circuit SWout is provided between the output side of the A conversion circuit 136a and the voltage follower circuit 137-2a.
2a is provided, and a changeover switch circuit SWout3a is provided between the output side of the D / A conversion circuit 136a and the voltage follower circuit 137-3a.

A pair of changeover switch circuits SWin1a
The changeover switch circuit SWout1a is a circuit related to generation of a grayscale display voltage output from the output terminal OUTa, and the changeover control signal t1 is supplied to its control terminal. The changeover switch circuit SWin1a and the changeover switch circuit SWout1a are connected to the changeover control signal t1.
ON / OFF is controlled based on

A pair of changeover switch circuits SWin2a
The changeover switch circuit SWout2a is a circuit relating to generation of a gradation display voltage output from the output terminal OUTa, and the changeover control signal t2 is supplied to its control terminal. The changeover switch circuit SWin2a and the changeover switch circuit SWout2a are connected to the changeover control signal t2.
ON / OFF is controlled based on

A pair of the changeover switch circuits SWin3a
The changeover switch circuit SWout3a is a circuit relating to generation of a gradation display voltage output from the output terminal OUTa, and the changeover control signal t3 is supplied to its control terminal. The changeover switch circuit SWin3a and the changeover switch circuit SWout3a have the changeover control signal t3.
ON / OFF is controlled based on

Although not shown in FIG. 9, the input-side changeover switch circuits SWin1a to SWin3a are provided in accordance with digital display data (bits), for example, 64 bits for 6-bit display. In the case of digital display data, each changeover switch circuit is provided with 6 circuits for each bit.

Voltage follower circuits 137-1a to 1
The output terminals of 37-3a are connected to each other and to the shared output terminal OUTa, and the output signals of the voltage follower circuits 137-1a to 137-3a are sent to the switch circuit 200 via the output terminal OUTa. To be

The switch circuit 200 is formed on a liquid crystal panel (display device) and includes switches 200a to 200a.
It is composed of 200c. These switches 200
a to 200c are time-divisionally switched based on the switching control signals t1 to t3 (the switching control signals shown in FIG. 3 or 6). That is, the switch 20
0a to 200c are the changeover switch circuits SWin1a.
~ When SWin3a is on, it turns on respectively,
When it is off, it is turned off.

In other words, the switch 200a, the pair of changeover switch circuits SWin1a and the changeover switch circuit S.
Wout1a is turned on or off at the same time based on the switching control signal t1. The switch 200b and the pair of changeover switch circuits SWin2a and SWout2a are based on the changeover control signal t2.
Turn on or off at the same time. Switch 200c
And the pair of changeover switch circuits SWin3a and SWout3a are simultaneously turned on or off based on the changeover control signal t3.

According to the configuration of FIG. 9, the number of liquid crystal drive voltage output terminals can be surely reduced (can be reduced to 1/3 of the case of FIG. 1) as compared with the configuration of FIG. As a result, the liquid crystal panel can be made smaller and the pitch can be made finer for higher definition, and high reliability can be obtained.

[0133]

As described above, the driving device for a display device according to the present invention has a plurality of input side switching means for sending the display data to the gradation display voltage selecting means and the gradation display voltage. A plurality of output side switching means to be sent to the low impedance conversion means, a pair of input side switching means and output side switching means corresponding to each output terminal of the display device are sequentially selected in time division,
It is characterized by further comprising a switching control means for repeating these selections during one horizontal period.

According to the above invention, when the display data is input, one of the plurality of gradation display voltages is selected by the gradation display voltage selecting means in accordance with the display data. The gradation display voltage selected in this way is sent to the low impedance conversion means, where it is made into a low impedance, and then output to each terminal of the display device. As a result, the display device displays the display data.

At this time, the pair of input side switching means and output side switching means corresponding to the respective output terminals of the display device are sequentially selected in a time division manner by the switching control means provided in the drive device. One of a plurality of gradation display voltages is selected by the gradation display voltage selection means in accordance with the display data input via the selected input side switching means,
It is sent to the low impedance conversion means via the output side switching means selected at the same time as the input side switching means. The selection relating to the pair of input side switching means and output side switching means is repeated during one horizontal period.

As described above, since one gradation display voltage selecting means is shared by a plurality of pairs of switching means each including a plurality of input side switching means and a plurality of output side switching means, the display device is further improved. It is possible to cope with the increase in the number of terminals (increase in the number of gradation display voltage selection means) due to the demand for larger size and higher definition and the increase in the number of elements in the gradation display voltage selection means accompanying multi-gradation display. In addition, it is possible to achieve the effect that it is possible to further reduce the chip area and reduce the cost accordingly.

It is preferable that the switching control means is composed of a shift register circuit, and the input side switching means and the output side switching means are selected in a time division manner based on the output signal of each stage of the shift register circuit. In this case, the switching control means can be realized with a simple structure.

The switching control means selects the input side switching means and the output side switching means in a time division manner so that the two input side switching means and the two output side switching means are not selected at the same time. Is preferred.

In this case, the switching control means simultaneously operates two switches.
Switching control is performed so that one input side switching means and two output side switching means are not selected at the same time. This gives 2
It is possible to reliably prevent current from flowing back between the switching means when switching is performed between the input side switching means and between the two output side switching means, and to reliably reduce switching noise. It also has the effect of being able to.

The switching control means comprises a shift register circuit and an overlap prevention circuit. This overlap prevention circuit is
An AND operation of the output signal of each stage of the shift register circuit and a delayed version of this output signal is performed, and the input side switching means and the output side switching means can be selected in time division based on the operation result. preferable. In this case, the switching control means can be realized with a simple structure.

The output signal of the low impedance conversion means is sent to the switch means provided on the display device through a common output terminal, and the switch means corresponds to each output terminal of the display device. It is preferable that a plurality of switch circuits are provided, and the opening and closing of these switch circuits are sequentially controlled in a time division manner in synchronization with the pair of corresponding input side switching means and output side switching means.

In this case, a pair of input side switching means and output side switching means and a switch circuit corresponding to each output terminal of the display device are selected in synchronization. Accordingly, one output terminal in the drive device is shared by the plurality of low impedance conversion means, so that the number of output terminals in the drive device can be reduced more reliably. Therefore, it becomes possible to narrow the pitch for further enlargement and high definition of the display device,
It also has an effect that high reliability can be obtained.

The display device module is preferably constructed by using the drive device for the display device. This allows
The present invention has an effect that it is possible to realize a display device module having a narrow pitch and high reliability with respect to an increase in size and definition of a display device.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a more detailed configuration example of a level shifter circuit of the source driver, a D / A conversion unit including a switch circuit, and an output circuit.

FIG. 2 is a block diagram showing a configuration example of a source driver according to the present invention.

FIG. 3 is a timing chart of the switching control signal of FIG.

FIG. 4 is a circuit diagram showing a configuration example of a switch switching signal generation circuit according to the present invention.

5 is a timing chart of a main part of the switch switching signal generation circuit shown in FIG.

FIG. 6 is a timing chart of another switching control signal.

FIG. 7 is a circuit diagram showing another configuration example of the switch switching signal generation circuit according to the present invention.

8 is a timing chart of a main part of the switch switching signal generation circuit shown in FIG.

FIG. 9 is a block diagram showing another configuration example of the source driver according to the present invention.

FIG. 10 is a block diagram illustrating both the present invention and the prior art, and is a block diagram showing a configuration example of an active matrix liquid crystal display device.

11 is a circuit diagram showing a configuration example of the liquid crystal panel of FIG.

FIG. 12 is a waveform diagram showing an example of a liquid crystal drive waveform of the liquid crystal panel.

FIG. 13 is a waveform diagram showing another example of the liquid crystal drive waveform of the liquid crystal panel.

FIG. 14 is a block diagram showing a configuration example of a conventional source driver.

FIG. 15 is a circuit diagram showing a configuration example of a conventional reference voltage generating circuit.

FIG. 16 is an explanatory diagram showing a configuration example of a conventional selection circuit.

FIG. 17 is an explanatory diagram showing an example of a conventional gradation voltage characteristic.

FIG. 18 is a block diagram showing a configuration example of a drive circuit of a conventional display device.

[Explanation of symbols]

92 source driver 135 level shifter circuit 136 D / A conversion section (gradation display voltage selection means) 137 output circuit (low impedance conversion means) SWin1a to SWin3a changeover switch circuit (input side changeover means) SWout1a to SWout3a changeover switch circuit (output Side switching means) 139 Switch switching signal generation circuit (switching control means)

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 641 G09G 3/20 641C F term (reference) 2H093 NA53 NC03 NC22 NC23 NC24 NC26 NC27 NC32 ND06 ND42 5C006 AA16 AF42 AF83 BB16 BC12 BC20 BF03 BF04 BF06 BF07 BF11 BF24 BF25 BF43 BF46 5C080 AA10 BB05 DD22 DD26 DD27 EE29 FF11 JJ02 JJ03 JJ04

Claims (6)

[Claims] 1. A gradation display voltage selecting means for inputting display data and selecting one from a plurality of gradation display voltages according to the display data, and lowering the impedance of the selected gradation display voltage. A drive device for a display device, comprising: a low impedance conversion means for outputting to each terminal of the display device; a plurality of input side switching means for transmitting the display data to the gradation display voltage selection means; A plurality of output side switching means for sending a voltage to the low impedance conversion means,
It further comprises a switching control means for sequentially selecting a pair of input side switching means and output side switching means corresponding to each output terminal of the display device in a time division manner and repeating these selections for one horizontal period. Drive device for display device. 2. The switching control means selects the input side switching means and the output side switching means in a time division manner so that two input side switching means and two output side switching means are not selected at the same time. The drive device for the display device according to claim 1, wherein 3. The switching control means comprises a shift register circuit, and selects the input side switching means and the output side switching means in a time division manner based on the output signal of each stage of the shift register circuit. The drive device for the display device according to claim 1. 4. The switching control means comprises a shift register circuit and an overlap prevention circuit, and the overlap prevention circuit comprises:
An AND operation of the output signal of each stage of the shift register circuit and a delayed version of this output signal is performed, and the input side switching means and the output side switching means are selected in time division based on the operation result. The drive device for a display device according to claim 2. 5. An output signal of the low impedance conversion means is sent to a switch means provided on the display device through a common output terminal, and the switch means corresponds to each output terminal of the display device. A plurality of switch circuits provided in the same manner, and these switch circuits are sequentially opened and closed in a time division manner in synchronization with the corresponding pair of input side switching means and output side switching means. Claim 1,
The drive device for the display device according to 2, 3, or 4. 6. A display device module using the drive device for a display device according to claim 1, 2, 3, 4, or 5. Description: