JP2003124463A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can improve element characteristics. SOLUTION: The semiconductor device is provided with a substrate 21 having a projecting semiconductor element region 23 and a gate electrode 26 which is formed on the upper and lateral side of the element region 23 with gate insulating films 25a and 25b interlaid. In the element region 23, a source region and a drain region are provided separately from each other so that a channel region is formed opposite to the gate electrode 26. At least one selected from the group consisting of the film thickness of the gate insulating films 25a and 25b, the material of the gate insulating films and the material of the gate electrode is different between the upper side of the element region 23 and the lateral side thereof.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular it relates to an improved structure of a MOS transistor.

[0002]

2. Description of the Related Art Conventionally, in a MOS integrated circuit, particularly a MOS type transistor, miniaturization of elements has been attempted not only to achieve a high degree of integration, but also to speed up circuit operation and reduce power consumption. FIG. 22 shows a cross section of a conventional MOS transistor having a planar structure. In this MOS transistor, as shown in FIG. 22, a gate electrode 103 is formed on a semiconductor substrate 101 via a gate insulating film 102, and a field oxide film 104 separates elements.

In such a structure, problems have arisen as the device is miniaturized. Typical factors are the film thickness of the gate insulating film 102 and the impurity concentration in the semiconductor substrate 101. Gate insulating film 10
The film thickness of 2 has become thinner with the miniaturization of the element, but when the film thickness is 4 nm or less, a direct tunneling phenomenon occurs, and the gate current is changed to the semiconductor substrate 101.
Therefore, there is a problem that the circuit operation is not stably performed.

Regarding the impurity concentration, it has become higher with the miniaturization of the element, but the substrate concentration is 10
There is a problem that a leak current due to tunneling flows between the source / drain diffusion layer and the semiconductor substrate 101 from the vicinity of more than ¹⁸ cm ⁻³ . Therefore, it is difficult to miniaturize the conventional MOS transistor having a planar structure to a gate length of 0.1 μm or less due to the thickness of the gate insulating film, the impurity concentration of the semiconductor substrate, and the short channel effect. Conceivable.

In consideration of the above problems, a MOS transistor having a structure shown in FIGS. 23A and 23B has been proposed in order to further miniaturize the device (for example, Japanese Patent Laid-Open No. 2000-242242). Japanese Unexamined Patent Publication No. 64-42176, JP-A-6-6
4-27270). In this MOS transistor, a convex portion 105a is formed by forming a groove serving as an element isolation region in the semiconductor substrate 5, and a polycrystalline polysilicon film or a direct silicon oxide film 110 is formed in the groove via an insulating film or the like. The gate electrode 106 is formed via the gate insulating film 109 formed on the upper and side portions of the buried and convex portion 105a, and the source region 107 and the drain region 108 are formed using the gate electrode 106 as a mask. . The MOS transistor having such a configuration (hereinafter, abbreviated as a convex transistor) has good cutoff characteristics.

Further, in this convex transistor,
By setting the width of the convex portion 105a so that the convex portion 105a in the element region is completely depleted by the depletion layer extending from the gate electrode, the influence on the gate electrode with respect to the channel potential can be increased, and as a result, the drain can be increased. The short channel effect can be suppressed by suppressing the influence of the electrodes. Further, in this convex transistor, since the current flows on the surface of the convex portion 105a, the current on the side surface can also be used, so that a larger current than that of the MOS transistor having a normal planar structure can be caused to flow. .

[0007]

However, the conventional convex transistor has the following problems. That is, firstly, the channel width is dependent on the determination of the threshold value. Therefore, the degree of freedom in threshold control is small. In particular, when the channel width is wide, a hump occurs in the characteristic diagram showing the relationship between the current and the voltage because the parasitic transistor on the side operates.

Secondly, in the region of the convex portion 105a which is not covered with the gate electrode 106, that is, in the region deeper than the region of the convex portion surrounded by the gate electrode 106, the control cannot be performed by the gate electrode 106, so that the source A short channel effect due to a punch through phenomenon occurs between the region 107 and the drain region 108. Therefore, it is difficult to reduce the gate length.

Thirdly, in the region deeper than the region of the convex portion surrounded by the gate electrode 106, when the drain voltage is increased, the lines of electric force extending from the drain region 108 are directed toward the source region 107, Gate electrode 10
6 alone cannot sufficiently suppress the fluctuation of the channel potential due to the drain voltage. In particular, in the case of a short channel, the element characteristics are not so improved because the width L of the gate electrode 106 in the direction of the source region 107-drain region 108 is short.

The present invention has been made in view of the above points, and an object thereof is to provide a semiconductor device capable of suppressing the short channel effect due to the punch-through phenomenon. Another object of the present invention is to provide a semiconductor device capable of improving element characteristics.

[0011]

The first invention of the present invention is as follows:
A substrate having a convex semiconductor element region, a gate electrode formed on an upper surface and a side surface of the element region through a gate insulating film, and a channel region formed on the upper surface of the element region with the gate electrode interposed therebetween. A source region and a drain region of the first conductivity type, which are formed inside the convex portion and below the channel region, and have a concentration higher than that of the channel region. A semiconductor device having a high-concentration impurity region containing a second conductivity type impurity is provided.

According to a second aspect of the present invention, a substrate having a convex semiconductor element region, a gate electrode formed on an upper surface and a side surface of the element region via a gate insulating film, and the gate electrode sandwiched therebetween. A source region and a drain region provided so as to form a channel region on the upper surface of the element region, and characteristics of a transistor formed on the upper surface of the element region and a transistor formed on the side surface of the element region. Provided is a semiconductor device having different characteristics. For example, a second invention of the present invention comprises a substrate having a convex semiconductor element region and a gate electrode formed on a top surface and a side surface of the element region via a gate insulating film, and Is provided with a source region and a drain region spaced apart from each other so that a channel region is formed facing the gate electrode, and the gate insulation is provided between an upper surface of the element region and a side surface of the element region. Film thickness,
There is provided a semiconductor device characterized in that at least one selected from the group consisting of a material of a gate insulating film and a material of a gate electrode is different from each other.

According to a third aspect of the present invention, a substrate having a semiconductor element region having a convex shape, a gate electrode formed on a top surface and a side surface of the element region via a gate insulating film, and the gate electrode sandwiched therebetween. A source region and a drain region of a first conductivity type provided on an upper surface and a side surface of the element region, and the source region and the drain region formed on an upper surface and a side surface of the element region are mutually formed inside the element region. Provided is a semiconductor device which is not in contact.

According to a fourth aspect of the present invention, a substrate having a convex semiconductor element region, a gate electrode formed on an upper surface and a side surface of the element region via a gate insulating film, and the gate electrode sandwiched therebetween. A source region and a drain region provided so as to form a channel region on the upper surface of the device region, and an electrode held at a constant potential via an insulating film is formed on a side portion of the drain region, Provided is a semiconductor device characterized in that a width W of a convex element region satisfies the following expression (I).

W ≦ 2√2 (ε _S · φ _F / q · N _sub ) ^1/2 (I) (where, q is an electronic charge (coulomb), φ _F is the Fermi level (eV of the semiconductor substrate) ), Ε _S is the dielectric constant (farads / cm) of the semiconductor substrate, and N _sub is the impurity concentration (cm ⁻³ ) of the semiconductor substrate.) A fifth aspect of the present invention is a semiconductor element region having a convex shape. A substrate having; a gate electrode formed on an upper surface and a side surface of the element region through a gate insulating film; a source region provided so as to form a channel region on the upper surface of the element region with the gate electrode sandwiched; A semiconductor device comprising: a drain region; and an electrode formed to cover a side portion of the drain region and capable of being set to the same potential as the gate electrode. For example, a fifth invention of the present invention is a substrate having a semiconductor element region having a convex shape,
A gate electrode formed on a top surface and a side surface of the device region via a gate insulating film, and a source region and a drain region so that a channel region is formed in the device region so as to face the gate electrode. Are spaced apart from each other, and the gate electrode has a top surface and a side surface of a first portion of the element region that is interposed between the source region and the drain region and a second portion of the device region where the drain region is provided. Provided is a semiconductor device, which is formed so as to cover a side surface.

According to a sixth aspect of the present invention, a substrate having a convex semiconductor element region, a gate electrode formed on a top surface and a side surface of the element region via a gate insulating film, and the element region are covered. The device further includes an insulating film having a contact hole, and a pair of contact wirings that fill the contact hole and are in contact with the device region. A channel region is formed in the device region so as to face the gate electrode. Source region and drain region are spaced apart from each other and are in contact with the pair of contact wirings, respectively, and at least one of the pair of contact wirings is part of an upper surface and part of a side surface of the element region. And the thickness of the source region or the drain region in contact with the contact wiring is not in contact with the contact wiring. To provide a semiconductor device, characterized in that thicker at a position in contact with the contact wire as compared to the location.

According to a seventh aspect of the present invention, a substrate having a convex semiconductor element region, a gate electrode formed on a top surface and a side surface of the element region through a gate insulating film, and the element region are covered. The device further includes an insulating film having a contact hole, and a pair of contact wirings that fill the contact hole and are in contact with the device region. A channel region is formed in the device region so as to face the gate electrode. As described above, the source region and the drain region are provided apart from each other and in contact with the pair of contact wirings, respectively, and the diameter of the contact portion of each of the pair of contact wirings with the element region is equal to that of the element region. Provided is a semiconductor device having a width larger than that of an upper surface.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, a semiconductor substrate is used.
Is a silicon substrate or a semiconductor such as a silicon film on the insulating layer.
SOI (Silicon On Insulator) substrate with body film
Can be used. As the material of the gate insulating film,
SiO₂Etc. can be used. With the material of the gate electrode
Then, polysilicon, molybdenum, tungsten, M
oSi ₂, WSi₂, TiSi₂Can be used
It Further, as the material of the element isolation film, CVD-SiO
₂, Polysilicon, boron phosphorus glass (BPSG), etc.
Can be used.

In the first and third aspects of the present invention,
The source and drain diffusion layer regions are formed by doping the top and sides of the convex device region with impurities. In this case, the source and drain diffusion layer regions formed by the impurities introduced from the side of the convex element region are
The source and drain diffusion layer regions formed by the impurities introduced from above the convex element region are connected without directly contacting each other inside the convex element region. Such a structure, that is, the structure in which the source and drain diffusion layer regions are formed on the upper surface and the side surface of the convex element region is equivalent to the structure in which the shallow diffusion layer is formed in the planar transistor.

In the first and third aspects of the invention, as a method for doping impurities into the convex element region, an ion implantation method, a vapor phase diffusion method, an ion implantation method and a solid phase from obliquely above the convex element region are used. A method such as a combination with a diffusion method can be used. The conditions of these methods need to be set appropriately.

In the first and third aspects of the invention, the high concentration impurity region is formed inside the convex portion and below the channel region. In addition, the high concentration impurity region is
It is preferably formed in the element region below the gate electrode. The presence of the high-concentration impurity region at this position can suppress the depletion layer extending from the drain region under the gate electrode to the channel region, and can realize complete depletion of the channel portion of the convex element region. . Thereby, punch-through under the gate electrode can be prevented.

According to the first and third aspects, since the source and drain diffusion layer regions can be formed from the upper and side portions of the convex element region, the channel width can be increased while the effective element channel width is increased. A diffusion layer can be formed in a region shallow from the surface. As a result, it is possible to improve the punch-through breakdown voltage in the central portion of the channel region where the potential is difficult to control by the gate electrode.

Further, according to the first and third inventions, a high-concentration impurity region containing an impurity of a conductivity type opposite to that of the source and drain diffusion layers at a concentration higher than that of the channel surface is formed in the central portion of the channel region. Therefore, the depletion layer extending from the drain electrode to the channel region can be suppressed in a relatively deep region that is difficult to be controlled by the gate electrode, and thus the short channel effect can be suppressed. Further, by appropriately selecting the type and amount of impurities to be introduced into the portion in contact with the source / drain diffusion layer region and the channel region in the central portion of the channel, an increase in the junction capacitance between the diffusion layer and the substrate is prevented. be able to.

In the second aspect of the present invention, the characteristics of the transistor mean a threshold value, a transconductance and the like. In order to make the characteristics different between the transistor formed on the upper surface of the element region and the transistor formed on the side surface of the element region, the film thickness of the gate insulating film, the material of the gate insulating film, And at least one selected from the group consisting of materials of the gate electrode are set to be different on the upper surface and the side surface of the element region.

The second invention of the present invention is characterized in that the characteristics of the transistor formed on the upper surface of the element region and the characteristics of the transistor formed on the side surface of the element region are different. A transistor formed on the upper surface of the element region,
By changing the characteristics of the transistor formed on the side surface of the element region, specifically, on the corner portion, the following effect is exerted on the entire transistor.

The gate electrode formed from the upper surface to the side surface of the element region exerts a relatively large electric field at the intersection of the upper surface and the side surface, that is, the corner portion. As a result, a depletion layer having a larger extension than the flat upper surface is formed in the corner portion of the element region. When the depletion layers extending from the respective corners in the width direction of the channel region overlap each other, the depth of the depletion layer at the center of the channel region in the width direction of the gate electrode is such that the gate electrode is provided only on the upper surface of the element region. If you go deeper. In such a state, the transistor characteristics are dominated by the transistors formed in the corners.

In addition, since the transistor formed in the corner portion has a larger control of the gate electrode and the electric field in the channel portion is stronger than the transistor formed in the flat portion (upper surface), the influence of the semiconductor substrate bias is exerted. It becomes difficult to appear. Therefore, when depletion progresses and the depletion layers extending from the side surface come close to each other, the change in the electric field in the channel region with respect to the change in the gate voltage becomes large, so that good cutoff characteristics can be obtained. The element characteristics greatly change depending on the length of the depletion layer extending from the corner and the distance from the depletion layer extending from other corners.

Based on such an operating principle, by separately controlling the controlling force of the gate electrode at the corner portion and the flat portion (upper surface), the element characteristic in which both transistor characteristics are combined, so-called hump characteristic is obtained. A stable circuit operation can be performed without generating.

In the fourth and fifth aspects of the present invention, an oxide film or the like can be used as the insulating film formed on the side portion of the drain region. Moreover, polysilicon or the like can be used as the material of the electrode held at a constant potential.

In the fourth and fifth inventions, it is preferable that the electrode held at a constant potential is electrically connected to the gate electrode. In the fourth and fifth aspects of the present invention, an electrode held at a constant potential is formed on a side portion of the drain region via an insulating film, and the width W of the convex element region is W ≦ 2√2.
(Ε _S · φ _F / q · N _sub ) ^1/2 (where q is the electronic charge (coulomb), φ _F is the Fermi level (eV) of the semiconductor substrate,
ε _S is the dielectric constant (farads / cm) of the semiconductor substrate, and N _sub is the impurity concentration (cm ⁻³ ) of the semiconductor substrate. )
It is characterized by satisfying.

By setting the width W of the element region so as to satisfy the above expression, all the convex portions between the electrodes held at a constant potential are depleted. In addition, since the electrode that shields the lines of electric force is formed on the side of the drain region,
The lines of electric force extending from the drain region do not extend in the direction of the source region, and terminate at almost the side electrodes. As a result, the decrease in the potential of the channel region due to the drain potential is suppressed,
The short channel effect can be effectively suppressed.

In the fourth and fifth inventions, a substrate having a convex semiconductor element region, a gate electrode formed on a top surface and a side surface of the element region through a gate insulating film, and the gate electrode A semiconductor including a source region and a drain region provided on the upper surface of the device region with a gap between them, and an electrode that is formed so as to cover a side portion of the drain region and can be set to the same potential as the potential of the gate electrode. Provide a device.

Also in this embodiment, the lines of electric force extending from the drain region can be terminated by the side electrodes, and the short channel effect can be suppressed.

Embodiments of the present invention will be specifically described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a diagram for explaining a manufacturing process of a semiconductor device according to a first invention of the present invention. First, as shown in FIG. 1A, a silicon oxide film 2 having a thickness of 1 is formed on a silicon substrate 1 by, for example, a thermal oxidation method.
The thickness is about 0 nm. Next, the polysilicon film 3 is formed to a thickness of about 200 nm by using the chemical vapor deposition method. Then, a silicon oxide film 4 having a thickness of about 200 nm is formed thereon by using the chemical vapor deposition method. Further, a resist film 5 is formed thereon and patterned by, for example, a photolithography method to form an element isolation region having a desired shape.

Next, the silicon oxide film 4 and the polysilicon film 3 are sequentially etched using the resist film 5 as a mask by anisotropic etching, for example, reactive ion etching (RIE), to form the opening 6. Processed and resist film 5
Peel off. After that, as shown in FIG. 1B, the silicon oxide film 2 in the opening 6 is removed by an NH ₄ F solution or the like. Next, using the silicon oxide film 4 as a mask, RI
An element isolation trench 7 to be an element isolation region is formed to a depth of about 500 nm by using an anisotropic etching method such as E.

Next, after removing the silicon oxide film 4 with an NH ₄ F solution or the like, the silicon oxide film 4 is removed by a thermal oxidation method for the purpose of removing defects and the like generated when the silicon substrate 1 is etched. The film 8 is formed with a thickness of about 10 nm.

Next, as shown in FIG.
By using a phase growth method or the like, for example, a filling material is formed in the element isolation trench 7.
SiO₂ 9 is deposited on the order of 1 μm. Then, the filling material S
iO ₂ 9 is a reactive ion etching method or CMP (Chem
ical mechanical polishing)
Etch back until the surface of the silicon film 3 is exposed,
To substantiate. Then, the exposed polysilicon film 3 is compared, for example.
For example, peel using a method such as CDE (Chemical Dry Etching).
Let go. Then, as shown in FIG._FourF melting
The surface of the element isolation region 9 is chamfered by etching with a liquid or the like.
For example, about 300 nm recedes from the surface of the flannel formation region.
To form the convex silicon portion 10 to be the channel region.
It

Next, as shown in the plan view of FIG.
A thermal oxide film 11 having a thickness of, for example, 10 nm is formed on the surface of the convex silicon portion 10 by a thermal oxidation method or the like, and then a resist film 12 is applied on the element channel region and patterned into a desired shape by, for example, a photolithography method.

Next, using the resist film as a mask, impurities of the same conductivity type as the substrate are doped by, for example, an ion implantation method, and the high-concentration impurity region 13 as shown in FIG. To form.

After that, the resist film is removed and, for example, NH
The oxide film on the surface of the convex silicon portion is peeled off with a ₄ F solution or the like, and the thermal oxide film 14 having a thickness of 6 nm, for example, is formed again on the surface of the convex silicon portion by a thermal oxidation method or the like to form a gate electrode. A polysilicon film 15 doped with phosphorus is formed with a thickness of about 200 nm. Then, a resist film is applied thereon and patterned into a desired gate electrode pattern by, for example, a photolithography method. Then, the polysilicon film is etched by using, for example, an anisotropic etching method to form a gate electrode as shown in FIG.

Next, as shown in FIG. 3B, using the gate electrode as a mask, impurities are ion-implanted from diagonally above the element formation region in a self-aligned manner, and as shown in FIG. The electrode 16 is formed. In this case, the diffusion layer region due to the impurities introduced from the side of the convex silicon does not come into contact with the inside of the convex silicon even after a thermal process such as the subsequent activation process, A structure is formed in contact with the introduced diffusion layer region. This structure is formed by doping conditions of impurities introduced from the convex silicon side portion and the upper surface, for example, ion implantation conditions and diffusion conditions by the subsequent thermal process.
The depth of the diffusion layer is determined.

After that, a silicon oxide film is deposited on the entire surface by a normal process by a CVD method, contact holes reaching the source electrode, the drain electrode, and the gate electrode are formed in the silicon oxide film, and an Al wiring is arranged to dispose the device. To complete.

FIG. 6 shows an element manufactured as described above (in which about 1 × 10 ¹⁸ cm ^{−3 of the} same conductivity type as the substrate is introduced between the source and drain electrodes inside the channel).
3 shows a change in threshold voltage with respect to the channel length of the. For comparison, data of an element in which an impurity of the same conductivity type as that of the substrate is introduced between the source and drain electrodes inside the channel at about 1 × 10 ¹⁶ cm ⁻³ is also shown in FIG. As is clear from FIG. 6, the element according to the first aspect of the present invention can suppress the short channel effect more effectively.

Further, FIG. 7 shows a channel of the device manufactured as described above (an impurity of the same conductivity type as that of the substrate is introduced at about 1 × 10 ¹⁸ cm ⁻³ between the source and drain electrodes inside the channel). The change of the subthreshold coefficient with respect to the length is shown. Also here, for comparison, data of an element in which an impurity of the same conductivity type as that of the substrate is introduced at about 1 × 10 ¹⁶ cm ⁻³ between the source and drain electrodes inside the channel is also shown in FIG. 7. As is clear from FIG. 7, the element according to the first aspect of the present invention can effectively suppress the deterioration of the subthreshold coefficient due to punch through.

(Embodiment 2) FIG. 8A is a sectional view showing an embodiment of a semiconductor device (MOS transistor) according to the second invention of the present invention. In the figure, 21 indicates a semiconductor substrate. In this embodiment, a p-type silicon substrate is used as the semiconductor substrate 21. Concavities and convexities are formed on the semiconductor substrate 21, the concave portion 22 corresponds to the element isolation region, and the convex portion 23 corresponds to the element region. The protrusion 23 may be formed on the semiconductor substrate 21 by epitaxial growth or may be formed by an etching method. In this embodiment, the convex portion 23
Has a height of 0.6 μm and a width of 0.3 μm. Further, the p-type impurity concentration of the convex portion 23 is about 5 × 10 ¹⁵ cm ⁻³ . Note that the source region and the drain region, which are n-type impurity diffusion layers, are formed in the protrusion 23 at a depth of 0.05 μm from the upper surface of the protrusion 23.

An insulating film 24 is formed on the recess 22 so as to be filled with SiO ₂ having a thickness of 0.3 μm. A silicon oxide film is formed as the gate insulating film 25 on the upper surface and the side surface of the convex portion 23. The thickness of the gate insulating film 25 is 12 nm on the upper surface 25a and 6 nm on the side surface 25b. Insulating film 24 and gate insulating film 2
On the layer 5, a gate electrode 26 is formed of phosphorus-doped polysilicon with a thickness of 0.2 μm. In this way, the semiconductor device (element) according to the second aspect of the present invention is configured.

FIG. 8B shows the expansion of the depletion region generated in the convex portion 23 when a positive potential is applied to the gate electrode 26 of the transistor shown in FIG. 8A. Figure 8
As can be seen from (B), the extension I of the depletion region in the center of the flat portion of the upper surface of the convex portion 23 is smaller than that of the side surface and the corner portion 27. Therefore, the characteristics of this transistor are governed by the characteristics of the transistor in the corner portion 27. further,
When the potential of the gate electrode 26 is increased, the depletion regions from the side surfaces are connected to each other, and the depletion region is less likely to be controlled by the gate electrode 26 formed on the upper surface. Therefore, since the increase of the potential of the gate electrode thereafter is all spent on the formation of the inversion layer, the ratio of the increase of the carriers in the inversion layer with respect to the increase of the gate voltage becomes large, and a good cutoff characteristic can be obtained.

Here, a typical drain current (I) of a MOS transistor formed on a semiconductor substrate having a convex portion
_D) - the gate voltage (V _G) characteristics shown in FIG. FIG. 9 (A)
Shows the characteristics when the gate electrode is formed only on the flat portion on the upper surface of the convex portion. In this case, since the control power of the gate electrode is weak, the threshold value is slightly high and is about 0.7V. In this case, no steep slope of log I _D -V _G characteristics.
This tendency similarly appears even when the transistor formed on the upper surface of the convex portion is dominant. Such a characteristic is observed when the extension of the depletion region from the side surface due to the potential of the gate electrode formed on the side surface of the convex portion is small.

On the other hand, when the control power of the gate electrode at the corner is strong, the drain current-gate voltage characteristic is shown in FIG.
As shown in (B). That is, the threshold is low and the inclination of the log I _D -V _G characteristics is steep. This occurs when the depletion regions extending from the side surface of the convex portion are connected to each other. This is because the subsequent expansion of the depletion region is structurally suppressed, and the carriers in the inversion layer increase as the gate voltage increases. However, such a characteristic occurs only when the width of the gate electrode is relatively small. When the width of the gate electrode is so wide that the depletion regions from the side surfaces are not connected to each other, the drain current-gate voltage characteristic is as shown in FIG. 9C. That is, FIG.
The characteristic curves of (A) and FIG. 9 (B) are overlapped. In this case, a hump may occur on the characteristic curve, which may adversely affect the circuit operation.

In the case of the structure shown in FIG. 8, since the gate insulating film 25b formed on the side surface of the convex portion 23 has a small thickness and the gate electrode formed on the side surface has a strong control force, the corner portion 2
The characteristics of the transistor configured in 7 mainly appear.

Even in the structure shown in FIG. 23, that is, in the structure in which the thickness of the gate insulating film formed on the upper surface and the side surface of the convex portion is equal, the electric field from both the upper and side gate electrodes is applied to the corner portion. Since the concentration is concentrated, the characteristics of the transistor at the relatively corner portion mainly appear, but the tendency becomes more remarkable in the case of the structure shown in FIG. Therefore, in the structure shown in FIG. 8, the characteristics of FIG. 9B are maintained up to the region where the width of the gate electrode is wider and the region where the impurity concentration of the semiconductor substrate is higher. This means that the transistor characteristics can be changed by changing the film thickness of the gate insulating film on the upper surface and the side surface of the convex portion 23. This allows
The margin of circuit design and the margin of threshold setting are expanded.

10 to 12 are sectional views showing another embodiment of the semiconductor device according to the second invention of the present invention. Figure 1
0, the gate insulating film 25a formed on the upper surface of the convex portion 23
Is 6 nm, and the thickness of the gate insulating film 25b formed on the side surface of the convex portion 23 is 12 nm. in this case,
Since the control power of the gate electrode 26 formed on the side surface is weakened, the characteristics of the transistor formed by the corner portion 27 are weakened, and the characteristics of the transistor formed by the upper surface of the convex portion 23 mainly appear. Therefore, the structure shown in FIG. 10 is effective when an element that is not easily affected by the transistor formed in the corner portion 27 is required.

In FIG. 11, as the gate insulating film 28a formed on the upper surface of the convex portion 23, the thickness 1 having a relative dielectric constant of 3.9 is used.
A 2 nm silicon oxide film is used, and a 12 nm-thick silicon nitride film having a relative dielectric constant of 7.5 is used as the gate insulating film 28b formed on the side surface of the convex portion 23. In this case, since the gate insulating film 28b formed on the side surface of the convex portion 23 has a relative dielectric constant about twice that of the gate insulating film 28a formed on the upper surface of the convex portion 23, the characteristics of the transistor formed in the corner portion 27 are improved. Mainly appears, and practically the same result as that of the element having the structure shown in FIG. 8 is obtained. However, compared with the structure shown in FIG. 8, the film thickness of the gate insulating film 28 b formed on the side surface of the convex portion 23 is smaller than that of the gate insulating film 25.
Since it is twice as large as b, the reliability of the gate insulating film is improved. If there is no problem in reliability, the thickness of the gate insulating film 28b formed on the side surface of the convex portion 23 can be reduced to further enhance the characteristics of the transistor formed in the corner portion 27.

In this structure, the gate insulating films 28a and 28a
If the materials of 8b are made different, many modified examples can be considered. For example, the gate insulating film 2 formed on the upper surface of the convex portion 23
By using a silicon nitride film as 8a and a silicon oxide film as the gate insulating film 28b formed on the side surface of the convex portion 23, the characteristics shown in FIG. 9A can be obtained. The materials for the gate insulating films 28a and 28b can be appropriately selected and combined from a silicon oxide film, a silicon nitride film, a tantalum oxide film, a strontium titanate film, a ferroelectric film, or the like. In this case, since the film thickness of the gate insulating films 28a and 28b can be arbitrarily selected, the width of the gate electrode, the threshold value, etc. can be freely defined in the circuit design.

In FIG. 12, phosphorus-doped polysilicon is used as the gate electrode 29a formed on the upper surface of the convex portion 23, and tungsten silicide is used as the gate electrode 29b formed on the side surface of the convex portion 23. In addition, the gate insulating films 20 a and 2 formed on the upper surface and the side surface of the convex portion 23.
The film thicknesses of 0b are both 60 nm.

In this structure, due to the work function difference between the materials of the gate electrodes 29a and 29b formed on the upper surface and the side surface of the convex portion 23, the threshold value of the transistor formed on the side surface of the convex portion 23 is formed on the upper surface of the convex portion 23. 0.4V higher than the threshold of the transistor. Therefore, in this case, the element characteristics are as shown in FIG. 9A in which the characteristics of the transistor formed by the corner portion 27 are weak and the characteristics of the transistor formed by the upper surface of the convex portion 23 are strong. If the material of the gate electrode on the upper surface and the side surface of the convex portion 23 is exchanged, the device characteristics will be as shown in FIG.
As shown in (B).

In this structure, the material of the gate electrode on the upper surface and the side surface of the convex portion 23 may be different, and can be arbitrarily selected and combined from materials such as polysilicon, tungsten silicide, or metal such as tungsten. .

The element shown in FIG. 12 is, for example, as shown in FIG.
It is manufactured according to the steps shown in FIGS. That is, first, a 12 nm-thick silicon oxide film by thermal oxidation is formed as the gate insulating film 30a on the upper surface of the convex portion 23 of the semiconductor substrate 21. Then, a 200 nm-thick polysilicon film doped with phosphorus is formed by the CVD method as the gate electrode 29a on the gate insulating film 30a. Further, a 200 nm thick silicon oxide film 31 is formed by the CVD method.

Next, a resist layer is formed in the element region by photolithography, and the silicon oxide film 3 is formed by RIE using this photoresist pattern as a mask.
Etch 1. Next, as shown in FIG. 13A, after removing the resist layer, a polysilicon film is formed by RIE using the etched silicon oxide film 31 as a mask,
The silicon oxide film formed by thermal oxidation and the semiconductor substrate 21 are etched. The etching depth of the semiconductor substrate 21 is set to 0.6 μm. Since the silicon oxide film formed by thermal oxidation is very thin, it can be processed simultaneously with other polysilicon films and semiconductor substrates without special measures.

Next, as shown in FIG. 13B, a silicon oxide film having a thickness of 10 nm is formed on the surface as a gate insulating film 30b by thermal oxidation. Then, a silicon oxide film 32 having a thickness of 1 μm is formed by the CVD method, and a resist layer 33 for planarization is further formed, and the resist film 33 is flowed by basing. Next, as shown in FIG.
Etching back is performed by a method to leave the silicon oxide film 32 from the bottom of the recess of the semiconductor substrate 11 to a thickness of 0.3 μm. At this time, the silicon oxide film 3 on the polysilicon film
1 is removed at the same time as etch back.

Finally, a 100 nm-thickness tungsten silicide film 34 is formed thereon by a CVD method or a sputtering method, patterned by a photolithography method, and then RIE is performed to form a desired gate electrode pattern. Thus, the device having the structure shown in FIG. 12 is obtained.

Further, the polysilicon film which is the gate electrode 29a is not formed in FIG.
By adding the step of removing the polysilicon film in (C), the thickness of the gate oxide film on the upper surface of the convex portion 23 becomes smaller than that on the side surface of the convex portion 23. Can be produced. Furthermore, FIG.
When the thermal nitriding step is performed instead of the thermal oxidation step of (B), only the gate insulating film formed on the side surface of the convex portion 23 can be the silicon nitride film. Further, the gate insulating film formed on the side surface of the convex portion 23 may be formed by deposition by CVD instead of thermal oxidation. In this case,
In (C), a tantalum oxide film having a thickness of 20 nm is formed on the entire surface.
Can be realized by leaving the tantalum oxide film only on the side surface of the convex portion 23 by the RIE method. As described above, by forming at least the gate insulating film on the upper surface of the convex portion 23 first, a desired element structure can be realized by a simple process.

In the second aspect of the present invention, the effect is obtained by changing at least one of the thickness of the gate insulating film, the material of the gate insulating film, and the material of the gate electrode on the upper surface and the side surface of the convex portion. Since it is exhibited, the effect of the present invention is exhibited even if two or more of the above are applied in combination. Further, in one LSI chip, elements in which the film thickness of the gate insulating film on the upper surface and the side surface of the convex portion, the material of the gate insulating film, the material of the gate electrode are changed and those which are not changed may be mixed.

(Embodiment 3) In the convex transistor as shown in FIG. 23A, the contact wiring to the source region 107 and the drain region 108 is usually formed by patterning the gate electrode 106 to form the source region 107 and the drain. A region 108 is formed, an interlayer insulating film is formed, a contact hole is formed by a photolithography method,
After that, a contact wiring layer is formed to fabricate. In this case, the contact hole or the convex portion 105a
If the position is shifted, there is a problem that the contact area between the source region 107 and the drain region 108 and the contact wiring layer is reduced and the contact resistance is increased.

Therefore, in the semiconductor device according to the present invention, it is preferable to form the contact wiring as shown in FIG. That is, first, the element is manufactured as described above. As the insulating film 24, in addition to the silicon oxide film, a silicon oxide film formed by using a gas such as LP-TEOS or TEOS-O ₃ can be used.

Next, an interlayer insulating film 41 such as a silicon oxide film is formed on the entire surface of the device, a resist is further formed thereon, the resist is patterned by a photolithography method, and the resist pattern is used as a mask for anisotropic etching. To form a contact hole. Then, after removing the resist, a polysilicon film or an amorphous silicon film having a thickness of 30 to 100 nm is conformally formed. Next, a mask is formed using a photolithography method, and ion implantation is performed using the mask to form a polysilicon film or an amorphous silicon film formed over the region 42 where the contact is formed, which has a high solid solubility limit or higher. Impurity is introduced at a concentration. In this case, when forming the contact of the n ⁻ / n ⁺ diffusion layer,
Impurities having an n-type conductivity type such as phosphorus and arsenic are used as impurities, and impurities having a p-type conductivity type such as boron are used as impurities when forming a contact of the p ⁻ / p ⁺ diffusion layer.

Then, rapid thermal annealing (RT
The impurity introduced into the polysilicon film or the amorphous silicon film is solid-phase diffused into the projections 23 by the method A) or a method using a normal diffusion furnace, whereby the source region 47 and the drain region 48 are contacted with respect to the contact holes. Are formed in a self-aligned manner. Next, the polysilicon film or the amorphous silicon film is completely or selectively removed, and the contact wiring layer 43 is formed according to a normal contact wiring technique. In this way, FIG.
The contact wiring as shown in FIG. 4 can be formed.

According to the above method, it is possible to realize the elements having different driving capabilities by using the convex portions 23 having the same width. That is, as shown in FIG. 15A, an element that does not require a large driving capability requires contact wiring with a contact hole having a width equal to or narrower than the width of the upper surface of the convex portion 23, which requires a greater driving capability. 14B, as shown in FIG. 14B, contact wiring is performed using a contact hole having a width wider than the upper surface of the convex portion 23. By doing so, the effective channel width of the device can be controlled by the size of the contact hole. Further, according to the above method, even if the contact hole is formed so as to be displaced from the source region 47 and the drain region 48, the increase in contact resistance is suppressed as much as possible. In addition, the element manufactured by the above method,
The source region 47 and the drain region 48 are formed in self-alignment with the contact holes.

The advantages of the device having this structure are shown in FIGS.
This can be understood by comparing with (B). That is,
In the conventional convex transistor, unlike the normal case of FIG. 16A, when the source region 47 and the drain region 48 are displaced from the contact hole as shown in FIG. Is reduced, and the device characteristics are affected by the parasitic resistance. On the other hand, in the device manufactured by the above method, as shown in FIG. 15, the source region 47 and the drain region 48 are formed in self-alignment with all the regions 44 of the convex portion 23 opened by the contact holes. Therefore, the contact area between the contact wiring layer 43 and the source region 47 and the drain region 48 is not extremely reduced, and the deterioration of the device characteristics due to the increase of the contact resistance can be suppressed to the minimum. In the above method, the element structure to be formed changes depending on whether or not the contact hole is displaced with respect to the source region 47 and the drain region 48.

(Embodiment 4) FIG. 17 is a perspective view showing another example of a semiconductor device (MOS transistor) according to the present invention.

This device has an impurity concentration of 1 × 10 ¹⁶ cm ^-3
The p-type silicon substrate 51 is etched by 0.7 μm to form a protrusion 52 having a width of 0.1 μm, the insulating film 53 is embedded in the element isolation region, and the insulating film 53 is etched by 0.3 μm from the upper surface of the protrusion. After that, boron is ion-implanted into the convex portion 52, so that 0.
A 1 × 10 ¹⁸ cm ⁻³ p-type impurity layer 54 is formed deeper than the 3 μm portion (deeper than the upper surface of the insulating film 53 in FIG. 17), and then a 4 nm thick gate insulating film 55 is interposed. To form the gate electrode 56, and finally to form the source region 57 and the drain region 58.

According to the element having this structure, since the high-concentration p-type impurity layer 54 is not in contact with the source region 57 and the drain region 58, the concentration of the p-type impurity layer 54 can be controlled without degrading the withstand voltage of the diffusion layer. It can be increased without any upper limit, which dramatically increases the suppression effect of the short channel effect.
Moreover, the capacitance of the diffusion layer can be reduced.

Although the NMOS is described in this embodiment, the PMOS can be manufactured in the same manner. The concentration of the impurity layer that is the channel region may be such that the entire convex portion 52 is completely depleted by the voltage applied to the gate electrode on the side surface of the convex portion 52. Further, in the present embodiment, the etching method is used for forming the convex portion 52, but it may be formed by epitaxial growth. In this case, a p-type doped epitaxial layer may be used as the p-type impurity layer 54.

In the present embodiment, when forming the convex portion 52, it is preferable to form a forward taper of 100 °, for example, as shown in FIG. Thereby, the gate electrode 5
It is possible to prevent the gate electrode from remaining on the side surface of the convex portion 52 after forming 6, and to prevent a short circuit between the gate electrodes 56.

In this embodiment, the contact wiring shown in the third embodiment can be formed. However, in this case,
It is necessary to have a structure in which the junction breakdown voltage between the drain region and the semiconductor substrate due to the contact does not decrease.

In this embodiment, the region having a relatively high impurity concentration is preferably formed in the element region below the gate electrode. The term "below the gate electrode" means below the upper surface of the field oxide film that will be the element isolation region. Further, the impurity concentration of the region having a higher impurity concentration than that of the channel region needs to satisfy the condition of suppressing the short channel effect such as punch through, while the impurity concentration of the channel region is completely depleted by the gate voltage. Therefore, it is necessary to make the concentration low.

The present embodiment is characterized in that the element region has a region having a relatively high impurity concentration below the channel region of the convex portion. Therefore, the channel region is completely depleted, the short channel effect is suppressed, the carrier mobility is improved, and the punch-through breakdown voltage between the source region and the drain region is improved by the high impurity concentration region. You can

(Embodiment 5) FIG. 19A shows the fourth embodiment of the present invention.
3 is a perspective view showing an embodiment of a semiconductor device (MOS transistor) according to the invention of FIG. Further, FIGS. 19B and 19C are cross-sectional views taken along line XIXB-XIXB and line XIXC-XIXC in FIG. 17A, respectively.

Reference numeral 61 in the figure denotes a semiconductor substrate having a convex portion 62. A gate electrode 64 is formed on the semiconductor substrate 61 via a gate insulating film 63. In the gate electrode 64, an opening 65 reaching the diffusion layer formed in the convex portion 62 is formed, and that region serves as a drain region 66. Furthermore, the source region 6 is sandwiched by the channel region 67.
8 is formed.

The element having such a structure can be manufactured according to FIGS. 20 (A) to 20 (C). That is, as shown in FIG. 20 (A), a well-known electron beam exposure method is used on the (100) surface of a semiconductor substrate 61 which is a silicon substrate having 1 × 10 ¹⁶ cm ⁻³ of p-type impurities. After forming a resist layer in a region having a width of 0.25 μm and a length of 1.5 μm to be a channel region, a silicon protrusion 62 having a height of 0.5 μm is formed by RIE. Next, as shown in FIG. 20B, a silicon oxide film having a thickness of 10 nm is formed as the gate oxide film 63 by thermal oxidation on the semiconductor substrate 61, and phosphorus is further doped as the gate electrode 64 thereon. A polysilicon film was formed and patterned by electron beam exposure. In this state, the gate electrode 64
Leaves the polysilicon film not only on the channel region but also on the side surface of the drain region 66.

Then, as shown in FIG. 20C, an opening 65 is formed in the polysilicon film on the drain region 66 by the RIE method, the acceleration voltage is 50 kV, and the dose amount is 2 × 10.
Arsenic is ion-implanted at ¹⁵ cm ⁻³ and annealed at 900 ° C. for 1 hour to form a source region 68 and a drain region 66 having a depth of 0.2 μm. After that, the source region 68, the drain region 66, and the gate electrode 64
A contact hole and a contact wiring are formed using an electron beam exposure method. At this time, the width W of the convex portion 62 is W ≦ 2√2 (ε _S · φ _F / q · N _sub ) ^1/2 (wherein, q is an electronic charge (coulomb), and φ _F is a Fermi quasi of the semiconductor substrate. (EV), ε _S is the dielectric constant of the semiconductor substrate (farad /
cm) and N _sub are impurity concentrations (c
m ^-3 ). ) Is satisfied.

As described above, in this embodiment, the gate electrode 64 is formed also on the side surface of the drain region 66, and the width W of the convex element region satisfies the above expression with respect to the width W of the element region. Therefore, not only is the channel region depleted, but the electrodes that shield the lines of electric force are formed on the sides of the drain region, so the lines of electric force extending from the drain region do not extend toward the source region, End with the electrode of the part. As a result, a decrease in the potential of the channel region due to the drain potential can be suppressed, and the short channel effect can be effectively suppressed.

When the short channel effect of the device manufactured as described above and the conventional device was measured, the conventional device showed a decrease in the threshold value due to the short channel effect at a channel length of 0.4 μm. In the case of the present invention, no decrease in the threshold due to the short channel effect was observed up to the channel length of 0.25 μm.

In this embodiment, the width W of the convex portion 52 is 0.2 μm.
The gate insulating film 63 has a thickness of 10 nm. It is apparent that the short channel effect can be suppressed to a shorter channel length by further reducing the width W of the convex portion 62 or further reducing the film thickness of the gate insulating film 63.

FIG. 21 is a perspective view showing another embodiment of the semiconductor device according to the fourth invention of the present invention. This structure is
The remaining side surface of the gate electrode 64 by RIE is used. That is, a mask pattern is provided on the gate electrode,
By using ordinary anisotropic etching such as RIE and appropriately selecting the anisotropic etching conditions, the gate electrode 64 can be formed while leaving the gate electrode 69 on the side surface of the convex portion 62 of the drain region 66. In this case, the source region 68
Although the gate electrode 69 is formed on the side surface of the convex portion 62 of
There is no particular problem in terms of suppressing the short channel effect.

The present invention is not limited to the above-mentioned embodiments, but P-channel MOSFET and N-channel MOSFE.
It is needless to say that the present invention can be applied to any of T and can be modified in various ways.

The present invention can be effectively applied to, for example, a cell portion of a semiconductor memory device or the like where a narrow channel width is required. In this case, by using the SOI substrate as the substrate, using the element according to the present invention in the memory cell portion, and applying the partially depleted element in the peripheral element portion, it is possible to realize a semiconductor device operating at high density and at high speed. .

As described above, the first and third aspects of the present invention
Since the semiconductor device of the invention of the invention has a high-concentration impurity region containing a second conductivity type impurity at a concentration higher than the concentration at the surface of the channel region in the convex transistor, the semiconductor device of the invention has a convex-shaped semiconductor element region. Due to the three-dimensional expansion, the current driving capability of the device can be increased, the short channel effect and punch through can be prevented without limiting the characteristics of the channel depletion type device, and the device can be miniaturized. Can be realized.

In the semiconductor device of the second invention of the present invention, the characteristics of the transistor formed on the upper surface of the element region and the characteristics of the transistor formed on the side surface of the element region in the convex transistor are different from each other. The degree of freedom in setting and circuit pattern design is increased, and the element characteristics can be selected according to the purpose of the circuit, and the performance of the integrated circuit can be improved.

Further, in the semiconductor device of the fourth and fifth inventions of the present invention, at least a side portion of the source region and the drain region of the convex transistor to which a high potential is applied is provided with a constant potential through an insulating film. The width W of the convex element region in which the held electrode is formed is W ≦ 2√2 (ε _S · φ _F /
q · N _sub ) ^1/2 (where q is electronic charge (coulomb),
φ F is the Fermi level (eV) of the semiconductor substrate, ε _S is the dielectric constant of the semiconductor substrate (farads / cm), and N _sub is the impurity concentration of the semiconductor substrate (cm ⁻³ ). Therefore, it is possible to realize a fine transistor having a large driving force and a high-density and high-performance integrated circuit.

[Brief description of drawings]

1A to 1C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to a first invention of the present invention.

2A and 2B are cross-sectional views for explaining the manufacturing process of the semiconductor device according to the first aspect of the present invention.

3A and 3B are cross-sectional views for explaining the manufacturing process of the semiconductor device according to the first aspect of the present invention.

FIG. 4 is a sectional view taken along line IV-IV in FIG.

5 is a cross-sectional view taken along the line VV of FIG.

FIG. 6 is a graph showing the relationship between channel length and threshold voltage.

FIG. 7 is a graph showing the relationship between channel length and subthreshold coefficient.

8A is a cross-sectional view showing an embodiment of a semiconductor device according to a second invention of the present invention, and FIG. 8B is a view showing the expansion of a depletion region in a convex portion of the semiconductor device shown in FIG. 8A. .

9A to 9C are characteristic diagrams showing drain current-gate voltage characteristics.

FIG. 10 is a sectional view showing another embodiment of the semiconductor device according to the second invention of the present invention.

FIG. 11 is a sectional view showing another embodiment of the semiconductor device according to the second invention of the present invention.

FIG. 12 is a cross-sectional view showing another embodiment of the semiconductor device according to the second invention of the present invention.

13A to 13D are manufacturing process diagrams of the semiconductor device shown in FIG.

FIG. 14 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.

15A and 15B are cross-sectional views showing a semiconductor device according to a third embodiment of the present invention.

16A is a cross-sectional view showing a normal contact state of a conventional semiconductor device, and FIG. 16B is a cross-sectional view showing a contact state when the conventional semiconductor device is misaligned.

FIG. 17 is a sectional view showing an embodiment of a semiconductor device according to the third invention of the present invention.

FIG. 18 is a view for explaining the taper of the convex portion of the element shown in FIG.

19A is a perspective view showing an embodiment of a semiconductor device according to a fourth invention of the present invention, and FIG. 19B is an XIXB- of FIG.
Sectional drawing which follows the XIXB line, (C) is sectional drawing which follows the XIXC-XIXC line of (A).

20A to 20C are views for explaining a manufacturing process of the semiconductor device shown in FIG.

FIG. 21 is a perspective view showing an embodiment of a semiconductor device according to the fourth invention of the present invention.

FIG. 22 is a sectional view showing a conventional semiconductor device.

FIG. 23A is a perspective view showing a conventional semiconductor device;
(B) is sectional drawing which follows the XXIIIB-XXIIIB line of (A).

[Explanation of reference numerals] 1 ... Silicon substrate, 2, 4, 8, 31, 32 ... Silicon oxide film, 3, 15 ... Polysilicon film, 5, 12 ... Resist film, 6, 65 ... Opening portion, 7 ... Element isolation Groove, 9 ... SiO
₂ , 10 ... Convex silicon part, 11, 14 ... Thermal oxide film, 1
3 ... High-concentration impurity regions, 16 ... Drain electrodes 21, 5
1, 61 ... Semiconductor substrate, 22 ... Recesses, 23, 52, 62
... Projections, 24, 53 ... Insulating films, 25a, 25b, 28
a, 28b, 30a, 30b, 55, 63 ... Gate insulating film, 26, 29a, 29b, 56, 64 ... Gate electrode,
27 ... Corner part, 33 ... Resist layer, 34 ... Tungsten silicide film, 41 ... Interlayer insulating film, 42 ... Region where contact is formed, 43 ... Contact wiring layer, 44 ...
Region, 54 ... p-type impurity layer, 57, 68 ... source region,
58, 66 ... Drain region, 67 ... Channel region.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/78 617K 617S 617T 618C (72) Inventor Shin Yoshimi 1 Komukai-Toshiba-cho, Kawasaki-shi, Kanagawa Incorporated company Toshiba Research and Development Center (72) Inventor Mamoru Terauchi 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki City, Kanagawa Prefecture Incorporated Toshiba Research and Development Center (72) Inventor Shigeru Kawanaka Komukai, Saiwai-ku, Kawasaki City, Kanagawa Prefecture Toshiba Town No. 1 F-term in Toshiba Research & Development Center, a stock company (reference) HJ16 HL03 HL08 HL14 HM02 HM12 NN02 NN23 NN35 NN62 QQ11 QQ19 5F140 AA06 AA10 AA18 AA21 AC32 AC36 BA01 BB05 BC15 BD05 BD07 BD16 BD18 BE07 BF01 BF04 BF07 BF08 BF40 BF42 BF44 BF51 BG28 BG30 BG31 BG37 BH05 BH08 BH13 BH19 BH30 BH40 BJ01 BJ04 BJ05 BJ23 BK10 BK13 BK14 BK16 BK21 BK25 CE03 CB04

Claims (16)

[Claims] 1. A substrate having a convex semiconductor element region, and a gate electrode formed on a top surface and a side surface of the element region via a gate insulating film, wherein the gate electrode is provided in the element region. A source region and a drain region are provided apart from each other so as to form a channel region facing each other, and a film thickness of the gate insulating film and a gate are provided between an upper surface of the element region and a side surface of the element region. A semiconductor device, wherein at least one selected from the group consisting of a material of an insulating film and a material of a gate electrode is different from each other. 2. The gate insulating film is different in thickness between a portion located on an upper surface of the device region and a portion located on a side surface of the device region. The semiconductor device described. 3. The portion of the gate insulating film located on the upper surface of the device region is thicker than the portion of the gate insulating film located on the side surface of the device region. Semiconductor device. 4. The portion of the gate insulating film located on the side surface of the device region is thicker than the portion of the gate insulating film located on the upper surface of the device region. Semiconductor device. 5. The material of the gate insulating film is different from each other between a portion located on an upper surface of the device region and a portion located on a side surface of the device region. Semiconductor device. 6. The relative dielectric constant of the portion of the gate insulating film located on the side surface of the device region is larger than that of the portion of the gate insulating film located on the upper surface of the device region. Item 2. The semiconductor device according to item 1. 7. The relative dielectric constant of the portion of the gate insulating film located on the upper surface of the device region is larger than that of the portion of the gate insulating film located on the side surface of the device region. Item 2. The semiconductor device according to item 1. 8. The material of the gate electrode is different from that of a portion located on an upper surface of the device region and a portion located on a side surface of the device region. Semiconductor device. 9. The work function of a portion of the gate electrode located on a side surface of the device region is larger than that of a portion of the gate electrode located on an upper surface of the device region. The semiconductor device described. 10. The work function of the portion of the gate electrode located on the upper surface of the device region is larger than that of the portion of the gate electrode located on the side surface of the device region. The semiconductor device described. 11. A substrate having a convex semiconductor element region, and a gate electrode formed on a top surface and a side surface of the element region via a gate insulating film, wherein the gate electrode is provided in the element region. A source region and a drain region are provided apart from each other so as to form a channel region facing each other, and the gate electrode is a first portion of the element region interposed between the source region and the drain region. And a side surface of the second portion where the drain region is provided, the semiconductor device being formed. 12. The semiconductor device according to claim 11, wherein the gate electrode is formed to further cover a side surface of a third portion of the element region where the source region is provided. 13. The device region includes the first to third portions and a fourth portion located below the first to third portions, and the gate electrode is formed to further cover a side surface of the fourth portion. The semiconductor device according to claim 12, wherein: 14. A substrate having a convex semiconductor element region, a gate electrode formed on an upper surface and a side surface of the element region through a gate insulating film, and a contact hole covering the element region and provided with a contact hole. An insulating film and a pair of contact wirings that fill the contact hole and are in contact with the device region are provided. A source region and a drain are formed in the device region so that a channel region is formed facing the gate electrode. Regions are provided apart from each other and in contact with the pair of contact wirings, respectively, at least one of the pair of contact wirings contact both a part of the upper surface and a part of the side surface of the element region, The thickness of the source region or the drain region in contact with the contact wiring is larger than that in the position not in contact with the contact wiring. Wherein a thicker at a position in contact with the transfected lines. 15. A substrate having a convex semiconductor element region, a gate electrode formed on a top surface and a side surface of the element region via a gate insulating film, and a contact hole covering the element region and provided with a contact hole. An insulating film and a pair of contact wirings that fill the contact hole and are in contact with the device region are provided. A source region and a drain are formed in the device region so that a channel region is formed facing the gate electrode. A region spaced apart from each other and in contact with the pair of contact wirings, respectively, and a diameter of a contact portion of each of the pair of contact wirings with the element region is larger than a width of an upper surface of the element region. A semiconductor device characterized by: 16. The semiconductor according to claim 15, wherein the thickness of the source region and the drain region at a contact portion with the pair of contact wirings is thicker on the side surface side than in the center of the element region. apparatus.