JP2003101399A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can realize a high-speed operation by a MOS transistor by eliminating a pull-up resistance value depen dence of a rise time and which allows a bus high-speed operation and a low power consumption to be compatible. SOLUTION: A High level propagated via an element 11 is input to an element 12 and an element 13, and hence an element 15 (N-channel MOS transistor) is shifted from a conducting state to an interrupting state. On the contrary, an element 14 (P-channel MOS transistor) is shifted from the interrupting state to the conducting state. When an output terminal state is shifted to the High level, the output of the feedback inverter of an element 16 is changed to a Low level, the element 12 is changed to the High level, and the element 14 is shifted to the interrupting state. The element 14 is interrupted by receiving the change of the output terminal state.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using an electric circuit system combining a plurality of semiconductors, such as OA equipment, AV equipment, and portable electronic equipment. 2. Description of the Related Art Conventionally, a power supply voltage level has been raised by using an open drain output circuit as shown in FIG. Such an open drain output terminal circuit,
Nch (N channel) MOS (Metal Oxid)
e Semiconductor The transistor has a drain connected to the output terminal and a source (s
source) is grounded. In the open drain output terminal circuit, a plurality of output terminals or input / output terminals can be connected by wired OR (logical sum), and the output line is powered by one or more pull-up resistors or a device equivalent thereto. Voltage level (hereinafter Hi
gh level), and the raised Hig
h level is maintained. Further, an output buffer circuit in which P-channel and N-channel MOS transistors are connected in a complementary manner as shown in FIG.
The output terminal state is quickly raised to the power supply voltage level by the (P-channel) type MOS transistor. [0003] With respect to an open drain terminal capable of handling a high-frequency signal, Japanese Patent Application Laid-Open No. 6-006203 discloses an output circuit which requires a special mode switching signal and switches the output in accordance with this switching signal. Japanese Patent Application Laid-Open No. 5-284000 discloses an open drain terminal capable of handling a high-frequency signal and having an output of L (Lo).
A digital signal output stage circuit is described which does not hinder the transition to w). In addition, Japanese Unexamined Patent Publication
Japanese Patent Application Laid-Open No. 222977 describes a semiconductor device and an electronic apparatus capable of switching between a normal output and an open drain output. [0004] However, in the conventional open drain output terminal circuit, the rise time depends on the pull-up resistance value, which hinders realization of high-speed operation. Therefore, an object of the present invention is to make the rise time dependent on the pull-up resistance value while taking advantage of the fact that an open drain output circuit can connect a plurality of output terminals or input / output terminals with a wired OR connecting outputs of respective gates. It is an object of the present invention to provide a semiconductor device capable of realizing both high-speed operation of a bus and low power consumption by realizing high-speed operation by a MOS transistor and extremely increasing a pull-up resistance value. According to the present invention, a plurality of output terminals connected to a P-channel MOS transistor are provided, and a plurality of input / output signals from the output terminals are wired. In a semiconductor device having an open drain type output circuit connectable by OR, an output signal obtaining means for obtaining an output signal from the output terminal whose output level has been raised to a power supply voltage level by the P-channel type MOS transistor And the output signal obtained by the output signal obtaining means
A connection means for connecting to another output terminal, and a state transition means for shutting off a P-channel MOS transistor based on a logical change of each output terminal connected by the connection means and causing a transition to a high impedance state. With the provision, the above object is achieved. Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to FIG. 1 and FIG. FIG. 1 is a diagram showing a configuration of the open drain type output circuit of the semiconductor device according to the present embodiment. Also, FIG.
FIG. 5 is a diagram illustrating an open drain output circuit signal waveform.
FIG. 2 shows transition states of terminals and internal signals when the open drain type output circuit of FIG. 1 operates. Both input signal (IN) and output terminal (OUT) are Lo
From the w level state (state 1 in FIG. 2), the input signal (IN)
Will be described (state 2 in FIG. 2). When the High level propagated by the element 11 is input to the elements 12 and 13, the element 15 (N-channel MOS transistor) transitions from the conductive state to the cutoff state. Conversely, the element 14 (P-channel MOS transistor) transitions from the cutoff state to the conduction state. At this time, the effect of the pull-up resistance element connected as the element 17 is minute, and the output terminal (OU
T) The state is raised to the high level by the element 15.
The effect is large. Further, the output terminal state transitions to the high level, so that the output of the feedback inverter of the element 16 goes to the low level and the output of the element 12 goes to the high level.
Level to change the element 14 to the cutoff state. In response to the change in the state of the output terminal, the element 14 is cut off. By shutting off both elements 14 and 15, the state of the output terminal (OUT) is changed by element 17
The High level is maintained (state 3 in FIG. 2). At this time, as long as the other output circuits do not output a Low level, even if the resistance value of the element 17 is sufficiently large, the output terminal state is as follows.
High levels can be maintained. Next, a case where the input signal (IN) transits to a low level will be described (state 4 in FIG. 2). When the Low level propagated by the element 11 is input to the elements 12 and 13, the element 15 changes from the cutoff state to the conduction state, and the element 14 keeps the cutoff state. At this time, the effect of the element 17 is minimal, and the state of the output terminal changes to the low level by the element 15.
While the state of the output terminal maintains the Low level, the power supply (VC
From C), a current depending on the resistance value of the element 17 flows between GND (state 1 in FIG. 2). As described above, in the open drain type output circuit of the present embodiment, even if the pull-up resistance value of the element 17 is sufficiently increased (for example, several mega-ohms), the element 1
4 allows the output to be quickly changed to a high level. In addition, the inverter circuit of the element 16 is Hig
The higher the threshold for determining the h level is, the greater the effect of sufficiently raising the output terminal state to the high level. Similarly, by making the input / output propagation time of the element 16 longer than the time for raising the output terminal to the high level by the element 14, the effect of quickly and sufficiently raising the output terminal to the high level can be enhanced. In the open drain type output circuit of this embodiment, an N-channel transistor is used when a wired OR connected signal line changes from High to Low, and a P-channel transistor is used when changing from Low to High. Since each is used, a high-speed transition can be realized in either case. Further, in the open drain type output circuit of the present embodiment,
After the output level is raised to the power supply voltage level by the Pch-type MOS transistor in a short time, the transition to the high impedance state can be achieved by cutting off the Pch-type MOS transistor using the change in the output terminal logic. Further, by sufficiently increasing the pull-up resistance value, it is possible to suppress the power consumption in the low-level output state while realizing a high-speed operation. In addition,
Although the present embodiment refers to an open drain output circuit, a similar effect can be obtained for an open drain input / output circuit having an input circuit.
The resistance element of the element 17 can be applied to a case where an active device such as a transistor is used as long as the resistance element has a constant resistance value. Further, the resistance element can be applied to a case where the resistance element is incorporated in a semiconductor device having an open drain output circuit. According to the first aspect of the present invention, output signal obtaining means for obtaining an output signal from an output terminal whose output level has been raised to the power supply voltage level by a P-channel MOS transistor, and obtaining the output signal A connection means for connecting an output signal obtained by the means to another output terminal by a wired OR, and a P-channel type MOS transistor is cut off based on a logical change of each output terminal connected by the connection means, thereby setting a high impedance state. And a state transition means for making a transition to a low-level output state while realizing a high-speed operation by sufficiently increasing the pull-up resistance value. Consumption can be kept very low.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a configuration of an open drain type output circuit of a semiconductor device according to the present embodiment. FIG. 2 is a diagram showing an open drain output circuit signal waveform. FIG. 3 is a diagram showing a conventional open drain output terminal circuit. FIG. 4 is a diagram showing an output buffer circuit. [Explanation of Signs] 11-17 elements

Claims (1)

Claims: 1. An open circuit having a plurality of output terminals connected to a P-channel MOS transistor, wherein a plurality of input / output signals from the output terminals can be connected by a wired OR. In a semiconductor device having a drain type output circuit, an output signal obtaining unit for obtaining an output signal from the output terminal whose output level has been raised to a power supply voltage level by the P-channel MOS transistor; Connection means for connecting the output signal thus obtained to another output terminal by a wired OR, based on a logical change of each output terminal connected by the connection means, interrupting the P-channel MOS transistor and transiting to a high impedance state And a state transition means for causing the semiconductor device to change.