JP2003101389A - Oscillation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an oscillation circuit capable of obtaining a stable triangular wave even when an oscillation frequency becomes high. SOLUTION: Switching of charging and discharging is conducted by using a logic circuit which has two comparators 1, 2 and a flip-flop circuit 6. A current source is switched by adopting a system for turning on, off the emitters of transistors Q2 , Q3 . Thus, an influence of a switching speed in the circuit is eliminated, the change in the amplitude of the triangular wave can be suppressed even in the high oscillation frequency, thereby obtaining the stable triangular wave.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillator circuit, and more particularly to an oscillator circuit compatible with high speed switching.

[0002]

2. Description of the Related Art A conventional oscillator circuit will be described below with reference to FIGS. The conventional oscillator circuit is composed of a charge / discharge circuit and a comparator section as shown in FIG. The emitters of the npn transistors Q4 to Q7 are grounded. A resistor R is provided at the inverting input terminal of the comparator 101.
The npn transistor Q7 is connected via the line 2.
The base of the npn transistor Q7 is the comparator 101.
Is connected to the output terminal of. The output terminal of the comparator 101 is connected to the inverter 102, and the output terminal of the inverter 102 is connected to the base of the npn transistor Q4.

The operation of the circuit shown in FIG. 3 will be described below. When the voltage of the capacitor C1 is 0 volt, the output of the comparator 101 becomes low level, the output of the inverter 102 becomes high level, the npn transistor Q7 is turned off, and the npn transistor Q4 is turned on. Therefore, the npn transistors Q5, Q
6 is turned off. Therefore, the pnp transistor Q3
A current I ₁ flows into the capacitor C1 from the capacitor C1, and the capacitor C1 is in a charged state, and the voltage rises. By the way, the reference voltage V _A of the inverting input terminal of the comparator 101 is as shown in the following mathematical expression 1.

[0004]

[Formula 1] V _A = V _CC × (R2 + R3) / (R1 + R
2 + R3)

When the voltage of the capacitor C1 continues to rise and exceeds the voltage V _A , the output of the comparator 101 is inverted to a high level, the output of the inverter 102 becomes a low level, the npn transistor Q7 is turned on, and the npn transistor Q7 is turned on. The transistor Q4 is turned off.
Therefore, the npn transistors Q5 and Q6 are turned on. By the way, since the npn transistor Q7 is in the ON state, the reference voltage V _B of the inverting input terminal of the comparator 101 is as shown in the following Expression 2.

[0006]

[Formula 2] V _B = V _CC × (R ₂ / (R ₁ + R ₂ ))

When the npn transistors Q5 and Q6 are turned on, a current flows from the capacitor C1 to the npn transistors Q5 and Q6. That is, the discharge state occurs and the voltage decreases. When the voltage of the capacitor C1 continues to decrease and becomes lower than V _B , the output of the comparator 101 is inverted and becomes low level, the output of the inverter 102 becomes high level, the npn transistor Q7 is turned off, and the npn transistor Q4 is turned on. Then, charging is started again. Repeat the above operation,
A triangular wave is generated in the capacitor C1.

[0008]

Incidentally, in recent years, switching regulators have been
The oscillation frequency is getting higher. However, in the above-described conventional oscillation circuit, when the oscillation frequency increases, a switching response of the transistor causes a time lag between the switching operation of the npn transistor Q4 used as a switching element and the switching operation of the npn transistor Q7, which causes on / off. There is a delay (storage time) in switching. Here, as shown in FIG. 4, when the oscillation frequency becomes higher, the amplitude of the triangular wave tends to increase with respect to the oscillation frequency. In DC / DC, a problem occurs because the switch timing is determined with reference to this triangular wave, and a stable triangular wave cannot be obtained due to the influence thereof. An object of the present invention is to solve the above problems and provide an oscillation circuit that can obtain a stable triangular wave even if the oscillation frequency becomes high.

[0009]

The present invention includes first and second aspects.
In an oscillation circuit having a charge / discharge unit including a pnp transistor and a capacitor, and a charge / discharge control unit, the charge / discharge control unit has a first input terminal voltage and a second input higher than the first input terminal voltage, respectively. First having a terminal voltage
And a second comparator, and a first one sent to the emitters of the first and second pnp transistors, respectively.
And a flip-flop circuit having a second output,
The first output level and the second output level are configured to be different at a time point when the voltage of the capacitor is lower than the first input terminal voltage and a time point when the voltage is higher than the second input terminal voltage. It is characterized by

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a diagram showing a configuration of an oscillator circuit of the present invention. The present invention also comprises a charge / discharge circuit and a comparator section. Of these, the charge / discharge circuit is almost the same as the conventional one, but the configuration of the comparator section is different from the conventional one. The configuration of this oscillator circuit will be described below.

The npn transistors Q5 and Q6 are emitters.
It is grounded. The inverting input terminal of comparator 1 is not
Grounded via anti-R2 and resistor R3, via resistor R1
V _ccIt is connected to the. Non-inverting input of comparator 1
The output terminal and the inverting input terminal of the comparator 2 are pnp transformers.
It is connected to the collector of the transistor Q3. COMPARE
Input terminal of comparator 1 and non-inverting input terminal of comparator 2
The child is an emitter of the pnp transistor Q3 via the resistor R6.
Connected to the computer. AND circuit 3 includes comparator 1,
The output of 2 is inverted and the signal is ANDed and inverted.
Output to the set terminal S of the flip-flop circuit 6
To do. The output signal of the comparator 2 is output from the NOT circuits 4 and 5.
It is output to the reset terminal R via. flip flop
The output Q of the circuit 6 is applied to the emitter of the pnp transistor Q2.
It is connected. Output Q bar of flip-flop circuit 6
Is connected to the emitter of the pnp transistor Q3
It

The collectors of the pnp transistors Q2 and Q3 are connected to the collectors of the npn transistors, and the collectors are connected to the bases of the npn transistors Q5 and Q6. The npn transistors Q5 and Q6 have their emitters grounded.

The operation of the oscillator circuit according to the present invention will be described below with reference to FIG. FIG. 2 is a timing chart explaining the operation of the oscillation circuit of FIG. Here, when the voltage of the capacitor C1 is 0V, the output of the comparator 1 becomes L level and the output of the comparator 2 becomes H level. Therefore, the flip-flop circuit 6
The output Q (hereinafter referred to as the FF circuit) becomes H level, the output Q bar becomes L level, the npn transistor Q3 is turned on, and the capacitor C1 is charged. Condenser C
When the voltage of 1 exceeds the inverting input terminal voltage V _L of the comparator 2 and rises to the non-inverting input terminal voltage V _{H of} the comparator 1 (V _H >C1> V _L ), the output of the comparator 2 becomes L level, The output Q of the FF circuit 6 is still H
Level, the output Q-bar remains at L level.

When the charging further proceeds and the voltage of the capacitor C1 exceeds the non-inverting input terminal voltage V _H of the comparator 1 (C1> V _H ), the output of the comparator 1 becomes H level and the output of the comparator 2 becomes L level. Become. Therefore, the output Q of the FF circuit 6 is at L level and the output Q bar is at H level.
Level, the npn transistor Q3 turns off, and np
The n-transistor Q2 turns on. Therefore, the capacitor C1 is discharged.

After that, when the discharge progresses and the voltage of the capacitor C1 falls below the non-inverting input terminal voltage V _H of the comparator 1 and drops below the inverting input terminal voltage _VL of the comparator 2 (V _H <C1 ≦ V _L ), the comparator The output of 1 becomes L level, and the output of the comparator 2 becomes H level. Therefore, the output Q of the FF circuit 6 becomes H level, the output Q bar becomes L level, the npn transistor Q3 is turned on, and the npn transistor Q2 is turned off. Therefore, the capacitor C1 is charged again. By repeating such operations, a triangular wave is generated.

As described above, in the oscillation circuit having the above-described structure, switching between charging and discharging is performed by using the logic circuit including the two comparators 1 and 2 and the flip-flop circuit 6.
The current source is switched by adopting a method of turning on / off the emitters of the transistors Q2 and Q3. This is equivalent to the base grounding operation, and improves the switching delay which has been a problem in the conventional technology.

Further, by eliminating the switching transistor (Q7 in FIG. 3) used for determining the threshold value of the comparator in the prior art, it becomes possible to speed up the circuit response.

[0018]

According to the present invention, the influence of the switching speed in the circuit can be eliminated to suppress the fluctuation of the triangular wave amplitude even at a high oscillation frequency, and a stable triangular wave can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an oscillator circuit of the present invention.

FIG. 2 is a timing chart explaining the operation of the oscillation circuit of FIG.

FIG. 3 is a diagram showing a configuration of a conventional oscillator circuit.

4 is a graph showing the relationship between the oscillation frequency and the amplitude of the triangular wave generated in the circuit of FIG.

[Explanation of symbols]

1, 2 comparator 3 AND circuit 4,5 NOT circuit 6 flip-flop circuits

Claims (3)

[Claims] 1. An oscillation circuit having a charge / discharge unit including first and second pnp transistors and a capacitor, and a charge / discharge control unit, wherein the charge / discharge control unit has a first input terminal voltage and the first input terminal voltage, respectively. First and second comparators having a second input terminal voltage higher than the input terminal voltage of
And a flip-flop circuit having first and second outputs delivered to the emitter of the second pnp transistor, the time when the voltage of the capacitor falls below the first input terminal voltage and the second input terminal. An oscillating circuit, wherein the first output level and the second output level are configured to be different at the time when the voltage exceeds the voltage. 2. An AND circuit that receives the output signals of the first and second comparators and outputs the output signals to a set terminal of the flip-flop circuit, and the reset terminal of the flip-flop circuit includes the AND circuit. The oscillator circuit according to claim 1, wherein the output signal of the second comparator is input. 3. The oscillator circuit according to claim 2, wherein the first input terminal and the second input terminal are an inverting input terminal and a non-inverting input terminal, respectively.