JP2003101027A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a vertical power MOSFET whose cell spacings can be made to shrink fully, whose drain dielectric strength can be improved without sacrificing the ON-resistance, and which uses trench side surfaces as channels, and to provide a method of manufacturing a MOSFET. SOLUTION: A plurality of trenches 10 are formed in a vertical power MOSFET which uses trench side surfaces as channels so as to make the distances between the trenches not larger than 1.5 μm. In this way, by restricting the distance between the trenches, the drain breakdown voltage can be improved without sacrificing the ON-resistance of the transistor. The trenches 10, whose bottoms are arranged in a drain region 1', are formed in a semiconductor substrate 1 vertically from the main surface of the substrate and gate insulation films 4, formed on the sidewalls of the trenches, and gate electrodes 5, which are buried in the trenches and whose upper surfaces are placed higher than junction planes between source regions and base regions and lower than the main surface of the substrate, are provided in the semiconductor substrate 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trench arrangement structure of a vertical power MOSFET in which a gate electrode is embedded in a trench formed in a semiconductor substrate and a side surface of the trench serves as a channel region.

[0002]

2. Description of the Related Art A vertical power MOSFET (hereinafter referred to as UMOS) in which a gate electrode is embedded in a trench formed in a conventional semiconductor substrate and a side surface of the trench serves as a channel region.
Has a plurality of trenches in which a gate electrode such as polysilicon is embedded, and the pitch between the trenches is about 2.3 to 3.0 μm. Since the diameter of the trench is about 0.5 μm, the distance between adjacent trenches is usually about 1.8 to 2.5 μm.
FIG. 14 is a sectional view and a plan view of a conventional trench contact type UMOS. The portion along the line AA 'in the plan view is the cross-sectional view. The semiconductor substrate 101 uses, for example, a p-type silicon semiconductor. An n-base region 102 doped with an n-type impurity is formed in the surface region of the semiconductor substrate 101. On the n-base region 102, a p-source region 103 whose one surface is the main surface of the semiconductor substrate 101 is formed. A region on the back surface side where these regions are not formed is a p-drain region 101 '. A plurality of trenches 110 are formed from the main surface of the semiconductor substrate 101 toward the inside. The trench 110 is formed from the main surface on which the p-source region 103 is formed to the p-drain region 1.
It has reached a predetermined depth of 01 '. Trench 110
A gate insulating film 104 such as a silicon oxide film formed by thermal oxidation is formed on the side wall.

The gate insulating film 104 is formed in the trench 11
0 side wall and extends on the main surface of the semiconductor substrate 101 around the trench. The distance between adjacent trenches is 2.3 to
It is about 3.0 μm. A gate 105 made of polysilicon or the like is embedded in the trench 110 covered with the gate insulating film 104. This polysilicon gate 1
The surface of 05 constitutes almost the same surface as the main surface of the semiconductor substrate 101. An interlayer insulating film 106 such as a silicon oxide film formed by CVD is deposited and formed on the surface of the polysilicon gate 105 and the surface of the gate insulating film 104. Further, on the main surface of the semiconductor substrate 101, the interlayer insulating film 106 is penetrated between the trenches 110 and the base region 1 is formed.
An opening 107 reaching 02 is formed.

The openings 107 are formed between the trenches 110, and are formed and arranged in a zigzag pattern, for example, on the main surface of the semiconductor substrate 101 as shown in the plan view of the semiconductor substrate of FIG. 14 (source electrodes are not shown). There is. In addition, the polysilicon gate 105 embedded in each trench 110 is
These polysilicon gates 105, which are wired so as to be electrically connected to each other, are connected to the semiconductor substrate 101.
It is electrically connected to the gate extraction electrode 105 'formed on the main surface. In this state, the main surface of the semiconductor substrate 101 is covered with the interlayer insulating film 106 except for the opening 107 and the gate extraction electrode 105 '. A source electrode 108 is formed on the interlayer insulating film 106 so as to be electrically insulated from the gate lead electrode 105 '. The source electrode 108 is electrically connected to the source region 103 and the base region 102 which are also embedded in the opening 107 and exposed inside the opening 107. The source electrode 108 is made of, for example, aluminum, and a barrier metal layer is interposed (not shown) at a portion facing the source region 103 and the base region 102. A drain electrode 109 electrically connected to the drain region 101 'is formed on the back surface of the semiconductor substrate 101.
However, in this structure, in order to maintain the insulation between the polysilicon gate 105 and the source electrode 108 and as a countermeasure against the misalignment margin of the exposure technique, when the opening 107 is formed by etching the interlayer insulating film 106, the trench 110 of the trench 110 is formed. There is a distance from the opening end to the end of the opening 107.

[0005]

When the distance between the trenches is large (the cell pitch is wide), the profile of the equipotential lines in the region between the trenches becomes dense along the trench shape and the electric field is concentrated. Withstand voltage tends to decrease. Conventional trench gate products have a mesa region width (distance between adjacent trenches) of at least 2.0 μm, usually 2.3 to 3.0 μm. Power M in this design range
When trying to increase the drain breakdown voltage of OSFET FET
There is a problem that the drain withstand voltage is lowered when the on resistance of the device is increased or when the on resistance is tried to be decreased (the impurity concentration is increased). Regarding the mesa region width, it has been impossible to design the width of the mesa region to be 2.0 μm or less because there is a problem of alignment margin between the contact pattern and the underlying trench pattern. The present invention has been made in view of the above circumstances, and uses a trench side surface as a channel that can sufficiently shrink the cell pitch interval and reduce the on-resistance (of the FET) without sacrificing the drain breakdown voltage. A semiconductor device including a vertical power MOSFET and a method for manufacturing the same are provided.

[0006]

The present invention is characterized in that the distance (mesa region width) between adjacent trenches of a vertical power MOSFET having a trench side surface as a channel is 1.5 μm or less. By thus defining the distance between the trenches, the drain breakdown voltage can be improved without sacrificing the on-resistance of the transistor. That is, the semiconductor device of the present invention includes a semiconductor substrate, a drain region formed on the semiconductor substrate and having one surface exposed on the back surface of the semiconductor substrate, and a drain region formed on the semiconductor substrate and contacting the other surface of the drain region. A base region that is partially exposed at the semiconductor substrate main surface at a plurality of locations, and a source region that is formed on the semiconductor substrate and has one surface in contact with the base region and the other surface exposed at the semiconductor substrate main surface A trench formed such that a bottom surface thereof is arranged in the drain region in the vertical direction from the main surface of the semiconductor substrate; a gate insulating film formed substantially only on the sidewall of the trench; and a trench embedded in the trench. A gate electrode whose surface is above the junction surface between the source region and the base region and lower than the main surface of the semiconductor substrate; A drain electrode formed in contact with the drain region on the back surface of the substrate, wherein formed in the semiconductor substrate main surface, and a source electrode in contact with said source region and said base region, said trench,
A plurality of trenches are formed at a predetermined interval, and the distance between the adjacent trenches is 1.5 μm or less. By thus defining the distance between the trenches, the drain breakdown voltage can be improved without sacrificing the on-resistance of the transistor.

An insulating film may be formed on the surface of the gate electrode, the portion of the trench where the gate electrode is not buried, and the gate insulating film exposed at the peripheral portion of the trench. A reflowable insulating film may be embedded in a portion of the trench where the gate electrode is not embedded. In this structure, since the insulation distance can be set in the vertical direction of the substrate, the distance between the trenches can be shortened as compared with the conventional case. The trench is filled with a reflowable interlayer insulating film, and dry etching or anisotropic etching is performed so that the interlayer insulating film remains only right above the trench, and then the interlayer insulating film is reflowed before the source / base region. Since the metal to be the source electrode, which is the electrode, is formed, the main surface of the semiconductor substrate becomes flat, and the metal film such as aluminum to be the source electrode can be easily formed. A silicon nitride film is formed between the reflowable insulating film and the surface of the gate electrode and between the reflowable insulating film and the gate insulating film exposed in a portion of the trench where the gate electrode is not buried. It may be done.

A semiconductor device of the present invention includes a semiconductor substrate, a drain region formed on the semiconductor substrate and having one surface exposed on the back surface of the semiconductor substrate, and another surface formed on the semiconductor substrate and the other surface of the drain region. A base region that is in contact with the semiconductor substrate, one surface is in contact with the base region, the other surface is a source region that is exposed to the semiconductor substrate main surface, and a bottom surface in the vertical direction from the semiconductor substrate main surface. A trench formed so as to be arranged in the drain region, a gate insulating film formed on the sidewall of the trench and extending to a peripheral portion thereof, and a trench filled in the trench, the surface of which is the source. A gate electrode formed above the junction surface between the region and the base region and lower than the main surface of the semiconductor substrate, and the drain on the back surface of the semiconductor substrate. A drain electrode formed to be in contact with the region, a source electrode formed on the semiconductor substrate main surface and in contact with the source region and the base region, and the trench is formed in plural at a predetermined interval, The distance between the adjacent trenches is characterized by being 1.5 μm or less. An opening may be formed in the main surface of the semiconductor substrate, and the source electrode may be in contact with the source region and the base region through the opening.

According to the method of manufacturing a semiconductor device of the present invention, the semiconductor substrate main portion is in contact with the drain region of which one surface is exposed on the back surface of the semiconductor substrate and the other surface of the drain region, and the semiconductor substrate main part is partially formed at a plurality of locations. A base region exposed on a surface and a source region having one surface in contact with the base region and the other surface exposed on the semiconductor substrate main surface; and a bottom surface extending vertically from the semiconductor substrate main surface to the drain region. Forming a plurality of trenches so that the distance between adjacent trenches is 1.5 μm or less, and forming a gate insulating film substantially only on the sidewalls of the trenches; A step of forming a gate electrode so that the surface thereof is located above the junction surface between the source region and the base region and lower than the main surface of the semiconductor substrate. And forming a drain electrode in contact with the drain region in the semiconductor substrate back surface,
And a step of forming a source electrode on the main surface of the semiconductor substrate in contact with the source region and the base region.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. First, referring to FIG. 1 to FIG.
An example will be described. In this embodiment, the structure of a power MOSFET (abbreviated as UMOS) having a trench side surface as a channel is formed by embedding an interlayer insulating film between a gate and a source formed in the upper portion of the trench inside the trench, and a source contact is self-aligned. It is premised on the structure that can be done in. In this structure, the interlayer power buried type trench power MOSFET can be formed more narrowly because the distance between adjacent trenches (mesa region width) is not limited by the contact alignment accuracy. Figure 1 is UM
2 is a cross-sectional view of a semiconductor device having an OS structure, FIG. 2 is a perspective view of the semiconductor substrate shown in FIG. 1 (source electrodes and drain electrodes are not shown), and a cross-sectional view of a portion along the line AA ′, and FIG.
1 is a plan view of the semiconductor device shown in FIG. 1, FIG. 4 is a cross-sectional view of a process for manufacturing the semiconductor device, FIG. 5 is a plan view showing another example of this embodiment, and FIG. 6 is AA 'of FIG. FIG. 7 is a cross-sectional view of a portion along the line, FIG. 7 is a characteristic diagram illustrating the relationship between the distance (mesa region width) between adjacent trenches of the power MOSFET and the drain breakdown voltage. FIG. 8 is the present invention and the conventional power MOSF.
It is a schematic sectional drawing of the semiconductor substrate explaining the drain breakdown voltage of ET.

The semiconductor substrate 1 uses, for example, a p-type silicon semiconductor. An n-base region 2 doped with an n-type impurity is formed in the surface region of the semiconductor substrate 1. n
A p-source region 3 is formed in contact with the base region 2, one surface of which is the main surface of the semiconductor substrate 1. The region on the back surface side of the semiconductor substrate in which these regions are not formed is the p-drain region 1 '. The p-drain region 1'is n
It has a low concentration drain drift region 1 ″ (having a lower concentration than the drain region 1 ′) in contact with the base region 2. A plurality of elongated trenches 10 are formed from the main surface of the semiconductor substrate 1 toward the inside. The trench 10 extends from the main surface where the source region 3 is formed to a predetermined depth of the low concentration drain drift region 1 ″. That is,
The bottom surface of the trench 10 is formed in the drain region 1 '. A gate insulating film 4 such as a silicon oxide film formed by thermal oxidation is formed on the sidewall of the trench 10. Although the gate insulating film 4 is formed substantially up to the opening end of the trench 10, it may be formed below the main surface of the semiconductor substrate 1 depending on the etching method.

Trench 10 covered with gate insulating film 4
A gate electrode 5 made of polysilicon or the like is embedded in the. The surface of the polysilicon gate 5 is lower than the main surface of the semiconductor substrate 1. The distance between the surface of the polysilicon gate 5 and the main surface of the semiconductor substrate 1 is about 0.
It is 2 μm or more. However, it is formed so that an insulation distance from the surface of the polysilicon gate 5 to the source electrode 8 can be secured. The depth of the surface of the polysilicon gate 5 excluding the gate lead portion from the main surface of the semiconductor substrate 1 is formed to be shallower than the junction depth of the source / base junction portion.
Surface of polysilicon gate 5 and polysilicon gate 5
The thickness of the gate insulating film 4 exposed from the
A silicon nitride film 7 having a thickness of about 100 nm is formed, and an interlayer insulating film 6 such as BPSG having a high reflow property is formed on the silicon nitride film 7. The interlayer insulating film 6 is reflowed to have its surface flattened and completely embedded in the trench 10.

As shown in FIG. 2, in the source / base / drain regions between the trenches 10, the n ⁺ high-concentration contact region 2 ′ of the base region 2 in the middle is formed at a plurality of points on the main surface of the semiconductor substrate 1. Exposed. That is, the source region 3 and the contact region 2'are alternately arranged on the main surface of the semiconductor substrate 1. A source electrode 8 electrically connected to the base region 2 and the source region 3 is formed thereon. As shown in FIG. 3, the interlayer insulating film 6 is formed almost only on the trench 10 to expose the source region 3 and the contact region 2 ', and the source electrode 8 is deposited thereon. . Further, the polysilicon gates 5 embedded in the respective trenches 10 are wired so as to be electrically connected to each other, and the wired polysilicon gates 5 are formed on the main surface of the semiconductor substrate 1. It is electrically connected to the electrode 5 '. A lead wire 5 ″ is connected to the gate lead electrode 5 ′. The source lead electrode 8 is made of, for example, aluminum, and a portion facing the source region 3 and the contact region 2 is T.
A barrier metal layer such as an iW film may be interposed. In addition, the back surface of the semiconductor substrate 1 has a drain region 1 ′.
A drain electrode 9 electrically connected to is formed. In addition, the distance d between adjacent trenches (width of mesa region)
Is 1.5 μm or less.

In this embodiment, since the gate surface is formed to be recessed from the semiconductor substrate main surface, the distance from the surface of the polysilicon gate to the semiconductor substrate main surface is substantially between the gate electrode and the source electrode. Insulation distance (0.4 to 0.5
mm). Since the insulating distance is set in the vertical direction, the remaining width of the gate insulating film 5 can be reduced, and since the contact region 2'of the base region 2 is exposed on the main surface of the semiconductor substrate 1, the source region 3 and the base region It is not necessary to form an opening (see FIG. 14) for contacting the region 2 with the source electrode 8, and the distance (d) between the trenches 5 and 5 can be reduced to the above value by that amount. Therefore, the cell pitch of the trench can be sufficiently shrunk. The silicon nitride film captures impurities such as phosphorus and boron that migrate from the reflowable insulating film to the gate electrode and stabilizes transistor characteristics.

4A to 4D are sectional views showing steps of forming the semiconductor device having the UMOS structure. The semiconductor substrate 1 is in contact with the p-drain region 1 ′ and the other surface of the drain region 1 ′ whose one surface is exposed on the back surface of the semiconductor substrate 1, and is partially exposed on the main surface of the semiconductor substrate 1 at a plurality of points. The p-source region 3 is formed in which the base region 2 and one surface are in contact with the base region 2 and the other surface is exposed on the main surface of the semiconductor substrate 1. Next, the trench 10 is formed so that the bottom surface is arranged in the drain region 1 ′ in the vertical direction from the main surface of the semiconductor substrate 1. After that, a silicon oxide film is formed on the entire main surface of the semiconductor substrate by thermal oxidation to form the gate insulating film 4. And trench 1
Inside 0, a polysilicon gate 5 is formed such that its surface is above the junction surface between the source region 3 and the base region 2 and is buried at a position lower than the main surface of the semiconductor substrate 1. Next, a silicon nitride film 7 having a film thickness of about 10 to 100 nm is formed on the main surface of the semiconductor substrate 1 including the inside of the trench 10. Further, a reflowable insulating film 6 such as a BPSG film is deposited on the silicon nitride film 7. After that, the reflowable insulating film 6 is etched by a dry etching method.

Next, the embedded reflowable insulating film 6 is formed.
Is reflowed at a temperature of about 900 ° C. The reflowable insulating film 6 is completely embedded in the trench 10. Then, the drain electrode 9 is formed on the back surface of the semiconductor substrate 1 so as to be in contact with the drain region 1 ′, and the source electrode 8 is formed on the main surface of the semiconductor substrate 1 which is in contact with the source region 3 and the base region 2 on the main surface of the semiconductor substrate 1. It is formed by a sputtering method or the like. Since the main surface of the semiconductor substrate is flatter than before, the adhesion of the electrodes is improved. Although the reflow insulating film is used as the interlayer insulating film in this embodiment, the present invention is not limited to this, and an insulating film having no reflow property may be used. However, when such an insulating film is used, it is necessary to form the insulating film by a method different from the reflowable one.

Next, a modification of this embodiment will be described with reference to FIGS. The semiconductor device having the UMOS structure shown in this modification is basically the same as the semiconductor device shown in FIG. 1, except for the insulating structure for covering the trench and the drain region. In this example, only the insulating film 6'made of a silicon oxide film or the like is buried and formed in the upper portion of the trench 10 where the gate electrode 5 is not buried. That is, no silicon nitride film is present in this semiconductor device. Therefore, it does not have the action and effect peculiar to the silicon nitride film of capturing impurities such as phosphorus and boron that migrate from the reflowable insulating film to the gate electrode and stabilizing the transistor characteristics. Further, in the drain region, a low-concentration drain drift region 1 ″ is formed between the drain region 1 ′ (high-concentration region) and the base region 2. In this modification, the gate surface is located above the main surface of the semiconductor substrate. Since it is formed so as to be recessed, the distance from the surface of the polysilicon gate to the main surface of the semiconductor substrate is substantially equal to the insulation distance between the gate electrode and the source electrode. Since the remaining width of the gate insulating film 5 can be reduced, and since the contact region of the base region is exposed on the main surface of the semiconductor substrate, an opening for contacting the source region and the base region 2 with the source electrode 8 is formed. (See FIG. 14) is not necessary, and the distance (d) between the trenches 5 and 5 can be narrowed to 1.5 μm or less.

FIG. 7 shows the results of the dependency of the drain breakdown voltage of the semiconductor device having this UMOS structure on the distance between adjacent trenches. In the figure, the vertical axis represents the drain breakdown voltage (V), and the horizontal axis represents the distance d (μm) between adjacent trenches. The black circles represent the characteristics of the p-channel (pch) UMOS (power MOSFET having a trench side surface as a channel) shown in FIG.
White circles show the characteristics of n-channel (nch) UMOS. When the reference value of the drain breakdown voltage is set to 40 V, the breakdown voltage is improved by 2 to 3 V when the distance d between adjacent trenches (width of mesa region) is set to about 1.5 μm or less from the conventional value of about 2 μm. This has the effect of reducing the on-resistance by 0.5 mΩ when the drain is designed to have the same drain breakdown voltage as the conventional one. As described above, in this embodiment, by defining the distance between the trenches, the drain breakdown voltage can be improved without sacrificing the on-resistance of the transistor.

Next, the function and effect of this embodiment will be further described with reference to FIG. FIG. 8 is a conceptual diagram of a semiconductor substrate for explaining the drain breakdown voltage of the power pch type MOSFET of the present invention and the conventional one, and a conventional one (FIG. 8 (a)) between adjacent trenches (mesa region width) and a conventional one. Fig. 9 shows an equipotential line profile of a narrower version of the invention (Fig. 8 (b)). The reason why the breakdown voltage becomes higher as the space between adjacent trenches (width of the mesa region) becomes narrower will be described with reference to this conceptual diagram. The factor that determines the breakdown voltage of the power MOSFET is the width (W) of the depletion layer extending from the main junction between the n layer of the base and the p layer of the drain. The width of the depletion layer is determined by the concentration of the semiconductor substrate, and in a substrate with a low concentration, the depletion layer extends further and the breakdown voltage increases. Also, when the depletion layer hits a conductor or a region having a different dielectric constant, the depletion layer is bent and bent (for example, the tip of the trench).
Therefore, the electric field may be partially concentrated to deteriorate the breakdown voltage. At that time, the depletion layer W2 extending to the p-layer side and n
The depletion layer W1 extending to the layer side extends so that the total carriers are the same. Usually, the base concentration is about 10 to 10 times higher than the drain concentration in the drift region, so the depletion layer W2 extending to the drain side extends about 10 to 10 times better than the depletion layer W1 extending to the base side. (FIG. 8A).

When the cell pitch is reduced (the distance between trenches is reduced), the depletion layer W1 extending to the base side
Is not much different from the case where the cell pitch is wide, but the amount of carriers confined inside the drain side is small due to the low carrier concentration on the drain side and the extremely narrow space between trenches. It is designed to extend to the outside of the trench immediately. Even when the depletion layer extends to the outside of the trench, when the cell pitch is wide (in the case of the conventional example), the termination of the depletion layer does not easily become flat, but when the cell pitch is narrow (in the case of the present invention), the depletion layer terminates. Is likely to be flat, that is, a parallel electric field is likely to occur, and local concentration of the electric field is less likely to occur. To summarize the above, when the cell pitch is narrow, the depletion layer is more likely to extend farther than when the cell pitch is wide, and the equipotential line profile in the region sandwiched by the trenches becomes sparse, reducing the concentration of the electric field. As a result, the breakdown voltage tends to improve. The depletion layer end on the base side is 0
In V, the drain side depletion layer termination portion indicates the drain bias voltage (eg, −30 V). It is considered that in this depletion layer, equipotential lines of 0 to -30 V are distributed as shown by the black line.

Further, there is a correlation between the drain breakdown voltage (Vdss) and the on-resistance (Ron). Here, a -30V power pch type MOSFET will be described as an example. Ron
The relationship between (Ω) and Vdss (V) is generally expressed by equation (1). Ron (Ω) = A × Vdss + B (1) A and the constant B in the equation (1) vary depending on the specifications of the element.
If the breakdown voltage improvement amount that is over-spec is ΔVdss, the resistance reduction effect amount is ΔRon = A × ΔVdss.
-30V power Pch type MOSFE which is taken as an example here.
Regarding T, A and B are experimentally A = 1.7E-4 (Ω /
V) and B = -1.3E-4 (Ω) are obtained. If the breakdown voltage improvement due to the narrowing of the trench cell pitch is set to about 2.4 V, the Ron reducing effect is ΔRon = 1.7.
E-4 x 2.4 = 4.1 E-4 (Ω) = 0.41 (m
Ω).

Next, a second embodiment will be described with reference to FIGS. 9 is a cross-sectional view of a semiconductor device having a UMOS structure, FIG. 10 is a perspective view of a semiconductor substrate in which the electrode display shown in FIG. 9 is omitted, FIG. 11 is a plan view of the semiconductor device shown in FIG. 9, and FIG. FIG. 3 is a cross-sectional view showing the entire semiconductor substrate. The semiconductor substrate 21 uses, for example, a p-type silicon semiconductor. An n-base region 22 doped with n-type impurities is formed in the surface region of the semiconductor substrate 21. n-
A p-source region 23 having one surface serving as the main surface of the semiconductor substrate 21 is formed in contact with the base region 22. A region on the back surface side where these regions are not formed is a p-drain region 21 '. A plurality of elongated trenches 20 are formed from the main surface of the semiconductor substrate 21 toward the inside.
The trench 20 reaches the predetermined depth of the drain region 21 ′ from the main surface where the source region 23 is formed. That is, the bottom surface of the trench 20 is formed in the drain region 21 '. On the sidewall of the trench 20, for example,
A gate insulating film 24 such as a silicon oxide film formed by thermal oxidation is formed. The gate insulating film 24 is
From the sidewall of the trench 20 to the semiconductor substrate 21 around the trench
It extends slightly above the main surface of. The distance from the open end of the trench 20 in the extended portion to the tip is 0 to 0.3 μm.
It is about m.

Trench 2 covered with gate insulating film 24
A gate 25 made of polysilicon or the like is embedded in 0. The surface of the buried polysilicon gate 25 is lower than the main surface of the semiconductor substrate 21. The distance between the surface of polysilicon gate 25 and the main surface of semiconductor substrate 21 is 0.2 μm or more. The polysilicon gate 25 excluding the gate lead portion is formed to be shallower than the junction depth of the source / base junction portion. An interlayer insulating film 26 such as BPSG having a high reflow property is formed on the surface of the polysilicon gate 25 and the surface of the gate insulating film 24 exposed from the polysilicon gate 25. The interlayer insulating film 26 is reflowed and has a rounded surface.

As shown in FIG. 10, in the source / base / drain regions between the trenches 20, the n ⁺ high-concentration contact region 22 ′ of the base region 22 in the middle is formed at a plurality of locations on the main surface of the semiconductor substrate 21. Exposed. That is,
Source regions 23 and contact regions 22 'are alternately arranged on the main surface of the semiconductor substrate 21. A source electrode 28 electrically connected to the base region 22 and the source region 23 is formed thereon. As shown in FIG. 11, the interlayer insulating film 26 is formed almost only on the trench 20, the source region 23 and the contact region 22 'are exposed, and the source electrode 28 is deposited on these. .
Further, the polysilicon gates 25 embedded in the respective trenches 20 are wired so as to be electrically connected to each other, and the wired polysilicon gates 25 are formed on the main surface of the semiconductor substrate 21. Electrode 2
5'is electrically connected. Gate extraction electrode 2
A lead wire 25 ″ is connected to 5 ′. The source electrode 28 is made of, for example, aluminum, and has a source region 2
3 and a portion facing the contact region 22 'are made of TiW.
A barrier metal layer such as a film may be interposed. In addition, the back surface of the semiconductor substrate 21 has the drain region 2
A drain electrode 29 electrically connected to 1'is formed (see FIG. 12). The distance d (mesa region width) between the adjacent trenches 25 is 1.5 μm or less.

In this embodiment, since the gate surface is formed so as to be recessed from the main surface of the semiconductor substrate, the distance from the trench opening end to the tip portion of the extended portion of the gate insulating film covered with the interlayer insulating film. And the sum of the distances from the polysilicon gate surface to the main surface of the semiconductor substrate is substantially equal to the insulation distance between the gate electrode and the source electrode. In the structure in which the opening used to electrically connect the source region and the base region to the source electrode is formed in the substrate, since the remaining width of the gate insulating film covered with the interlayer insulating film is a substantial insulating distance, In this embodiment, the remaining width of the gate insulating film can be reduced by keeping the insulation distance in the vertical direction. Further, since the contact region of the base region is exposed on the main surface of the semiconductor substrate, it is not necessary to form an opening for contacting the source region and the base region with the source electrode, and the trench can be narrowed accordingly. Therefore, it becomes possible to sufficiently shrink the cell pitch by setting the distance between trenches to 1.5 μm or less. In addition, since the surface of the interlayer insulating film is rounded, the adhesion of the source electrode is enhanced, and a structure having high mechanical strength without step breakage can be obtained.

Next, a process of manufacturing the semiconductor device having the UMOS structure will be described. The semiconductor substrate 21 made of silicon or the like is in contact with the other surface of the p-drain region 21 'and the drain region 21' whose one surface is exposed on the back surface, and is partially exposed on the main surface of the semiconductor substrate 21 at a plurality of locations. An n-base region 22 and a p-source region 23 having one surface in contact with the base region 22 and the other surface exposed to the main surface of the semiconductor substrate 21 are formed. It is also possible to adopt a process of forming the source after forming the trench. Next, the bottom surface of the semiconductor substrate 21 in the vertical direction extends from the main surface to the drain region 2.
A trench 20 is formed so as to be arranged in 1 '. After that, a gate insulating film 24 such as a silicon oxide film is formed on the main surface of the semiconductor substrate 21 including the sidewalls of the trench 20. Next, a polysilicon film including the inside of the trench 20 is deposited on the main surface of the semiconductor substrate 21, and this is patterned so that the surface of the source region 2 is inside the trench 20.
A gate electrode 25 made of polysilicon is formed so as to be located above the junction surface between the semiconductor substrate 21 and the base region 22 and below the main surface of the semiconductor substrate 21. Polysilicon gate 2 embedded in the trench 20
A reflowable insulating film such as a BPSG film is deposited on the gate insulating film 24 and the gate insulating film 24.

A mask having a predetermined pattern made of photoresist is arranged on the reflowable insulating film 26, and the insulating film 26 is etched by anisotropic etching using this mask to form the polysilicon gate 2 in the trench 20.
A reflowable insulating film 26 is patterned on the gate insulating film 24 in the portion where the trenches 5 are not buried and in the peripheral portion of the trench. The mask covers the trench 20 and its periphery. The patterned insulating film 26 is formed according to the mask. Next, after removing the photoresist mask, the reflowable insulating film 26 patterned by etching is reflowed at 900 ° C. or higher to completely fill the trench 20 with the reflowable insulating film 26. The surface can be rounded (see FIG. 10). Next, the drain electrode 29 is formed on the back surface of the semiconductor substrate 21 so as to be in contact with the drain region 21 ', and the source electrode 28 is formed on the main surface side so as to be in contact with the base region 22 and the source region 23 (see FIG. 9). In this embodiment, shrinking of the cell pitch can be sufficiently achieved, and refilling can be performed by reflow even if there is misalignment in contact exposure (patterning process of a reflowable insulating film).

FIG. 12 is a sectional view of a semiconductor substrate showing a completed semiconductor device of this embodiment. Next, FIG.
The third embodiment will be described with reference to FIG. Figure 13 shows UMO
It is sectional drawing and the top view of the semiconductor device of S structure. This sectional view corresponds to a portion along the line AA 'in the plan view. Since the semiconductor device of this embodiment has the opening for contacting the source region and the base region with the source electrode, it is difficult to make the distance d between the trenches a predetermined width by that amount, and it is very careful. It is necessary to proceed with the process while paying attention to. UMO formed on the semiconductor substrate of this embodiment
S (vertical power MOSFET in which a gate electrode is embedded in the trench and the side surface of the trench serves as a channel region)
Has a plurality of trenches in which a gate electrode such as polysilicon is embedded, and the distance between the trenches is about 1.5 or less, and the diameter of the trench is about 0.5 μm.

For the semiconductor substrate 31, for example, a p-type silicon semiconductor is used. An n-base region 32 doped with n-type impurities is formed in the surface region of the semiconductor substrate 31. The semiconductor substrate 31 has one surface on the n-base region 32.
A p-source region 33 that serves as the main surface of is formed. A region on the back surface side where these regions are not formed is a p-drain region 31 '. A plurality of trenches 30 are formed from the main surface of the semiconductor substrate 31 toward the inside. The trench 30 reaches the predetermined depth of the p-drain region 31 ′ from the main surface where the p-source region 33 is formed. A gate insulating film 34 such as a silicon oxide film formed by thermal oxidation is formed on the sidewall of the trench 30. The gate insulating film 34 is formed in the trench 3
0 side wall and extends on the main surface of the semiconductor substrate 31 around the trench. The distance between adjacent trenches is 1.5 μm
It is below the level. A gate 35 made of polysilicon or the like is embedded in the trench 30 covered with the gate insulating film 34. The surface of the polysilicon gate 35 is
It forms almost the same surface as the main surface of the semiconductor substrate 31. An interlayer insulating film 36 such as a silicon oxide film formed by CVD is deposited and formed on the surface of the polysilicon gate 35 and the surface of the gate insulating film 34. Further, on the main surface of the semiconductor substrate 31, the interlayer insulating film 36 is provided between the trenches 30.
An opening 37 that penetrates through and reaches the base region 34 is formed.

The openings 37 are formed between the trenches 30 on the main surface of the semiconductor substrate 31, for example, in a zigzag pattern. Further, the polysilicon gates 35 embedded in the respective trenches 30 are wired so as to be electrically connected to each other, and the wired polysilicon gates 35 are
Gate extraction electrode 3 formed on the main surface of the semiconductor substrate 31
5'is electrically connected. In this state, the main surface of the semiconductor substrate 31 is covered with the interlayer insulating film 36 except for the opening 37 and the gate lead electrode 35 '. A source electrode 38 is formed on the interlayer insulating film 36 so as to be electrically insulated from the gate lead electrode 35 '. The source electrode 38 is also embedded inside the opening 37 and the opening 3 is formed.
7. Source region 33 and base region 3 exposed inside
2 is electrically connected. The source electrode 38 is made of, for example, aluminum, and a barrier metal layer is interposed (not shown) at a portion facing the source region 33 and the base region 32. The back surface of the semiconductor substrate 31 is
A drain electrode 39 electrically connected to the drain region 31 'is formed. With this structure, the trench 30 is formed when the opening 37 is formed by etching the interlayer insulating film 36 in order to maintain the insulation between the polysilicon gate 35 and the source electrode 38 and as a countermeasure against the misalignment margin of the exposure technique. There is a distance from the open end of the opening to the end of the opening 37.

In this embodiment, the distance (mesa region width) between adjacent trenches of a vertical power MOSFET having a trench side surface as a channel is set to 1.5 μm or less, so that the on-resistance of the transistor is sacrificed. The drain breakdown voltage can be improved without doing so. The power MOSFET having a channel on the side surface of the trench according to the present invention, in which the distance between adjacent trenches is 1.5 μm or less, can be applied to any conventionally known type.

[0032]

As described above, according to the present invention, the distance (mesa region width) between adjacent trenches formed in the vertical power MOSFET having the trench side surface as the channel is 1.5 μm.
Since it is configured as follows, it is possible to reduce the on-resistance without sacrificing the drain breakdown voltage of the transistor.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device having a UMOS structure according to a first embodiment of the present invention.

2 is a perspective view of a semiconductor device having a UMOS structure (illustration of electrodes formed above and below a semiconductor substrate is omitted) shown in FIG. 1 and a cross-sectional view of a portion along line AA ′ of this perspective view.

3 is a partially transparent plan view of the semiconductor device having the UMOS structure shown in FIG.

FIG. 4 is a partial perspective sectional view illustrating a process of the semiconductor device having the UMOS structure shown in FIG.

FIG. 5 is a cross-sectional view of a semiconductor device having a UMOS structure according to the first embodiment of the present invention (display of electrodes formed above and below a semiconductor substrate is omitted).

6 is a cross-sectional view of the semiconductor device having the UMOS structure shown in FIG.

FIG. 7 is a characteristic diagram showing the relationship between the distance between adjacent trenches (mesa region width) (d) of the semiconductor device and the drain breakdown voltage.

FIG. 8 is a schematic cross-sectional view of a semiconductor substrate for explaining the drain breakdown voltage of a semiconductor device (power MOSFET) of the present invention and a conventional UMOS structure.

FIG. 9 is a sectional view of a semiconductor device having a UMOS structure according to a second embodiment of the present invention.

10 is a perspective view of the semiconductor device having the UMOS structure shown in FIG. 9 (illustration of electrodes formed above and below a semiconductor substrate is omitted).

11 is a partial perspective plan view of the semiconductor device having the UMOS structure shown in FIG. 9 as seen from above.

12 is a cross-sectional view showing the entire semiconductor substrate of the semiconductor device shown in FIG.

FIG. 13 is a sectional view and a plan view of a semiconductor device having a UMOS structure according to a third embodiment of the present invention (the plan view does not show the electrodes formed above and below the semiconductor substrate, and the cross section is the plan view). The portion along the line AA ′ in FIG.

FIG. 14 is a sectional view and a plan view of a conventional semiconductor device having a UMOS structure (the plan view does not show electrodes formed above and below a semiconductor substrate, and the cross section is taken along the line AA ′ of the plan view). Represents the part).

[Explanation of symbols]

1, 21, 31, 101 ... Semiconductor substrate, 1 ', 2
1 ', 31', 101 '... Drain region, 1 "...
-Low-concentration drain drift region, 2, 22, 32, 10
2 ... Base region, 3, 23, 33, 103 ... Source region, 4, 24, 34, 104 ... Gate insulating film, 5, 25, 35, 105 ... Gate electrode (polysilicon gate) ) 5 ', 25', 105 '... Gate extraction electrode, 5 ", 25" ... Lead, 6, 6',
26, 36, 106 ... Insulating film, 7 ... Silicon nitride film, 8, 28, 38, 108 ... Source electrode,
9, 29, 39, 109 ... Drain electrodes 10, 2
0, 30, 110 ... Trench, 37, 107 ...
Opening.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takaka Ino             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside (72) Inventor Akihiko Osawa             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside (72) Inventor Takeshi Ota             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside (72) Inventor Junji Takahashi             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside F-term (reference) 4M104 AA01 BB01 BB02 BB36 CC05                       DD02 FF18 FF22 GG09 GG10                       GG14 GG18 HH09 HH12 HH14                       HH20

Claims (7)

[Claims] 1. A semiconductor substrate, a drain region formed on the semiconductor substrate and having one surface exposed at the back surface of the semiconductor substrate, and a drain region formed on the semiconductor substrate, contacting the other surface of the drain region, and partially A base region exposed at the semiconductor substrate main surface at a plurality of locations; a source region formed on the semiconductor substrate, one surface contacting the base region and the other surface exposed at the semiconductor substrate main surface; A trench formed so that the bottom surface is arranged in the drain region in the vertical direction from the main surface of the substrate, a gate insulating film formed substantially only on the sidewall of the trench, and a surface embedded in the trench. A gate electrode formed above the junction surface between the source region and the base region and lower than the main surface of the semiconductor substrate; A drain electrode formed to be in contact with a drain region; and a source electrode formed on the main surface of the semiconductor substrate and in contact with the source region and the base region, wherein the trench is formed in plural at predetermined intervals. The semiconductor device, wherein the distance between the adjacent trenches is 1.5 μm or less. 2. An insulating film formed on the surface of the gate electrode, a portion of the trench where the gate electrode is not buried, and the gate insulating film exposed in the peripheral portion of the trench. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, further comprising a reflowable insulating film embedded in a portion of the trench where the gate electrode is not embedded. 4. A gate insulating film exposed between the reflowable insulating film and the surface of the gate electrode and between the reflowable insulating film and a portion of the trench where the gate electrode is not buried. The semiconductor device according to claim 3, wherein a silicon nitride film is formed. 5. A semiconductor substrate, a drain region formed on the semiconductor substrate and having one surface exposed on the back surface of the semiconductor substrate, and a base region formed on the semiconductor substrate and in contact with the other surface of the drain region. A source region formed on the semiconductor substrate, one surface of which is in contact with the base region and the other surface of which is exposed to the semiconductor substrate main surface, and a bottom surface in the vertical direction from the semiconductor substrate main surface in the drain region. A trench formed so as to be disposed; a gate insulating film formed on the sidewall of the trench and extending to a peripheral portion thereof; and a trench filled in the trench, the surface of which is the source region and the base region. A gate electrode formed above the junction surface of the semiconductor substrate and lower than the main surface of the semiconductor substrate, and in contact with the drain region on the back surface of the semiconductor substrate. A drain electrode formed, and a source electrode formed on the main surface of the semiconductor substrate and in contact with the source region and the base region, wherein the trench is formed in plural at predetermined intervals, and between the adjacent trenches. The semiconductor device is characterized in that the distance is less than 1.5 μm. 6. The semiconductor device according to claim 5, wherein an opening is formed in the main surface of the semiconductor substrate, and the source electrode is in contact with the source region and the base region through the opening. apparatus. 7. A drain region of which one surface is exposed to the back surface of the semiconductor substrate, a base region which is in contact with the other surface of the drain region and is partially exposed to the main surface of the semiconductor substrate at a plurality of locations, and one surface of the semiconductor substrate. Forming a source region which is in contact with the base region and the other surface of which is exposed to the semiconductor substrate main surface, and a plurality of bottom surfaces are arranged in the drain region in the vertical direction from the semiconductor substrate main surface. Forming trenches such that the distance between adjacent trenches is 1.5 μm or less; forming a gate insulating film substantially only on the trench sidewalls; A step of forming a gate electrode so as to be buried above a junction surface with the base region and lower than the main surface of the semiconductor substrate; A method of manufacturing a semiconductor device, comprising: forming a drain electrode so as to be in contact with a rain region; and forming a source electrode on the main surface of the semiconductor substrate in contact with the source region and the base region.