JP2003101021A - Field effect transistor and method of manufacturing the same - Google Patents

Abstract

(57) [Summary] [Technical object] A technique for enhancing the avalanche breakdown withstand capability of a field effect transistor. According to a MOSFET of the present invention, a buried region for forming a first PN junction together with a body region is disposed below a body region.
When a high voltage is applied to the MOSFET 1, the first PN junction 85 undergoes avalanche breakdown, and current flows through the first PN junction 85. The first PN junction 85 is located on the bottom surface of the body region 32, Even if the area is large and a large current flows through the first PN junction 85, the current flows uniformly throughout the first PN junction 85, and current concentration hardly occurs. Therefore, element destruction due to current concentration hardly occurs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly to a field effect transistor having high breakdown voltage and low resistance.

[0002]

2. Description of the Related Art Conventionally, a field effect transistor has been used as a power control element which allows a current to flow in the thickness direction of a substrate. With reference to FIG. 39, reference numeral 105 is an example of a conventional field effect transistor, which includes a silicon single crystal substrate 11
Have one. A drain layer 112 formed by epitaxial growth is arranged on the surface of the single crystal substrate 111.

A silicon single crystal substrate 111 is heavily doped with N-type impurities, and a drain electrode film 148 is formed on the back surface thereof. Further, the drain layer 112 is lightly doped with N-type impurities, and a P-type base region 154 is formed near the surface thereof.

A source region 161 is further formed in the base region 154 by diffusing N-type impurities from the surface thereof.

Reference numeral 110 is a channel region located between the edge portion of the source region 161 and the edge portion of the base region 154. A gate insulating film 126 and a gate electrode film 127 are arranged in this order above the channel region 110. An interlayer insulating film 141 is formed on the surface and side surfaces of the gate electrode film 127, and a source electrode film 144 is arranged on the surface.

The base region 154 as described above is arranged in an island shape near the surface of the drain region 112, and one base region 154 and the source region 161 and the channel region 110 arranged in the base region 154. And 1
Individual cells 101 are formed.

FIG. 40 is a plan view showing the surface of the drain region 112, in which a plurality of rectangular cells 101 are arranged in a matrix. When this field effect transistor 105 is used, the source electrode film 144 is placed at the ground potential,
A positive voltage is applied to the drain electrode film 148, and a gate voltage (positive voltage) higher than the threshold voltage is applied to the gate electrode film 127.
Is applied, an N-type inversion layer is formed on the surface of the P-type channel region 110, and the source region 161 and the conductive region 111 are formed.
And are connected by the inversion layer, and the field effect transistor 105 becomes conductive.

When a voltage below the threshold voltage (eg, ground potential) is applied to the gate electrode film 127 from that state, the inversion layer disappears and the field effect transistor 105 is cut off.

In the field effect transistor 105 having the above structure, when the voltage applied to the drain electrode film 148 is increased, the PN of the base region 154 and the drain region 112 is increased.
Avalanche breakdown occurs at the bond interface. In this case, the current flows to the side of the cell 101 arranged in the peripheral portion of one element, and the current tends to concentrate in a portion having a small area, so that the element is easily broken. .

[0010]

SUMMARY OF THE INVENTION The present invention was created in order to solve the above-mentioned disadvantages of the prior art, and an object thereof is to provide a field effect transistor having a high breakdown voltage and a low resistance.

[0011]

In order to solve the above-mentioned problems, the invention according to claim 1 is such that an impurity of the second conductivity type is diffused from the drain layer of the first conductivity type and the surface side of the drain layer. And a diffusion region having a diffusion depth shallower than the thickness of the drain layer, and a diffusion region of the first conductivity type from the surface side of the body region. And a source region of the first conductivity type disposed inside the body region,
A channel region which is a part of the body region and is located between an edge of the body region and an edge of the source region;
At least the gate insulating film arranged on the surface of the channel region, and a gate electrode film arranged on the surface of the gate insulating film, the surface of the channel region is changed by the voltage applied to the gate electrode film. When inverted, a field effect transistor in which the drain layer and the source region located outside the channel region are electrically connected, and the field effect transistor is located in the drain layer and is in contact with the body region. The impurity concentration of a portion of the drain layer that is in contact with the body region is configured such that the buried region has the highest impurity concentration. The invention according to claim 2 is the field effect transistor according to claim 1, wherein the outer peripheral edge portion of the buried region is located inside the outer peripheral edge portion of the body region. The invention according to claim 3 is the field-effect transistor according to claim 1 or 2, further comprising a semiconductor layer disposed on a surface of the drain layer opposite to the body region. The invention according to claim 4 is the field-effect transistor according to claim 3, wherein the substrate body is of the first conductivity type. A fifth aspect of the present invention is the field-effect transistor according to the third aspect, wherein the substrate body is of the second conductivity type. The invention according to claim 6 is the field-effect transistor according to claim 1, further comprising a Schottky electrode arranged on a surface of the drain layer opposite to the body region. A Schottky junction was formed between the Schottky electrode and the drain layer. The invention according to claim 7 is formed by diffusing impurities of the second conductivity type from the first conductivity type drain layer and the surface side of the drain layer, and the diffusion depth thereof is the thickness of the drain layer. And a diffusion region formed by diffusing impurities of the first conductivity type from the surface side of the body region, the first conductivity type being disposed inside the body region. Source area of
A channel region which is a part of the body region and is located between an edge of the body region and an edge of the source region;
At least the gate insulating film arranged on the surface of the channel region, and a gate electrode film arranged on the surface of the gate insulating film, the surface of the channel region is changed by the voltage applied to the gate electrode film. When inverted, a field effect transistor in which the drain layer and the source region located outside the channel region are electrically connected, and the field effect transistor is located in the drain layer and is in contact with the body region. Of the PN junction formed by the body region and a region of the first conductivity type having a buried region and located outside the body region, a PN junction formed by the buried region and the body region It is configured to have the lowest breakdown voltage. The invention according to claim 8 is the first
A drain layer of conductivity type, a body region of second conductivity type arranged in the drain layer, a source region of first conductivity type arranged in the body region, an edge of the body region and the source region. A gate insulating film disposed on the surface of the body region between the edge and a gate electrode film disposed on the surface of the gate insulating film. When the surface of the body region between the edge of the body region and the edge of the source region is inverted,
A method of manufacturing a field effect transistor, wherein a drain layer located outside the body region and the source region are electrically connected to each other.
Diffusing conductivity type impurities into the drain layer to form a low resistance region composed of a first conductivity type diffusion region;
Impurities of the second conductivity type are diffused into at least the low resistance region from the surface side of the drain layer so as to be shallower than the bottom surface of the low resistance region, and the second conductivity type is provided on the surface side of the low resistance region and its periphery. And forming the body region composed of the diffusion region.

The field effect transistor of the present invention has a drain layer. The drain layer is a layer that is electrically connected to the source region when a voltage is applied to the gate electrode film to invert the channel region and a current flows between the source region and the drain layer. Therefore, it is generally composed of a first conductivity type epitaxial layer or an epitaxial layer and an impurity region diffused therein.

The drain layer of the present invention has a buried region located between the bottom surface of the body region and the substrate body and in contact with the body region. The drain layer is in contact with the body region. The impurity concentration of is set so that the impurity concentration of the buried region is the highest.

Therefore, of the PN junctions formed by the drain layer and the body region, the PN junction formed by the buried region and the body region has the lowest breakdown voltage. Therefore, avalanche breakdown occurs at the PN junction formed by the buried region and the body region, and a current flows through this PN junction.

If the area of the PN junction formed by the buried region and the body region is large, even if avalanche breakdown occurs in the PN junction and a large current flows, the current spreads throughout the large area PN junction. The current is less likely to be concentrated, and the element breakdown due to the current concentration is less likely to occur. Therefore, element breakdown is less likely to occur as compared with the conventional case in which avalanche breakdown occurs around the base region and the current is concentrated at one location.

In the present invention, the substrate body may form a MOSFET having the same first conductivity type as the drain layer, or an IGBT having a second conductivity type opposite to the drain layer. Good.

Further, according to the method of manufacturing a field effect transistor of the present invention, impurities of the first conductivity type are diffused into the drain layer from the surface side of the drain layer to form a low resistance formed of the diffusion region of the first conductivity type. After forming the region, the second conductivity type impurity is diffused into the low resistance region and its periphery from the surface side of the drain layer so as to be shallower than the bottom surface of the low resistance region.
A body region composed of a diffusion region of the second conductivity type is formed on the surface side of the low resistance region and its periphery. As a result, the low resistance region is in contact with the body region and is buried below the body region. Here, if the impurity concentration of the low resistance region is increased and the breakdown voltage of the PN junction formed by the low resistance region and the body region is lowered, the buried region in the field effect transistor of the present invention is formed in this low resistance region. You can

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. Hereinafter, a method for manufacturing a MOSFET that is a field effect transistor according to an embodiment of the present invention will be described. In the following, the first conductivity type impurities are N type impurities, and the second conductivity type impurities are P type impurities.

First, a substrate provided with an N ⁺ type substrate body made of silicon and an N ⁻ type epitaxial layer formed on the surface thereof is prepared. A plurality of elements described later can be formed on the substrate. 1 to 13 are sectional views for explaining the manufacturing process of one of the plurality of elements. In the figure, reference numeral 10 indicates a substrate, reference numeral 11 indicates a substrate body, and reference numeral 12 indicates an epitaxial layer.

Next, when the substrate 10 is subjected to thermal oxidation treatment, as shown in FIG.
As shown in, a thermal oxide film 13 made of a silicon oxide film is formed on the surface of the epitaxial layer 12. Next, a resist solution is applied to the surface of the thermal oxide film 13 to form a resist film, and then patterning is performed. Reference numeral 61 in FIG. 3 indicates a patterned resist film.

FIG. 31 shows a plan view of one element in the state of FIG. FIG. 3 shows a sectional view taken along the line AA of FIG. As shown in FIG. 31, the resist film 61 has a plurality of ring-shaped openings 51 formed by patterning, and the ring-shaped openings 51 are arranged concentrically. The outermost peripheral opening 51 is arranged such that its outer edge portion is located inside by a predetermined distance from the edge defining one element, and the innermost peripheral opening 51 is arranged so as to surround the central portion of one element. Has been done.

Next, using the resist film 61 as a mask, the thermal oxide film 13 exposed on the bottom surface of the opening 51 of the resist film 61 is etched to remove the resist film 61. The state is shown in FIG. Reference numeral 52 in the drawing denotes an opening of the thermal oxide film 13 formed by etching the thermal oxide film 13, and the epitaxial layer 12 is exposed from the bottom of the opening 52.

Next, when the surface of the thermal oxide film 13 is irradiated with a P-type impurity such as B, the thermal oxide film 13 serves as a mask and the P-type impurity is implanted into the bottom surface of the opening 52. As shown in FIG. High concentration layer 14 is formed.

Then, when the substrate 10 is heat-treated, as shown in FIG. 6, the P-type high-concentration layer 14 is diffused to form a guard ring region 15 composed of a P-type diffusion region, and at the same time, the guard ring region is formed. 15 The surface is covered with a thermal oxide film. The guard ring region 15 is formed in the same planar shape as the opening 51 of the resist film 61 described above.

In FIG. 6, from the edge defining one element,
The area up to a position further inside by a predetermined distance from the inner end of the innermost guard ring area 15 is referred to as a peripheral area, and is denoted by reference numeral 7
2 shows. In addition, a region inside the peripheral region 72 in one element is referred to as a cell region and is denoted by reference numeral 71.

Next, as shown in FIG. 7, a patterned resist film 66 is formed on the surface of the thermal oxide film 13. The resist film 66 has openings 4 that cover the entire cell region 71.
4 are provided.

When the thermal oxide film 13 is etched using the resist film 66 as a mask, the thermal oxide film 13 formed in the cell region 71 is removed and the surface of the epitaxial layer 12 in the cell region 71 is exposed. After that, the resist film 66 is removed. The state is shown in FIG. Then, when the substrate 10 is subjected to thermal oxidation treatment, a thermal oxide film 16 made of a silicon oxide film is formed on the surface of the epitaxial layer 12 in the cell region 71 as shown in FIG.

Next, as shown in FIG. 10, the thermal oxide film 16,
A patterned resist film 62 is formed on the surface of 13. The resist film 62 has openings 5 in the cell region 71.
3 and has a groove 47 in the peripheral region 72. The planar shape of the resist film 62 is shown in FIG. Note that FIG. 10 corresponds to the sectional view taken along the line BB of FIG. 32.

Of the opening 53 and the groove 47, the opening 53 is
Two elongated openings 73 ₁ and 7 3 each formed in an elongated shape
3 _2, one of the connecting opening 75 and a plurality of branch openings 7
4 and.

The ends of a plurality of branch-shaped openings 74 are connected to the two trunk-shaped openings 73 ₁ and 73 ₂ . The connection opening 75 and the respective branch opening 74, the stem opening 73 _1, 73 ₂
Is perpendicular to. The surface of the thermal oxide film 16 is exposed at the bottom of the opening 53.

On the other hand, the groove 47 is formed in a ring shape, the inner end of which is located outside the outer edge of the outermost guard ring region 15, and is arranged concentrically with the guard ring region 15. ing. The surface of the thermal oxide film 13 is exposed at the bottom of the groove 47.

Next, the thermal oxide films 16 and 13 are etched using the resist film 62 as a mask. Then, the opening 53
And the thermal oxide films 16 and 13 on the bottom surface of the groove 47 are removed.
As shown in FIG. 5, the thermal oxide film 16 in the cell region 71 is formed with openings 54 having the same pattern as the openings 53 in the resist film 62, and the thermal oxide film 13 in the peripheral region 72 is formed with grooves 50 having the same pattern as the grooves 47. To be done. Bottom of opening 54 and groove 50
The epitaxial layer 12 is exposed at the bottom of the.

The resist film 62 is removed, and the thermal oxide film 16,
The element formation surface is irradiated with N-type impurities using 13 as a mask. Here, phosphorus is used as the N-type impurity, and the dose amount is 2 × 10 ¹³ cm ^-2 . Then, the N-type impurities are removed from the epitaxial layer 1 at the bottom of the opening 54 and the groove 50.
2, and the opening 54 as shown in FIG.
At the bottom of the trench 50 and the trench 50, the first implantation region 18 of N-type impurity is formed.
Is formed.

Next, the substrate 10 is heat treated. here,
The heat treatment is performed at a temperature of 1100 ° C. for 200 minutes. Then, as shown in FIG. 13, the low-resistance region 20 is formed by diffusing the impurities of the first implantation region 18 and diffusing the N-type impurities in the cell region 71, and on the surface side of the outer peripheral portion of the substrate 10, Outermost peripheral conductive region 5 formed of N-type impurity diffusion region
And the cell region 71 and the peripheral region 72 are formed.
A thermal oxide film is formed on the low resistance region 20 and the outermost peripheral conductive region 5 are covered with the thermal oxide film.

Then, a patterned resist film 67 is formed on the surfaces of the thermal oxide films 16 and 13 as shown in FIG. The resist film 67 has an opening 59 that is larger than the low resistance region 20 in the cell region 71.
Are arranged so that the low resistance region 20 is located inside thereof, and the peripheral region 72 has a groove 43 arranged on the outermost peripheral conductive region 5.

When the thermal oxide film 16 is etched using the resist film 67 as a mask, the thermal oxide films 16 and 13 located on the bottom surface of the opening 59 and the bottom surface of the groove 43 are removed, and in the peripheral region 72, the outermost peripheral conductive region is formed. 5 is exposed, and in the cell region 71, the epitaxial layer 12 and the low resistance region 20 are exposed. After that, the resist film 67 is removed. A sectional view of the cell region 71 in that state is shown in FIG.
Note that FIGS. 15 to 27 are cross-sectional views of the manufacturing process in the cell region 71.

Next, an N-type impurity is applied to the element formation surface. Here, phosphorus is used as the N-type impurity, and the dose amount is 2 × 10 ¹² cm ⁻² . Then, the peripheral area 7
2, N-type impurities are implanted into the outermost peripheral conductive region 5,
Since the guard ring region 15 is covered with the thermal oxide film 13, N-type impurities are not implanted. On the other hand, the cell area 71
In the low resistance region 20 and the epitaxial layer 12, N
A type impurity is implanted, and as shown in FIG. 16, a second implantation region 23 is formed by implanting an N type impurity in the epitaxial layer 12 in the low resistance region 20 and its peripheral region.

Next, the substrate 1 is formed under the condition that a thermal oxide film is not formed.
0 is heat-treated. Here, the temperature in the nitrogen atmosphere is 1100.
Heat treatment is performed for 500 minutes under the condition of ° C. Then, the impurities contained in the second implantation region 23 are not included in the epitaxial layer 1
2 and the low resistance region 20.

By the way, the impurities contained in the second implantation region 23 are N-type, and the epitaxial layer 12 and the low resistance region 20 are also N-type. Have the same conductivity type. Further, even when the low resistance region 20 is formed, the first implantation region 18 is formed.
Since the impurity diffused from is N type and the epitaxial layer 12 is also N type, the diffused impurity and the diffused impurity of the object to be diffused have the same conductivity type also in this case.

In these cases, since the PN junction is not formed between the diffused region formed by the diffused impurities and the diffused object, the diffused impurities and the diffused region have the same conductivity type. If, then the diffusion depth cannot be originally specified. Therefore, in this case, the position where the impurity concentration of the diffusion region is double the impurity concentration of the object to be diffused is defined as the diffusion depth of the diffusion region.

At this time, when the second implantation region 23 is diffused, the first high concentration region 24 is formed on the low resistance region 20 and the second high concentration region is formed on the surface side of the epitaxial layer 12. 25 is formed.

Assuming that the diffusion depth of the low resistance region 20 is defined at the position where the impurity concentration of the low resistance region 20 is twice as high as that of the epitaxial layer 12, the diffusion depth is defined as the diffusion depth. Is shallower than the depth from the surface to the boundary surface between the epitaxial layer 12 and the substrate body 11, and the bottom surface of the low resistance region 20 is located above the bottom surface of the epitaxial layer 12.

If the diffusion concentration of the second high concentration region 25 is defined at the position where the impurity concentration of the second high concentration region 25 becomes twice as high as that of the epitaxial layer 12, the diffusion depth is defined. The diffusion depth is shallower than the diffusion depth of the low resistance region 20, and the bottom surface of the second high concentration region 25 is located above the bottom surface of the low resistance region 20.

The diffusion depth of the first high concentration region 24 is equal to the second
Assuming that the diffusion depth is the same as the diffusion depth of the high-concentration region 25, the first high-concentration region 24 is formed in the low-resistance region 20 in which the N-type impurity has already been diffused, from the second implantation region 23. Since it is configured by diffusing N-type impurities,
The impurity concentration of the high concentration region 24 of the
The concentration is higher than 5.

Then, as shown in FIG. 18, the substrate 10 is thermally oxidized to form a gate insulating film 27 made of a thermal oxide film in the first and second high concentration regions 24 and 25. next,
As shown in FIG. 19, on the entire surface of the gate insulating film 27,
The gate electrode film 28 is formed by the CVD method. Here, the gate electrode film 28 is formed by depositing polysilicon in which impurities are previously doped.

Next, after forming a resist film on the surface of the gate electrode film 28, patterning is performed to form an opening 55 described later in the cell region 71 and a groove described later in the peripheral region 72 as shown in FIG. Then, the gate electrode film 28 is exposed from the bottom of the opening 55 and the bottom of the groove. Reference numeral 63 in FIG. 20 shows a patterned resist film.

The planar shape of the resist film 63 is shown in FIG. 20 corresponds to the sectional view taken along the line CC of FIG.
In FIG. 33, reference numeral 7 indicates a groove formed in the peripheral region 72. As shown in FIG. 33, the opening 55 described above is used.
Has a comb shape similar to the opening of the resist film 65 described above in plan view, and the inner end portion thereof has the first high concentration region 24.
Are arranged so as to be located outside by a certain distance from the outer edge of the. Further, the groove 7 described above is arranged between the edge of the substrate 10 and the innermost circumference of the guard ring region 15.

When the gate electrode film 28 is etched using the resist film 63 as a mask, the opening 55 and the gate electrode film 28 on the bottom surface of the groove 7 are removed as shown in FIG.
After removing the resist film 63, the gate insulating film 27 is etched by using the gate electrode film 28 as a mask to remove the gate insulating film 27, and in the cell region 71, the resist is formed on the gate electrode film 28 and the gate insulating film 27. An opening of the same size is formed at the same position as the opening 55 of the film 63, and the first high-concentration region 24 and the outer edge portion of the first high-concentration region 24 are formed on the bottom surface of the opening so as to be constant from the outer edge portion. The second high-concentration region 25 located up to a position outside by a distance is exposed. On the other hand, in the peripheral region 72, the gate electrode film 28 exposed at the bottom of the trench 7 and the gate insulating film 27 are completely removed, and the outermost peripheral conductive region 5 and the thermal oxide film 13 are exposed.

Next, with the gate electrode film 28 and the gate insulating film 27 as a mask, P-type impurities are irradiated on the element formation surface. As shown in FIG. 22, the irradiated P-type impurity has a first high-concentration region 24 exposed on the bottom surface of the opening 56 of the gate electrode film 28 and the gate insulating film 27 and a second high-concentration region around it. And a third layer of P-type impurities on both surface sides of the first and second high-concentration regions 24 and 25.
An injection region 31 of is formed. Here, boron is used as the P-type impurity and the dose amount is 2 × 10 ¹³ cm ^-2 .

Next, the substrate 10 is heat-treated under the condition that the thermal oxide film is not formed. Here, at a temperature of 1135 ° C,
It is heat-treated for 400 minutes. Then, the third implantation region 3
One P-type impurity diffuses to form a body region 32 formed of a P-type impurity diffusion region as shown in FIG.

This P-type impurity diffuses into both the first and second high concentration regions 24 and 25, but the second high concentration region 2
The diffusion depth of the body region 32 in 5 is shallower than the diffusion depth of the second high concentration region 25. Also, the first
Since the N-type impurity concentration of the high-concentration region 24 is higher than that of the second high-concentration region 25, in the body region 32, the diffusion depth in the first high-concentration region 24 is the second high-concentration region. It becomes shallower than the diffusion depth in the concentration region 25.

Therefore, in the first high-concentration region 24, even if the P-type impurity is diffused to form the body region 32, the first high-concentration region remains below the body region 32. The edge portion of the body region 32 is laterally diffused,
It sunk into the position below the gate insulating film 27.

The body region 32 has a comb shape like the opening 55 of the resist film 63 described above in plan view, and only one body region 32 is arranged for one device. Therefore, the area occupied by the body region 32 inside one element is large.

Reference numeral 22 indicates an embedded region which is a remaining portion of the first high concentration region 22. The edge of the embedded region 22 is located inside the edge of the body region 32 and It is embedded under the region 32.

The buried region 22 is arranged along the bottom of the body region 32 having a comb shape in a plan view, and is made into a comb shape like the body region 32 in a plan view and arranged in series.

In this state, the surface of the body region 32 is exposed, and as shown in FIG. 24, a patterned resist film 64 is formed on the exposed surface of the body region 32. As shown in a plan view of FIG. 34, the resist film 64 has a comb shape in a plan view similar to the body region 32, and its outer edge portion is located inside the outer edge portion of the body region 32 by a predetermined distance. It is arranged to.

Note that FIG. 24 corresponds to a sectional view taken along the line DD of FIG. A gap 57 is formed between the outer edge of the resist film 64 and the inner end of the gate electrode film 28. The gap 57 has a ring shape in a plan view, and an outer peripheral edge thereof coincides with an edge portion of the gate electrode film 28,
The inner edge matches the edge of the resist film 64. In the cell region 71, the body region 32 is exposed on the bottom surface of the gap 57. In the peripheral region 72, the thermal oxide film 13 and the outermost peripheral conductive region 5 are exposed.

Next, the resist film 64 is used as a mask to irradiate the element formation surface with N-type impurities.
25, N-type impurities are implanted into the surface side of the body region 32 exposed on the bottom surface of the gap 57, as shown in FIG.
A type impurity implantation region 35 is formed. Further, in the peripheral region 72, N-type impurities are implanted into the outermost peripheral conductive region 5. Here, As is used as the N-type impurity, and the dose amount is set to 5 × 10 ¹⁵ cm ⁻² .

Next, after removing the resist film 64, the substrate 10 is heat-treated under the condition that a thermal oxide film is not formed. Here, heat treatment is performed for 10 minutes in a nitrogen atmosphere at a temperature of 1000 ° C. Then, the impurity-implanted region 35 diffuses, and an N-type source region 36 is formed on the surface side of the body region 32, as shown in FIG. A plan view of this state is shown in FIG. FIG. 26 corresponds to the sectional view taken along the line EE of FIG. 36.

The edges of the body region 32 and the source region 36 are sunk to the position below the gate insulating film 27 by lateral diffusion as described above. Body area 3
The lateral diffusion amount of 2 is larger than the lateral diffusion amount of the source region 36, and the edge of the source region 36 does not protrude from the edge of the body region 32. A body region 32 remains between the edge. Reference numeral 80 indicates a channel region which is a body region located between the edge of the source region 36 and the edge of the body region 32. The channel region 80 is the gate insulating film 2
7, the gate insulating film 27 and the gate electrode film 28 are disposed above the channel region 80. Next, as shown in FIG. 27, an insulating film 38 is formed on the surfaces of the gate electrode film 28, the source region 36 and the body region 32 by the CVD method. Here, a silicon oxide film is formed as the insulating film 38.

Next, a patterned resist film 65 is formed on the surface of the insulating film 38. The resist film 65 is provided with an opening 58 on the surface of the source region 36 and the body region 32 located inside the source region 36.
An opening for a gate pad is provided in a region (not shown) on 8 and a groove 49 is provided on the outermost peripheral conductive region 5.

Next, when the insulating film 38 is etched using the resist film 65 as a mask, as shown in FIG. 29, the opening 58, the opening of the gate pad and the insulating film 38 exposed at the bottoms of the grooves 49 are removed. The source region 36 and the body region 32 are exposed at the bottom of the opening 58, the gate electrode film is exposed at the bottom of the opening of the gate pad, and the outermost peripheral conductive region 5 is exposed at the bottom of the groove 49.

Next, the resist film 65 is removed, and a metal film 46 is formed on the element formation surface as shown in FIG. Next, the metal film 46 is patterned to form a source electrode film 45 and a gate pad (not shown) separated from the source electrode film 45 as shown in FIG. 35, and the source electrode film is formed on the outermost peripheral conductive region 5. After the outermost peripheral conductive film 98 separated from the gate pad and the gate pad is formed, a protective film 99 is formed on the surfaces of the source electrode film 45, the gate pad and the outermost conductive film 98.
To form a film.

Next, openings (not shown) are provided in the protective film 99 in the region where the gate pad is formed and the region on the source electrode film 45, respectively, to expose the gate pad and the source electrode film 45 from the respective openings. The source electrode film 45 exposed on the bottom surface of one opening is used as a source pad, and the gate pad is exposed on the bottom surface of the other opening. External terminals (not shown) are connected to these gate pads and source pads, respectively.

Next, when a metal film is formed on the surface of the substrate 10 opposite to the element formation surface to form the drain electrode film 91,
A MOSFET as shown by reference numeral 1 in FIG. 37 is formed. In this MOSFET 1, when the source electrode film 45 is connected to the ground potential and a positive voltage is applied to the drain electrode film 91 and a positive voltage equal to or higher than the threshold voltage is applied to the gate electrode film 28, An N-type inversion layer is formed on the surface, the surface portion of the drain region 25 and the source region 39 are connected by the inversion layer, and the MOSF
ET1 becomes conductive. Then, a current flows from the source region 39 through the inversion layer to the drain region 25. At this time, as described above, the edge of the embedded region 22 is located inside the edge of the body region 32, and the embedded region 22 is
Is located at the bottom of the body region 32, the source region 39 is not connected to the buried region 22.

When the gate electrode film 28 is connected to the ground potential from the conductive state, the inversion layer disappears and the MOSFET
1 shuts off.

In the MOSFET 1, as described above, the comb-like embedded region 22 is arranged at the bottom of the comb-like body region 32, and the space between the embedded region 22 and the body region 32 is shown in FIG. Thus, the first PN junction 85 is formed. A second PN junction 86 is formed between the body region 32 and the second high concentration region 25.

As described above, the impurity concentration of the buried region 22 is higher than that of the second high-concentration region 25, and the first P formed by the buried region 22 and the body region 32 is formed.
The breakdown voltage of the N junction 85 is lower than the breakdown voltage of the second PN junction 86 formed by the second high concentration region 25 and the body region 32. When a high voltage is applied to the MOSFET 1, the first PN junction 85 undergoes avalanche breakdown, a current flows through the first PN junction 85, and no current flows through the second PN junction 86.

As described above, the first PN junction 85 is
It is formed between one body region 32 arranged in a comb shape and one embedded region 22 arranged along the bottom surface thereof, and the first PN junction 85 has the same planar shape as the body region 32. It is comb-shaped. Such first PN junction 85
Has substantially the same length as the body region 32, and the width of the comb-shaped first PN junction is increased.
The area of the joint 85 is large.

Even if a large current flows through such a first PN junction 85 due to avalanche breakdown, the large current flows evenly over the entire first PN junction 85 having a large area, and current concentration hardly occurs. Therefore, compared with the conventional element in which the current concentration occurs due to the avalanche breakdown, the element is less likely to be destroyed.

Although the case of manufacturing the MOSFET has been described above, as shown by reference numeral 2 in FIG.
When a collector layer 95 is formed using a P-type silicon single crystal substrate instead of the substrate body 11 made of N ⁺ -type silicon, and a collector electrode 96 is formed on the collector layer 95 so as to make ohmic contact with the collector layer 95, a PN junction is formed. IGB used
A T-type field effect transistor is obtained. This field effect transistor 2 is also included in the present invention.

The present invention also includes a Schottky junction type IGBT element as indicated by reference numeral 3 in FIG. In this Schottky junction type IGBT element 3, the substrate body 11 is not provided, and the Schottky electrode film 97 is arranged on the back surface side of the epitaxial layer 12.

This Schottky electrode film 97 forms a Schottky junction with the epitaxial layer 12, and a Schottky diode in which the Schottky electrode film 97 serves as an anode and the epitaxial layer 12 side serves as a cathode is formed. There is.

When the positive voltage higher than the threshold voltage is applied to the gate electrode film 28 with the source electrode film 45 connected to the ground potential and the positive voltage applied to the Schottky electrode film 97, it is close to the surface of the channel region 80. The part is inverted to N type.

The second high-concentration region 25 is in contact with the epitaxial layer 12, and when the surface portion of the channel region is inverted into N type, the inversion layer connects the source region 36 and the epitaxial layer 12. In this state, the Schottky junction is forward biased, so a current flows from the epitaxial layer 12 side toward the source region 36, and the Schottky junction type IGBT element 3 is brought into a conductive state.

In the above embodiment, the first conductivity type in the present invention is N type and the second conductivity type is P type. However, the first and second conductivity types in the present invention are not limited to this. Alternatively, conversely, the first conductivity type may be P type and the second conductivity type may be N type.

Further, in the above-described embodiment, one embedded region 22 is arranged almost all over the body region 32, and the planar shape thereof is comb-like like the planar shape of the body region 32. The invention is not limited to this. For example, a plurality of embedded regions may be provided, and each embedded region may be arranged below the body region 32 with a predetermined interval.

Although the body region 32 and the buried region 22 are formed in a comb shape in each of the above-described embodiments, the present invention is not limited to this, and for example, FIG.
As shown in the plan view of FIG. 2, a plurality of cells 205 may be arranged in the vicinity of the surface of the drain region 25 so as to be separated from each other to form one element 7.

Each cell 205 has a body region 3
2, the source region 36, the channel region 80, and the buried region 22. In each cell 205, the body region 32, the source region 36, and the channel region 80
The diffusion depth and the impurity concentration of the buried region 22 are the same as those of the element having the comb-shaped body region in plan view.

The source region 36 is formed in a ring shape, the outer edge of which is spaced apart from the edge of the body region 32, and the channel region 80 is between the outer edge of the source region 36 and the edge of the body region 32. positioned. Embedded area 2
2 has the same shape as the body region 32,
Is located inside.

As described above, in the element 7 in which the plurality of cells 205 are arranged, at least one embedded region 22 is arranged for each body region 32 of each cell 205. As a result, avalanche breakdown can occur in each of the body regions 32.

FIG. 42 shows the case where the planar shapes of the body region 32 and the buried region 22 are rectangular, but the planar shapes of the body region 32 and the buried region 22 when a plurality of cells 205 are arranged are not limited to this. For example, it may be formed in a circular shape, a triangular shape, or a hexagonal shape.

[0083]

The device breakdown due to avalanche breakdown is less likely to occur.

[Brief description of drawings]

FIG. 1 is a first sectional view explaining a manufacturing process of a field effect transistor of an example of the present invention.

FIG. 2 is a second cross-sectional view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 3 is a third cross-sectional view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 4 is a fourth sectional view illustrating a manufacturing process of the field effect transistor of the example of the present invention.

FIG. 5 is a fifth cross-sectional view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 6 is a sixth cross-sectional view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 7 is a seventh cross-sectional view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 8 is an eighth cross-sectional view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 9 is a ninth cross-sectional view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 10 is a tenth cross-sectional view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 11 is an eleventh cross-sectional view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 12 is a twelfth cross-sectional view illustrating the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 13 is a thirteenth cross-sectional view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 14 is a fourteenth cross-sectional view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 15 is a fifteenth sectional view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 16 is a sixteenth cross-sectional view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 17 is a seventeenth cross-sectional view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 18 is an eighteenth cross-sectional view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 19 is a nineteenth cross-sectional view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 20 is a twentieth cross-sectional view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 21 is a twenty-first cross-sectional view illustrating the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 22 is a twenty-second sectional view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 23 is a twenty-third cross-sectional view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 24 is a twenty-fourth cross-sectional view illustrating the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 25 is a twenty-fifth sectional view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 26 is a 26th cross-sectional view illustrating the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 27 is a 27th cross-sectional view illustrating the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 28 is a twenty-eighth cross-sectional view illustrating the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 29 is a 29th cross-sectional view illustrating the manufacturing process of the field-effect transistor of the example of the present invention.

FIG. 30 is a thirtieth sectional view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 31 is a first plan view illustrating a manufacturing process of the field effect transistor of the example of the present invention.

FIG. 32 is a second plan view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 33 is a third plan view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 34 is a fourth plan view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 35 is a thirty-first sectional view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 36 is a fifth plan view illustrating the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 37 is a cross-sectional view illustrating a field effect transistor of an example of the present invention.

FIG. 38 is another example of the present invention, in which I using a PN junction is used.
Diagram for explaining a GBT type field effect transistor

FIG. 39 is a cross-sectional view illustrating the structure of a conventional field effect transistor.

FIG. 40 is a plan view for explaining the arrangement of conventional field effect transistors.

FIG. 41 is a diagram for explaining an IGBT field effect transistor using a Schottky junction, which is another example of the present invention.

FIG. 42 is a view for explaining a field effect transistor in which a plurality of cells are arranged in a matrix, which is another example of the present invention.

[Explanation of symbols]

11 ... Board main body 12 ... Epitaxial layer 22 ... Embedded area 27: Gate insulating film 28: Gate electrode film 32: Body area 36 ... Source area 45 ... Source electrode film 80: Channel area 91 ... Drain electrode film

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identification Code FI Theme Coat (Reference) H01L 21/336 H01L 29/78 658A

Claims (8)

[Claims] 1. A drain layer of a first conductivity type and a drain layer of a second conductivity type formed by diffusing impurities of a second conductivity type from a surface side of the drain layer, and a diffusion depth thereof is larger than a thickness of the drain layer. A body region formed of a shallow diffusion region, and a diffusion region formed by diffusing a first conductivity type impurity from the surface side of the body region, the first conductivity type source disposed inside the body region. A region, a channel region that is a part of the body region and is located between an edge of the body region and an edge of the source region, a gate insulating film disposed on at least a surface of the channel region, A gate electrode film disposed on the surface of the gate insulating film, and when the surface of the channel region is inverted by a voltage applied to the gate electrode film, the gate electrode film is positioned outside the channel region. A field effect transistor in which a rain layer and the source region are electrically connected, the field effect transistor having a buried region located in the drain layer and in contact with the body region; A field effect transistor configured such that a portion of the buried region which is in contact with the body region has the highest impurity concentration. 2. The field effect transistor according to claim 1, wherein an outer peripheral edge portion of the buried region is located inside an outer peripheral edge portion of the body region. 3. The field effect transistor according to claim 1, further comprising a semiconductor layer disposed on a surface of the drain layer opposite to the body region. 4. The field effect transistor according to claim 3, wherein the substrate body is of the first conductivity type. 5. The field effect transistor according to claim 3, wherein the substrate body is of a second conductivity type. 6. A Schottky electrode disposed on the surface of the drain layer opposite to the body region, and a Schottky junction is formed between the Schottky electrode and the drain layer. Item 3. The field effect transistor according to item 1 or 2. 7. A drain layer of the first conductivity type and a drain layer of the second conductivity type formed by diffusing impurities of the second conductivity type from the surface side of the drain layer, and the diffusion depth thereof is shallower than the thickness of the drain layer. A body region formed of a diffusion region and a diffusion region formed by diffusing a first conductivity type impurity from the surface side of the body region, the first conductivity type source region being disposed inside the body region. A channel region that is a part of the body region and is located between an edge of the body region and an edge of the source region; a gate insulating film disposed at least on a surface of the channel region; A gate electrode film disposed on the surface of the insulating film, and when the surface of the channel region is inverted by a voltage applied to the gate electrode film, the gate electrode film located outside the channel region is inverted. A field effect transistor in which an in layer and the source region are electrically connected to each other, wherein the field effect transistor has an embedded region located in the drain layer and in contact with the body region, and outside the body region. A region of the first conductivity type located,
A field-effect transistor configured to have the lowest breakdown voltage of a PN junction formed by the buried region and the body region among PN junctions formed by the body region. 8. A first-conductivity-type drain layer, a second-conductivity-type body region disposed in the drain layer, a first-conductivity-type source region disposed in the body region, and the body. A gate insulating film arranged on the surface of the body region between the edge of the region and the edge of the source region, and a gate electrode film arranged on the surface of the gate insulating film, When the surface of the body region between the edge of the body region and the edge of the source region is inverted by the applied voltage, the drain layer located outside the body region and the source region are electrically connected. A method of manufacturing a field effect transistor, comprising: diffusing impurities of a first conductivity type into the drain layer from a surface side of the drain layer to form a low resistance region including a diffusion region of a first conductivity type. Process An impurity of a second conductivity type is diffused into at least the low resistance region from a surface side of the drain layer so as to be shallower than a bottom surface of the low resistance region, and a second conductivity type is provided on a surface side of the low resistance region and its periphery. A method of manufacturing a field effect transistor, comprising the step of forming the body region formed of a diffusion region of a mold.