JP2003092375A - Semiconductor device, its manufacturing method and its inspection method - Google Patents

Abstract

(57) [Problem] To provide a mounting structure capable of mounting a large number of semiconductor devices without increasing a mounting area. Provided is a high-performance, small-sized semiconductor device with a small mounting area.
Provided is a semiconductor device inspection method that can easily inspect a contact state and the like. SOLUTION: A bonding pad is provided on one main surface of a semiconductor chip on which an element region is formed and at least one other surface, and the semiconductor chip is formed so that the outer peripheral edge of the semiconductor chip and the outer peripheral edge of the package substantially coincide with each other. It is characterized by the following.
As a result, external connections can be made in portions other than on the mounting board, and the degree of freedom in mounting can be increased. In addition, even if the bonding pads are formed on the mounting board without any gap, since the bonding pads are formed on the other surface than the main surface, it is necessary to inspect the continuity between the bonding pads and the circuit pattern on the mounting board. Thereby, it is possible to easily inspect the connection status between the mounting board and the semiconductor device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a method of manufacturing the same, and an inspection method thereof.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been reduced in size due to the development of processing technology. Particularly, chip size packages (CSP) occupy a small mounting area on a mounting substrate and have a small volume. Increasing adoption in equipment. A conventional semiconductor device will be described with reference to FIG. C
In an SP type semiconductor device, as shown in FIG. 21, a semiconductor chip 1801 is resin-sealed so as to have the same size as this semiconductor chip to form a chip size package 1802, and further on the surface, Bumps made of solder balls or the like are arranged in a grid pattern to form CSP terminals 1803, and a mounting substrate 18 on which a desired circuit pattern (not shown) is formed via the CSP terminals.
It is implemented in 04.

Here, the semiconductor chip 1801 is a CS
It is arranged face down on the P package 1802 (face down) and has a bump structure. The semiconductor chip 1801 is connected to a lead frame or a film carrier having an external connection terminal 1803 via a bonding pad, and is sealed in a chip size package 1802 leaving the external connection terminal. The semiconductor chip 1801 is sealed in the chip size package 1802 with an adhesive such as resin, or the surfaces of the semiconductor chip 1801 and the chip size package 1802 are in contact with each other without a gap.

Furthermore, when mounting on a mounting board 1804 such as a printed circuit board, a circuit pattern on the mounting board 1804 is formed by a conductive metal such as solder or a conductive paste on the lower surface of the chip size package without any gap. (Not shown).

[0005]

In a semiconductor device using a chip size package, there is no gap in the joint surface with the mounting substrate and it cannot be observed from the outside. Therefore, the contact condition with the substrate is unknown and the contact failure is discovered. There was a problem that I could not do it.

Further, in a semiconductor device using such a chip size package, even if the mounting area is reduced, electronic parts cannot be mounted on the semiconductor device and must be arranged side by side. There is also a problem that the area of the mounting board increases when the components are attached.

Since the terminals are not exposed to the outside,
It is difficult to confirm and analyze the operation of the semiconductor device and the mounting board.

The present invention has been made in view of the above circumstances, and provides a semiconductor device in which an electronic component can be additionally arranged and connection with another circuit element can be facilitated without increasing the mounting area. The purpose is that.

Still another object is to provide a mounting structure capable of mounting a large number of semiconductor devices without increasing the mounting area. Another object of the present invention is to provide a small-sized semiconductor device having high functionality and a small mounting area.

In addition, it is an object of the present invention to provide a semiconductor device inspection method capable of easily inspecting a contact state and the like.

[0011]

Therefore, according to the first aspect of the present invention, one main surface of a semiconductor chip in which an element region is formed,
A bonding pad is provided on at least another surface, and the outer peripheral edge of the semiconductor chip and the outer peripheral edge of the package are formed to substantially coincide with each other.

According to such a structure, external connection can be made on a portion other than on the mounting substrate, and the degree of freedom in mounting can be increased. Even if it is mounted on the mounting board without any gaps, the bonding pad is formed on the surface other than the main surface. Therefore, the conduction state between the bonding pad and the circuit pattern on the mounting board should be inspected. This makes it possible to easily inspect the connection status between the mounting substrate and the semiconductor device.

In a second aspect of the present invention, the semiconductor chip is
A main surface on which an element region is formed, a bonding pad exposed from the package on a back surface side opposite to the main surface, and a circuit element connected to the bonding pad. And
According to such a configuration, in addition to the above effect, it becomes possible to mount the circuit element without increasing the mounting area.

According to a third aspect of the present invention, at least two semiconductor chips each having a bonding pad on one main surface having an element region and a back surface opposite to the main surface are laminated. The bonding pads are directly connected to each other via bumps, and are integrally resin-sealed so that the outer peripheral edge of the semiconductor chip substantially coincides with the outer peripheral edge of the package. With this configuration, it is possible to stack and integrate two semiconductor chips, and to provide a highly reliable semiconductor device that is small and has a small contact resistance because the wiring length for connection is small. It becomes possible.

In a fourth aspect of the present invention, the semiconductor chip is
It is characterized by comprising a bonding pad formed on a side surface corresponding to the outer peripheral surface of the chip.

According to this structure, connection with other electronic parts and inspection are facilitated.

According to a fifth aspect of the present invention, in the semiconductor device having the structure according to any one of claims 2 and 3, the bonding pad on the rear surface side of the semiconductor chip is in contact with an element region formed in the semiconductor chip. It is characterized in that it is connected to the contact hole thus formed.

According to this structure, since the bonding pad is formed so as to contact the element region,
Since the contact can be formed without forming a through hole penetrating the substrate, it is possible to form the contact without increasing the element area.

According to a sixth aspect of the present invention, in the semiconductor device having the structure according to the fourth aspect, the bonding pad is formed on a conductive film filled in a trench formed to include a dicing line. There is.

According to this structure, by forming a trench in the dicing line and forming a conductive film such as a metal film on the inner wall of the trench, dicing is facilitated and the package side wall is made of metal. Since the same state as when sealed can be formed, it is possible to improve the moisture resistance in addition to the effect of the fourth aspect.

In a seventh aspect of the present invention, a desired element region is formed in a semiconductor substrate, and the first and second element regions are respectively contacted with the main surface of the semiconductor substrate and a surface facing the main surface. A semiconductor element substrate forming step of forming a bonding pad, the semiconductor element substrate is mounted on a wiring member having an external connection terminal, and at least a part of the first or second bonding pad is formed on the external connection terminal forming surface. So as to expose on the side opposite to each other, a step of resin-sealing and forming a package, and a dicing step of cutting and separating the package together with the wiring member into individual semiconductor devices. Characterize.

According to this structure, the resin is sealed so that at least a part of the first bonding pad or the second bonding pad is exposed on the side opposite to the external connection terminal forming surface by using a normal CSP process. Only by stopping, it becomes possible to easily obtain a small-sized semiconductor device which can be easily mounted.

In the eighth aspect of the present invention, in the step of forming a semiconductor element substrate, a step of forming a high-concentration impurity diffusion region in contact with the element region from a surface opposite to the surface in which the element region is formed. It is characterized by including.

According to this structure, the contact for forming the bonding pad can be easily formed, so that the contact can be formed without increasing the area.

In a ninth aspect of the present invention, in the semiconductor element substrate forming step, a high-concentration impurity diffusion region is formed so as to be connected at two ends facing each other, and a high concentration impurity diffusion region is formed so as to contact the element region. The method is characterized by including a step of forming a concentration impurity diffusion region.

With this structure, the contacts for forming the bonding pads can be easily formed by forming the contacts from both sides, so that it is possible to form the contacts without increasing the area.

In the tenth aspect of the present invention, in the step of forming a semiconductor element substrate, at least one through hole is formed in each semiconductor device region, and both surfaces of the substrate are electrically connected through the through hole. It is characterized by including.

According to this structure, a contact can be easily formed on both sides by forming a through hole by laser processing or etching and making the inside of the through hole conductive.

In the eleventh aspect of the present invention, a desired element region is formed in a semiconductor substrate, a first bonding pad is formed on a main surface of the semiconductor substrate, and a desired depth is formed from a surface facing the main surface. To form a high-concentration impurity diffusion region for contact so as to reach the height of the semiconductor element substrate, the semiconductor element substrate, the wiring member having an external connection terminal through the first bonding pad. Mounting, resin sealing, and forming a package, thinning the semiconductor element substrate from the back surface side until the contact high-concentration impurity diffusion region is exposed, and forming the contact high-concentration impurity diffusion region A step of forming a second bonding pad, and a dicing process for cutting and separating the package together with the wiring member into individual semiconductor devices. Characterized in that it comprises and.

According to this structure, after the resin is sealed and the semiconductor substrate is fixed with the sealing resin and the wiring member, the semiconductor element substrate is exposed from the back surface from the back surface until the contact high-concentration impurity diffusion region is exposed. Since the semiconductor element substrate is thinned, the high-concentration impurity diffusion region for contact may be shallow. Therefore, the substrate area required for the high-concentration impurity diffusion region for contact can be reduced, and it is possible to easily provide a small-sized and highly reliable semiconductor device.

In a twelfth aspect of the present invention, a trench having a desired depth is formed at a position including a dicing line of a semiconductor substrate, a desired element region is formed in the semiconductor substrate, and a conductive layer is formed in the trench. Filling, forming a semiconductor element substrate, mounting the semiconductor element substrate on a wiring member having an external connection terminal, resin-sealing, to form a package, the package together with the wiring member A cutting step of cutting and separating along the dicing line so that the conductive layer is exposed on the cut surface, and separating into individual semiconductor devices.

According to this structure, it is extremely easy to form a contact on the side surface only by forming the trench in advance, and since the cut surface is covered with a conductive film such as a metal film, It is possible to prevent moisture from entering the element region of the substrate, improve the moisture resistance, and further improve the reliability of the semiconductor device.

In the thirteenth aspect of the present invention, bonding pads are provided on one main surface of the semiconductor chip on which the element region is formed and at least one other surface, and the outer peripheral edge of the semiconductor chip and the outer peripheral edge of the package are substantially aligned with each other. A step of mounting the semiconductor device thus formed on a mounting board having a test terminal, a step of mounting a probe on the test terminal and a bonding pad exposed on the other surface, and inspecting the same. It is characterized by including.

According to this structure, even if the semiconductor device is mounted on the mounting board without any gaps, the bonding pad is formed on the surface other than the main surface. By inspecting the electrical connection with the circuit pattern, it becomes possible to easily inspect the connection state between the mounting substrate and the semiconductor device.

As described above, according to the present invention, by processing the semiconductor chip in advance, it is possible to find a contact failure between the semiconductor device using the chip size package and the mounting substrate without increasing the substrate area. it can. Further, it becomes possible to easily mount an electronic component on this, and to perform an operation check and an analysis.

[0036]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) A first embodiment of the present invention will be described below. In this semiconductor device, in a semiconductor element having a bonding pad 3 on the surface of a semiconductor chip (semiconductor substrate) 1, both sides of the semiconductor chip are electrically connected by a through hole 2 formed by etching and the back side of the semiconductor chip is also bonded. A feature of the structure having the pad 4 is that the degree of freedom in electrical connection of the semiconductor chip can be increased.

The semiconductor device according to the first embodiment of the present invention is shown in FIGS.
As shown in its sectional view, top perspective view and bottom perspective view,
A chip size package characterized in that etching processing is performed so as to penetrate a semiconductor chip (semiconductor element substrate) 1 and a bonding pad 4 is also formed on a back surface side through a through hole 2 in which a conductive material is embedded. It is a semiconductor device having a structure. Here, the circuit element 1s formed by a normal method is formed on the surface of the semiconductor element substrate. Here, examples of the conductive material with which the through hole 2 is filled include aluminum, tungsten, and copper. However, other metals or resins having similar functions may be used. FIG. 3 is a top view of the semiconductor chip in a state where the semiconductor device of FIG. 2 is not sealed, and shows the semiconductor chip 1 in which the circuit element 1s is formed in the center and the bonding pad 3 is formed.

FIG. 3 is a view of the semiconductor device of FIG. 1 viewed from the bottom surface of the semiconductor chip. The bonding pad is electrically connected to the back surface of the semiconductor chip 1 through the through holes (not shown). 3 is formed.

The method of manufacturing this semiconductor device will be described below. First, as shown in FIG. 1A, the semiconductor substrate 1
While forming a desired element region therein, a through hole 2 is formed by etching so as to penetrate the semiconductor substrate, and a conductive layer such as tungsten is filled in the inside. The semiconductor substrate 1 has a main surface and a surface facing the main surface, the first surface contacting the element region, respectively.
And the second bonding pad 4 contacting the through hole is formed. Here, the through hole 2 is connected to the element region in the semiconductor substrate via the first bonding pad 3 or directly.

Then, as shown in FIG. 1B, the semiconductor element substrate having the element regions thus formed in the semiconductor substrate is connected to the wiring board 5 through the bumps 3a.

Further, as shown in FIG. 1C, an insulating resin 7 such as a polyimide resin is filled between the semiconductor element substrate and the wiring substrate 5 and fixed to be integrated.

Then, as shown in FIG. 1D, external connection terminals 8 made of solder balls are formed so as to be electrically connected to the semiconductor element substrate through the contact holes 6 of the wiring substrate 5.

Finally, as shown in FIG. 1 (e), the semiconductor element substrate is divided along with the resin along the dicing line indicated by the broken line, and cut into individual semiconductor devices.

The semiconductor device thus formed is
Using a normal CSP process, it is easy to perform resin sealing so that at least a part of the first or second bonding pad 3, 4 is exposed on the side opposite to the external connection terminal forming surface. It is possible to obtain a semiconductor device that is small and easy to mount.

Further, in the first embodiment, through holes are formed by etching in order to electrically connect both sides of the semiconductor element substrate, but it is extremely difficult to form through holes having a high aspect ratio. Because
As a modification, a high-concentration impurity diffusion region may be used to make a contact.

First, as shown in FIG. 5A, a high concentration impurity diffusion region 12a is formed by implanting and diffusing impurity ions from the main surface side of the semiconductor substrate 1 in which a desired element region is formed.

Then, as shown in FIG. 5B, high-concentration impurity diffusion regions 12b are formed by injecting and diffusing impurity ions from the surfaces opposite to the main surface.

According to this structure, the contact for forming the bonding pad can be easily formed, so that a good contact can be obtained without increasing the area required for the contact.

Further, as shown in FIGS. 6A and 6B, a through hole H may be formed by laser processing, and the conductive film 13 may be filled in the through hole H.

This makes it possible to obtain good contacts on both sides as well. By the way, in a normal semiconductor device, the circuit element 1S is formed on the semiconductor chip 1, and the electrical connection to the outside is performed by using the bonding pad 3 on the same surface. This pad is usually formed only on the front surface of the semiconductor chip, and electrical connection cannot be made on the back surface of the semiconductor chip. But pad 3
On the back surface side of the surface on which the semiconductor chip is formed, a vertical hole is formed by etching using a laser device or chemicals, and by embedding a conductive metal or a conductive resin in the hole, the back surface side of the semiconductor chip The pads can be arranged on the semiconductor chip, which allows the semiconductor chip to be arranged on the package or the mounting substrate face down. Further, it becomes possible to stack or effectively utilize another semiconductor chip on the back surface side of the semiconductor chip where nothing has been conventionally formed.

As described above, according to the present embodiment, in the semiconductor device having the bonding pad on the surface of the semiconductor chip, the pad is provided also on the back surface side, so that other elements are laminated or the probe is installed from the back surface side. It is possible to contact and test.

Although the semiconductor device having the chip size package structure has been described in the first embodiment, the present invention is not limited to the chip size package structure and can be applied to a normal resin-sealed semiconductor device. Needless to say. For example, a structure in which a part of the back surface of the semiconductor chip is exposed from the sealing resin may be used.

(Second Embodiment) In the second embodiment of the present invention, in order to achieve electrical connection on both sides,
A high-concentration impurity diffusion region is formed to a depth in the middle,
After mounting, the semiconductor substrate is characterized by being polished from the back surface side to be thinned.

FIGS. 7A to 7F show the manufacturing method. First, as shown in FIG. 7A, a desired element region is formed in the semiconductor substrate 1, and a high-concentration impurity diffusion region 22 is formed from the element region formation surface side to a desired depth.

Thereafter, first bonding pads 3 are formed on the main surface of the semiconductor substrate 1 so as to contact the element regions. Here, the high concentration impurity diffusion region 22 does not penetrate to the back surface side.

Then, as shown in FIG. 7B, the semiconductor element substrate having the element region thus formed in the semiconductor substrate is connected to the wiring board 5 through the bumps 3a.

Further, as shown in FIG. 7C, an insulating resin 7 such as a polyimide resin is filled between the semiconductor element substrate and the wiring substrate 5 and fixed to be integrated.

Then, as shown in FIG. 7D, external connection terminals 8 made of solder balls are formed so as to be electrically connected to the semiconductor element substrate through the contact holes 6 of the wiring substrate 5.

Subsequently, as shown in FIG. 7E, the semiconductor substrate 1 is polished from the back surface side, and is thinned to reach the high-concentration impurity diffusion region. Note that this step may be etching.

Finally, as shown in FIG. 7 (f), the semiconductor element substrate is divided along with the resin along with the dicing line, and cut into individual semiconductor devices.

The semiconductor device thus formed is
Similar to the first embodiment, a normal CSP process is used to expose at least a part of the first or second bonding pad 3, 4 on the side opposite to the external connection terminal forming surface. It is possible to easily obtain a small-sized semiconductor device which can be easily mounted simply by resin-sealing.

Since the semiconductor element substrate is once fixed to the package and then thinned, not only the effect that the thickness of the semiconductor element substrate can be reduced but also the mechanical strength is sufficiently maintained. However, it is possible to provide a small and highly reliable semiconductor device. Also,
Since the depth of the impurity diffusion region may be shallow, it is possible to further reduce the horizontal area.

(Third Embodiment) The third embodiment of the present invention will be described below.
The embodiment will be described with reference to FIGS. 8 and 9. Although the semiconductor device is mounted face down in the first embodiment, it may be formed face up.

According to this structure, as shown in FIGS. 8 and 9, since the bonding pads are formed on both surfaces of the substrate, it is possible to mount the device without wire bonding while having a face-up structure. In addition, the electrical connection to other components on the upper surface becomes easy.

In this semiconductor device, as shown in FIG. 8, a through hole 802 is formed in a semiconductor element substrate 801, a first bonding pad 803 is formed so as to be in contact with this through hole 802, and the back surface side is formed. Also, the second bonding pad 804 is formed, and this is connected face-up to the conductive region 806 of the wiring substrate 805 having the multilayer wiring structure via the bump 804S. Also, solder balls 808 are formed on the back surface side of the wiring board 805. The semiconductor element substrate 801 is fixed to the wiring board via an adhesive 807.

Here, examples of the conductive material that enters the through hole 802 include aluminum, tungsten, and copper. However, other metals or resins having the same function may be used. FIG. 9 is a view of the semiconductor device of FIG. 8 seen from the upper surface of the semiconductor chip.

Also with this structure, the measurement and analysis of the circuit element formed in the semiconductor element substrate can be achieved very easily via the first bonding pad.

That is, the circuit connection to the wiring board can be made by direct bonding without wire bonding, and after mounting on the package, the inspection is performed through the first bonding pad 803 exposed on the upper surface. Is possible.

As a result, it becomes possible to apply a probe to the circuit element on the surface via the first bonding pad and perform image analysis by non-contact means.

(Fourth Embodiment) In the fourth embodiment of the present invention, a semiconductor device is miniaturized by forming bonding pads on both sides of a semiconductor chip and arranging a plurality of semiconductor chips vertically. Is to realize.

The structure of the semiconductor device according to the fourth embodiment of the present invention is shown in FIGS. Here, the semiconductor chip alone is a stack of two semiconductor chips similar to those described in the third embodiment. In FIG. 10, the semiconductor chip B811 is stacked on the semiconductor chip A801, and the second bonding pad 814 formed on the back surface side of the semiconductor chip B811 and the first bonding pad 803 on the front surface side of the semiconductor chip A801 are bumped 814S. While connecting via
It is fixed with an insulating resin 807.

The connection between the bonding pads on both surfaces of the semiconductor element substrate is achieved by forming through holes 802 and 812 by etching and embedding a conductive material in the same manner as in the third embodiment.

FIG. 9 is a top view of the semiconductor device shown in FIG. Here, the insulating resin 807 is used to bond the semiconductor chip A 801 and the semiconductor chip B 811, and the bump 806 has the second bonding pad 814 formed in the through hole 812 and the first bonding pad 803 of the semiconductor chip 801. Plays the role of electrically connecting. The bumps 814S are not necessary for all the pads, and are arranged only on one of the opposing bonding pads located at the portions where the semiconductor chip A801 and the semiconductor chip B811 need to be electrically connected. The semiconductor chip A801 and the semiconductor chip B811 are
The chips may not be the same chip, for example, the semiconductor chip A80
Chips having different functions, such as a microcomputer chip 1 and a semiconductor chip B811, may be stacked.

As described above, according to the present embodiment, in the semiconductor element having the bonding pad on the surface of the semiconductor chip, the pad is also provided on the back surface of the semiconductor chip by the etching process, so that they are arranged in multiple layers. This makes it possible to downsize the semiconductor device and reduce the mounting area.

Further, instead of fixing with an insulating adhesive, the entire structure may be sealed with a sealing package that exposes only the bonding pads for connecting to an external circuit.

(Fifth Embodiment) Next, the fifth embodiment of the present invention will be described.
The embodiment will be described. In this example, a semiconductor device having a bonding pad on the surface of the semiconductor chip is characterized by having a pad also on the side surface of the semiconductor chip, so that the degree of freedom in electrical connection of the semiconductor chip is increased.

The structure of the semiconductor device according to the fifth embodiment of the present invention is shown in FIGS. In this semiconductor device, as shown in FIGS. 12 and 13, a first bonding pad 1203 is formed on the surface of a semiconductor chip 1201 in which a desired element region is formed, and is connected to the first bonding pad 1203. With this, the conductive contact region 12 exposed on the side surface of this semiconductor chip
No. 02 is provided. A trench is formed in the conductive contact region 1202 by etching, and a conductive material is embedded therein. Here, examples of the conductive material that enters the inside of the conductive contact region 1202 include aluminum, tungsten, and copper. However, other metals or resins having the same function may be used. FIG. 13 is a top view of the semiconductor device of FIG. 12, showing the conductive contact region 1202 connected to the bonding pad 1203 on the surface of the semiconductor chip 1201 exposed on the side surface of the semiconductor chip and the contact on the side surface of the semiconductor chip. It is possible to take.

A normal semiconductor device is a semiconductor chip 120.
The device region is formed on the surface of the semiconductor chip 1 and is electrically connected to the outside using the bonding pad 1203 on the surface. This pad is usually formed only on the surface of the semiconductor chip, and the side surface of the semiconductor chip is not electrically connected. Could not be done. Therefore, if the pad is used for wire bonding or bonding by the bump method, or if the surface of the semiconductor chip is fixed with resin, it becomes difficult to electrically connect the pad. However, by forming a groove on the side surface of the semiconductor chip by etching and embedding a conductive metal or a conductive resin in the groove so as to connect to the bonding pad 1203, a side surface of the semiconductor chip where nothing has been conventionally arranged The terminals can be disposed on the terminals, which allows electrical connection to the terminals even after processing such as wire bonding or direct bonding using bumps.

As described above, according to the present embodiment, in the semiconductor element having the bonding pad on the surface of the semiconductor chip, since the pad is also provided on the side surface of the semiconductor chip by the etching process, the pad on the surface side is used for the wire. Even after connection processing such as bonding, it is possible to electrically connect the terminals to the terminals from the side surface of the semiconductor chip.

(Sixth Embodiment) Next, as a sixth embodiment of the present invention, a manufacturing process of a semiconductor device having a CSP structure having a bonding pad on the side surface as described above will be described in detail.

Here, as shown in FIG. 14, a trench 23 having a desired depth is formed at a position including a dicing line of the semiconductor device substrate 21 to form a desired device region in the semiconductor substrate, and The semiconductor layer is filled with a conductive layer, mounted on a wiring member 25 having an external connection terminal 28 made of a solder ball, and sealed with a resin to form a package 27, and then the semiconductor element substrate 21 and the package 27.
Together with the wiring member 25 are cut and separated along the dicing line so that the conductive layer is exposed on the cut surface, and separated into individual semiconductor devices.

Here, a trench having a desired depth is formed at a position including a dicing line of a semiconductor substrate, a desired element region is formed in the semiconductor substrate, and a conductive layer is filled in the trench. A step of forming an element substrate, a step of mounting the semiconductor element substrate on a wiring member having an external connection terminal, resin-sealing to form a package, and the package together with the wiring member on a cut surface. A cutting step of cutting and separating along the dicing line so that the conductive layer is exposed, and separating into individual semiconductor devices.

First, as shown in FIG. 14A, a trench 23 is formed in the semiconductor substrate 21 by etching to a desired depth so as to include a dicing line. Then, a desired element region is formed.

Thereafter, as shown in FIG. 14B, a highly doped polycrystalline silicon layer 26 is formed in the trench 23, and thermal diffusion is performed to form the trench 2 in the trench 2.
3, the high-concentration diffusion layer 26 is exposed on the surface of the semiconductor substrate 21 exposed inside.
To form.

Then, as shown in FIG. 14C, a tungsten film 26s is formed in the trench 23.

As shown in FIG. 14D, the semiconductor element substrate having the element region thus formed in the semiconductor substrate is connected to the wiring board 25 through the bumps 23a.

Further, an insulating resin 27 such as a polyimide resin is filled between the semiconductor element substrate and the wiring board 5 and fixed to be integrated.

Then, as shown in FIG. 14E, the semiconductor element substrate is divided along with a resin along a dicing line indicated by a broken line, and cut into individual semiconductor devices.

Finally, as shown in FIG. 14F, the heavily doped polycrystalline silicon layer 2 exposed on the cut surface is formed.
6. The bonding pad 24 is formed so as to cover the interface between the high concentration diffusion layer 25 and the tungsten film 26s.

The semiconductor device thus formed is
By forming a trench in advance using a normal CSP process, it becomes very easy to form a contact on the side surface. Further, since the cut surface is covered with a conductive film such as a metal film, the substrate is cut from the cut surface. It is possible to suppress the invasion of water into the element region, improve the moisture resistance, and further improve the reliability of the semiconductor device.

(Seventh Embodiment) Next, as a seventh embodiment of the present invention, a stack in which a plurality of semiconductor chips described in the fifth embodiment (FIG. 10) are vertically stacked and arranged. An example in which the body is mounted on the wiring board according to the third embodiment shown in FIG. 8 will be described. With this configuration, the semiconductor device can be downsized, and the mounting area can be reduced.

The structure of the semiconductor device according to the seventh embodiment of the present invention is shown in FIGS. In FIG. 15, in this structure, the semiconductor chip A 801 and the semiconductor chip B 811 are stacked and eight of the first and second bonding pads 803, 804, 813, 814 formed on both sides via through holes 802, 812, respectively.
03, 814 are interconnected via bumps 803S, and are further fixed to a chip-sized wiring board 805 having a wiring pattern.
The same parts as those in the drawing numbers in the third and fifth embodiments are designated by the same reference numerals.

On the semiconductor chip A 801, an electronic component 820 is mounted on the surface of the semiconductor chip A, which is electrically connected to the element region forming surface side of the semiconductor chip A, through a conductive paste 819. . 16 is shown in FIG.
5 is a top view of the semiconductor device of No. 5, in which terminals 808 arranged in a grid pattern are formed on the bottom surface.

In a semiconductor device using a normal chip size package, the semiconductor chip A 801 is arranged face down, and bump connection is made with a wiring board as a chip size package. The electrical connection to the outside was made from the bonding pad, the chip size package, and the terminal. This pad is usually formed only on the surface of the semiconductor chip, and electrical connection cannot be made on the back side of the semiconductor chip, that is, the upper surface of the semiconductor device.

However, in the present invention, a through hole is formed by etching or the like so as to be electrically connected to the pad 803, and a conductive metal or a conductive resin is embedded in the through hole to form an external connection terminal on the upper surface of the semiconductor device. It is possible to arrange the semiconductor chips and the electronic components by stacking them. The semiconductor chip A801 and the semiconductor chip B811 are
The chips may not be the same chip, for example, the semiconductor chip A80
Chips having different functions, such as a microcomputer chip 1 and a semiconductor chip B1811, may be stacked. The electronic component 820 is a conductive paste 819.
Thus, the through hole 802 is connected and electrically connected. Depending on the electronic component, the entire back surface may be fixed with a resin such as an adhesive together with the conductive paste 819.

As described above, according to the present embodiment, in the semiconductor device having the bonding pad on the front surface of the semiconductor chip, the pad is also provided on the back surface of the semiconductor chip by the etching process. They can be placed one on top of the other, making it possible to reduce the size of the semiconductor device and reduce the mounting area.

(Eighth Embodiment) The structure of a semiconductor device according to an eighth embodiment of the present invention is shown in FIGS. This semiconductor device has a structure in which a pad is also provided on the side surface of the semiconductor chip according to the fourth embodiment, and by mounting an electronic component directly on the pad, the mounting board is downsized and the mounting area is reduced. It is a thing.

The same semiconductor chip as that of the semiconductor device shown in FIGS. 12 and 13 is used, and the same parts are designated by the same reference numerals.

The wiring board 805 is the same as that used in the seventh embodiment (FIGS. 15 and 16), and external connection terminals 808 made of solder balls are formed.
Further, the contact region 1 formed so as to be connected to the bonding pad 1203 on the surface of the semiconductor chip 1201.
202 is exposed on the side surface of the semiconductor chip, and an electronic component is connected to this contact region 1202. Here, the contact region 1202 can be obtained by forming a high-concentration impurity diffusion region or filling a trench with a conductive material such as aluminum, tungsten, or copper. FIG. 18 is a top view of the semiconductor device of FIG.

As described above, according to the present embodiment, in the semiconductor device having the bonding pad on the surface of the semiconductor chip, the terminals are also provided on the side surface of the semiconductor chip by the etching process. They can be placed directly, which enables downsizing of the mounting board and reduction of the mounting area.

(Ninth Embodiment) An inspection method using the semiconductor device of the present invention will be described below. 9th of this invention
19 shows a configuration of a semiconductor device according to the embodiment.
The semiconductor device having the bonding pad 803 formed on the upper surface described in the third embodiment of the present invention is mounted on the mounting board 1 via the solder balls as the external connection terminals 808.
01 is fixed on the test terminal 102 formed on 01, and after fixing, the probes P1 and P2 are brought into contact with the bonding pad 803 and the test terminal 102 on the upper surface of the semiconductor device to inspect the contact state.

In a semiconductor device using an ordinary chip size package, semiconductor chips 801 are connected face down, and bump connections are made with a wiring board as a chip size package 805. For electrical connection to the outside, the terminals 8 arranged in a grid on the lower surface of the chip size package are used.
I'm going from 08. This terminal 808 is mounted on the mounting substrate 101.
It is connected without any gap, and the state of connection cannot be confirmed from the outside. Therefore, for confirmation, it is common to incorporate a test circuit or the like into the semiconductor device.

However, according to this structure, the conduction to the terminal 808 is ensured by the through hole 802, and the terminal 808 and the mounting substrate 1018 test terminal 102 are provided.
To the test terminal 1 on the mounting substrate 101 by contacting the probe P1 with the through hole 802.
02 by contacting the probe P2 with the probe P1 and the probe P2 to check the electrical resistance value of the probe P1 to confirm the electrical contact state, and thus the terminal 808 and the mounting substrate 101.
You can confirm contact with.

As described above, according to the present embodiment, since the semiconductor element having the bonding pad on the surface of the semiconductor chip has the electrode on the back surface of the semiconductor chip by the etching process, it is mounted on the mounting substrate by the chip size package. Even if the terminals cannot be seen from the outside, the contact between the semiconductor device and the mounting board can be confirmed, and the contact test between the semiconductor device and the mounting board becomes possible.

Furthermore, according to this structure, the probe of the measuring instrument is brought into contact with the electrode on the rear surface of the semiconductor chip not only for the continuity test but also for the case where the contact surface between the mounting substrate and the terminal cannot be seen due to the chip size package. Then, by confirming the electrical state, the operation test and the operation analysis of the semiconductor device and the mounting board which are operating on the mounting board can be performed without installing the measurement terminals and the like on the mounting board.

(Tenth Embodiment) FIG. 20 shows the structure of a semiconductor device according to a tenth embodiment of the present invention. In this example, the semiconductor device having the contact region 1202 formed on the side surface, which has been described in the fourth embodiment of the present invention, is tested on the mounting substrate 101 via the solder balls as the external connection terminals 1208. After being fixed on the terminal 102, the probe P is fixed after the fixing as in the ninth embodiment.
It is characterized in that the inspection is carried out according to 1, P2.

According to this method, a semiconductor device having a bonding pad on the surface of the semiconductor chip has a structure in which electrodes are also provided on the side surfaces of the semiconductor chip by etching, and the mounting board and the terminal are contacted by a chip size package. Even if the surface cannot be seen, the contact test between the semiconductor device and the mounting board can be performed by confirming the continuity between the electrodes on the side surface of the semiconductor chip and the test terminals on the mounting board, and a reliable mounting inspection can be performed. Have.

According to this structure, the probe of the measuring instrument is brought into contact with the electrode on the back surface of the semiconductor chip not only for the continuity test but also for the case where the contact surface between the mounting substrate and the terminal cannot be seen due to the chip size package. By checking the electrical state, the operation test and the operation analysis of the semiconductor device and the mounting board which are operating on the mounting board can be performed without installing a measurement terminal or the like on the mounting board.

[0109]

As described above, according to the present invention, the bonding pads are provided on one main surface of the semiconductor chip in which the element region is formed and at least the other surface thereof, and the outer peripheral edge of the semiconductor chip and the outside of the package are substantially provided. Since the peripheral edges are formed so as to coincide with each other, there are two areas in which contact can be made.
It becomes a surface, and the degree of freedom of connection can be obtained, and mounting is possible without increasing the substrate area. Further, it becomes possible to improve the workability of contact failure inspection between the semiconductor device using the chip size package and the mounting substrate, mounting of electronic components on the semiconductor device, operation check of semiconductor device, and analysis.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a semiconductor device formed by a manufacturing process according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a semiconductor device formed by a manufacturing process according to a first embodiment of the present invention.

FIG. 4 is a diagram showing a semiconductor device formed by a manufacturing process according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a modified example of the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a modification of the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 8 is a diagram showing a third embodiment of the present invention.

FIG. 9 is a diagram showing a third embodiment of the present invention.

FIG. 10 is a diagram showing a fourth embodiment of the present invention.

FIG. 11 is a diagram showing a fourth embodiment of the present invention.

FIG. 12 is a diagram showing a fifth embodiment of the present invention.

FIG. 13 is a diagram showing a fifth embodiment of the present invention.

FIG. 14 is a diagram showing a sixth embodiment of the present invention.

FIG. 15 is a diagram showing a seventh embodiment of the present invention.

FIG. 16 is a diagram showing a seventh embodiment of the present invention.

FIG. 17 is a diagram showing an eighth embodiment of the present invention.

FIG. 18 is a diagram showing an eighth embodiment of the present invention.

FIG. 19 is a diagram showing a ninth embodiment of the invention.

FIG. 20 is a diagram showing a tenth embodiment of the invention.

FIG. 21 is a diagram showing a conventional semiconductor device.

[Explanation of symbols]

1 Semiconductor substrate 2 through holes 3 Bonding pad 4 Bonding pad 801 Semiconductor chip 802 through hole 803 Bonding pad 804 Bonding pad

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 25/18 (72) Inventor Satoshi Hori 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F-term (Reference) 5F044 QQ07 RR03 RR12

Claims (13)

[Claims] 1. A bonding pad is provided on one main surface of a semiconductor chip in which an element region is formed and at least another surface, and is formed so that the outer peripheral edge of the semiconductor chip and the outer peripheral edge of the package are substantially aligned with each other. A semiconductor device characterized by the above. 2. The semiconductor chip comprises a main surface on which an element region is formed, and a bonding pad exposed from the package on a back surface side opposite to the main surface, and further connected to the bonding pad. 2. The semiconductor device according to claim 1, comprising a circuit element. 3. At least two semiconductor chips each having a bonding pad on one main surface where an element region is formed and on a back surface side opposite to the main surface are laminated, and the bonding pads are bonded to each other. A semiconductor device, which is directly connected via a bump and is integrally resin-sealed so that an outer peripheral edge of a semiconductor chip and an outer peripheral edge of a package substantially coincide with each other. 4. The semiconductor device according to claim 1, wherein the semiconductor chip comprises a bonding pad formed on a side surface corresponding to an outer peripheral surface of the semiconductor chip. 5. The semiconductor device having the structure according to claim 2, wherein the bonding pad on the back surface side of the semiconductor chip is formed so as to contact an element region formed in the semiconductor chip. A semiconductor device characterized by being connected to a contact hole. 6. The semiconductor device having the structure according to claim 4, wherein the bonding pad is formed on a conductive film filled in a trench formed to include a dicing line. Semiconductor device. 7. A desired element region is formed in a semiconductor substrate, and first and second bonding pads for contacting the element region are formed on a main surface of the semiconductor substrate and a surface facing the main surface, respectively. A semiconductor element substrate forming step, the semiconductor element substrate is mounted on a wiring member having an external connection terminal, and at least a part of the first or second bonding pad faces the external connection terminal formation surface. So that the semiconductor device is sealed with a resin to form a package, and a dicing process of cutting and separating the package together with the wiring member into individual semiconductor devices. Manufacturing method. 8. The step of forming a semiconductor element substrate includes the step of forming a high-concentration impurity diffusion region so as to contact the element region from a surface opposite to a surface on which the element region is formed. 8. The method for manufacturing a semiconductor device according to claim 7. 9. In the semiconductor element substrate forming step, a high-concentration impurity diffusion region is formed so that two surfaces facing each other are connected at a tip, and a high-concentration impurity diffusion region is contacted with the element region. 8. The method for manufacturing a semiconductor device according to claim 7, further comprising a forming step. 10. The step of forming a semiconductor element substrate includes the step of forming at least one through hole in a region to be each semiconductor device and electrically connecting both surfaces of the substrate through the through hole. 8. The method for manufacturing a semiconductor device according to claim 7. 11. A desired element region is formed in a semiconductor substrate, a first bonding pad is formed on a main surface of the semiconductor substrate, and a desired depth is reached from a surface facing the main surface. A step of forming a high-concentration impurity diffusion region for a contact on the substrate to form a semiconductor element substrate, and mounting the semiconductor element substrate on a wiring member having an external connection terminal via the first bonding pad, and sealing with a resin. Stopping, forming a package, thinning the semiconductor element substrate from the back surface side until the contact high-concentration impurity diffusion region is exposed, and a second bonding pad on the contact high-concentration impurity diffusion region. And a dicing step of cutting and separating the package together with the wiring member into individual semiconductor devices. A method for manufacturing a characteristic semiconductor device. 12. A semiconductor device comprising: forming a trench having a desired depth at a position including a dicing line of a semiconductor substrate to form a desired device region in the semiconductor substrate; and filling a conductive layer in the trench. A step of forming a substrate; a step of mounting the semiconductor element substrate on a wiring member having an external connection terminal, resin-sealing to form a package; and a step of forming the package together with the wiring member on a cut surface. A method of manufacturing a semiconductor device, comprising: a cutting step of cutting along the dicing line so as to expose the conductive layer, and cutting into individual semiconductor devices. 13. A bonding pad is provided on one main surface of a semiconductor chip on which an element region is formed and at least another surface, and is formed so that the outer peripheral edge of the semiconductor chip and the outer peripheral edge of the package substantially coincide with each other. And mounting a semiconductor device on a mounting board having a test terminal, and mounting a probe on the test terminal and a bonding pad exposed on the other surface and inspecting the semiconductor device. Semiconductor device inspection method.