JP2003085994A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] PROBLEM TO BE SOLVED: To provide not only nonvolatile memory but also volatile memory
By performing redundancy relief, the yield is greatly improved. SOLUTION: A flash memory 2 and a RAM 3 are built-in.
Semiconductor device with defective bits
The rescue information storage mat 2 in the flash memory 2
e, the relief information stored in the flash memory 2
Block 3₁, 3 _TwoTransfer to Relief information flash
Memory 2, memory block 3₁~ 3_nAny of
Identifier and which memory bit to indicate
Data to indicate whether to replace
You. Identifier comparison circuits 2a, 3a₁~ 3a_nIs set in advance
Whether the specified memory identifier matches the memory identifier
And if they match, the corresponding rescue register is rescued.
Stored in the redundant mat according to the repaired data.
To relieve the defective bit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to redundant relief of a volatile memory in a semiconductor integrated circuit device having a nonvolatile memory and a volatile memory built therein. It is a thing.

[0002]

2. Description of the Related Art For example, in a semiconductor integrated circuit device having a built-in non-volatile memory, a so-called microcomputer with a built-in flash memory, the flash memory is provided with a defect relief technique.

In this technique, when a defective row or column or memory cell exists in the memory array of the flash memory, a spare row or column is input when an address signal of a memory mat corresponding to the defective portion is input. Is to be selected.

As an example in which this kind of redundancy repair technique is described in detail, there is "Ultra High Speed MOS Device" P329-P331 issued on February 10, 1986 by Baifukan Co., Ltd., Shin Kayama (ed.). , In this document, DR
AM (Dynamic Random Access)
The redundancy circuit technology in Memory) is described.

[0005]

However, the inventor of the present invention has found that the rescue technique for the semiconductor integrated circuit device as described above has the following problems.

That is, a semiconductor integrated circuit device such as a microcomputer with a built-in flash memory is generally provided with a volatile memory such as a RAM for temporarily storing input / output data and operation data that can be read / written at any time. However, defect relief in this volatile memory is not considered.

Therefore, when a defect occurs in a memory cell of a volatile memory, the semiconductor integrated circuit device becomes a defective product, and the yield of the semiconductor integrated circuit device decreases.

An object of the present invention is to provide a semiconductor integrated circuit device capable of significantly improving the yield by redundantly repairing not only a non-volatile memory but also a volatile memory.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the semiconductor integrated circuit device of the present invention is provided with a memory identifier, a memory mat area for storing relief information for storing relief information composed of relief data, a memory identifier given in advance, and the memory for storing relief information. The memory identifier stored in the mat area is compared with the first comparison storage section that stores the rescue data stored in the rescue information storage memory mat area when they match, and the first comparison storage section. Non-volatile memory provided with a relief bit area for relieving a defective memory bit area including a defective bit based on the stored relief data, a memory identifier given in advance and stored in the relief information storing memory mat area A second comparison storage unit that compares the stored memory identifier with the stored memory identifier, and stores the repair data stored in the memory mat area for storing the repair information when they match. , Those having a based on the repair data stored in the comparison storage unit of the second, and the volatile memory provided a redundant bit region for relieving a defective memory bit area including a defective bit.

In the semiconductor integrated circuit device of the present invention, a relief information storage memory mat area for storing relief information consisting of a memory identifier and relief data, a memory identifier given in advance, and the relief information storage memory. Based on the permission signal output from the first identifier comparison unit that compares the memory identifier stored in the mat area and outputs the permission signal when they match, the relief information A first repair data storage section for storing the repair data stored in the storage memory mat area, and a defective memory bit area including a defective bit based on the repair data stored in the first repair data storage section. A non-volatile memory provided with a repair bit area for repairing the memory, a memory identifier given in advance, and a memory identifier stored in the memory mat area for storing the repair information Are stored in the relief information storage memory mat area based on the second identifier comparing section that outputs a permitting signal when they match and the permitting signal output from the second identifier comparing section. A second relief data storage section for storing relief data and a relief bit area for relieving a defective memory bit area including a defective bit based on the relief data stored in the second relief data storage section are provided. And a volatile memory.

Further, the semiconductor integrated circuit device of the present invention is
The relief information storage memory mat area in which the relief information including the memory identifier and the relief data is stored is compared with the memory identifier stored in advance in the relief information storage memory mat area. At this time, a first identifier comparing section for generating an enable bit and an enable bit output from the first identifier comparing section are stored, and the relief data stored in the relief information storing memory mat area is stored. A nonvolatile memory having a first relief data storage section and a relief bit area for relieving a defective memory bit area including a defective bit based on the relief data stored in the first relief data storage section; , The memory identifier given in advance and the memory identifier stored in the memory mat area for storing relief information are compared, and if they match, the error is detected. A second identifier comparing section for generating a table bit, a second identifier storing section for storing the enable bit output from the second identifier comparing section, and a second storing the relief data stored in the relief information storing memory mat area. The repair data storage section and the volatile memory provided with a repair bit area for repairing a defective memory bit area including a defective bit based on the repair data stored in the second repair data storage section are provided. It is a thing.

Further, the semiconductor integrated circuit device of the present invention has a nonvolatile memory and a volatile memory built therein, and the nonvolatile memory stores relief information storing relief information including a memory identifier and relief data. Memory mat area, and a decoder section for decoding the memory identifier stored in the relief information storing memory mat area and outputting a permission signal to a non-volatile memory or a volatile memory according to the decoding result, and a decoder section. Based on the permission signal of
A first repair data storage section for storing repair data stored in the repair information storage memory mat area, and a defective memory including a defective bit based on the repair data stored in the first repair data storage section. Second relief data for storing relief data stored in the relief information storing memory mat area based on a permission signal of the decoder unit in the volatile memory. A storage unit and a relief bit area for relieving a defective memory bit area including a defective bit based on the relief data stored in the second relief data storage unit are provided.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a layout diagram of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing a configuration of a flash memory and a RAM provided in the semiconductor integrated circuit device of FIG. 3 is an explanatory diagram showing an example of the data structure of the relief information stored in the relief register provided in the flash memory of FIG. 2, and FIG. 4 is an explanatory diagram of relief in the flash memory and RAM of FIG. Figure 5
4 is an explanatory diagram of a memory identifier used for repair in the flash memory and RAM of FIG. 4, and FIG. 6 is an explanatory diagram showing an example of data reading / writing when repairing the flash memory and RAM of FIG. Figures and 7
2 is a flowchart of a repair test in the flash memory and RAM of FIG. 2, and FIG. 8 is a flash memory of FIG.
It is a flowchart which shows an example of the test order of the memory test in AM.

In the present embodiment, the semiconductor integrated circuit device 1 is a flash memory built-in type microcomputer. The semiconductor integrated circuit device 1 includes a flash memory (nonvolatile memory) 2, a RAM (volatile memory) 3, and C.
PU4, FPU5, multiplier 6, DMAC7, interrupt controller 8, BSC9, peripheral circuit 10, I / O ports 11 to 13, internal address bus 14, internal data bus 1
5, a peripheral address bus 16, a peripheral data bus 17, a control signal bus 18, and the like, which are formed on one semiconductor substrate.

As shown in FIG. 1, the flash memory 2 is provided on the upper left side, and a RAM 3 is provided on the right side of the flash memory 2. Below the flash memory 2, a CPU 4, an FPU 5, and a multiplier 6 are provided.

A DMAC 7 is provided below the RAM 3. An interrupt controller 8 is located below the multiplier 6, and a BSC 9 is located below the DMAC 7.
Is provided. Interrupt controller 8 and B
A peripheral circuit 10 is provided below SC9.

An I / O port 11 is provided above the RAM 3, and I / O ports 12 and 13 are provided on the right side of the RAM 3 from above to below.

The flash memory 2 is composed of a non-volatile semiconductor memory and stores various information such as programs and data. The RAM 3 is a memory that can be read / written at any time, and temporarily stores input / output data, operation data, and the like.

The CPU 4 reads the information stored in the flash memory 2 by a predetermined signal from the outside and performs a predetermined process. Further, the data generated by the processing of the CPU 4 and which needs to be stored even after the power supply to the semiconductor integrated circuit device 1 is temporarily stopped is written in the flash memory 2. Will be done.

The FPU 5 is a floating-point processing unit (Floating-point Processing Unit).
Unit), which performs floating-point arithmetic processing to speed up the data processing capability of the semiconductor integrated circuit device 1.

The multiplier 6 performs a multiplication process on all bits to be operated in parallel. The DMAC7 is a DMA (Dir
This is a control circuit that performs memory address selection and read / write control when performing ect Memory Access) processing.

The interrupt controller 8 controls interrupt processing from the CPU 4 and other peripheral circuits.
The BSC 9 divides the address space and outputs control signals according to various memories and peripheral devices.

The peripheral circuit 10 is, for example, a timer or a serial communication interface (SCI). The I / O port 11 is a port for inputting an address signal, the I / O port 12 is a port for inputting / outputting data, and the I / O port 13 is inputting / outputting various control signals. .

Then, the flash memory 2, the RAM 3,
CPU4, DMAC7, and I / O port 11 are
They are connected to each other via the internal address bus 14.
In addition, flash memory 2, RAM 3, FPU 5, multiplier 6, DMAC 7, BSC 9, and I / O port 1
The two are connected to each other via an internal data bus 15.

Further, the interrupt controller 8 and the BSC
9, peripheral circuit 10, and I / O ports 11 to 13
Are connected via a peripheral address bus 16 and a peripheral data bus 17, respectively.
BSC 9 and I / O port 13 are control signal bus 1
8 are connected to each other.

FIG. 2 is an explanatory diagram showing the configurations of the flash memory 2 and the RAM 3.

The flash memory 2 includes an identifier comparison circuit (first comparison storage unit, first identifier comparison unit) 2a, a relief register (first comparison storage unit, first relief data storage unit) 2b, and an input register. An output control unit 2c, a memory mat 2d, a relief information storage mat (relief information storage memory mat) 2e, and the like are provided.

The identifier comparing circuit 2a stores a preset unique memory identifier, compares the memory identifier with the transferred memory identifier, and determines whether or not the memory identifiers match. .

The relief register 2b is an identifier comparison circuit 2a.
When it is determined that the memory identifiers match, the relief data is stored. The input / output control unit 2c controls input / output of commands, external addresses, data, etc. based on the control signal.

The memory mat 2d and memory cells, which are the minimum unit of storage, are regularly arranged in an array. For example, data writing and erasing are performed by passing a tunnel current over the entire channel portion of the memory cell. , Discharging and injecting charges in the floating gate. In addition, the memory mat 2d is provided with a redundant mat (relief bit area) for relieving a defective memory cell or memory line.

Similarly, the rescue information storage mat 2e also has a structure in which memory cells are regularly arranged in an array, and the rescue information storage mat 2e stores rescue data and rescue information including a memory identifier. It

The RAM 3 is composed of n memory blocks 3 _{1 to} 3 _n . Memory block 3 ₁ ~
3 _n is provided with _n memory mats 3d _{1 to} 3d n each of which is formed by dividing a memory cell array in which memory cells are regularly arranged in an array into a certain number of bits. Also in the memory mat 3d _{1-3d n,} redundant mat relieving the like defective memory cell or a memory line (redundant bit regions) are respectively provided.

In these memory blocks 3 _{1 to} 3 _n , identifier comparison circuits (second comparison storage section, second identifier comparison section) 3 a _{1 to} 3 a _n , relief registers (second comparison storage section, second comparison storage section, second comparison storage section, second comparison storage section, second comparison storage section) repair data storage unit) 3b ₁ ~3b _n, and input-output control unit 3c ₁ ~3c _n are respectively provided.

Each of the identifier comparison circuits 3a _{1 to} 3a _n stores a preset unique memory identifier. Each identifier comparator circuit 3a ₁ to 3 A _n compares a memory identifier stored and transferred memory identifier, determines whether the memory identifiers match.

Relief register 3b₁~ 3b_nIs the identifier ratio
Comparison circuit 3a₁~ 3a_nMemory identifier matched by
When it is determined that the relief data is stored. I / O controller
3c ₁~ 3c_nCommand based on control signal, outside
Input / output control of copy address and data.

The relief information is transferred between the flash memory 2 and the RAM 3 via the internal data bus 15, for example. Further, a relief information distribution data bus may be newly provided without going through the internal data bus 15.

[0040] Here, the repair information and the repair register 2b (, 3b ₁ ~3b _n) for data structures stored in, will be described with reference to FIG.

As the memory identifier, the written relief data is the flash memory 2 and the memory blocks 3 _{1 to} 3
_It shows which one of _n . The number of bits of this memory identifier depends on the memory block 3 _{1 to be} relieved.
Match the number of ~ 3 _n . The relief data is information indicating which memory bit is to be replaced with the redundant bit.

The repair register 2b (, 3b ₁ ~3b _n), the enable bit, and repair data are stored, respectively. The enable bit is set when the comparison results of the memory identifiers match, and is not set when they do not match. The relief data is stored when the memory identifiers match and is valid only when the enable bit is set.

Next, regarding the redundancy repair technique of the semiconductor integrated circuit device according to the present embodiment, an explanatory view of the repair in the flash memory 2 and the RAM 3 of FIGS. 1, 2 and 4 and the memory identifier of FIG. This will be described with reference to FIGS. 6A and 6B, an explanatory diagram of data reading / writing after repairing, and FIGS. 7 and 8.

First, the flash memory 2 and the RAM
The memory test in 3 is performed (step S101).
In this case, for example, writing / erasing of data, depletion, and the like.

Then, it is determined whether or not there is a defective bit in the process of step S101 (step S1).
02). If there are defective bits, it is determined whether or not all of these defective bits can be relieved (step S).
103).

The case where the repair is not possible means, for example, that the number of defective bits is larger than the storage capacity of the repair information storage mat 2e, or the I / O unit (for example, 32 bits) is replaced by the same redundant mat. This is the case when there are defective bits in two or more blocks.

When the relief is possible, the relief information is written in the relief information storage mat 2e of the flash memory 2 (step S104). If the repair cannot be performed, the semiconductor integrated circuit device 1 becomes a defective product.

After performing the processing of these steps S101 to S104 up to the final address (step S105), the relief information written in the relief information storage mat 2e is transferred, and the flash memory 2 and the RAM 3 are relieved (step S106). .

Then, the flash memory 2 and the RAM 3 from which the defective bit has been relieved are subjected to a normal memory test (step S107).

Further, these steps S101 to S107
As shown in FIG. 8, this process is performed individually in the order of the flash memory 2 and the memory blocks 3 _{1 to} 3 _n . The order of this memory test is only an example, and the test order is not particularly limited.

Furthermore, the flash memory 2 and RA
The relief in M3 will be described.

Here, as an example, as shown in FIG. 4, the semiconductor integrated circuit device 1 has an RA including one flash memory 2 and two memory blocks 3 ₁ and 3 _2.
M3 is built in.

As shown in FIG. 5, "11" is stored in the flash memory 2 and "0" is stored in the memory blocks 3 ₁ and 3 _2.
Memory identifiers of 1'and '10' are respectively assigned.

For example, the memory identifier is "10",
When '0101' is written in the rescue information storage mat 2e as rescue data indicating which memory bit is to be replaced with the redundant bit, these '100101' are stored.
Data is transferred as repair information to the flash memory 2 and the identifier comparison circuits 2a, 3a ₁ and 3a ₂ of the memory blocks 3 ₁ and 3 ₂ via the internal data bus 15.

Each identifier comparing circuit 2a, 3a₁, 3a
₂Is a relief when the preset memory identifier is input
It is compared whether it matches the memory identifier of the information. this
If memory block 3₂Memory identifier is '10'
Since there is memory block 3 ₂Identifier comparison circuit 3a₂
Is the relief register 3b₂As an enable bit
1'is set and the relief data '0101' is set.
Store.

When reading data, as shown in FIG. 6A, the repair data stored in the repair register 3b ₂ is decoded by the decoder D1, and the selector S1 is switched according to the result to decode the redundant mat. Switch to I / O.

Further, in the case of writing data, FIG.
As shown in (b), the mat switching selector S2 is switched according to the result of decoding of the repair data of the repair register 3b ₂ by the decoder D2 to switch to the redundant mat I / O. Therefore, when reading / writing data, the redundant mat is switched in I / O units.

As a result, in the present embodiment, defective bits in both the flash memory 2 and the RAM 3 can be relieved, so that the yield of the semiconductor integrated circuit device 1 can be improved.

[0059] Further, according to this embodiment, the flash memory 2, and RAM 3, the identifier comparator circuit 2a, but the identifier comparator circuit 3a ₁ to 3 A _n has a structure in which respectively, for example, as shown in FIG. 9 In addition, the flash memory 2 may be provided with an identifier decoder (decoder unit) 2f for decoding the memory identifier and transferring the result as a 1-bit enable signal.

Then, the enable signal and the relief data are
The data is transferred via the enable signal line EL and the rescue data bus SL.

The enable signal line EL for transferring the enable signal and the rescue data bus SL for transferring the rescue data may be newly provided as shown in FIG. 9 or may be provided in the internal data bus. Good.

As a result, the identifier comparison circuit for each of the memory blocks 3 _{1 to} 3 _n of the RAM 3 can be eliminated, and the number of signal lines for transferring the memory identifier can be reduced, so that the semiconductor integrated circuit device can be miniaturized. can do.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications are possible without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the above embodiment, one R
Although the configuration for relieving the defective bit of AM has been described,
Even when a plurality of volatile memories are provided in the semiconductor integrated circuit device, the defective bits of the plurality of nonvolatile memories can be relieved by recognizing each volatile memory by the memory identifier.

Further, not only the volatile memory in the semiconductor integrated circuit device but also all the volatile memories on the electronic circuit constituting the electronic system can be repaired, and the yield of the electronic system is improved. Can be made.

[0066]

The effects obtained by the typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) In a semiconductor integrated circuit device having a built-in non-volatile memory and volatile memory, defective bits in the volatile memory can be relieved.

(2) By the above (1), the yield of the semiconductor integrated circuit device can be improved.

[Brief description of drawings]

FIG. 1 is a layout diagram of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a configuration of a flash memory and a RAM provided in the semiconductor integrated circuit device of FIG.

3 is an explanatory diagram showing an example of a data structure of relief information stored in a relief register provided in the flash memory of FIG.

FIG. 4 is an explanatory diagram of repair in the flash memory and RAM of FIG.

5 is an explanatory diagram of a memory identifier used for repair in the flash memory and the RAM of FIG.

FIG. 6 is an explanatory diagram showing an example of data reading / writing when the flash memory and RAM of FIG. 4 are repaired.

7 is a flowchart of a repair test in the flash memory and RAM of FIG.

8 is a flowchart showing an example of a test order of a memory test in the flash memory and the RAM of FIG.

FIG. 9 is an explanatory diagram showing a configuration of a flash memory and a RAM provided in a semiconductor integrated circuit device according to another embodiment of the present invention.

[Explanation of symbols]

1 Semiconductor Integrated Circuit Device 2 Flash Memory (Nonvolatile Memory) 2a Identifier Comparison Circuit (First Comparison Storage Unit, First Identifier Comparison Unit) 2b Relief Register (First Comparison Storage Unit, First Relief Data Storage Unit) ) 2c output control unit 2d memory mat 2e relief information storing mat (memory mat storing redundant information) 2f identifier decoder (decoder) 3 RAM (volatile memory) 3 ₁ to 3 _n memory blocks 3a ₁ to 3 a _n identifier Comparison circuit (second comparison storage unit,
Second identifier comparison unit) 3b ₁ ~3b _n repair register (second comparison storage unit, the second repair data storage unit) 3c ₁ ~3c _n output control unit 3d _{1-3d n} memory mat 4 CPU 5 FPU 6 Multiplier 7 DMAC 8 Interrupt controller 9 BSC 10 Peripheral circuits 11-13 I / O port 14 Internal address bus 15 Internal data bus 16 Peripheral address bus 17 Peripheral data bus 18 Control signal buses D1, D2 Decoder S1 Selector S2 Mat switching selector EL enable signal line SL rescue data bus

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Naoki Yada             Hitachi, 145 Nakajima, Nanae-cho, Kameda-gun, Hokkaido             Inside North Sea Semiconductor Co., Ltd. F-term (reference) 5B018 GA04 HA21 NA06                 5B025 AD01 AD13 AE08                 5L106 AA01 AA02 AA10 CC01 CC09                       CC16 CC17 CC22 GG01 GG07

Claims (4)

[Claims] 1. A memory identifier, a memory mat area for storing relief information for storing relief information composed of relief data, a memory identifier given in advance and a memory identifier stored in the memory mat area for storing relief information. Based on the relief data stored in the first comparison storage unit and the first comparison storage unit that stores the relief data stored in the relief information storage memory mat area when they match. A nonvolatile memory provided with a relief bit area for relieving a defective memory bit area including a defective bit is compared with a memory identifier given in advance and a memory identifier stored in the relief information storing memory mat area, A second comparison storage unit for storing the relief data stored in the relief information storage memory mat area when they match, and the second comparison storage unit Based on the stored repair data, the semiconductor integrated circuit device which is characterized in that a volatile memory provided a redundant bit region for relieving a defective memory bit area including a defective bit. 2. A memory identifier and a memory mat area for storing relief information for storing relief information consisting of relief data, a memory identifier given in advance and a memory identifier stored in the memory mat area for storing relief information. Stored in the relief information storage memory mat area based on the permission signal output from the first identifier comparison unit that outputs a permission signal when they match A first relief data storage section for storing relief data and a relief bit area for relieving a defective memory bit area including a defective bit based on the relief data stored in the first relief data storage section are provided. When the non-volatile memory and the memory identifier stored in the relief information storage memory mat area are compared with each other A second identifier comparing section that outputs a permission signal, and a second identifier storing section that stores the relief data stored in the relief information storing memory mat area based on the permission signal output from the second identifier comparing section. A volatile memory having a repair data storage section and a repair bit area for repairing a defective memory bit area including a defective bit based on the repair data stored in the second repair data storage section is provided. A semiconductor integrated circuit device characterized by the above. 3. A memory identifier and a memory mat area for storing rescue information in which rescue information composed of rescue data is stored, a memory identifier given in advance and a memory identifier stored in the memory mat area for storing rescue information. And a first identifier comparing section for generating an enable bit when they match and the enable bit output from the first identifier comparing section is stored and stored in the relief information storing memory mat area. A first relief data storage section for storing the relief data and a relief bit area for relieving the defective memory bit area including the defective bit based on the relief data stored in the first relief data storage section. Non-volatile memory provided, memory identifier given in advance and memory identification stored in the memory mat area for storing relief information And a second identifier comparing unit that generates an enable bit when they match, and the enable bit output from the second identifier comparing unit is stored and stored in the rescue information storing memory mat area. A second repair data storage section for storing the repaired repair data, and a repair bit area for repairing a defective memory bit area including a defective bit based on the repair data stored in the second repair data storage section. And a volatile memory provided with the semiconductor integrated circuit device. 4. A semiconductor integrated circuit device having a non-volatile memory and a volatile memory built-in, wherein the non-volatile memory is for storing rescue information in which rescue information including a memory identifier and rescue data is stored. A memory mat area, a decoder section for decoding the memory identifier stored in the memory mat area for storing relief information, and outputting a permission signal to the non-volatile memory or the volatile memory according to a result of the decoding; A relief data storage unit for storing relief data stored in the relief information storage memory mat area based on a permission signal of a copy unit, and a relief data stored in the first relief data storage unit And a relief bit area for relieving a defective memory bit area including a defective bit. A second relief data storage unit for storing the relief data stored in the relief information storage memory mat area based on a permission signal of a copy section; and a relief data stored in the second relief data storage unit. And a relief bit area for relieving a defective memory bit area.