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JP2003084265A - Method for polishing liquid crystal panel substrate - Google Patents

Method for polishing liquid crystal panel substrate

Info

Publication number
JP2003084265A
JP2003084265A JP2001375340A JP2001375340A JP2003084265A JP 2003084265 A JP2003084265 A JP 2003084265A JP 2001375340 A JP2001375340 A JP 2001375340A JP 2001375340 A JP2001375340 A JP 2001375340A JP 2003084265 A JP2003084265 A JP 2003084265A
Authority
JP
Japan
Prior art keywords
pad area
liquid crystal
polishing
crystal panel
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001375340A
Other languages
Japanese (ja)
Inventor
Kokucho Ryo
國超 梁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hannstar Display Corp
Original Assignee
Hannstar Display Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hannstar Display Corp filed Critical Hannstar Display Corp
Publication of JP2003084265A publication Critical patent/JP2003084265A/en
Pending legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • B24B37/04Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/042Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B13/00Machines or devices designed for grinding or polishing optical surfaces on lenses or surfaces of similar shape on other work; Accessories therefor
    • B24B13/015Machines or devices designed for grinding or polishing optical surfaces on lenses or surfaces of similar shape on other work; Accessories therefor of television picture tube viewing panels, headlight reflectors or the like
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/133302Rigid substrates, e.g. inorganic substrates
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00Materials and properties
    • G02F2202/22Antistatic materials or arrangements

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Nonlinear Science (AREA)
  • Liquid Crystal (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method for polishing a liquid crystal panel. SOLUTION: The liquid crystal panel is subjected to polishing after a protective element 33 is stuck to pad regions 311, 312 arranged on a thin film transistor substrate 31. The protective element is removed from the thin film transistor substrate after polishing the liquid crystal panel.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は液晶パネル研磨方法
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal panel polishing method.

【0002】[0002]

【従来の技術】液晶パネルの重量を軽減するための従来
の方法は、化学機械研磨方法(CMP)、化学エッチング
法及び低密度のガラス基板を用いる方法がある。本発明
は化学機械研磨方法に対し改良を加えたものである。
2. Description of the Related Art Conventional methods for reducing the weight of a liquid crystal panel include a chemical mechanical polishing method (CMP), a chemical etching method, and a method using a low density glass substrate. The present invention is an improvement over the chemical mechanical polishing method.

【0003】公知の化学機械研磨方法は2種の方法があ
る。第1つの方法は、薄膜トランジスタ(TFT)基板と
カラーフィルター(CF)基板とを組み合わせた後、研磨
を施すものである。その後、切割、液晶の注入/封止及
び偏光板の接合が行われる。
There are two types of known chemical mechanical polishing methods. The first method is to combine a thin film transistor (TFT) substrate and a color filter (CF) substrate and then perform polishing. After that, cutting, liquid crystal injection / sealing, and polarizing plate bonding are performed.

【0004】しかし、図1で示されるように、従来の研
磨処理は液晶を注入する前に行われるため、研磨液がパ
ネル13に滲み出るのを防止するシール剤12を設けな
ければいけない。また、研磨によって基板が薄くなるた
め、後段の工程の困難度が増す。又、シール剤12を配
置する空間も必要で、基板上の利用可能面積が減少して
しまう。
However, as shown in FIG. 1, since the conventional polishing process is performed before the liquid crystal is injected, the sealing agent 12 must be provided to prevent the polishing liquid from seeping out to the panel 13. In addition, since the substrate is thinned by polishing, the difficulty of the subsequent steps increases. Further, a space for arranging the sealant 12 is also required, which reduces the usable area on the substrate.

【0005】第2の方法は、薄膜トランジスタ基板とカ
ラーフィルター基板とを組み合わせた後、切割、液晶の
注入/封止工程を施して、次に研磨工程を行い、最後に
偏光板を接合するものである。
The second method is to combine a thin film transistor substrate and a color filter substrate, then perform a cutting process, a liquid crystal injection / sealing process, a polishing process, and finally a polarizing plate. is there.

【0006】しかし、第2の方法では以下の問題が生じ
る恐れがある。 1.図2で示されるように、研磨加工時、液晶パネル2
1のパッド区域22が露出して、回路が損傷し、腐蝕が
生じる。 2.液晶パネルが研磨される前に、静電気防止(ESD)
リングが研磨除去されるので、静電気により液晶パネル
が破損する。静電気防止リングが研磨前に除去されてい
ない場合には、液晶パネルの研磨後、ESDリングを取り
除く工程を施さなければならず、これにより、ガラス基
板が薄くなる虞がある。
However, the following problem may occur in the second method. 1. As shown in FIG. 2, during polishing, the liquid crystal panel 2
The one pad area 22 is exposed, damaging the circuit and causing corrosion. 2. Antistatic (ESD) before the LCD panel is polished
Since the ring is removed by polishing, the liquid crystal panel is damaged by static electricity. If the antistatic ring is not removed before polishing, a step of removing the ESD ring must be performed after polishing the liquid crystal panel, which may result in thinning of the glass substrate.

【0007】[0007]

【発明が解決しようとする課題】本発明の目的は従来方
法をできるだけ変えずに液晶パネルの歩留りを向上する
ことのできる液晶パネルの研磨方法を提供することにあ
る。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for polishing a liquid crystal panel, which can improve the yield of the liquid crystal panel without changing the conventional method as much as possible.

【0008】[0008]

【課題を解決するための手段】本発明の一態様では、パ
ッド区域の設けられた薄膜トランジスタ基板を備える液
晶パネルの研磨方法が提供される、上述の方法は、保護
素子を用意する工程と、保護素子により薄膜トランジス
タ基板のパッド区域を被覆する工程と、液晶パネルに対
して研磨を施す工程と、保護素子を薄膜トランジスタ基
板から除去する工程とからなる。
According to one aspect of the present invention, there is provided a method of polishing a liquid crystal panel including a thin film transistor substrate having a pad area. The method comprises the steps of providing a protective element and protecting the protective element. The device comprises the steps of covering the pad area of the thin film transistor substrate, polishing the liquid crystal panel, and removing the protective element from the thin film transistor substrate.

【0009】本発明の別の態様では、パッド区域を備え
る薄膜トランジスタ基板及びカラーフィルタ基板を有す
る液晶パネルの研磨方法が提供される。予め、液晶パネ
ルは所定の大きさに切割され、液晶を注入した後、封止
されている。前記方法は、保護素子を用意し、保護素子
により薄膜トランジスタ基板のパッド区域を被覆する。
液晶パネルに対して研磨を施して、保護素子を薄膜トラ
ンジスタ基板から除去する。
In another aspect of the present invention, there is provided a method of polishing a liquid crystal panel having a thin film transistor substrate having a pad area and a color filter substrate. The liquid crystal panel is cut into a predetermined size in advance, and after injecting liquid crystal, it is sealed. The method provides a protection element and covers the pad area of the thin film transistor substrate with the protection element.
The liquid crystal panel is polished to remove the protective element from the thin film transistor substrate.

【0010】保護素子は複数の層からなり、パッド区域
と接触する層は導電性を有することが好ましい。薄膜ト
ランジスタ基板のパッド区域は、ゲートパッド区域とデ
ータパッド区域とを備え、ゲートパッド区域を被覆する
保護素子とデータパッド区域を被覆する保護素子は連続
していても連続していなくてもよい。
The protective element comprises a plurality of layers, the layer in contact with the pad area preferably being electrically conductive. The pad area of the thin film transistor substrate comprises a gate pad area and a data pad area, and the protective element covering the gate pad area and the protective element covering the data pad area may or may not be continuous.

【0011】[0011]

【発明の実施の形態】以下に本発明の好ましい実施の形
態について、図面を参照しながら詳しく説明する。
BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described in detail below with reference to the drawings.

【0012】図3a〜図3cは本発明の第1実施形態の
液晶パネル研磨方法を示す。図3aで示されるように、
液晶パネル30は、薄膜トランジスタ基板31及びカラ
ーフィルタ基板32を備える。液晶パネル30は所定の
大きさに形成後、液晶が注入され、液晶が封止される。
その後、液晶パネル30は研磨される。薄膜トランジス
タ基板31上にゲートパッド区域312とデータパッド
区域311とからなるパッド区域が設置される。
3a to 3c show a liquid crystal panel polishing method according to a first embodiment of the present invention. As shown in Figure 3a,
The liquid crystal panel 30 includes a thin film transistor substrate 31 and a color filter substrate 32. After the liquid crystal panel 30 is formed into a predetermined size, the liquid crystal is injected and the liquid crystal is sealed.
Then, the liquid crystal panel 30 is polished. A pad area including a gate pad area 312 and a data pad area 311 is provided on the thin film transistor substrate 31.

【0013】本発明の液晶パネル研磨方法は、図3aで
示されるように、保護素子33を用意する工程と、図3
bで示されるように、保護素子33を薄膜トランジスタ
基板31のパッド区域311、312を覆うように貼り
付ける工程と、図3cで示されるように、液晶パネル3
0に対して研磨を施して、保護素子33を薄膜トランジ
スタ基板31から除去する工程と、からなる上述のよう
に、本発明では、研磨工程の前に保護素子33の貼り付
け工程を行い、研磨工程の後に保護素子33の除去工程
を行うだけで、研磨工程中、パネル上の回路(図示しな
い)を保護することが出来、他にシール剤は必要ない。
即ち、本発明は、公知の工程をできるだけ変えないで、
液晶パネルを軽量化するすることが出来、液晶パネルの
完成品の歩留りを向上することができる。
The liquid crystal panel polishing method of the present invention comprises the steps of preparing a protective element 33, as shown in FIG.
b, attaching the protective element 33 to cover the pad areas 311, 312 of the thin film transistor substrate 31, and the liquid crystal panel 3 as shown in FIG. 3c.
As described above, the protective element 33 is removed from the thin film transistor substrate 31 by polishing the protective element 33 from the thin film transistor substrate 31, and in the present invention, the protective element 33 is attached before the polishing step. The circuit (not shown) on the panel can be protected during the polishing step only by removing the protective element 33 after the above step, and no other sealant is required.
That is, the present invention does not change known steps as much as possible,
The liquid crystal panel can be reduced in weight, and the yield of finished liquid crystal panels can be improved.

【0014】又、保護素子33は複数の層からなり、パ
ッド区域311、312と接触する層は導電性を有す
る。これにより、保護素子33は図3bで示されるよう
にパッド区域311、312上に設置された時、ゲート
パッド区域312に接触する保護素子332とデータパ
ッド区域311に接触する保護素子331は連続してい
るため、保護素子33は回路保護膜の機能を有するだけ
でなく、静電気防止の効能も併せ持つ。
The protective element 33 is composed of a plurality of layers, and the layer contacting the pad areas 311 and 312 is electrically conductive. Accordingly, when the protection element 33 is installed on the pad areas 311, 312 as shown in FIG. 3b, the protection element 332 contacting the gate pad area 312 and the protection element 331 contacting the data pad area 311 are continuous. Therefore, the protection element 33 has not only the function of the circuit protection film but also the effect of preventing static electricity.

【0015】図4は本発明の第2実施形態の液晶パネル
研磨方法を示す。第2実施形態では、ゲートパッド区域
312上に設けられた保護素子332とデータパッド区
域311上に設けられた保護素子331とが用いられ
る。この場合、データパッド区域311とゲートパッド
区域312とは保護素子331、332により接続され
ない。
FIG. 4 shows a liquid crystal panel polishing method according to the second embodiment of the present invention. In the second embodiment, the protection element 332 provided on the gate pad area 312 and the protection element 331 provided on the data pad area 311 are used. In this case, the data pad area 311 and the gate pad area 312 are not connected by the protection elements 331 and 332.

【0016】図5は本発明の第3実施形態の液晶パネル
研磨方法を示す。第3実施形態では、第1実施形態と異
なる液晶パネル40の研磨方法を提供する。図5で示さ
れる液晶パネル40は薄膜トランジスタ基板41及びカ
ラーフィルター42で構成され、薄膜トランジスタ基板
41上には、ゲートパッド区域412と2つのデータバ
ッド区域411とからなるパッド区域が設けられてい
る。
FIG. 5 shows a liquid crystal panel polishing method according to a third embodiment of the present invention. The third embodiment provides a polishing method of the liquid crystal panel 40 different from the first embodiment. The liquid crystal panel 40 shown in FIG. 5 is composed of a thin film transistor substrate 41 and a color filter 42, and a pad area including a gate pad area 412 and two data pad areas 411 is provided on the thin film transistor substrate 41.

【0017】図5の薄膜トランジスタ基板41は図3a
の薄膜トランジスタ基板31と比べると、データパッド
区域を一つ多く有するが、そのもう一つのデータパッド
区域を覆う保護素子を貼り付ければよい。このように、
異なる形式のパネルであっても、本発明の研磨方法は製
品の歩留りを向上することが出来る。
The thin film transistor substrate 41 of FIG. 5 is shown in FIG.
Although it has one more data pad area as compared with the thin film transistor substrate 31, the protection element covering the other data pad area may be attached. in this way,
Even for different types of panels, the polishing method of the present invention can improve the product yield.

【0018】尚、図5中で、ゲートパッド区域412に
貼接された保護素子とデータパッド区域411に貼接さ
れた保護素子も連続するか連続しないかを選択すること
が出来る。言い換えると、保護素子としては、第1実施
形態のように一体のものでもよく、第2実施形態のよう
に分割されたものでもよい。
In FIG. 5, the protection element attached to the gate pad area 412 and the protection element attached to the data pad area 411 can be either continuous or non-continuous. In other words, the protective element may be integrated as in the first embodiment or may be divided as in the second embodiment.

【0019】[0019]

【発明の効果】本発明のパネルの研磨方法によれば、製
品の歩留りを向上することが出来る。
According to the panel polishing method of the present invention, the yield of products can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来の液晶パネルの概略平面図。FIG. 1 is a schematic plan view of a conventional liquid crystal panel.

【図2】別の従来の液晶パネルの側面図。FIG. 2 is a side view of another conventional liquid crystal panel.

【図3】本発明の第1実施形態に従う液晶パネルの研磨
方法を示す図である。
FIG. 3 is a diagram showing a method of polishing a liquid crystal panel according to the first embodiment of the present invention.

【図4】本発明の第2実施形態に従う液晶パネルの研磨
方法を示す図である。
FIG. 4 is a diagram showing a method of polishing a liquid crystal panel according to a second embodiment of the present invention.

【図5】本発明の第3実施形態に従う液晶パネルの研磨
方法を示す図である。
FIG. 5 is a diagram showing a polishing method for a liquid crystal panel according to a third embodiment of the present invention.

【符号の説明】[Explanation of symbols]

30、40…液晶パネル、31、41…TFT基板、3
2、42…カラーフィルタ基板、33、331,332
…保護素子、311、411…データパッド区域、31
2、412…ゲートパッド区域。
30, 40 ... Liquid crystal panel, 31, 41 ... TFT substrate, 3
2, 42 ... Color filter substrate, 33, 331, 332
... Protection element 311, 411 ... Data pad area, 31
2, 412 ... Gate pad area.

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】パッド区域の設けられた薄膜トランジスタ
基板を含む液晶パネルの研磨方法であって、 保護素子を用意する工程(a)と、 前記保護素子により前記薄膜トランジスタ基板の前記パ
ッド区域を被覆する工程(b)と、 前記液晶パネルに対して研磨を施す工程(c)と、 前記保護素子を前記薄膜トランジスタ基板から除去する
工程(d)と、からなることを特徴とする研磨方法。
1. A method of polishing a liquid crystal panel including a thin film transistor substrate having a pad area, the method comprising: providing a protective element; and covering the pad area of the thin film transistor substrate with the protective element. A polishing method comprising: (b); a step (c) of polishing the liquid crystal panel; and a step (d) of removing the protective element from the thin film transistor substrate.
【請求項2】前記保護素子は複数の層からなり、前記パ
ッド区域に接触する層は導電性を有することを特徴とす
る請求項1に記載の研磨方法。
2. The polishing method according to claim 1, wherein the protective element is composed of a plurality of layers, and the layer contacting the pad area is conductive.
【請求項3】前記工程(c)において、前記パッド区域
はゲートパッド区域とデータパッド区域とからなり、前
記ゲートパッド区域を被覆する保護素子と前記データパ
ッド区域を被覆する保護素子が連続していることを特徴
とする請求項2に記載の研磨方法。
3. In the step (c), the pad area comprises a gate pad area and a data pad area, and a protection element covering the gate pad area and a protection element covering the data pad area are continuously formed. The polishing method according to claim 2, wherein
【請求項4】前記工程(c)において、前記パッド区域
はゲートパッド区域とデータパッド区域とからなり、前
記ゲートパッド区域を被覆する保護素子と前記データパ
ッド区域を被覆する保護素子が連続していないことを特
徴とする請求項2に記載の研磨方法。
4. In the step (c), the pad area comprises a gate pad area and a data pad area, and a protective element covering the gate pad area and a protective element covering the data pad area are continuous. The polishing method according to claim 2, wherein the polishing method is absent.
【請求項5】パッド区域を備える薄膜トランジスタ基板
及びカラーフィルタ基板とを有し、所定の大きさに切割
され、液晶が注入された後、封止された液晶パネルの研
磨方法であって、 保護素子を用意する工程(a)と、 前記保護素子により前記薄膜トランジスタ基板のパッド
区域を被覆する工程(b)と、 前記液晶パネルに対して研磨を施す工程(c)と、 前記保護素子を前記薄膜トランジスタ基板から除去する
工程(d)と、からなることを特徴とする研磨方法。
5. A method for polishing a liquid crystal panel, comprising a thin film transistor substrate having a pad area and a color filter substrate, cut into a predetermined size, filled with a liquid crystal, and sealed. (A), a step (b) of covering a pad area of the thin film transistor substrate with the protective element, a step (c) of polishing the liquid crystal panel, and a step of providing the protective element with the thin film transistor substrate. And a step (d) of removing from the polishing method.
【請求項6】前記保護素子は複数の層からなり、前記パ
ッド区域に接触する層は導電性を有することを特徴とす
る請求項5に記載の研磨方法。
6. The polishing method according to claim 5, wherein the protective element is composed of a plurality of layers, and the layer contacting the pad area is conductive.
【請求項7】前記工程(c)において、前記パッド区域
はゲートパッド区域とデータパッド区域とからなり、前
記ゲートパッド区域を被覆する保護素子と前記データパ
ッド区域を被覆する保護素子が連続していることを特徴
とする請求項6に記載の研磨方法。
7. In the step (c), the pad area comprises a gate pad area and a data pad area, and a protection element covering the gate pad area and a protection element covering the data pad area are continuously formed. The polishing method according to claim 6, wherein:
【請求項8】前記工程(c)において、前記パッド区域
はゲートパッド区域とデータパッド区域とからなり、前
記ゲートパッド区域を被覆する保護素子と前記データパ
ッド区域を被覆する保護素子が連続していないことを特
徴とする請求項6に記載の研磨方法。
8. In the step (c), the pad area comprises a gate pad area and a data pad area, and a protection element covering the gate pad area and a protection element covering the data pad area are continuous. The polishing method according to claim 6, wherein the polishing method is absent.
JP2001375340A 2001-09-12 2001-12-10 Method for polishing liquid crystal panel substrate Pending JP2003084265A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW90122574 2001-09-12
TW90122574 2001-09-12

Publications (1)

Publication Number Publication Date
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ID=21679298

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Application Number Title Priority Date Filing Date
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Country Status (2)

Country Link
US (1) US20030049994A1 (en)
JP (1) JP2003084265A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7182877B2 (en) 2002-12-10 2007-02-27 Seiko Epson Corporation Method for manufacturing electro-optical device, electro-optical device, and electronic apparatus
KR100712108B1 (en) 2004-12-10 2007-04-27 삼성에스디아이 주식회사 Organic electroluminescent display and manufacturing method thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220029015A (en) * 2020-09-01 2022-03-08 엘지디스플레이 주식회사 Display device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7182877B2 (en) 2002-12-10 2007-02-27 Seiko Epson Corporation Method for manufacturing electro-optical device, electro-optical device, and electronic apparatus
KR100712108B1 (en) 2004-12-10 2007-04-27 삼성에스디아이 주식회사 Organic electroluminescent display and manufacturing method thereof

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