JP2003078919A - Image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image pickup device that has many pixels and can easily suppress color resolution from being deteriorated, false color from being produced and the color S/N from being degraded even when the sensitivity is increased by summation of pixels. SOLUTION: Summing electric charges stored in four pixels in the same color closely distributed to each other over a plurality of rows and columns as to pixels in first, second and third colors produces a summed electric charge and individually detecting the summed electric charge produces a unit signal used to generate an image signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup device, and more particularly, to an image pickup device having a large number of pixels arranged in a staggered manner.

[0002]

2. Description of the Related Art Since the integration technology and mass production technology of CCD (charge coupled device) was established, image pickup devices such as digital still cameras and digital video cameras using CCD type solid-state image pickup devices as area image sensors have been rapidly developed. Is popular in

In the CCD type solid-state image pickup device, a vertical charge transfer device (VCCD), in which a large number of pixels are arranged in a matrix over a plurality of rows and a plurality of columns on one surface of a semiconductor substrate, and which is composed of a CCD, For example, one pixel row is provided along each pixel row. Further, a horizontal charge transfer device (HCCD) composed of a CCD is arranged so as to be electrically connectable to an output terminal of each vertical charge transfer device.

For example, a single plate type C used for color photography
In the CD-type solid-state imaging device, a large number of photoelectric conversion elements (for example, photodiodes) are arranged in a matrix on one surface of a semiconductor substrate, and a color filter array is arranged above the photoelectric conversion elements.
The color filter array is composed of color filters arranged one above each photoelectric conversion element. If necessary, microlenses are arranged on the color filters.

When light is incident on a pixel, an amount of charge corresponding to the amount of light is accumulated in the photoelectric conversion element of this pixel. The charges accumulated in each pixel (photoelectric conversion element) are read out to the vertical charge transfer element and transferred to the horizontal charge transfer element. The charge of each pixel belonging to one pixel row is read to the corresponding vertical charge transfer element at the same timing and transferred to the horizontal charge transfer element at the same timing. The horizontal charge transfer device sequentially transfers charges in a predetermined direction and outputs the charges.

The charges output from the horizontal charge transfer element are
It is detected by the output circuit unit formed on the semiconductor substrate or another substrate. The electric charge after being detected is absorbed in the power supply voltage after being swept out to the drain region, for example.

An image pickup apparatus using a CCD type solid-state image pickup element generates an image signal by using a signal voltage (pixel signal; unit signal) output from an output circuit section.

Conventionally, in a CCD type solid-state image sensor used as an area image sensor, a large number of pixels are arranged in a square matrix (including those having different numbers of rows and columns).

In recent years, there has been a demand for higher resolution and higher sensitivity of a CCD type solid-state image pickup element, and a pixel in which high integration of photoelectric conversion elements is easy while keeping a large light receiving area of each photoelectric conversion element. The staggered arrangement has become popular.

Here, the "pixel shift arrangement" referred to in the present specification refers to each pixel in an odd-numbered pixel row,
Each of the pixels in the even-numbered pixel row is shifted by about 1/2 of the pixel pitch in the pixel row in the column direction, and for each pixel in the odd-numbered pixel row, in the even-numbered pixel row Each pixel is approximately one pixel pitch within the pixel row
/ 2, which means an arrangement of a large number of pixels, which is shifted in the row direction and in which each pixel column includes only pixels in odd rows or even rows. The pixel shift arrangement is one mode in which a large number of pixels are arranged in a matrix over a plurality of rows and a plurality of columns.

The above-mentioned "about 1 of the pitch of the pixels in the pixel row"
"/ 2" means that the obtained CC does not include 1/2 but is out of 1/2 due to factors such as a manufacturing error, a pixel position rounding error caused by design or mask fabrication, etc.
It also includes a value that can be regarded as substantially equal to 1/2 in view of the performance of the D image sensor and the image quality of the image. In the above, "about 1 of the pixel pitch in the pixel row
The same applies to "/ 2".

[0012]

When the subject is too dark, it is not possible to obtain sufficient photographic sensitivity even with an image pickup apparatus using a solid-state image pickup element in which a large number of pixels are arranged in a shifted manner. When the subject is at a short distance, a flash device such as a strobe may be used to obtain sufficient shooting sensitivity even when the subject is dark. Even if such a flash device is used, sufficient photographing sensitivity may not be obtained.

It is possible to sensitize the image pickup device by adding (mixing) charges read out from a plurality of pixels in the vertical charge transfer element, in the horizontal charge transfer element or in the output circuit section. In this specification, adding charges read from a plurality of pixels may be referred to as “pixel addition”.

For example, in an image pickup device using a single-plate type solid-state image pickup device having a color filter array of three primary colors, it depends on the structure of the color filter array and the method of pixel addition.
When pixel addition is performed between three adjacent pixels, addition signals (G + R + B), (2G + B), (G + R + B), and (2G + R) may be continuously generated. Here, G, R, and B represent the output signals of the green pixel, the red pixel, and the blue pixel, respectively.

When such an addition signal is generated, the signal component of the color information decreases, so that the color resolution deteriorates and the S / N ratio of the color decreases.

An object of the present invention is to have a large number of pixels, and it is easy to suppress deterioration of color resolution, occurrence of false color and deterioration of S / N ratio of color even when sensitized by pixel addition. Another object of the present invention is to provide a simple imaging device.

[0017]

According to one aspect of the present invention, a large number of pixels arranged in a plurality of rows and a plurality of columns and electric charges accumulated in the pixels are read out and the electric charges are detected. And a unit signal generation unit that generates a unit signal used for generating an image signal, each of the plurality of pixels includes a color filter, and the first color pixel, The unit signal generation unit is classified into three types of two-color pixels and third-color pixels, and the unit signal generation unit (i) individually detects an electric charge accumulated in each of the pixels to generate the unit signal. And (ii) for each of the first to third color pixels, the added charge is obtained by adding the charges accumulated in the four pixels of the same color, which are distributed close to each other over a plurality of rows and a plurality of columns. To generate a unit signal by separately detecting the added charge Imaging apparatus is provided that the addition read operation, it is possible to selectively perform that.

When performing pixel addition in an image pickup device having a large number of pixels composed of a first color pixel, a second color pixel, and a third color pixel, four pixels of the same color are selected as described above. By adding, it becomes easy to obtain a lot of luminance signals (luminance information) and it becomes easy to obtain a lot of color information necessary for generating a green, red, or blue color signal.

As a result, even when pixel addition is performed, it is easy to suppress a decrease in color resolution, the occurrence of false colors, and a decrease in color S / N ratio.

The first color pixel, the second color pixel, or the third color pixel referred to in the present specification includes a pixel provided with a colorless and transparent filter and a pixel not provided with a color filter. The “color of the color filter” includes colorless and transparent. “Classifying pixels by color of color filter” means classifying pixels by color of color filters including colorless and transparent, and classifying pixels that do not have color filters as one group. To do.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 schematically shows a plane arrangement of pixels in a solid-state image pickup device 100 used in an image pickup apparatus according to a first embodiment. As shown in the figure, in the solid-state imaging device 100, a large number of green pixels G, red pixels R,
And the blue pixels B are arranged in a shifted manner.

Each pixel has a photoelectric conversion element and a color filter arranged above the photoelectric conversion element. The shape of the pixel shown in FIG. 1 shows the outline of the color filter included in this pixel. The color of a pixel indicates the color of the color filter included in this pixel.

The individual pixel rows are classified into a first type pixel row PR1 composed of only green pixels G and a second type pixel row in which red pixels R and blue pixels B are alternately and repeatedly arranged. You can The second type pixel row is further divided into a second type pixel row PR2A and a second type pixel row PR2B in which the arrangement of the red pixels R and the blue pixels B is reversed.

From the downstream side (the lower side of the paper of FIG. 1) to the upstream side (the upper side of the paper of FIG. 1), the first type pixel row PR1 and the second pixel row PR1
The similar pixel row PR2A, the first kind pixel row PR1, and the second kind pixel row PR2B are repeatedly arranged in this order.
The first type pixel row PR1 at the bottom of the page corresponds to the most downstream pixel row.

In the present specification, the movement of charges from a pixel (photoelectric conversion element) to a unit signal generation section (output circuit section) described later is regarded as one flow, and relative movement of individual members and the like. The position is referred to as "how much upstream", "how many downstream", etc., as necessary.

In the solid-state image pickup device 100, when the pixel addition is performed, the luminance information is deteriorated, the false color is generated, and the color S is reduced.
Pixel addition is performed between four pixels of the same color so that the reduction of the / N ratio is suppressed. Hereinafter, this pixel addition is referred to as “four pixel addition”.

FIG. 2 shows an example of a combination of pixels that are added to each other when the 4-pixel addition is performed using the solid-state image pickup device 100. In the figure, for the sake of convenience, the size of each pixel is made smaller than the size in FIG. 1, the distance between them is expanded, and the shape is also changed. In addition, FIG. 2 also schematically shows the horizontal charge transfer element 40 and the output circuit section 50 that form part of the unit signal generation section.

In the case of 4-pixel addition, eight consecutive pixel rows form one unit U, and each unit U is
Further, it is divided into a first block BL1 composed of four pixel rows on the downstream side and a second block which is opposed by the four pixel rows on the upstream side.

Four green pixels G connected by two-dot chain lines distributed in every other two pixel columns in the same block BL1 or BL2 are added before being detected by the output circuit section 50. .

The red pixels R are added together before being detected by the output circuit section 50 by the four red pixels R connected by the broken lines which are distributed in two pixel columns every other column in each unit U.

As with the red pixel R, the blue pixel B is also detected by the output circuit section 50 as four pixels connected by alternate long and short dash lines distributed in every other two pixel columns in each unit U. Added before.

The charges read from the end pixels which are not pixel-added are transferred to the output circuit section 50 and then swept out.

By devising the driving method of the unit signal generating section, it is possible to generate the added charge by mixing (adding) the charges read from the four pixels with each other in the output circuit section 50, and to add the added charge. Can also be generated in the horizontal charge transfer device 40. In either case, in the vertical charge transfer device not shown in FIG.
It is preferable to add in advance the charges read from the respective pixels.

Since the charges accumulated in the four pixels of the same color are added before being detected by the output circuit section 50, the output from the output circuit section 50 increases and the S / N ratio can be improved. it can.

The signal output from the unit signal generation section (output circuit section 50) based on the detection of the added charge does not become a white color signal, and this signal always includes color information of green, red, or blue. . It is possible to obtain resolution signals of many colors as compared with the case where pixel addition including a combination of pixels for which a white color signal is generated is performed.

FIG. 3 shows the geometric center of four pixels which are added to each other when four-pixel addition is performed with the combination shown in FIG. 2 by the color G, R, or B of the pixel.

As is apparent from the figure, the unit signal generation based on the 4-pixel addition in the combination shown in FIG. 2 is performed by the green pixel G, the red pixel R, and the blue pixel arranged at the positions shown in FIG. This is almost equivalent to generating a unit signal based on the charges read from B.

Color information can be obtained using the unit signal generated by the output circuit unit based on the addition of four pixels for each of the green pixel, the red pixel, and the blue pixel.
Since the unit signal is generated based on the addition signal obtained by adding the four charges, it is possible to obtain color information having a high S / N ratio.

Since there are many sampling points in the horizontal direction (pixel row direction), the occurrence of false colors is small. In the vertical direction (pixel column direction), the resolution is reduced because eight pixel rows are one unit. However, since the sampling points for green, which is important for obtaining the luminance information, are distributed in the vertical direction at the same rate as in the horizontal direction, the degree of reduction in resolution in the vertical direction is small.

Therefore, in the solid-state image pickup device 100, the deterioration of the color resolution, the occurrence of false color, and the decrease of the S / N ratio of the color are suppressed even when the 4-pixel addition is performed.

FIGS. 4 to 10 show an example of the operation sequence in the case where 4-pixel addition is performed with the combination shown in FIG. In these figures, the photoelectric conversion element 1 in the solid-state image sensor 100 is shown.
0, the vertical charge transfer element 20 (including the read gate 30), the horizontal charge transfer element 40, and the output circuit section 50 are schematically shown in a planar arrangement. Vertical charge transfer element 2
0, the horizontal charge transfer element 40, and the output circuit section 50 constitute a unit signal generation section.

The reference numerals in which the Arabic numerals and the lowercase Roman letters shown in FIGS. 4 to 10 are combined represent the charges accumulated in the individual photoelectric conversion elements 10. The Arabic numeral in each reference numeral indicating the electric charge indicates that the pixel (photoelectric conversion element row) in which the electric charge is counted from the downstream side in each unit U (see FIG. 2) (photoelectric conversion element row). It represents whether the electric charge is accumulated in the conversion element 10). The lowercase Roman letters indicate that the charge is the charge stored in the pixel represented by the uppercase letter in FIG.

For example, the reference numeral "1g" indicates the electric charge accumulated in the green pixel G belonging to the first pixel row. Similarly, the reference numeral “8b” indicates the electric charge accumulated in the blue pixel B belonging to the eighth pixel row.

First, as shown in FIG. 4A, charges are accumulated in each pixel (photoelectric conversion element 10). By making light incident on individual pixels, electric charge is accumulated in these pixels.

Next, as shown in FIG. 4B, in each unit U (see FIG. 2), the green pixel G belonging to the seventh pixel row (first-class pixel row) counted from the downstream side is selected. The accumulated charge 7g is read to the corresponding vertical charge transfer element 20.
The arrow representing the read gate 30 also indicates the charge read direction.

The squares in each vertical charge transfer device 20 indicate one transfer stage having four vertical transfer electrodes. However,
The small squares on the most downstream side of each of the vertical charge transfer devices 20 indicate a transfer stage having only two vertical transfer electrodes.
The configuration of the vertical charge transfer device 20 will be described later in detail with reference to FIG.

Next, as shown in FIG. 5A, the charge 7g in each vertical charge transfer element 20 is transferred to the downstream side by one transfer stage. Each charge 7g is distributed in the transfer stage corresponding to the fifth pixel row (first type pixel row) counted from the downstream side in each unit U.

Subsequently, as shown in FIG. 5B, in each unit U, the third pixel row counted from the downstream side (first pixel row)
Electric charge 3g accumulated in the green pixel G belonging to
And, the charges 5g accumulated in the green pixel G belonging to the fifth pixel row (first type pixel row) are read out to the corresponding vertical charge transfer element 20. A charge of 7 is generated in each vertical charge transfer device 20.
g and 5 g of electric charge are added, and it becomes an electric charge (7g + 5g).

Next, as shown in FIG. 6A, the charges in each vertical charge transfer element 20 are transferred to the downstream side by one transfer stage. Each charge 3g is distributed in the transfer stage corresponding to the first pixel row (first-type pixel row) counted from the downstream side in each unit U.

Subsequently, as shown in the figure, in each unit U, the charge 6r accumulated in the red pixel R or the blue pixel B belonging to the sixth pixel row (second type pixel row) counted from the downstream side. Alternatively, the electric charge 8b or 8r accumulated in the blue pixel B or the red pixel R belonging to 6b and the eighth pixel row (second type pixel row) is read to the corresponding vertical charge transfer element 20.

Next, as shown in FIG. 6B, in each unit U, the first pixel row counted from the downstream side (first pixel row)
1 g of electric charge accumulated in the green pixel G belonging to the pixel row)
Are read out to the corresponding vertical charge transfer device 20. In each vertical charge transfer element 20, charge 3g and charge 1g are added,
It becomes an electric charge (3g + 1g).

Next, as shown in FIG. 7A, the charges in each vertical charge transfer element 20 are transferred to the downstream side by two transfer stages. Each charge 6r or 6b is distributed in the transfer stage corresponding to the second pixel row (second-class pixel row) counted from the downstream side in each unit U. Also, each charge 8b or 8r
Are distributed in the transfer stages corresponding to the fourth pixel row (second-class pixel row) counted from the downstream side in each unit U.

Next, as shown in FIG. 7B, the data is accumulated in the red pixel R or the blue pixel B belonging to the second pixel row (second type pixel row) counted from the downstream side in each unit U. The charges 2r or 2b and the charges 4b or 4r accumulated in the blue pixel B or the red pixel R belonging to the fourth pixel row (second type pixel row) are read to the corresponding vertical charge transfer element 20.

Second vertical charge transfer device 2 counting from the left
0, and within each of the vertical charge transfer elements 20 every three from the vertical charge transfer element 20, the charge 6r and the charge 2
r and are added to form a charge (6r + 2r), and charge 8b and charge 4b are added to form a charge (8b + 4b).

The charges 6b and the charges 2b are added in the fourth vertical charge transfer element 20 counted from the left and in each third vertical charge transfer element 20 from the vertical charge transfer element 20. The charge becomes (6b + 2b), and the charge 8r and the charge 4r are added to each other to obtain the charge (8r + 4b).
r).

Next, as shown in FIG. 8A, charge transfer for one transfer stage in each vertical charge transfer element 20 is performed, and horizontal transfer is performed from each vertical charge transfer element 20 which is an odd number counted from the left. The charges (3g + 1g) are transferred to the charge transfer element 40. Each charge (3g + 1g) is applied to the horizontal charge transfer device 40.
Are transferred at the same timing, for example.

The squares in the horizontal charge transfer element 40 indicate one transfer stage (one packet) in the horizontal charge transfer element 40. 1
One transfer stage includes, for example, two horizontal transfer electrodes. The configuration of the horizontal charge transfer element 40 will be described later in detail with reference to FIG.

Thereafter, each of the charges (3g + 1g) transferred to the horizontal charge transfer device 40 is sequentially transferred to the output circuit section 50.

The operation of the output circuit section 50 is controlled, and the charges (3g + 1g) sequentially output from the horizontal charge transfer element 40 are added two by two in the output circuit section 50 to generate added charges. Each of the added charges is a mixture of the four charges accumulated in the four green pixels G, excluding noise charges that are inevitably mixed. Each time the added charge is generated, the output circuit section 50 detects the added charge and generates a signal voltage according to the amount. Further, a signal (unit signal) obtained by amplifying this signal voltage is output.

As a result, among the pixel addition combinations shown in FIG. 2, the unit signal based on the 4-pixel addition for the green pixels G distributed in the first block BL1 in the most downstream unit U is output circuit section. It is output from 50.

Next, as shown in FIG. 8B, charge transfer for one transfer stage in each vertical charge transfer device 20 is performed, and horizontal transfer is performed from each vertical charge transfer device 20 which is an odd number counted from the left. The charge (7 g + 5 g) is transferred to the charge transfer element 40. Each charge (7g + 5g) is applied to the horizontal charge transfer device 40.
Are transferred at the same timing, for example.

Thereafter, each of the charges (7g + 5g) transferred to the horizontal charge transfer device 40 is sequentially transferred to the output circuit section 50.

The operation of the output circuit section 50 is controlled, and the charges (7g + 5g) sequentially output from the horizontal charge transfer element 40 are added two by two in the output circuit section 50 to generate added charges. Each of the added charges is a mixture of the four charges accumulated in the four green pixels G, excluding noise charges that are inevitably mixed. Each time the added charge is generated, the output circuit section 50 detects the added charge and generates a signal voltage according to the amount. Further, signals (unit signals) obtained by amplifying this signal voltage are sequentially output.

As a result, of the pixel addition combinations shown in FIG. 2, the unit signal based on the 4-pixel addition for the green pixels G distributed in the second block BL2 in the most downstream unit U is output to the output circuit section. It is output from 50.

Next, as shown in FIG. 9A, charge transfer for one transfer stage in each vertical charge transfer element 20 is performed, and at the same time, from each vertical charge transfer element 20 corresponding to an even number counted from the left. The charges (6r + 2r) are transferred to the horizontal charge transfer element 40.

Next, as shown in FIG. 9B, each charge (6r + 2r) in the horizontal charge transfer element 40 is transferred to the downstream side (output circuit section 50 side) by two transfer stages.

Next, as shown in FIG. 10, charge transfer for one transfer stage in each vertical charge transfer element 20 is performed, and at the same time, from each left vertical charge transfer element 20 counted from the left, the horizontal charge transfer element 20 is transferred. Transfer the charge (8b + 4b) to 40. In the horizontal charge transfer device 40, charges (6r + 2r) and charges (8b + 4b) are alternately distributed in every other transfer stage.

After that, the charges (6r + 2r) and the charges (8b + 4b) in the horizontal charge transfer device 40 are sequentially transferred to the output circuit section 50.

The charge (6r + 2) first transferred from the horizontal charge transfer element 40 is controlled by controlling the operation of the output circuit section 50.
r) is swept out and the second and subsequent charges are added two by two to generate added charges. The individual added charge is a mixture of the charge (8b + 4b) and the charge (6b + 2b) or the charge (8b + 4b) except noise charge which is inevitably mixed.
r + 4r) and charges (6r + 2r) are mixed. Each time the added charge is generated, the output circuit section 50 detects the added charge and generates a signal voltage according to the amount. Further, a signal (unit signal) obtained by amplifying this signal voltage is output.

As a result, among the pixel addition combinations shown in FIG. 2, the unit signal based on the 4-pixel addition for the blue pixel B distributed in the most downstream unit U and the 4-pixel addition for the red pixel R are added. And the unit signal based on are output alternately from the output circuit section 50.

Hereinafter, until the 4-pixel addition in the combination shown in FIG. 2 is completed, the same applies to the second and subsequent units U counted from the downstream side in the same manner as described above. 4 pixel addition for pixel B,
Then, four pixel addition is performed on the red pixel R to cause the output circuit section 50 to sequentially generate the unit signals.

Next, a specific structure of the solid-state image pickup device 100 capable of performing the above-described 4-pixel addition will be described.

FIG. 11 schematically shows the planar arrangement of the photoelectric conversion element 10, the vertical charge transfer element 20, the horizontal charge transfer element 40, and the output circuit section 50 in the solid-state image pickup device 100.

A large number of photoelectric conversion elements 10 are formed on one surface of the semiconductor substrate 1 under the pixel shift arrangement. Each photoelectric conversion element 10 is composed of, for example, an embedded photodiode. The meanings of the reference symbols R, G, and B are the same as those in FIG.

A vertical charge transfer element 20 meandering along one pixel row (photoelectric conversion element row) one by one.
Are placed. Each of the vertical charge transfer elements 20 includes a vertical charge transfer channel 21 formed on the semiconductor substrate 1 and a plurality of first to first multiples arranged on the semiconductor substrate 1 with an electrically insulating film (not shown) interposed therebetween. The second vertical transfer electrodes 23 to 24 and the first to tenth auxiliary transfer electrodes 27a to 27j are included.

The first and second vertical transfer electrodes 23 to 24 are arranged one by one on the downstream side of one pixel row (photoelectric conversion element row). Each of the first vertical transfer electrodes 23 has a photoelectric conversion element 1
It also constitutes a read gate 30 which controls the charge transfer from 0 to the vertical charge transfer element 20. In FIG. 11, each read gate 30 is hatched in order to make the position of the read gate 30 easy to understand. The solid-state image sensor 100 is an all-pixel readout type solid-state image sensor.

Each vertical charge transfer device 20 is a four-phase drive type C
It's a CD. In order to form the above-mentioned unit U (see FIG. 2), and for each unit U, the first block BL1,
To form the second block BL2, seven pads P are formed.
And V1～PV7, have unique and wiring WL _1.

An individual read operation for individually detecting charges accumulated in each pixel to generate a unit signal and an addition read operation for generating a unit signal by performing 4-pixel addition described with reference to FIGS. 4 to 10. In order to perform both of the above, the first-phase drive signal is divided into drive signals φV1a and φV1b. The drive signals φV1a and φV1b have the same waveform except that read pulses are superimposed at different timings during the addition read operation. Drive signal φV1a is supplied to a predetermined first vertical transfer electrodes 23 and the auxiliary transfer electrode through the pad PV1 and the wiring WL _1, the drive signal φV1b first vertical transfer electrodes 23 in predetermined through pad PV2 and the wiring WL ₁ Is supplied to.

Similarly, the drive signal of the third phase is the drive signal φV.
3a to φV3c. These drive signals .phi.V3a to .phi.V3c have the same waveform except that the read pulses are superimposed at different timings during the addition read operation. The drive signal φV3a is supplied to the predetermined first vertical transfer electrode 23 and auxiliary transfer electrode via the pad PV4 and the wiring WL ₁ . The drive signal φV3b is the pad P
Via V5 and the wiring WL _1, the drive signal φV3c via the pads PV6 and wiring WL _1, is respectively supplied to a predetermined first vertical transfer electrodes 23.

The second-phase drive signal φV2 and the fourth-phase drive signal φV4 are supplied to a predetermined second vertical transfer electrode 24 and auxiliary transfer electrode via the pad PV3 or the pad PV4 and the wiring WL ₁ , respectively. It

The read pulse (potential is, for example, 15 V) is
It is superimposed on the drive signals φV1a, φV1b, φV3a, φV3b, or φV3c. When the read pulse is superimposed on the drive signal, the read gate is transferred from each photoelectric conversion element 10 to the first vertical transfer electrode 23 supplied with the drive signal to the vertical charge transfer element 20 corresponding to the photoelectric conversion element 10. The charge is read out via 30. Each vertical charge transfer element 20 has drive signals φV1a to φV1b, φV2,
Driven by φV3a to φV3c and φV4, the charges read from the photoelectric conversion element 10 are transferred toward the horizontal charge transfer element 40.

The horizontal charge transfer element 40 is composed of a two-phase drive type CCD driven by two-phase drive signals φH1 and φH2, and a horizontal charge transfer channel 41 formed on the semiconductor substrate 1 and the semiconductor substrate 1. And a large number of first to second horizontal transfer electrodes arranged via an electrically insulating film (not shown). One first horizontal transfer electrode and one adjacent second horizontal transfer electrode are electrically connected to form a set of horizontal transfer electrodes. However, in FIG. 11, the illustration of the first and second horizontal transfer electrodes is omitted, and only the outline of the entire horizontal transfer electrodes is schematically drawn.

The horizontal charge transfer element 40 transfers the charge received from the vertical charge transfer element 20 toward the output circuit section 50.

The output circuit section 50 includes the horizontal charge transfer element 40.
The electric charge output from is detected to generate a signal voltage, and the signal voltage is amplified and output.

FIG. 12 schematically shows the structure from the horizontal charge transfer element 40 to the output circuit section 50.

As shown in the figure, the semiconductor substrate 1 comprises an n-type semiconductor substrate 1a, for example, an n-type silicon substrate 1a, and a p-type impurity doped region 1b formed on one surface of the n-type semiconductor substrate 1a. Composed.

The horizontal charge transfer channel 41 is composed of an n-type impurity added region 41a and an n ^-- type impurity added region 41b formed in the p-type impurity added region 1b. n
Type impurity doped region 41a and n ⁻ type impurity doped region 41b
And are alternately and repeatedly arranged in this order when viewed from the output circuit section 50 side. The concentration of the n-type impurity in the n ⁻ -type impurity added region 41b is lower than the concentration of the n-type impurity in the n-type impurity added region 41a.

The first horizontal transfer electrodes 42 are arranged one by one on each n-type impurity doped region 41a through the electrical insulating film 3, and one on each n ⁻ type impurity doped region 41b.
The second horizontal transfer electrode 43 is arranged via the electrically insulating film 3. Two first horizontal transfer electrodes 42 and two second horizontal transfer electrodes 43 are arranged for each vertical charge transfer device 20.

4 corresponding to one vertical charge transfer device 20.
Of the first to second horizontal transfer electrodes 42 and 43 of the book, two downstream side electrodes are commonly connected and supplied with the drive signal φH2,
The two upstream wires are commonly connected and supplied with the drive signal φH1. One first horizontal transfer electrode 42, the second horizontal transfer electrode 43 on the upstream side thereof, and these horizontal transfer electrodes 4
The horizontal charge transfer channels 41 below 2, 43 are shown in FIGS.
One square (charge transfer stage) in the horizontal charge transfer device 40 shown in FIG.

Incidentally, the first to second horizontal transfer electrodes 42 to 43
Are covered with an electrically insulating film IF such as a thermal oxide film.

The output circuit section 50 includes, for example, an output gate 51 connected to the output terminal of the horizontal charge transfer element 40, and a floating diffusion region 52 (hereinafter, referred to as “ FD region 52 "), a floating diffusion amplifier 53 (hereinafter abbreviated as" FDA 53 ") electrically connected to the FD region, and a reset gate arranged adjacent to the FD region 52. 54 and a drain region 55 formed in the semiconductor substrate 1 adjacent to the reset gate 54.

The output gate 51 is, for example, a channel region 51a formed by an n-type impurity-added region formed in the p-type impurity-added region 1b, and a gate electrode arranged on the channel region 51a with the electrical insulating film 3 interposed therebetween. 51b. The gate electrode 51b is formed of an electrically insulating film I such as a thermal oxide film.
Covered by F.

The output gate 51 receives the supply of the DC voltage V _OG and transfers charges from the horizontal charge transfer element 40 to the FD region 52.

The FD region 52 is composed of, for example, an n ⁺ type impurity added region formed in the p type impurity added region 1b. The concentration of the n-type impurity in the n ⁺ -type impurity added region is higher than the concentration of the n-type impurity in the n-type impurity added region.

The FDA 53 has, for example, four transistors Q1, Q2, Q3, and Q4, detects charges in the FD region 52, and generates a signal voltage. Further, this signal voltage is amplified and output.

The reset gate 54 is, for example, a channel region 54a formed by an n ^-- type impurity-added region formed in the p-type impurity-added region 1b, and a gate arranged on the channel region 54a with the electrical insulating film 3 interposed therebetween. And an electrode 54b. The gate electrode 54b is covered with an electrically insulating film IF such as a thermal oxide film.

The reset gate 54 has a drive signal φR.
The charges driven by S to be detected by the FDA 53 or the charges that need not be detected by the FDA 53 are swept from the FD region 52 to the drain region 55.

The drain region 55 is composed of, for example, an n ⁺ type impurity added region formed in the p type impurity added region 1b. The charges swept to the drain region 55 are
For example, it is absorbed by the power supply voltage V _DD .

The above-mentioned FD region 52 and reset gate 5
4 and drain region 55 form a reset transistor.

Drive signal φ for driving the reset gate 54
By appropriately selecting the signal waveform of RS, the output circuit unit 50 can add a plurality of charges.

FIG. 13 shows the waveform of the drive signal φRS when the electric charges transferred from the horizontal charge transfer element 40 are detected one by one in the output circuit section 50 and the unit signal is generated as in the individual reading operation. The relationship with the potential of the FD region 52 (see FIG. 12) is shown.

As shown in the figure, the drive signal φRS under the individual read operation has a low level L at the same timing as the drive signal φH2 which is a signal having a phase opposite to that of the drive signal φH1.
(The potential is, for example, 0 V) and changes to the high level H (the potential is, for example, 3 V). However, the duration of the high level H of the drive signal φRS is the same as the high level H of the drive signal φH2.
Shorter than the duration of.

When the drive signal φRS becomes high level H, the reset gate 54 is opened, and the charge in the FD region 52 (see FIG. 12) is swept out to the drain region 55 (see FIG. 12). The potential of the FD region 52 becomes the power supply voltage V _DD ,
The output of the FD area 52 increases.

When the drive signal φRS becomes low level L,
The reset gate 54 is closed. At this time, the potential of the FD region 52 is slightly lowered due to the electrostatic coupling capacitance between the reset gate 54 and the FD region 52. This decrease in potential is indicated by the symbol EC in FIG.

The drive signal φH2 is at the high level H (potential is
For example, 3V) to low level L (potential is 0V)
Then, the charges are transferred from the horizontal charge transfer element 40 to the FD region 52. The potential of the FD region 52 is further lowered by the potential V _{q of the} transferred charges. The output from the FD region 52 is further lowered by the potential V _{q of the} transferred charges.

The FDA 53 detects the output from the FD region 52 at this time each time charge transfer is performed, generates a signal voltage, and further amplifies and outputs the signal voltage. This output becomes a unit signal.

14 (A) and 14 (B) respectively show the waveform of the drive signal φRS and the FD during the addition read operation.
The relationship with the potential of the region 52 is shown.

In FIG. 14A, the electric charge transferred from the horizontal charge transfer element 40 is output as in the case of performing the four-pixel addition for the green pixel G described with reference to FIGS. 4 to 10. 4 shows the relationship between the waveform of the drive signal φRS and the potential of the FD region 52 when the unit signal is generated by adding four each.

FIG. 14B shows a case where the horizontal charge transfer element 40 is used as in the case of performing the 4-pixel addition for the blue pixel and the 4-pixel addition for the red pixel R described with reference to FIGS. Drive signal φRS when the transferred electric charges are added by two in the output circuit section 50 to generate a unit signal
2 shows the relationship between the waveform and the potential of the FD region 52.

As shown in FIG. 14A, when the 4-pixel addition is performed for the green pixel G, the drive signal φRS is generated once every four cycles of the drive signal φH2 at the same timing as the drive signal φH2. It changes from low level L to high level H.

When the drive signal φRS becomes high level H,
As in the case of the individual read operation, the reset gate 54 is opened and the charge in the FD region 52 is swept out to the drain region 55. The output from the FD area 52 increases.

When the drive signal φRS becomes low level L,
The reset gate 54 is closed. At this time, the potential of the FD region 52 is slightly lowered due to the electrostatic coupling capacitance between the reset gate 54 and the FD region 52. This decrease in potential is indicated by the symbol EC in FIG.

While the drive signal φRS is at the low level L, the drive signal φH2 repeatedly changes from the high level H to the low level L and from the low level L to the high level H. During this time, every time the drive signal φH2 changes from the high level H to the low level L, the charges are transferred from the horizontal charge transfer element 40 to the FD region 52. While the drive signal φRS is at the low level L, 4 from the horizontal charge transfer element 40 to the FD region 52.
Charge transfer is performed twice.

Of these, in the first and third charge transfer,
The charges (3g + 1g) shown in FIG. 8A or the charges (7g + 5g) shown in FIG. 8B are transferred from the horizontal charge transfer element 40 to the FD region 52, respectively. In the second and fourth charge transfers, only noise charges are transferred from the horizontal charge transfer element 40 to the FD region 52.

When the first charge transfer from the horizontal charge transfer device 40 to the FD region 52 is performed, the potential of the FD region 52 is transferred (3g + 1g) or transferred (7g).
g + 5g), which is lowered by the potential V _q11 . FD area 52
The output from the device is also lowered by the potential V _{q11 of the} transferred charges. When the second charge transfer from the horizontal charge transfer device 40 to the FD region 52 is performed, the potential of the FD region 52 is further lowered by the potential V _{q12 of} the transferred noise charge. The output from the FD region 52 also becomes lower by the potential V _{q12 of the} transferred charges.

When the third charge transfer from the horizontal charge transfer device 40 to the FD region 52 is performed, the potential of the FD region 52 is transferred to the charge (3g + 1g) or the charge (7g).
g + 5g), which is lowered by the potential V _q13 . FD area 52
The output from the same also becomes lower by the potential V _{q13 of the} transferred charges. When the fourth charge transfer from the horizontal charge transfer element 40 to the FD region 52 is performed, the potential of the FD region 52 is further lowered by the potential V _{q14 of} the transferred noise charge. The output from the FD region 52 also becomes lower by the potential V _{q14 of the} transferred charges.

The FDA 53 detects the output from the FD region 52 at this time every time the charge transfer is performed four times, generates a signal voltage, and further amplifies and outputs the signal voltage. This output becomes a unit signal.

In FIG. 14A, the charge (3
g + 1g) or charge (7g + 5g) potential and noise charge potential are almost the same, but in reality, the charge (3g + 1g) or charge (7g + 5g) potential is much higher than the noise charge potential. Very expensive. Also, strictly speaking,
Read from green pixel G, red pixel R, or blue pixel B d
When the generated charges are transferred to the output circuit unit 50, noise charges are inevitably transferred together with these charges. In the description here, noise charges inevitably transferred together with the charges read from the green pixel G, the red pixel R, or the blue pixel B are ignored.

When performing the 4-pixel addition for the blue pixel B or the red pixel R, the charge (6r + 2r) transferred to the FD region 52 is first swept out to the drain region 55, and then shown in FIG. Drive signal φH2 of 2
The drive signal φRS is changed to the drive signal φH2 once per cycle.
The level changes from low level L to high level H at the same timing.

When the drive signal φRS becomes high level H,
As in the case of the individual read operation, the reset gate 54 is opened and the charge in the FD region 52 is swept out to the drain region 55. The output from the FD area 52 increases.

When the drive signal φRS becomes low level L,
The reset gate 54 is closed. At this time, the potential of the FD region 52 is slightly lowered due to the electrostatic coupling capacitance between the reset gate 54 and the FD region 52. This decrease in potential is indicated by the symbol EC in FIG.

While the drive signal φRS is at the low level L, the drive signal φH2 sequentially changes from the high level H to the low level L, from the low level L to the high level H, and from the high level H to the low level L. During this time, every time the drive signal φH2 changes from the high level H to the low level L, the charges are transferred from the horizontal charge transfer element 40 to the FD region 52. While the drive signal φRS is at the low level L, charge transfer from the horizontal charge transfer element 40 to the FD region 52 is performed twice.

The drive signal φRS is at the odd low level L
Between the horizontal charge transfer element 40 shown in FIG. 10 is transferred to the FD region 52 by the first charge transfer between the horizontal charge transfer elements 40 and the horizontal charge transfer shown in FIG. The charge (6b + 2b) in the element 40 is the FD region 5
2 is transferred.

The drive signal φRS is an even-numbered low level L
Between the horizontal charge transfer elements 40 shown in FIG. 10 is transferred to the FD region 52 by the first charge transfer between the horizontal charge transfer elements 40 and the horizontal charge transfer shown in FIG. The charge (6r + 2r) in the element 40 is the FD region 5
2 is transferred.

When the first charge transfer from the horizontal charge transfer device 40 to the FD region 52 is performed, the potential of the FD region 52 is transferred to the charges (8b + 4b) and (6b + 2).
b), (8r + 4r), or (6r + 2r) potential V
_q21 minutes lower. The output from the FD region 52 is also lowered by the potential V _{q21 of the} transferred charges. When the second charge transfer from the horizontal charge transfer element 40 to the FD region 52 is performed, the potential of the FD region 52 is transferred to the charges (8r + 4r), (6r + 2r), (8b + 4b),
_{Alternatively,} the potential _Vq22 of (6b + 2b) is further lowered. The output from the FD region 52 also becomes lower by the potential V _{q22 of the} transferred charges.

The FDA 53 detects the output from the FD region 52 at this time every time charge transfer is performed, generates a signal voltage, and further amplifies and outputs the signal voltage. This output becomes a unit signal.

By performing the above-described 4-pixel addition, it is possible to sensitize the image pickup apparatus using the solid-state image pickup element 100.

Next, the image pickup apparatus according to the first embodiment will be described.

FIG. 15 is a block diagram schematically showing the image pickup apparatus (digital still camera) according to the first embodiment. An image pickup apparatus 200 shown in the figure includes a solid-state image pickup device 100, an image pickup optical system 110, an analog / digital processing unit 115 (hereinafter abbreviated as A / D processing unit 115), a drive signal generation unit 120, and an image. Signal generator 13
0, a display device 140, a recording unit 150, a control unit 160, a shutter button 170, a mode selector 180, and a flash device 190.

Since the structure of the solid-state image pickup device 100 has already been described, the description thereof will be omitted here.

The image pickup optical system 110 includes, for example, a plurality of optical lenses, an optical lens driving mechanism for moving the optical lenses in the optical axis direction, an optical diaphragm, an optical diaphragm opening / closing mechanism for opening / closing the optical diaphragm, an optical low pass filter, and the like. And forms an optical image on the solid-state image sensor 100. In FIG. 15, the imaging optical system 110 is composed of one optical lens.
Is shown on behalf of. The arrow L in the figure indicates light.

The A / D processing section 115 includes the solid-state image pickup device 10.
0 (output circuit unit 50) receives a unit signal, performs analog gain adjustment, performs noise reduction processing by correlated double sampling, and then converts the digital signal.

The drive signal generation section 120 has a timing signal generation circuit 122 and a drive circuit 124.

The timing signal generation circuit 122 includes a storage element (not shown) in which data relating to generation timings of various signals generated at different timings according to the operation mode of the image pickup apparatus 200 are stored in advance.
Based on the data stored in the storage element, the timing signal generation circuit 122 generates various timing signals for unifying the operation timings of various circuits.
These timing signals are supplied to the drive circuit 124, the image signal generation unit 130, the control unit 160, and the like. The timing signal generation circuit 122 also generates a signal necessary for driving the solid-state imaging device 100. A part of this signal, for example, the drive signals φH1, φH2, and φRS is used for the solid-state image sensor 100.
To the driving circuit 124.

The drive circuit 124 is, for example, a vertical driver,
The vertical drive signal φV is configured based on the signal supplied from the timing signal generation circuit 122 and includes a DC power source and the like.
Signals such as 1a to φ1Vb, φV2, φV3a to φV3c, and φV4 are generated. This signal is supplied to the solid-state image sensor 100.

The image signal generator 130 includes a switching element 132 (hereinafter abbreviated as "SW element 132"),
It includes a first signal processing circuit 134, a second signal processing circuit 136, and a third signal processing circuit 138.

During the individual read operation and the addition read operation, the total number of unit signals output from the solid-state image pickup device 100 and the array of sampling points of color signals (see FIGS. 1 and 3 and FIG. 22 described later) are determined. different. Therefore, the image signal generation unit 130 includes the first signal processing circuit 134 and the second signal processing circuit 136.

The SW element 132 receives the supply of the output signal from the A / D processing unit 115, and when the output signal is a signal based on the individual reading operation, supplies the signal to the first signal processing circuit 134. When the output signal from the A / D processing unit 115 is a signal based on the addition read operation,
This signal is supplied to the second signal processing circuit 136.

The first signal processing circuit 134 and the second signal processing circuit 136 receive the output signal from the A / D processing unit 115 and perform various processes to generate image data for reproduction. These signals are supplied to the third signal processing circuit 138.

The third signal processing circuit 138 performs various processes based on the image data supplied from the first signal processing circuit 134 or the second signal processing circuit 136, and outputs an image signal in the final output form, for example, a display. The image signal output to the device 140 or the image signal output to the recording unit 150 is generated. The output format of the image signal to be generated is designated by the mode selector 180, for example. The image signal generated by the third signal processing circuit 138 is supplied to the display device 140 or the recording unit 150, and a part thereof, for example, a luminance signal or a control signal for autofocus is supplied to the control unit 160. It

The display device 140 is composed of, for example, a liquid crystal display, and displays a still image or a moving image based on the image signal supplied from the third signal processing circuit 138.

The recording section 150 includes a third signal processing circuit 138.
The image signal supplied from the device is recorded on a recording medium such as a memory card.

The control section 160 is composed of, for example, a central processing unit (CPU), and has a shutter button 170,
Mode selector 180 or third signal processing circuit 13
8 controls the operations of the image pickup optical system 110, the timing signal generation circuit 122, the SW element 132, the first signal processing circuit 134, the second signal processing circuit 136, and the third signal processing circuit 138. To do.

The mode selector 180 is used for the image pickup apparatus 200.
This is a switch for selecting the operation mode of.

The flash device 190 is composed of, for example, a strobe, and its operation is controlled by the controller 160.

The mode selector 180 allows the user to select which of the high image quality mode in which the individual reading operation is performed and the high sensitivity mode in which the additional reading operation is performed in the image pickup apparatus 200. Is configured so that It is possible to add an automatic photographing mode function that causes the control unit 160 to determine whether to perform the individual reading operation or the addition reading operation.

For example, after the power is turned on, the automatic photographing mode is forcibly set to a state in which a moving picture or a still picture can be displayed on the display device 140, and then the mode selector 180 selects another operation mode. Then, the display device 140 is allowed to display a moving image or a still image under the operation mode.

For example, under the high image quality mode, the display device 14 is operated.
When the amount of light from the subject displayed at 0 or its background is insufficient, the mode selector 180 selects the high sensitivity mode or the automatic shooting mode, and the image pickup apparatus 200 is sensitized by the addition of four pixels (addition read operation). be able to.

As described above, it is possible to easily suppress the deterioration of color resolution, the occurrence of false color and the decrease of S / N ratio of color even when the 4-pixel addition is performed. A subject image can be captured with a relatively high image quality.

If necessary, the flash device 190 can be operated to increase the amount of light from the subject.

In the digital still camera, the display device 14
0 is often used as a viewfinder.
In that case, a moving image is displayed on the display device 140. When the number of pixels of the solid-state image sensor 100 is small, it is possible to generate moving image data by the first signal processing circuit 134. When the number of pixels of the solid-state image pickup device 100 exceeds 1,000,000, for example, the solid-state image pickup device 100 is thinned out to generate a unit signal for a moving image, and a dedicated signal processing circuit (not shown) is separately provided so that the moving image It is preferable to generate the image data of

Next, another example of the operation sequence when performing the 4-pixel addition with the combination shown in FIG. 2 will be described with reference to FIGS.
This will be described with reference to FIG.

16 to 19 show the main part of the operation sequence in this example. Among the components shown in these figures, only the horizontal charge transfer element 140 is different from the horizontal charge transfer element 40 shown in FIGS. 4 to 10. The constituent members other than the horizontal charge transfer element 140 are the same as the constituent members shown in FIGS. 4 to 10 and are the same as the display method of FIG. 4 to FIG. 10 of the charge display method. Is omitted. The specific configuration of the horizontal charge transfer device 140 will be described later in detail with reference to FIG.

First, in accordance with the operation order described with reference to FIGS. 4A to 8A, as shown in FIG. 8A, each vertical charge corresponding to an odd number counted from the left. From the transfer element 20 to the horizontal charge transfer element 140, charge (3 g +
1g) is transferred.

Next, as shown in FIG. 16A, the charges (3g + 1) transferred from the vertical charge transfer element 20 at the left end are transferred.
g), and the charges (3g + 1g) transferred from every third vertical charge transfer device 20 based on the leftmost vertical charge transfer device 20 are not transferred in the horizontal charge transfer device 140 and are stopped, The other charges (3g + 1g) in the horizontal charge transfer device 140 are transferred to the downstream side by four transfer stages.

Two charges (3g + 1g) are added in the leftmost vertical charge transfer device 20 and in each transfer stage corresponding to every third vertical charge transfer device 20 based on this vertical charge transfer device 20. It Four-pixel addition is performed for the green pixel G in the first block BL1 (see FIG. 2). 16 to 19, the two added charges (3g + 1g) are represented by the symbol (3g + 1g) × 2.

Next, as shown in FIG. 16B, each charge (3g + 1g) × 2 in the horizontal charge transfer element 140 is set to 2 times.
Transfer downstream for the transfer stage.

Next, as shown in FIG. 17A, charge transfer for one transfer stage in each vertical charge transfer element 20 is performed,
Each vertical charge transfer device 20 that is an odd number counted from the left
The electric charge (7 g + 5 g) is transferred to the horizontal charge transfer element 140 from

Next, as shown in FIG. 17B, the charges (7 g + 5) transferred from the vertical charge transfer device 20 at the left end are transferred.
g), and the charges (7g + 5g) transferred from every third vertical charge transfer device 20 based on the leftmost vertical charge transfer device 20 are not transferred in the horizontal charge transfer device 140 but stopped in place. As it is, other charges (7g + 5g) and charges (3g + 1g) in the horizontal charge transfer device 140 × 2
Is transferred to the downstream side by two transfer stages.

Next, as shown in FIG. 18A, in the transfer stage corresponding to the leftmost vertical charge transfer element 20, and every other vertical charge transfer with reference to the leftmost vertical charge transfer element 20. Charge (7 g +) in each transfer stage corresponding to the element 20
5g) or (3g + 1g) × 2 is the horizontal charge transfer element 1
The other charges (7 g + 5 g) in the horizontal charge transfer device 140 are transferred by two transfer stages without being transferred in 40 and stopped in place.
Transfer to the downstream side.

Two charges (7g + 5g) are added in the leftmost vertical charge transfer device 20 and in each transfer stage corresponding to every third vertical charge transfer device 20 based on this vertical charge transfer device 20. It Four-pixel addition is performed on the green pixel G in the second block BL2 (see FIG. 2). 18 to 19, the two added charges (7g + 5g) are represented by the symbol (7g + 5g) × 2.

The third vertical charge transfer device 2 counting from the left
0, and 3 based on this vertical charge transfer device 20
In each transfer stage corresponding to every other vertical charge transfer device 20, charges (3g + 1g) are distributed.

Next, as shown in FIG. 18B, charge transfer for one transfer stage in each vertical charge transfer element 20 is performed, and horizontal charge is transferred from each vertical charge transfer element 20 corresponding to an even number counted from the left. Charge (6r + 2r) to transfer element 140
Alternatively, the charge (6b + 2b) is transferred.

Next, as shown in FIG. 19A, each charge in the horizontal charge transfer element 140 is transferred to the downstream side by four transfer stages.

In the transfer stage corresponding to the odd-numbered vertical charge transfer element 20 counting from the left, the charge (3g + 1)
g) × 2 or charge (7 g + 5 g) × 2 is distributed. The charge (6b + 2b) or the charge (6r + 2r) is distributed in the transfer stage corresponding to the even-numbered vertical charge transfer element 20 counted from the left.

Next, as shown in FIG. 19B, charge transfer for one transfer stage in each vertical charge transfer element 20 is performed, and horizontal charge is transferred from each vertical charge transfer element 20 corresponding to an even number counted from the left. Charge to transfer element 140 (8b + 4b)
Alternatively, the charge (8r + 4r) is transferred.

Second vertical charge transfer element 2 counting from the left
0, and 3 based on this vertical charge transfer device 20
The charge (8b + 4b) and the charge (6b + 2b) are added in each transfer stage corresponding to every other vertical charge transfer device 20. Four-pixel addition is performed for the blue pixel B in the most downstream unit U (see FIG. 2).

Fourth vertical charge transfer device 2 counting from the left
0, and 3 based on this vertical charge transfer device 20
The charges (8r + 4r) and the charges (6r + 2r) are added in each transfer stage corresponding to every other vertical charge transfer device 20. 4-pixel addition is performed for the red pixel R in the most downstream unit U (see FIG. 2).

After that, the charges in the horizontal charge transfer element 140 are sequentially transferred to the output circuit section 50. By controlling the operation of the output circuit section 50, the charges sequentially transferred from the horizontal charge transfer element 140 are detected one by one, and a signal voltage corresponding to the amount is generated. Further, a signal (unit signal) obtained by amplifying this signal voltage is output.

As a result, the combination 4 shown in FIG.
A unit signal based on the pixel addition is output from the output circuit unit 50.

Hereinafter, until the 4-pixel addition in the combination shown in FIG. 2 is completed, the second-units and subsequent units U counted from the downstream are also subjected to the 4-pixel addition for the green pixel G and the blue in the same manner as described above. 4 pixel addition for pixel B,
Then, four pixel addition is performed on the red pixel R to cause the output circuit section 50 to sequentially generate the unit signals.

In order to perform the 4-pixel addition in the above-described operation order, it is necessary to use the solid-state image pickup device having the horizontal charge transfer device 140 having a different structure from the horizontal charge transfer device 40 shown in FIG. .

FIG. 20 schematically shows the configuration of the horizontal charge transfer device 140 in the solid-state image pickup device 105 capable of performing 4-pixel addition in the operation order described with reference to FIGS. The horizontal charge transfer device 14 in the solid-state imaging device 105
The configuration other than 0 is the same as that of the solid-state imaging device 100 shown in FIG. Therefore, the illustration of the configuration other than the horizontal charge transfer element 140 is omitted except for some auxiliary transfer electrodes, and the explanation of the configuration other than the horizontal charge transfer element 140 is also omitted here.

In the illustrated horizontal charge transfer device 140, the drive signals of the first phase are drive signals φH1a, φH1b, and φH.
It is different from the horizontal charge transfer element 40 shown in FIG. 11 or FIG. 12 in that it is divided into three and supplied. Other configurations are similar to those of the horizontal charge transfer device 40. Figure 20
Among the components shown in FIG. 12, those common to the components shown in FIG. 12 are designated by the same reference numerals as those used in FIG. 12, and the description thereof will be omitted.

First supplied to the horizontal charge transfer device 140
The phase drive signals φH1a to φH1c have different waveforms when charge addition or partial charge transfer is performed in the horizontal charge transfer element 140, but are the same during the period in which charges are continuously transferred to the output circuit unit 50. It becomes a waveform.

Drive signal φH1a is supplied to every seventh transfer stage via pad PH1 and wiring WL ₁₀ .
Each of these transfer stages corresponds to the downstream end of the vertical charge transfer device 20. The drive signal φH1a is supplied to the transfer stage corresponding to the downstream end of the vertical charge transfer device 20 at the left end in FIGS.

Drive signal φH1b is supplied to every third transfer stage via pad PH2 and wiring WL ₁₀ .
Each of these transfer stages is a transfer stage corresponding to the downstream end of the vertical charge transfer device 20.
2 downstream from the transfer stage to which H1a is supplied, or 2
It is the upstream transfer stage.

[0178] driving signals φH1c via pads PH3 and the wiring WL _10, a transfer stage corresponding to the downstream end of the vertical charge transfer device 20, the drive signal φH1a, φH1b
Is supplied to the transfer stage that is not supplied with. These transfer stages are distributed every 7th.

The second phase drive signal φH2 is supplied to the pad PH4.
And the line WL ₁₀ to the transfer stage not corresponding to the downstream end of the vertical charge transfer device 20.

As already described with reference to FIGS. 16 to 19, four pixel addition is performed in the horizontal charge transfer element 140. Therefore, it is preferable that the horizontal charge transfer element 140 has a larger transfer capacity than the horizontal charge transfer element 40 shown in FIG. 11 or 12.

The transfer capacity of the horizontal charge transfer element 140 can be increased, for example, by increasing the channel width of the horizontal charge transfer channel 41 or by increasing the impurity concentration in the horizontal charge transfer channel 41 and increasing the drive signal high. It can be increased by also increasing the potential at the level.

By using the solid-state image pickup device 105 shown in FIG. 20, an image pickup device (digital still camera) similar to the image pickup device 200 shown in FIG. 15 can be constructed.

However, in the case of performing 4-pixel addition, as shown in FIG.
As already described with reference to FIGS. 6 to 19, the operations of the vertical charge transfer element 20, the horizontal charge transfer element 140, and the output circuit section 50 are different. Therefore, the desired 4-pixel addition cannot be performed only by disposing the solid-state image sensor 105 in place of the solid-state image sensor 100 shown in FIG.

It is necessary to change the function of the drive signal generator 120 shown in FIG. 15 so that the drive signal necessary for the 4-pixel addition described with reference to FIGS. 16 to 19 can be generated. . Specifically, it is necessary to change the data stored in the above-described storage element included in the timing signal generation circuit 122 into the predetermined data that matches the four-pixel addition operation described with reference to FIGS. Is.

In the solid-state image pickup device 105 and the solid-state image pickup device 100, a unit signal based on 4-pixel addition for the green pixel G, a unit signal based on 4-pixel addition for the blue pixel B, and a unit signal based on 4-pixel addition for the red pixel R. Unit signals based on pixel addition are output in different orders. Therefore, it is necessary to slightly change the configuration of the second signal processing circuit 136 as well.

Next, another example of a combination of pixels which are added to each other when four-pixel addition is performed will be described.

FIG. 21 is a solid-state image pickup device 10 shown in FIG.
Another example of a combination of pixels to be added to each other when four-pixel addition is performed using 0 will be shown. Since all the constituent elements shown in FIG. 2 are shown in FIG. 2, constituent elements common to those shown in FIG. 2 are designated by the same reference numerals as those used in FIG. Is omitted.

As shown in FIG. 21, in this example, for the blue pixel B and the red pixel R, four pixel addition is performed in the same combination as in the example shown in FIG.

For the green pixel G, the first block BL
Two green pixels G adjacent to each other in the column direction in 1 and two green pixels G adjacent to each other in the column direction in the second block BL2 are added to perform four-pixel addition. Of the four green pixels G to be added to each other, the two green pixels G belonging to the first block BL1 are two pixels as viewed from the output circuit section 50, as compared with the two green pixels G belonging to the second block BL2. Only the row is located upstream.

FIG. 22 shows 4 combinations of the combinations shown in FIG.
The geometric center of four pixels that are added to each other when pixel addition is performed is shown by the color G, R, or B of the pixel.

As is clear from the figure, the generation of the unit signal based on the 4-pixel addition in the combination shown in FIG.
This is almost equivalent to generating a unit signal based on the charges read from the green pixel G, the red pixel R, and the blue pixel B arranged at the positions shown in FIG.

Compared to the 4-pixel addition in the combination shown in FIG. 2, the number of green pixels G in the vertical direction (pixel column direction) is reduced, so the resolution in the vertical direction is reduced. On the other hand, the horizontal resolution is improved. Further, when the 4-pixel addition is performed in this combination, the configuration of the second signal processing circuit 136 becomes simple when configuring the imaging device 200 shown in FIG.

For this reason, the combination shown in FIG.
Even when pixel addition is performed, deterioration of color resolution, occurrence of false color, and decrease of color S / N ratio are suppressed.

When the 4-pixel addition is performed in the combination shown in FIG. 21, the 4-pixel addition is performed in the combination shown in FIG. 2 except that the operation for performing the 4-pixel addition for the green pixel G is partially different. The operation sequence is the same as when performing.

23 (A) and 23 (B) show the main part of the operation sequence in this example. Since all the components shown in these figures are shown in FIGS. 4 to 10, FIGS.
0 to the components common to those shown in FIG.
The same reference numerals as those used in 0 are attached and the description thereof is omitted.

When four-pixel addition is performed with the combination shown in FIG. 21, first, according to the operation sequence described with reference to FIGS. 4A to 8A, FIG. As shown in FIG. 5, the charges (3 g +) from each vertical charge transfer element 20 which is an odd number counted from the left to the horizontal charge transfer element 140.
1g) is transferred.

Next, as shown in FIG. 23A, each charge (3g + 1g) in the horizontal charge transfer device 40 is transferred to the downstream side by two transfer stages. The charges (3g + 1g) distributed in the most downstream are transferred from the horizontal charge transfer device 40 to the output circuit unit 50, and are swept out to the drain region 55 (see FIG. 12) here.

Next, as shown in FIG. 23B, charge transfer for one transfer stage in each vertical charge transfer element 20 is performed, and horizontal charge is transferred from each vertical charge transfer element 20 which is an odd number counted from the left. Charge to transfer element 140 (7g + 1g)
To transfer. The charge (7g + 5g) and the charge (3g + 1g) are added to every other transfer stage in the horizontal charge transfer device 40.
And are distributed alternately.

Next, the charges (7
g + 5g) and charges (3g + 1g) are sequentially transferred to the output circuit section 50.

The operation of the output circuit section 50 is controlled, and the charges transferred from the horizontal charge transfer element 40 are added two by two to generate added charges. Each individual charge is a mixture of charges (7g + 5g) and charges (3g + 1g) except for noise charges which are inevitably mixed. Each time the added charge is generated, the output circuit section 50 detects the added charge and generates a signal voltage according to the amount. Further, a signal (unit signal) obtained by amplifying this signal voltage is output.

As a result, among the pixel addition combinations shown in FIG. 23, the unit signal based on the 4-pixel addition for the green pixel G distributed in the most downstream unit U is
It is output from the output circuit section 50.

Thereafter, in accordance with the operation order described with reference to FIGS. 9A to 10, four pixel addition for the red pixel R and four pixel addition for the blue pixel B are performed, The output circuit unit 50 is caused to generate a unit signal based on the pixel addition of.

Hereinafter, until the 4-pixel addition in the combination shown in FIG. 2 is completed, the second-units and subsequent units U counted from the downstream are also subjected to the 4-pixel addition for the green pixel G and the blue in the same manner as described above. 4 pixel addition for pixel B,
Then, four pixel addition is performed on the red pixel R to cause the output circuit section 50 to sequentially generate the unit signals.

Next, an image pickup apparatus according to the second embodiment will be described.

FIG. 24 is a block diagram schematically showing an image pickup apparatus (digital still camera) according to the second embodiment. The image pickup apparatus 300 shown in the figure includes an image signal generation section 230 having a configuration and a function different from those of the image signal generation section 130 shown in FIG. 15, and the control section 160 shown in FIG. Added control unit 260
Equipped with. Further, the mode selector 18 shown in FIG.
A mode selector 280 having more operation modes that can be selected than 0 is provided.

Of the constituent members shown in FIG. 24, the constituent members common to those shown in FIG. 15 are designated by the same reference numerals as those used in FIG. 15, and the description thereof will be omitted.

The image signal generator 230 in the image pickup apparatus 300 shown in the drawing uses the first signal processing circuit 1 by the individual reading operation.
The image processing apparatus includes a combining processing circuit 234 that combines the image data output from the image processing apparatus 34 and the image data output from the second signal processing circuit 136 by the addition reading operation to generate one image data.

The image data output from the first signal processing circuit 134, the image data output from the second signal processing circuit 136, and the image data output from the synthesizing processing circuit 234 are stored in the second switching element 232 (hereinafter "Second
SW element 232 ”is abbreviated. ), It is distributed to the synthesis processing circuit 234 or the third signal processing circuit 236.

The third signal processing circuit 236 is one of the image data output from the first signal processing circuit 134, the image data output from the second signal processing circuit 136, and the image data output from the synthesizing processing circuit 234. Is supplied, an image signal in a final output form, for example, an image signal in a form output to the display device 140 or an image signal in a form output to the recording unit 150 is generated based on this image data. The output format of the image signal to be generated is designated by the mode selector 280, for example.

In addition to the function of control unit 160 shown in FIG. 15, control unit 260 has a function of controlling the operations of second SW element 232 and synthesis processing circuit 234.

The image pickup apparatus 300 is driven under which operation mode, for example, a high image quality mode for performing an individual reading operation, a high sensitivity mode for performing an addition reading operation, and an image synthesizing mode for performing synthesizing processing by the synthesizing processing circuit 232. Do you
It is configured so that the user can select it by the mode selector 280. Imaging device 20 shown in FIG.
Compared with 0, the number of operation modes that can be selected by the mode selector 280 is increased by one.

In the image pickup apparatus 300, as in the image pickup apparatus 200 shown in FIG. 15, the control unit 260 determines which one of the high image quality mode, the high sensitivity mode, and the image combination mode should be used for driving. An automatic shooting mode function can be added.

FIG. 25 shows the type of output from the solid-state image pickup device 100 when the flash device 190 is operated in the image combining mode to shoot a still image from the state where the display device 140 is used as a viewfinder. Shows the transition of.

In order to use the display device 140 as a viewfinder, the solid-state image pickup device 100 is a unit signal for displaying a moving image based on a moving image operation (for example, thinning operation) until time T ₁ defined by the blanking pulse VD1. Is generated and output. Therefore, even if the shutter button 170 is pressed between the time T ₁ and the time T ₂ defined by the blanking pulse VD2, the unit signal for moving images is captured by the solid-state image pickup until the time T ₂ when the next frame starts. It is output from the element 100. In FIG. 25, this output is described as “MV output”.

Under the image composition mode, time T ₁ and time T ₂
When the shutter button 170 is pressed at a time between and, the solid-state imaging device 100 first generates and outputs the unit signal under the addition read operation after the time T ₂ . In FIG. 25, this output is described as “high sensitivity output”. When the subject and its background are distant from each other, it is difficult to increase the amount of light from the background even if the flash device 190 is operated. To shoot the background brightly,
It is desired to sensitize the imaging device 300 by the addition read operation.

When the addition read operation is completed, the time T ₅ to the time T ₅ defined by the blanking pulse VD3 is reached.
_The next frame starts over ₆ . Time T ₂ and time T ₅
From time T ₃ to time T ₄ between and, the flash device 190 operates according to the shooting scene. By operating the flash device 190, a nearby subject receives a flash and becomes bright. For a subject in the vicinity, a signal of sufficient intensity can be obtained even by the individual reading operation.

Then, the solid-state image pickup device 100 operates at time T _5.
After that, the unit signal is generated and output under the individual reading operation. In FIG. 25, this output is described as “high resolution output”. If the flash device 190 is operated as described above, the flash device 190 is based on the high resolution output.
The image signal (still image signal) of the illuminated subject is generated by the light emission from.

The high-sensitivity output and high-resolution output from the solid-state image pickup device 100 are temporarily stored in a storage device (not shown in FIG. 24. For example, a DRAM is used). Then, the high-sensitivity output is signal-processed by the second signal processing circuit 136, and the high-resolution output is signal-processed by the first signal processing circuit 134.

The image data generated by the first signal processing circuit 134 and the image data generated by the second signal processing circuit 136 are supplied to the synthesizing processing circuit 234, where the image data is synthesized into one image data and then signaled. It is sent to the processing circuit 236. The signal processing circuit 236 receives the image data supplied from the synthesis processing circuit 234 and supplies one image signal for a still image to the display device 149 or the recording unit 150.

In the reproduced image based on this image signal, for example, the background of the subject becomes an image based on the addition reading operation, and the subject itself becomes an image based on the individual reading operation.

Even in a scene in which the subject and its background are dark, it is possible to obtain an image in which both the subject and its background are reproduced brightly.

Although the image pickup apparatus and the driving method thereof according to the embodiments have been described above, the present invention is not limited to the above embodiments. It will be apparent to those skilled in the art that various modifications, improvements, combinations and the like can be made.

For example, the arrangement of three types of pixels, that is, green pixels, red pixels, and blue pixels is not limited to the arrangement shown in FIG. Of the array shown in FIG. 1, one or two pixel rows on the most downstream side may be ignored, or one or two pixel columns on the left end side in FIG. 1 may be ignored.

The pixels are not limited to primary color pixels, but may be complementary color pixels.

FIGS. 26 and 27 schematically show the planar arrangement of pixels in the solid-state image pickup device including complementary color pixels, the vertical charge transfer device 20, the horizontal charge transfer device 40, and the output circuit section 50. Of the components shown in these figures,
11 is the same as the component shown in FIG.
The same reference numerals as those used in step 1 are attached and the description thereof is omitted.

The solid-state image sensor 107a shown in FIG.
In, the green pixel G, the cyan pixel Cy, and the yellow pixel Ye are arranged in a shifted manner. The green pixel G constitutes a first type pixel row, and the cyan color pixel Cy and the yellow pixel Ye constitute a second type pixel row.

The solid-state image sensor 107b shown in FIG.
In, the yellow pixel Ye, the cyan pixel Cy, and the magenta pixel Mg are arranged in a shifted manner. Yellow pixel Y
e constitutes the first type pixel row, and the cyan color pixel Cy and the magenta color pixel Mg constitute the second type pixel row.

The solid-state image sensor 107c shown in FIG.
In, the cyan color pixel Cy, the yellow color pixel Ye, and the magenta color pixel Mg are arranged in a shifted manner. The cyan pixel Cy forms the first type pixel row, and the yellow pixel Ye and the magenta color pixel Mg form the second type pixel row.

The solid-state image sensor 107d shown in FIG. 27B.
In, the white pixel W, the cyan pixel Cy, and the yellow pixel Ye are arranged in a shifted manner. The white pixel W constitutes a first type pixel row, and the cyan pixel Cy and the yellow pixel Ye have a transparent color filter or a transparent color filter instead of the white pixel W constituting the second type pixel row. A pixel which does not have can also be used.

In a CCD type single plate type solid-state image pickup device used as an area image sensor, a light shielding film is usually provided so that unnecessary photoelectric conversion is not performed in a portion other than the photoelectric conversion element. . If necessary, one microlens is arranged above each color filter.

FIG. 28 shows the solid-state image pickup device 10 shown in FIG.
It is sectional drawing which shows roughly one pixel in 0, and its periphery. This figure shows a light shielding film and a passivation film, which are not shown in FIG. 1, and members arranged above them as viewed from the semiconductor substrate 1. Among the constituent elements shown in FIG. 28, the constituent elements already shown in FIG. 11 are designated by the same reference numerals as those used in FIG. 11, and the description thereof will be omitted.

As shown in FIG. 28, the photoelectric conversion element 10
Is an embedded type formed by, for example, providing an n-type impurity added region 10a at a predetermined position of the p-type impurity added region 1b and providing ap ⁺ -type impurity added region 10b on the n-type impurity added region 10a. It is composed of a photodiode. The n-type impurity added region 10a functions as a charge storage region.

The p-type impurity added regions 1b are exposed one by one along the right side edge portion in FIG. 28 of each photoelectric conversion element 10 (n-type impurity added region 10a). This region in the p-type impurity doped region 1b is used as the channel region 30a for the read gate 30. The vertical charge transfer channel 21 and the photoelectric conversion element 10 corresponding thereto are
They are adjacent to each other via the channel region 30a.

The electrically insulating film 3 is formed of, for example, a single-layer silicon oxide film, a laminated film of a silicon oxide film and a silicon nitride film, or the like.

On the surface of the first vertical transfer electrode 23, an electrical insulating film IF made of a thermal oxide film or the like is formed. The same applies to the second vertical transfer electrode 24 and the auxiliary transfer electrode, which are not visible in FIG.

The channel stop region CS is provided in each photoelectric conversion element 1 except the portion where the channel region 30a is formed.
0 in plan view, the periphery of each vertical charge transfer channel 21 in plan view and the horizontal charge transfer channel 41 (FIG. 11).
And see FIG. 12). The channel stop region CS is formed, for example, by providing ap ⁺ -type impurity added region at a predetermined position of the p-type impurity added region 1b. The concentration of p-type impurities in the p ⁺ -type impurity added region is higher than the concentration of p-type impurities in the p-type impurity added region.

Each impurity-added region can be formed by, for example, ion implantation and subsequent annealing. p
The type impurity added region 1b can also be formed by, for example, an epitaxial growth method.

A light shielding film 60 is formed so as to cover the vertical charge transfer element 20, the horizontal charge transfer element 40, and the output circuit section 50 (see FIGS. 11 and 12). The light shielding film 60 has one opening 60 a above each photoelectric conversion element 10. Individual photoelectric conversion element 10
A region of the surface located inside the opening 60a in plan view serves as a light incident surface of the photoelectric conversion element 10.

The light shielding film 60 is formed by using a metal material such as aluminum, chromium, tungsten, titanium, molybdenum or the like, or an alloy material composed of two or more of these metals.

The passivation film 65 is the light shielding film 60.
Then, the electrical insulating film 3 exposed from the opening 60a is covered to protect the members thereunder. The passivation film 65 is formed of, for example, silicon nitride or silicon oxide.

The first flattening film 70 covers the passivation film 65. The first flattening film 75 is also used as a focus adjustment layer for a microlens 85 described later. An inner lens is formed in the first flattening film 70 as needed.

The first flattening film 70 is formed by applying a transparent resin such as photoresist to a desired thickness by, for example, spin coating.

One color filter is arranged on each photoelectric conversion element 10. The color filter is the first flattening film 7
Formed on 0. In FIG. 28, three green filters 75 are shown.

The color filter can be produced, for example, by forming a layer of resin (color resin) containing a pigment or dye of a desired color at a predetermined position by a method such as photolithography.

A second flattening film 80 is formed on each color filter to form a flat surface for forming the microlens 85. The second flattening film 80 is formed by applying a transparent resin such as a photoresist to a desired thickness by, for example, a spin coating method.

The microlens 85 serves as the second flattening film 8.
2 is formed on. The microlenses 85 are arranged one above each photoelectric conversion element 10. The microlens 85 has, for example, a refractive index of approximately 1.3 to 2.0.
After partitioning the layer made of the transparent resin (including photoresist) into a predetermined shape by photolithography or the like,
It is obtained by melting the transparent resin layer in each section by heat treatment, rounding the corners by surface tension, and then cooling. One section is one microlens 85
Becomes

[0247]

As described above, according to the present invention,
Color resolution degradation even when sensitized by pixel addition,
Provided is an imaging device that can easily suppress the occurrence of false colors and the reduction in S / N ratio of colors. It is possible to provide an imaging device that can easily capture a beautiful image of a dark scene.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a planar arrangement of pixels in a solid-state image pickup element used in an image pickup apparatus according to a first embodiment.

FIG. 2 is a schematic diagram showing an example of a combination of pixels when performing 4-pixel addition using the solid-state imaging device shown in FIG.

FIG. 3 is a schematic diagram showing the geometric center of four pixels which are added together in the combination shown in FIG. 2 by the color of the pixel.

4A and FIG. 4B are schematic diagrams showing part of the operation sequence when four-pixel addition is performed with the combination shown in FIG.

5 (A) and FIG. 5 (B) are schematic views showing another part of the operation sequence when performing the 4-pixel addition in the combination shown in FIG.

6 (A) and 6 (B) are schematic diagrams showing still another part of the operation sequence in the case of performing 4-pixel addition with the combination shown in FIG.

7 (A) and 7 (B) are schematic diagrams showing still another part of the operation sequence in the case of performing 4-pixel addition in the combination shown in FIG.

FIGS. 8A and 8B are schematic diagrams showing still another part of the operation sequence when performing the 4-pixel addition in the combination shown in FIG.

9 (A) and 9 (B) are schematic diagrams showing still another part of the operation sequence when performing the 4-pixel addition in the combination shown in FIG.

FIG. 10 is a schematic diagram showing still another part of the operation sequence in the case of performing 4-pixel addition with the combination shown in FIG.

11 is a schematic diagram showing a planar arrangement of a photoelectric conversion element, a vertical charge transfer element, a horizontal charge transfer element, and an output circuit section in the solid-state imaging device shown in FIG.

12 is a sectional view schematically showing a structure from the horizontal charge transfer device shown in FIG. 11 to an output circuit section.

FIG. 13 is a schematic diagram showing the relationship between the waveform of the drive signal φRS and the potential of the FD region when the output circuit section detects the charges transferred from the horizontal charge transfer element one by one and the unit signal is generated. is there.

FIG. 14A is a waveform of a drive signal φRS and a potential of an FD region when a unit signal is generated by detecting four charges transferred from a horizontal charge transfer element in an output circuit portion. FIG. 14B is a schematic diagram showing the relationship between the electric charge transferred from the horizontal charge transfer element and the electric charge transferred from the horizontal charge transfer element in the output circuit unit.
Drive signal φRS when detecting each one and generating a unit signal
FIG. 6 is a schematic diagram showing the relationship between the waveform of and the potential of the FD region.

FIG. 15 is a block diagram schematically showing an image pickup apparatus according to a first embodiment.

16 (A) and 16 (B) are schematic diagrams showing part of another operation sequence in the case of performing 4-pixel addition with the combination shown in FIG.

17 (A) and 17 (B) are schematic diagrams showing another part of another operation sequence in the case of performing 4-pixel addition with the combination shown in FIG.

18A and 18B are schematic diagrams showing still another part of another operation sequence in the case of performing 4-pixel addition in the combination shown in FIG.

19 (A) and FIG. 19 (B) are schematic diagrams showing still another part of another operation sequence in the case of performing 4-pixel addition in the combination shown in FIG.

FIG. 20 is a partial plan view schematically showing a horizontal charge transfer element included in a solid-state imaging device that performs 4-pixel addition in the operation order shown in FIGS.

FIG. 21 is a schematic diagram showing another example of pixel combinations when performing 4-pixel addition using the solid-state imaging device shown in FIG. 1.

22 is a schematic diagram showing the geometric center of four pixels which are added to each other in the combination shown in FIG. 21 by the color of the pixel.

23 (A) and FIG. 23 (B) are schematic diagrams each showing a part of another operation sequence in the case of performing 4-pixel addition with the combination shown in FIG. 21.

FIG. 24 is a block diagram schematically showing an image pickup apparatus according to a second embodiment.

25 is a diagram illustrating a case where the flash device is operated in the image compositing mode to capture a still image in the imaging device shown in FIG. 24;
6 is a timing chart showing the type of output from the solid-state image sensor and its timing.

26 (A) and 26 (B) each include a complementary color system pixel, and are capable of performing 4-pixel addition in the same combination as the combination shown in FIG. 2 or FIG. 21. It is a schematic diagram showing an example of a plane arrangement of a pixel in an image sensor, a vertical charge transfer element, a horizontal charge transfer element, and an output circuit section.

27 (A) and 27 (B) each include a pixel of a complementary color system, and are capable of performing 4-pixel addition by a combination similar to the combination shown in FIG. 2 or FIG. 21. It is a schematic diagram showing other examples of plane arrangement of a pixel, a vertical charge transfer element, a horizontal charge transfer element, and an output circuit part in an image sensor.

28 is a cross-sectional view schematically showing one pixel and its periphery in the solid-state imaging device shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 10 ... Photoelectric conversion element, 20 ... Vertical charge transfer element, 40 ... Horizontal charge transfer element, 50 ... Output circuit part, 100, 105, 107a-107d ... Solid-state image sensor, 134 ... 1st signal processing circuit , 136 ...
Second signal processing circuit, 138, 236 ... Third signal processing circuit, 200, 300 ... Imaging device, 234 ... Combining processing circuit, PR1 ... First type pixel row, PR2a, PR2b
... second type pixel row, G ... green pixel, R ... red pixel,
B ... Blue pixel, Cy ... Cyan color pixel, Ye ... Yellow pixel, M ... Magenta color pixel.

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 4M118 AA05 AB01 BA10 BA13 CA02                       DB06 DB08 DD04 DD08 DD09                       FA06 FA07 GC07 GD04 GD07                 5C065 AA01 AA03 BB13 BB48 CC01                       DD02 EE03 GG21

Claims (20)

[Claims] 1. A large number of pixels arranged in a plurality of rows and a plurality of columns, and a charge accumulated in the pixels is read out, the charges are detected, and a unit signal used for generating an image signal is detected. And a unit signal generating unit for generating, wherein the plurality of pixels each include a color filter,
The color of the color filter is classified into three groups of a first color pixel, a second color pixel, and a third color pixel, and the unit signal generation unit (i) individually charges the charges accumulated in each of the pixels. An individual read operation of detecting and generating the unit signal, and (ii) four pixels of the same color distributed close to each other over a plurality of rows and a plurality of columns for each of the first color pixel to the third color pixel An image pickup device capable of selectively performing an addition read operation of generating added charges by adding the charges accumulated in the, and separately detecting the added charges to generate a unit signal. 2. A plurality of pixels are arranged in a staggered manner, and the arrangement of the plurality of pixels is a first-type pixel row composed of only first-color pixels, second-color pixels and third-color pixels. Is an array in which a second type pixel row that is alternately and repeatedly arranged is alternately and repeatedly formed, and the unit signal generation unit sets the continuous eight pixel rows as one unit during the addition read operation, and The unit comprises a first block composed of four pixel rows on the downstream side and a second block composed of four pixel rows on the upstream side.
The first added charge is generated by adding charge accumulated in each of the four first color pixels distributed in two pixel columns every other column in the same block to generate the first added charge. The second added charge is generated by adding the charges accumulated in each of the four second color pixels distributed in the two pixel columns in every other column in the unit, and the second added charge is generated in the same unit every two columns. The imaging device according to claim 1, wherein the third added charge is generated by adding the charges accumulated in each of the four third color pixels distributed in one pixel column. 3. The four second color pixels and the four third color pixels
At least one of the second color pixel and the third color pixel adjacent to each other in the pixel row direction and adjacent to each other in at least one of the four pixels is the four first colors. The image pickup apparatus according to claim 2, wherein the image pickup apparatus is located in a pixel distribution area. 4. The arrangement of the second color pixel and the third color pixel is opposite to each other between the two second type pixel rows adjacent to each other with the first type pixel row interposed therebetween. The image pickup apparatus according to claim 2 or claim 3. 5. The vertical charge transfer device, wherein the unit signal generation unit is (i) arranged one by one in a pixel column and reading out charges accumulated in a corresponding pixel and transferring the charges in a predetermined direction. , (Ii) a horizontal charge transfer element that receives the charge output from each of the vertical charge transfer elements and sequentially transfers the charge, and (iii) the unit signal that receives the charge supplied from the horizontal charge transfer element The output device which produces | generates this, The imaging device of any one of Claims 1-4. 6. The image pickup device according to claim 5, wherein the unit signal generation unit can add charges accumulated in two pixels in the vertical charge transfer element during the addition read operation. 7. The unit signal generation unit generates the first added charge, the second added charge, and the third added charge in the output circuit unit during the addition read operation. The imaging device according to 6. 8. The unit signal generating section performs an operation of detecting all of the first added charges and an operation of detecting all of the second added charges and the third added charges during the addition read operation. The image pickup apparatus according to claim 2, which is separately performed in units. 9. The unit signal generation unit according to claim 5, wherein the first added charge, the second added charge, and the third added charge are generated in the horizontal charge transfer element during the addition read operation. The imaging device described. 10. The unit signal generation unit, in the addition read operation, in units of the unit, the first addition charge,
The image pickup apparatus according to claim 9, wherein the second added charge and the third added charge are detected one by one. 11. A first signal processing circuit for generating image data based on a unit signal generated by the unit signal generation unit during the individual reading operation, and a unit signal generation unit generated during the addition reading operation. The 2nd signal processing circuit which generates image data based on a unit signal, The imaging device according to any one of claims 1 to 10. 12. A synthesizing process capable of synthesizing image data for one frame by synthesizing image data generated by the first signal processing circuit and image data generated by the second signal processing circuit. The imaging device according to claim 11, further comprising a circuit. 13. A third signal processing circuit capable of generating an image signal based on image data output from any one of the first signal processing circuit and the second signal processing circuit. Item 11. The image pickup device according to item 11. 14. A third signal generation circuit that can generate an image signal based on image data output from any of the first signal processing circuit, the second color signal processing circuit, and the synthesis processing circuit. The image pickup apparatus according to claim 13, further comprising a signal processing circuit. 15. The first color pixel is a green pixel, and the second color pixel is one of a red pixel and a blue pixel,
The image pickup apparatus according to claim 1, wherein the third color pixel is one of the red pixel and the remaining blue pixel. 16. The first color pixel is a green pixel, the second color pixel is one of a yellow pixel and a cyan color pixel, and the third color pixel is the remaining one of the yellow pixel and the cyan color pixel. The imaging device according to any one of claims 1 to 14, which is one of them. 17. The first color pixel is a yellow pixel, the second color pixel is one of a cyan color pixel and a magenta color pixel, and the third color pixel is one of the cyan color pixel and the magenta color pixel. The imaging device according to any one of claims 1 to 14, which is the other one. 18. The first color pixel is a cyan color pixel, the second color pixel is one of a yellow pixel and a magenta color pixel, and the third color pixel is the remaining of the yellow pixel and the magenta color pixel. One of claims 1 to 14
The imaging device according to any one of 1. 19. The first color pixel is a white or colorless pixel, the second color pixel is one of a yellow pixel and a cyan color pixel, and the third color pixel is one of the yellow pixel and the cyan color pixel. The other one is Claim 1 to Claim 1.
The imaging device according to any one of 4 above. 20. The plurality of pixels are arranged in a pixel-shifted manner, and the arrangement of the plurality of pixels is a first-type pixel row composed of only first-color pixels, second-color pixels, and third-color pixels. Is an array in which a second type pixel row that is alternately and repeatedly arranged is repeatedly formed, and the unit signal generation unit sets eight consecutive pixel rows as one unit during the addition read operation, and The unit comprises a first block composed of four pixel rows on the downstream side and a second block composed of four pixel rows on the upstream side.
It is further divided into a block and a charge accumulated in each of the two first color pixels that are continuous in the pixel column direction in the first block, and a charge that is continuous in the pixel column direction in the second block.
The first accumulated charge of each of the first color pixels is added between two pixel columns every other column.
The second added charge is generated by generating the added charge, and adding the charges accumulated in each of the four second color pixels distributed in two pixel columns every other column in the same unit to generate the second added charge. The imaging device according to claim 1, wherein the third added charge is generated by adding the charges accumulated in each of the four third color pixels distributed in two pixel columns every other column.