JP2003078048A - Nonvolatile semiconductor memory and its operating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a nonvolatile semiconductor memory in which the occupied area by a nonvolatile semiconductor memory cell is reduced extremely, characteristics of the cell are prevented from lowering due to punch through, or the like, and high speed operation is realized. SOLUTION: The operating method of a nonvolatile semiconductor memory comprises a step for applying optimized voltages, respectively, to two second conductivity semiconductor regions (between BL2 and BL3, or BL3 and BL4) and a gate electrode 14, such that electrons supplied from one second conductivity semiconductor region 12 (BL2, BL4) become hot electrons in the vicinity of another semiconductor region 12 (BL3) so as to be injected into a charge storage means on the other side, at the time of writing in a nonvolatile semiconductor memory comprising a first conductivity semiconductor 11 having a level difference R on the surface, two second conductivity semiconductor regions 12 formed at the upper and bottom parts of the level difference and being separated vertically, a gate dielectric film 13 incorporating a spatially scattered charge storage means, and the gate electrode 14.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to, for example, MONOS.
(Metal Oxide Nitride Oxide Semiconductor) has a spatially discrete charge storage means such as a charge trap in a nitride film, and stores or stores data by an operation of injecting or extracting charge from the charge storage means. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device to be erased and a method of operating the same.

[0002]

2. Description of the Related Art In a non-volatile semiconductor memory device, a charge storage means (floating gate) for holding a charge is a continuous F
G (Floating Gate) type, MONOS type in which charge storage means (carrier traps, etc.) are spatially discretized, MNO
The S type and the like are known.

In the MONOS type memory element, ONO (Oxide Nitride Oxide) is formed on a semiconductor substrate forming a channel.
A film and a gate electrode are laminated, and source / drain regions having a conductivity type opposite to that of the channel are formed in the substrate surface region on both sides of the laminated pattern. Then, writing is performed by injecting charges from the substrate side to the ONO film having this charge storage capability. Further, in the erasing, the accumulated charges are extracted to the substrate side, or the opposite polarity charges that cancel the accumulated charges are injected into the ONO film.

In the conventional MONOS type storage element described above, the channel is formed on the surface of a flat single crystal silicon substrate.

[0005]

However, in the case where the channel is formed on the surface of a flat single crystal silicon substrate, in order to increase the information recording density, the size per unit storage element in the substrate surface should be reduced. I have to do it. Therefore, in order to miniaturize the semiconductor memory element, it is necessary to shorten the channel length (or gate length) between the source region and the drain region of the semiconductor memory element.
The miniaturization of the gate length causes a so-called short channel effect,
Typically, when the gate length is 0.1 μm or less, the transistor characteristics of the semiconductor memory element deteriorate. Especially,
In a conventional device in which a channel is formed along a flat substrate surface, when the gate length is shortened, punch-through occurs due to the drain voltage, and the size reduction reaches its limit.

An object of the present invention is to provide a non-volatile semiconductor memory device having a structure in which the area occupied by the semiconductor memory device is extremely small, and in which the deterioration of device characteristics due to punch through or the like can be easily prevented, and a method of operating the same.

[0007]

In order to achieve the above object, a method of operating a nonvolatile semiconductor memory device according to a first aspect of the present invention includes a first conductivity type semiconductor having a step on its surface and an upper part of the step. And at least two second conductivity type semiconductor regions formed in the bottom and separated in a direction perpendicular to the main surface of the first conductivity type semiconductor, and a spatially discrete charge storage means, and at least the step difference. And a gate dielectric film formed so as to cover a part of the side surface of the non-volatile semiconductor memory, and a gate electrode facing the side surface of the step with the gate dielectric film interposed therebetween. Then, at the time of writing, the electrons supplied from one of the second conductivity type semiconductor regions become hot electrons in the vicinity of the other second conductivity type semiconductor region and are injected into the charge storage means on the other side. Two first And between conductive type semiconductor region, to the above gate electrode, comprising the step of applying the optimized voltage, respectively.

The nonvolatile semiconductor memory device is preferably a high resistance channel adjacent to the end of the second conductivity type semiconductor region on the center side of the channel and having a higher concentration than the first conductivity type semiconductor in which the channel is formed. Further, it has a formation region, and at the time of writing, the electric field concentration is improved in the high resistance channel formation region to improve the injection efficiency of hot electrons.

Preferably, the method further comprises the step of applying a voltage to the first conductivity type semiconductor at the time of writing so that a pn junction formed between the first conductivity type semiconductor and the second conductivity type semiconductor region is reverse biased.

At the time of reading, a voltage in the same direction as that at the time of writing is preferably applied to the two second conductivity type semiconductor regions, and the channel is turned on or off depending on the presence or absence of the charges injected during the writing or the amount of the charges. The method further includes applying a voltage to the gate electrode.

A method of operating a nonvolatile semiconductor memory device according to a second aspect of the present invention is directed to a semiconductor of a first conductivity type having a step on its surface, and a semiconductor of the first conductivity type formed on top and bottom of the step. Two second conductivity type semiconductor regions separated in a direction perpendicular to the plane and a spatially discrete charge storage unit are included in the inside, and are formed so as to cover at least a part of the side surface of the step. A method for operating a non-volatile semiconductor memory device, comprising: a gate dielectric film; and a gate electrode facing the side surface of the step with the gate dielectric film interposed therebetween.
During erasing, a step of applying a voltage between the second conductivity type semiconductor region and the gate electrode is included so that hot holes are injected from the second conductivity type semiconductor region on the side where the electrons are injected.

In the method of operating a nonvolatile semiconductor memory device according to the first and second aspects, for example, when the first conductivity type is p-type and the second conductivity type is n-type, the first conductivity type semiconductor (for example, A second conductivity type impurity region (n ⁺ region) is formed above and below the step of the p-type well, and a channel is formed on the side surface of the step during writing. Charges, such as electrons, supplied from one n ⁺ region are accelerated in the channel and become hot electrons on the other n ⁺ region side,
By being injected into the charge storage means (for example, charge trap) in the gate dielectric film, the threshold voltage of the storage element changes to, for example, the higher side. When the high resistance channel formation region (p ⁺ region) is formed on the other n ⁺ region side, the potential drop is large and the electric field is concentrated in this high resistance channel formation region. Therefore, hot electrons are efficiently generated by the high electric field in the p ⁺ region, and the writing efficiency is high. Further, when a back bias for reverse biasing the pn junction formed between the p-type well and the n ⁺ region is applied, the gate voltage and the like can be reduced.

At the time of erasing, the surface of the n ⁺ region having a large voltage difference from the gate electrode is depleted, a high electric field is applied, and a band-to-band tunnel current flows. A hot hole is generated due to this tunnel current, which is attracted to the gate voltage and injected into the charge trap. As a result, the electrons accumulated by the writing are canceled and the threshold voltage of the memory element changes to, for example, the lower side.

During reading, a source-drain voltage having the same voltage application direction as during writing is applied, and a predetermined voltage is applied to the gate electrode. The storage element is turned on or off depending on the presence or absence of the charge accumulated in the charge trap or the amount of the charge. As a result, the potential difference between the n ⁺ regions changes only when the memory element is turned on, and this is amplified by the sense amplifier or the like and read. In this reading method, the source-drain voltage is applied in the same direction as in writing, and when applied to verify after writing, n ⁺
High-speed reading is possible because the charge / discharge time of the area is short.

A non-volatile semiconductor memory device according to a third aspect of the present invention is a semiconductor of a first conductivity type having a step on its surface, and a top and bottom of the step, which are perpendicular to the main surface of the semiconductor of the first conductivity type. Two second conductivity type semiconductor regions separated in different directions, and a high resistance channel formation region formed in a portion adjacent to at least one second conductivity type semiconductor region and having a higher concentration than the surrounding first conductivity type semiconductor. A gate dielectric film including a spatially discrete charge storage means therein and formed so as to cover at least a part of a side surface of the step,
And a gate electrode facing the side surface of the step with a gate dielectric film interposed. Further, preferably, at the time of writing, a pn formed between the second conductivity type semiconductor region and
It further comprises means for applying a voltage for reverse biasing the junction to the first conductivity type semiconductor.

In this non-volatile semiconductor memory device, since the channel is formed on the side surface of the step, the area on the plane pattern of the channel forming region is extremely small when the step is inclined, and the channel is formed when the step is vertical. The area of the area on the plane pattern is almost zero. Therefore, the area occupied by the element can be small. Further, since the channel length is determined by the depth of the step, even if the channel length is sufficient to suppress the punch through and the short channel effect, the area occupied by the element does not increase. In addition, since the charge storage means are spatially discrete, even if there is a leak path in the gate dielectric film, the accumulated charge that disappears is only part of the periphery of that leak path, and as a result, the charge retention characteristics are excellent. ing. Since the high resistance channel forming region (p ⁺ region) is formed at the channel side end of the second conductivity type impurity region (n ⁺ region), the writing efficiency is high and high speed data storage is possible as described above. . Further, since there is a means for back bias, the gate voltage and the like can be low at the time of writing as described above, and low voltage operation is possible.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings, taking a nonvolatile semiconductor memory having an n-channel MONOS type memory transistor as an example. In the case of the p-channel type, the following description can be similarly applied by appropriately reversing the conductivity type of impurities in the memory transistor, the polarities of carriers and voltage application conditions.

FIG. 1 is a plan view of a memory cell array according to an embodiment of the present invention. As shown in FIG. 1, trenches R are formed in stripes at regular intervals on a semiconductor substrate (including well or SOI layer), and word lines WL are orthogonal to the trench R at regular intervals. Are formed in stripes.

FIG. 2 is a diagram showing the impurity regions formed in the semiconductor substrate in the plan view of FIG. Impurity regions (source / drain regions) 12 to be sources or drains are formed as shown by the hatched portions in FIG. 2, and the source / drain regions 12 at the bottom of the groove R formed in the semiconductor substrate form the bit lines BL2. The bit lines BL1, BL1 are formed by the source / drain regions 12 in the semiconductor substrate in which BL4 and BL6 are formed and the groove R is not formed.
3, BL5 and BL7 are formed. In this way, the source / drain regions 12 are long in one direction and are arranged in parallel to each other, whereby the bit lines BL1 to B1.
L7 is formed. Although not shown, the bit lines BL1 to BL7 are connected to metal wirings (main bit lines) via contacts. In the drawing, the source / drain regions 12 are named bit lines BL and their roles are clearly shown. However, depending on the voltage application direction of the source / drain regions 12, the bit lines BL1 to BL7 serve as the source lines. Will also serve as.

The connection type of the memory cell array having the above configuration is a VG (Virtual Ground) type in which each of the bit lines BL1 to BL7 is shared between adjacent memory cells in the row direction.

FIG. 3 (a) is a sectional view taken along the line AA 'in FIG. 1, and FIG. 3 (b) is a sectional view taken along the line BB' in FIG.

As shown in FIGS. 3 (a) and 3 (b), the above-described grooves R are formed at regular intervals in the semiconductor substrate 11 made of, for example, p-type silicon or the like. Recesses are repeatedly formed. The "step of the first conductivity type semiconductor" of the present invention is formed on the side wall of the convex portion or the concave portion. On the bottom surface of the concave portion and the top surface of the convex portion, two source / drain regions 12 into which n-type impurities are introduced at a high concentration are formed so as to be separated from each other in the vertical direction of the substrate. The channel formation region is the source / drain region 1
2, that is, along the side surface of the step formed on the semiconductor substrate 11, in a direction substantially perpendicular to the substrate surface. Further, for example, a p-type impurity is introduced at a higher concentration than the channel forming region in a region on the side surface of the step which is in contact with the upper source / drain region 12, whereby the high resistance channel forming region 15 is formed.

A dielectric film (gate dielectric film) 13 having a charge storage ability is formed by covering the semiconductor substrate 11 having the above-mentioned step and laminating a plurality of insulating films, for example.

FIG. 4 shows an enlarged sectional view for explaining the detailed structure of the gate dielectric film 13. As shown in FIG. 4, the gate dielectric film 13 is composed of a bottom dielectric film 13a, a charge storage film 13b mainly responsible for charge storage, and a top dielectric film 13c in order from the lower layer.

The bottom dielectric film 13a is formed on the semiconductor substrate 11
Of a material having a larger bandgap, such as silicon dioxide SiO ₂ , silicon nitride SiN _x (x> 0), or silicon oxynitride SiO _x N _y (x, y> 0), without a trap or in a transistor. The film is composed of a film that does not have an amount of traps sufficient to change the threshold voltage, and its thickness is about 1 nm to 20 nm.

The charge storage film 13b is the bottom dielectric film 13
a material having a bandgap smaller than a and including a charge trap as a charge storage means, for example, silicon nitride Si
N _x (x> 0) or silicon oxynitride SiO _x N _y
It is composed of a film composed of (x, y> 0) and has a thickness of about 1 nm to 20 nm.

The top dielectric layer 13c is, for example, silicon dioxide SiO _2, silicon nitride SiN _{x (x>} 0), or silicon oxynitride _{SiO x N y (x, y} > 0) or transistor no trap consisting etc. In order to effectively prevent injection of holes from the gate electrode 14 and prevent a decrease in the number of times data can be rewritten, the film is composed of a film that does not have enough traps to change the threshold voltage of
Its thickness is about 3 to 20 nm.

A gate electrode 1 is formed on the gate dielectric film 13.
4 are formed. The gate electrode 14 is made of, for example, impurity-added polycrystalline silicon or amorphous silicon,
It composes a word line.

FIG. 5 shows an equivalent circuit diagram corresponding to the sectional view of the memory cell array shown in FIG. The two memory cell transistors shown in FIG. 5 are formed from one convex portion shown in FIG. 4 and the bottom portions of the concave portions on both sides thereof. That is, in the memory transistor shown in FIG. 4, the source / drain region 12 is formed on the upper surface of the convex portion and the bottom surface of the concave portion, and the channel forming region CH is formed on the side wall surface of the step of the semiconductor substrate 11 between them. Therefore, since the channel forming region CH is formed on both sides of one convex portion, two memory transistors are formed. Each bit line BL is commonly connected to the adjacent memory transistors.

In this nonvolatile memory, the semiconductor substrate 11
A channel forming region CH is formed along the side surface of the groove R formed above.
By adopting the structure having, it was possible to improve the degree of integration of information recording density without shortening the gate length of the memory transistor to a region where a short channel effect or punch through occurs.

Next, a method of manufacturing the memory cell shown in FIG. 1 will be described with reference to FIGS. 6 (a) to 8 (f). Note that FIGS. 6A to 8F correspond to the cross-sectional structure shown in FIG.

First, a p-well is formed in a prepared silicon wafer or the like by ion implantation of B ⁺ , BF ⁺ or the like, if necessary. A resist (not shown) having a pattern for forming the groove R shown in FIG. 1 is formed by photolithography on the surface of the semiconductor substrate 11 on which the memory transistor thus formed is to be formed, and the resist is used as a mask. , Anisotropic reactive ion etching (R
By performing IE (Reactive Ion Etching), the groove R is formed in a stripe shape. Alternatively, the dielectric film may be formed in a region of the semiconductor substrate where the groove R is not formed, and the dielectric film may be used as a mask to perform etching to form the stripes of the groove R.

Next, after removing a resist (not shown), a gate dielectric film 13 is formed on the semiconductor substrate 11 having the stripe-shaped grooves R. First, as the bottom dielectric 13a shown in FIG. 4, for example, silicon dioxide (SiO ₂ ), silicon nitride SiN _x (x> 0), or silicon oxynitride SiO _{x is used.}
A film made of N _y (x, y> 0) is deposited on the order of 1 nm to 20 nm. Of the above, the silicon dioxide film is formed by, for example, a thermal oxidation method. Further, the silicon nitride film is formed of, for example, trichlorosilane (SiHCl ₃ ) and ammonia (NH
₃ ) or chemical vapor deposition using silicon tetrachloride (SiCl ₄ ) and ammonia (NH ₃ ) as raw materials (Chemical Vapor Deposition).
Deposition: CVD). Or JVD
(Jet Vapor Deposition, M.Khara et al, “Highly Ro
bust Ultra-Thin Gate Dielectric for Giga Scale Tec
hnology, "Symp.VLSI Technology Digest, Honolulu, HI,
June 1998), or RTCVD (Rapid Thermal Che)
mical Vapor Deposition, SCSong et al, “Ultra T
hin CVD Si ₃ H ₄ Gate Dielectric for Deep-Sub-Micron
CMOS Devices, "IEDM Tech, Digest. SanFrancisco, CA,
December 1998). The source gas used is C
Same as VD. Alternatively, it is formed by nitriding using N ₂ radicals or atomic nitrogen radicals. Also,
The silicon oxynitride film is formed by nitriding a thermal oxide film with any one of nitrogen (N ₂ ), dinitrogen oxide (N ₂ O), ammonia (NH ₃ ), or dichlorosilane (SiH ₂ Cl ₂ ).
And nitrous oxide (N ₂ O) and ammonia (NH ₃ ), or trichlorosilane (SiHCl ₃ ) and nitrous oxide (N ₂ O) and ammonia (NH ₃ ), or silicon tetrachloride (SiCl ₄ ). It is formed by CVD using any combination of nitrous oxide (N ₂ O) and ammonia (NH ₃ ) as a source gas.

Next, on the bottom dielectric film 13a, as shown in FIG.
As the charge storage film 13b including the charge trap shown, for example,
For example, silicon nitride SiN_x (X> 0), silicon oxynitride SiO
_x N _y A film composed of (x, y> 0) is about 1 nm to 20 nm
Deposit once. Of the above, silicon nitride is, for example,
Lorsilane (SiH₂ Cl₂ ) And ammonia (NH
₃ ), Or trichlorosilane (SiHCl₃ ) And a
Nmonia (NH₃ ), Or silicon tetrachloride (SiCl)
_Four ) And ammonia (NH₃ ) As a raw material by CVD
Form. Further, the silicon oxynitride film is, for example, dichloro
Silane (SiH₂ Cl₂ ) And nitrous oxide (N₂ O) and a
Nmonia (NH₃ ) Or trichlorosilane (Si
HCl₃ ) And nitrous oxide (N₂ O) and ammonia (NH
₃ ) Or silicon tetrachloride (SiCl_Four ) And nitrous oxide
(N₂ O) and ammonia (NH₃ ) Any combination of
It is formed by a CVD method using a bonito as a source gas.

Next, as shown in FIG. 4, on the charge storage film 13b.
Silicon dioxide (SiO 2) is used as the top dielectric film 13c.
₂ ), Silicon nitride SiN_x (X> 0), or silicon oxynitride
Elemental SiO _x N_y A film made of (x, y> 0) has a thickness of 1 nm to 2
Deposit about 0 nm. Among the above, the silicon dioxide film is
For example, dichlorosilane (SiH₂ Cl₂ ) And nitrous oxide
Elementary (N₂ O) or trichlorosilane (SiHCl
₃ ) And nitrous oxide (N₂ O) or silicon tetrachloride (S
iCl_Four ) And nitrous oxide (N₂ O) as a raw material CVD
Formed by. Further, the silicon nitride film is, for example, a dichroic film.
Lusilane (SiH₂ Cl₂ ) And ammonia (NH₃ ),
Alternatively, trichlorosilane (SiHCl₃ ) And Ammoni
A (NH ₃ ), Or silicon tetrachloride (SiCl)_Four ) And a
Nmonia (NH₃ ) Is used as a raw material to form a film by CVD.
It Alternatively, it is formed by JVD or RTCVD. Well
Further, the silicon oxynitride film is formed of, for example, dichlorosilane (Si
H₂ Cl₂ ) And nitrous oxide (N₂ O) and ammonia (N
H₃ ) Or trichlorosilane (SiHCl₃ )When
Nitrous oxide (N₂ O) and ammonia (NH₃ ),Also
Is silicon tetrachloride (SiCl_Four ) And nitrous oxide (N₂ O)
And ammonia (NH₃ ) Any combination of ingredients
It is formed by CVD used as a gas.

As described above, the gate dielectric film 13 shown in FIG. 6B is formed.

Next, as shown in FIG. 7C, for example,
By ion-implanting n-type impurities such as As ⁺ and P ⁺ substantially perpendicularly to the substrate surface, the source / drain regions 12 are formed in the semiconductor substrate 11 on the upper surface of the convex portion and the bottom surface of the concave portion. The ion implantation for forming the source / drain regions 12 may be performed before the step of forming the gate dielectric film 13.

Next, polycrystalline silicon or amorphous silicon to which impurities have been added is deposited to fill the concave portion, and this is filled with RI.
Etch back by an anisotropic etching method such as E. As a result, as shown in FIG. 7D, the sidewall 14a is formed at the corner of the recess.

As shown in FIG. 8E, p-type impurities are implanted by the oblique ion implantation method while the lower portion of the channel forming region is protected by the sidewalls 14a, and the upper portion of the channel forming region has a high concentration p. Change to type. As a result, a high resistance channel forming region 15 is formed between the lower portion of the channel forming region and the source / drain region 12 above.

As shown in FIG. 8 (f), the same material as the sidewall 14a is deposited thickly, and thereafter, this is deposited on FIG.
The gate electrode 14 is patterned into the stripe shape shown in FIG.
To form.

In the subsequent steps, the non-volatile semiconductor memory is completed by forming an interlayer insulating film, forming a contact, forming an upper wiring layer, etc., if necessary.

In the above manufacturing method, the step of patterning the semiconductor substrate 11 and the step of forming the high-resistance channel forming region 15 are added as compared with the conventional cell in which the semiconductor substrate 11 has no step. These steps are few compared to the total manufacturing steps of the non-volatile semiconductor memory, and do not cause a significant cost increase. Moreover, there is an advantage that the structure is extremely simple and easy to make.

Next, an operation example of the above memory transistor will be described. Specifically, a method of writing, erasing, and reading data of 1-bit information in the memory transistor M21 shown in FIG. 4 will be described. The specifications of the gate dielectric film (ONO film) of the memory transistor used in this operation example are as follows: silicon dioxide / silicon nitride / silicon dioxide = 5 nm / 8 n
m / 5 nm. The depth of the groove R is 350 nm.

For data writing, with reference to the potential of the semiconductor substrate 11, 0 V and 5 V are applied to one of the two source / drain regions 12, and a positive voltage, for example, 5 to 6 V is applied to the gate electrode 14. . At this time, electrons are accumulated in the channel formation region CH to form an inversion layer (channel), and the electrons supplied from the source in the channel are accelerated by the electric field between the source and the drain, so that high kinetic energy is generated at the end of the drain. As a result, hot electrons having energy exceeding the energy barrier of the bottom dielectric film (silicon dioxide film) 13a are obtained. Part of the hot electrons has a certain probability of being a charge storage film (silicon nitride film) 13b.
Trapped in the trap formed on the drain side of the.

In the data reading, the potential of the semiconductor substrate 11 is used as a reference and 0 is applied to one of the source / drain regions 12.
V is applied and, for example, 1.5 V is applied to the other. In the case of fore read, 1.5 V is applied to the upper source / drain region 12 where the high resistance channel forming region 15 is provided, and the reference voltage 0 V is applied to the lower source / drain region 12.
Is applied. Further, a voltage within a range that does not change the number of trapped electrons in the charge storage film 13b, for example, 2.5 V is applied to the gate electrode 14. Under this bias condition, the charge storage film 1
The memory transistor is turned on or off depending on the presence or absence of trapped electrons in 3b or the amount of trapped electrons. That is, the memory transistor maintains the off state when the electrons are sufficiently injected into the charge storage film 13b, and the memory transistor is turned on when the electrons are not sufficiently injected into the charge storage film 13b. Only when the memory transistor is turned on, the potential difference between the source / drain regions 12 changes, and the presence or absence of this change is amplified by a detection circuit such as a sense amplifier and read out as stored information to the outside. Note that the voltage application direction between the source and the drain needs to be opposite to that at the time of writing, but reading can also be performed by reverse reading.

In data erasing, band-to-band tunneling is used. Specifically, a positive voltage, for example, 5V, is applied to one of the source / drain regions 12, here, the upper source / drain region 12 near the accumulated charge, based on the potential of the semiconductor substrate 11. Further, the source / drain region 12 on the lower side is opened, and a negative voltage, for example, −5 V is applied to the gate electrode 14. At this time, the surface of the source / drain region 12 to which 5V is applied is depleted, and a high electric field is generated in the depletion layer, so that a band-band tunnel current is generated. The holes resulting from the band-to-band tunnel current are accelerated by the electric field to obtain high energy. This high energy hole is attracted to the gate voltage and injected into the charge trap in the charge storage film 13b. As a result, the charges of the stored electrons in the charge storage film 13b are canceled by the injected holes, and the memory transistor is returned to the erased state, that is, the state where the threshold voltage is low.

In the method of operating the non-volatile memory according to this embodiment, since the high resistance channel forming region 15 is provided, the efficiency of electron injection during writing is high. Therefore,
As a result, the write gate voltage has been reduced to about 5 to 6 V from the conventional voltage close to 10 V. In addition, the writing speed was increased to 10 μs or less. When a well is formed in the substrate 11, for example, when a voltage for reverse biasing the pn junction formed by the source / drain regions 12, here a negative voltage is applied to the well,
Furthermore, the write gate voltage and the like can be reduced, which is desirable. The means for applying this back bias is not particularly shown,
It is included in the peripheral circuit of the memory cell array.

The electrical reliability of the memory cell was examined by using the above write, erase and read operations. As a result, regarding the data rewriting characteristics, the data holding characteristics, and the read disturb characteristics, it was found that the data rewriting can be guaranteed 100,000 times or more, and the data holding and read disturb can be guaranteed for 10 years. In addition, the data retention characteristic is 85 ° C, 1 degree after rewriting 100,000 times.
Satisfied with 0 years.

Regarding this data retention characteristic, the MONOS type memory transistor of this embodiment has the following merits as compared with the floating gate type. First, in the step of forming the groove R in the semiconductor substrate 11, in order to improve the verticality of the side wall of the groove, for example, when etching with strong anisotropy is adopted, the side wall of the groove R is somewhat damaged by etching. There is. In that case, the bottom dielectric film 1 formed on the side wall damaged by the etching
3a also has a poor quality film, that is, the bottom dielectric film 13a having many defects can be formed. When the vertical structure is applied to the floating gate type, the floating gate allows free movement of charges within the layer, and therefore, when a defect is locally formed in the bottom dielectric film 13a, However, all the charges held in the floating gate may leak to the substrate via the defect. On the other hand, since the charge traps in the film formed on the bottom dielectric film 13a are spatially discrete, the charges accumulated in the charge traps near the defect only leak, and Leakage of charges to the semiconductor substrate via defects can be reduced, and the characteristics are improved in comparison with the floating gate type in terms of data retention characteristics and reliability.

Modification 1 In this modification 1, a large number of electrically insulated conductors (hereinafter, referred to as small particle size) embedded in a gate dielectric film as a charge storage means of a memory transistor and having a particle size of, for example, 10 nanometers or less. A non-volatile semiconductor memory device using a conductor).

FIG. 9 is an enlarged cross-sectional view showing the structure of a memory transistor using a small grain conductor as the charge storage means. In this memory transistor, the gate dielectric film 23 has a bottom dielectric film 23a, discrete small-particle-diameter conductors 23b as charge storage means, and a dielectric film 23c covering the small-particle conductors 23b. Consists of.
Other configurations, that is, the semiconductor substrate 11, the channel formation region CH, the source / drain region 12, the gate electrode 14, and the high resistance channel formation region 15 are the same as those in FIG.

Each of the small grain conductors 23b is, for example, a fine amorphous Si _x Ge _1-x (0≤x≤1) or polycrystalline Si.
It is made of a conductor such as _x Ge _1-x (0 ≦ x ≦ 1). The size (diameter) of the small-particle conductors 23b is preferably 10 nm or less, for example, about 4.0 nm, and the individual small-particle conductors are spatially separated by the dielectric film 23c, for example, 4 nm. They are separated by a certain distance.
The bottom dielectric film 23a in this example can be appropriately selected within the range of 2.6 nm to 5.0 nm depending on the intended use. Here, the film thickness is set to about 4.0 nm.

A method of manufacturing the memory transistor having the above structure will be described. First, after forming the step of FIG. 6A, the bottom dielectric film 23a is formed by the same method as described in the description of FIG. 6B. Then, for example, LP-CVD
Si _x occurring in the initial process of the Si _x Ge _1-x film formation using the
An assembly of Ge _1-x small-diameter conductors is used as the bottom dielectric film 23.
It is formed on a. The small particle size conductor of Si _x Ge _1-x uses silane (SiH ₄ ) or dichlorosilane (DCS), germane (GeH ₄ ) and hydrogen as source gases.
It is formed at a film forming temperature of about 00 ° C to 900 ° C. The density and size of the small particle size conductor can be controlled by adjusting the partial pressure or flow rate ratio of silane or dichlorosilane and hydrogen. The larger the hydrogen partial pressure, the higher the density of the nuclei that are the source of the small particle size conductor. Alternatively, a non-stoichiometric composition of SiO _x is silane or dichlorosilane and nitrous oxide (N ₂ O) is a raw material gas at 500 ° C. to 800 ° C.
It is formed at a film forming temperature of about 900 ° C. to 1100 ° C.
By annealing at a high temperature, the SiO ₂ and Si small-particle-diameter conductor phases are separated, and an aggregate of Si small-particle-size conductors embedded in SiO ₂ is formed. Next, the small particle size conductor 23b
A dielectric film 23c is formed by LP-CVD to have a thickness of, for example, about 7 nm so as to be embedded therein. In this LP-CVD, the source gas is a mixed gas of dichlorosilane (DCS) and dinitrogen oxide (N ₂ O), and the substrate temperature is 700 ° C., for example. At this time, the small particle size conductor 23b is embedded in the dielectric film 23c. After that, a conductive film to be a word line is formed,
The memory transistor is completed through a step of collectively patterning the gate electrode 14.

The small-particle-diameter conductor 23b thus formed
Functions as a carrier trap discretized in the plane direction. Each small particle conductor 23b can hold several injected electrons. Note that the small-particle-diameter conductor 23b may be made smaller to hold a single electron.

Modification 2 This modification 2 is an AMG (Alternate Metal virtual Gro
und) type memory cell array structure.

FIG. 10 shows an equivalent circuit diagram of the AMG type memory cell array. In this memory cell array, n × m memory transistors forming each memory cell are arranged in a matrix, and the gates of the memory transistors in each row are connected to any of the word lines WL1, WL2, ..., WLn.

Impurity diffusion layers DR1, DR2, ..., DR
5, are long in the column direction and are repeatedly formed at regular intervals in the row direction. These impurity diffusion layers function as source / drain regions and are shared by two adjacent memory transistor columns, as in a normal VG type memory cell array. Odd-numbered impurity diffusion layers DR1, DR3, D
R5, ... Are bit lines BL1, BL2, BL3, which are arranged above the bit lines BL1, BL2, BL3 via the select transistor ST0.
…It is connected to the. The select transistor ST0 is
It is controlled by the bit line selection signal BLSEL. The bit line comprises a metal layer, for example a layer of aluminum. The even-numbered impurity diffusion layers DR2, DR4, ... Are arranged substantially in the center between the bit lines and are configured to be selectively connectable to either of the bit lines on both sides. That is, the even-numbered impurity diffusion layers are connected to the right bit line via the select transistor ST1 controlled by the select signal SEL, and the left bit via the select transistor ST2 controlled by the inverted signal SEL_ of the select signal. Connected to the wire.

This n × m memory transistor group and 3
A basic unit (sub-array) is configured by the select transistors ST0, ST1, ST2 of the type, and the sub-array is repeatedly arranged to configure the entire memory cell array.

In the AMG type memory cell array, it is possible to select only every other column of the prepared memory cell array due to its structure. However, for example, by setting the number of cell columns in the sub-array to twice the number of required data columns and switching the operable memory cell columns between odd and even columns, virtually all memory cells are effective. Used for data storage.
In addition, due to the configuration capable of switching columns, a normal VG
Unlike the memory cell array of the type, it is possible to operate in page units. Further, since the distance between the bit lines is relaxed, even if the memory transistor is miniaturized, the wiring pitch of the bit lines is unlikely to be a limitation for reducing the memory cell array area.

The nonvolatile memory of the present embodiment can be applied to a memory transistor structure other than the modification 1 described above and a memory cell array structure other than the modification 2 described above.

Gate dielectric film 13 of memory transistor
The configuration of is the so-called MONOS exemplified in the above embodiment.
The present invention is not limited to the three-layer dielectric film used in the mold. There are two requirements for the gate dielectric film, that is, a plurality of dielectric films that are stacked are included and that charge storage means such as a charge trap is discretized. A configuration can be adopted. For example, a bottom dielectric film made of silicon dioxide or the like, such as a so-called MNOS type,
It may have a two-layer structure with a film having charge holding ability made of silicon nitride or the like formed thereon.

It is known that a dielectric film made of a metal oxide such as aluminum oxide Al ₂ O ₃ , tantalum oxide Ta ₂ O ₅ and zirconium oxide ZrO ₂ also contains many traps. In the MNOS type, it can be adopted as a film having a charge retention ability.
Furthermore, when other metal oxides are used as the material of the charge storage film 13b, for example, there are films made of oxides of titanium, hafnium and lanthanum, or films made of silicates of tantalum, titanium, zirconium, hafnium and lanthanum. Can also be adopted.

Alkali oxide is used as the material of the charge storage film 13b.
Minium (Al₂ O₃ ) Is selected, for example,
For example, aluminum chloride (AlCl₃ ) And carbon dioxide (C
O₂ ) And hydrogen (H₂ ) Is used as a gas source,
Or aluminum alkoxide (Al (C₂ H_Five O)
₃ , Al (C₃ H₇ O)₃ , Al (C_Four H₉ O)₃ etc)
Pyrolysis of is used. As the material of the charge storage film 13b, acid
Tantalum oxide (Ta₂ O_Five ) Is selected, for example,
For example, tantalum chloride (TaCl_Five ) And carbon dioxide (CO
₂ ) And hydrogen (H₂ ) Gas as a raw material for CVD,
Is TaCl₂ (OC₂ H_Five )₂ C_Five H ₇ O₂ , Or
Ta (OC₂ H_Five )_Five Pyrolysis of is used. Charge storage film 1
As a material for 3b, zirconium oxide (ZrO_x ) Is selected
If selected, for example, Zr in an oxygen atmosphere
Tattering method is used.

Similarly, the bottom dielectric film 13a and the top dielectric film 13c are made of silicon dioxide, silicon nitride,
Not limited to silicon oxynitride, for example, aluminum oxide A
The material may be selected from any of l ₂ O ₃ , tantalum oxide Ta ₂ O ₅ , and zirconium oxide ZrO ₂ . The method for forming these metal oxides is as described above. Further, the bottom dielectric film 13a and the top dielectric film 13c are made of titanium,
A film made of hafnium or lanthanum oxide may be used,
Alternatively, a film made of silicate of tantalum, titanium, zirconium, hafnium, or lanthanum can be used.

Besides, various modifications can be made without departing from the scope of the present invention.

[0066]

According to the nonvolatile semiconductor memory device and the method of operating the same of the present invention, the size (occupied area) is smaller than that of a semiconductor memory element having a channel in the first conductivity type semiconductor surface having a flat surface. It is extremely small, and even if the element is miniaturized, deterioration of electrical characteristics due to the effect of fine shape can be prevented, and the data retention characteristics and the like are not deteriorated. Further, since it has a high resistance channel forming region, the charge injection efficiency is high and a high speed operation is possible.

[Brief description of drawings]

FIG. 1 is a plan view of a memory cell array according to an embodiment of the present invention.

FIG. 2 is a diagram showing a region into which impurities are introduced in the plan view shown in FIG. 1 according to the embodiment of the present invention.

FIG. 3 relates to an embodiment of the present invention, (a) is A- of FIG.
FIG. 2B is a sectional view taken along line A ′, and FIG. 1B is a sectional view taken along line BB ′ in FIG. 1.

FIG. 4 is an enlarged cross-sectional view of two cells adjacent in the row direction in the memory cell array according to the embodiment of the present invention.

5 is an equivalent circuit diagram corresponding to the cross-sectional view of FIG. 4 in the memory cell array according to the embodiment of the present invention.

6A and 6B are cross-sectional views after formation of a groove portion in a semiconductor substrate and FIG. 6B is a cross-sectional view after formation of a gate dielectric film in manufacturing a memory cell array according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view after formation of source / drain regions and a cross-sectional view after formation of sidewalls in manufacturing a memory cell array according to an embodiment of the present invention.

8A and 8B are cross-sectional views at the time of forming the high resistance channel formation region and FIG. 8F is a cross-sectional view after the word lines are formed in the manufacturing of the memory cell array according to the embodiment of the present invention.

FIG. 9 is a sectional view of a memory transistor showing a first modification of the embodiment of the present invention.

FIG. 10 is an equivalent circuit diagram showing a memory cell array system in Modification 2 of the embodiment of the present invention.

[Explanation of symbols]

11 ... Semiconductor substrate, 12 ... Source / drain region, 13
... Gate dielectric film, 13a ... Bottom dielectric film, 13b ...
Charge storage film, 13c ... Top dielectric film, 14 ... Gate electrode, 15 ... High resistance channel forming region, R ... Trench.

Continued front page    F-term (reference) 5F083 EP17 EP18 EP22 EP48 EP49                       EP64 EP69 EP75 ER02 ER05                       ER06 ER11 ER21 GA01 GA09                       JA02 JA03 JA06 KA08 KA13                       PR21 PR37                 5F101 BA42 BA44 BA45 BA46 BA47                       BA54 BB02 BC06 BC11 BC12                       BC13 BD10 BD13 BD15 BD16                       BD33 BH02 BH09

Claims (10)

[Claims] 1. A first-conductivity-type semiconductor having a step on its surface, and two second-conductivity-type semiconductor regions formed at the top and bottom of the step and separated in a direction perpendicular to the main surface of the first-conductivity-type semiconductor. And a gate dielectric film which includes a spatially discrete charge storage means inside and is formed so as to cover at least a part of the side surface of the step, and the step of the step with the gate dielectric film interposed. A method of operating a non-volatile semiconductor memory device having a gate electrode facing each other, wherein electrons supplied from one of the second conductivity type semiconductor regions at the time of writing in the vicinity of the other second conductivity type semiconductor region. Between the two second-conductivity-type semiconductor regions, so that hot electrons are injected into the charge storage means on the other side,
A method of operating a non-volatile semiconductor memory device, comprising the step of applying an optimized voltage to each of the gate electrodes. 2. The non-volatile semiconductor memory device is adjacent to an end of the second conductivity type semiconductor region on a channel center side,
The semiconductor device further has a high-resistance channel formation region having a higher concentration than the first conductivity type semiconductor in which a channel is formed, and improves the concentration of an electric field in the high-resistance channel formation region during writing to improve hot electron injection efficiency. An improved method of operating a non-volatile semiconductor memory device according to claim 1, wherein the method is improved. 3. The first conductivity type semiconductor, at the time of writing,
2. The method of operating a non-volatile semiconductor memory device according to claim 1, further comprising the step of applying a voltage such that a pn junction formed between the second conductivity type semiconductor region and the second conductivity type semiconductor region is reverse biased. 4. The first conductivity type semiconductor, at the time of writing,
3. The method of operating a nonvolatile semiconductor memory device according to claim 2, further comprising the step of applying a voltage such that a pn junction formed between the second conductivity type semiconductor region and the second conductivity type semiconductor region is reverse biased. 5. The second side on the side where the electrons are injected at the time of erasing.
2. The method of operating a nonvolatile semiconductor memory device according to claim 1, further comprising the step of applying a voltage between the second conductive type semiconductor region and the gate electrode so that hot holes are injected from the conductive type semiconductor region. . 6. A voltage for applying a voltage in the same direction as that for writing to the two second conductivity type semiconductor regions at the time of reading, and turning on or off the channel depending on the presence or absence of charges injected during the writing or the amount of charges. The method of operating a nonvolatile semiconductor memory device according to claim 1, further comprising applying a voltage to the gate electrode. 7. A voltage for applying a voltage in the same direction as that for writing to the two second conductivity type semiconductor regions during reading, and turning on or off the channel depending on the presence or absence of charges injected during writing and the amount of charges. 4. The method for operating a nonvolatile semiconductor memory device according to claim 3, further comprising applying a voltage to the gate electrode. 8. A first-conductivity-type semiconductor having a step on the surface, and two second-conductivity-type semiconductor regions formed on the top and bottom of the step and separated in a direction perpendicular to the main surface of the first-conductivity-type semiconductor. And a gate dielectric film which includes a spatially discrete charge storage means inside and is formed so as to cover at least a part of the side surface of the step, and the step of the step with the gate dielectric film interposed. A method of operating a non-volatile semiconductor memory device having a gate electrode facing each other, wherein a hot hole is injected from a second conductivity type semiconductor region on a side where the electron is injected during erasing. A method of operating a non-volatile semiconductor memory device, comprising the step of applying a voltage between a second conductivity type semiconductor region and the gate electrode. 9. A first-conductivity-type semiconductor having a step on the surface, and two second-conductivity-type semiconductor regions formed on the top and bottom of the step and separated in a direction perpendicular to the main surface of the first-conductivity-type semiconductor. And a high resistance channel forming region formed in a portion adjacent to at least one of the second conductivity type semiconductor regions and having a higher concentration than the surrounding first conductivity type semiconductor region, and a spatially discretized charge storage means inside. A non-volatile semiconductor memory device including a gate dielectric film formed to cover at least a part of the side surface of the step and a gate electrode facing the side surface of the step with the gate dielectric film interposed. . 10. The non-volatile memory according to claim 9, further comprising means for applying a voltage for reverse biasing a pn junction formed between the second conductivity type semiconductor region and the second conductivity type semiconductor region, to the first conductivity type semiconductor during writing. Semiconductor memory device.