JP2003077728A - Lamination inductor - Google Patents
Lamination inductorInfo
- Publication number
- JP2003077728A JP2003077728A JP2002206936A JP2002206936A JP2003077728A JP 2003077728 A JP2003077728 A JP 2003077728A JP 2002206936 A JP2002206936 A JP 2002206936A JP 2002206936 A JP2002206936 A JP 2002206936A JP 2003077728 A JP2003077728 A JP 2003077728A
- Authority
- JP
- Japan
- Prior art keywords
- coil
- chip
- terminal electrodes
- conductor
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000003475 lamination Methods 0.000 title abstract description 4
- 239000004020 conductor Substances 0.000 claims description 29
- 238000000605 extraction Methods 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 description 10
- 238000000034 method Methods 0.000 description 5
- 229910000859 α-Fe Inorganic materials 0.000 description 5
- 230000004907 flux Effects 0.000 description 3
- 239000000696 magnetic material Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 229910020816 Sn Pb Inorganic materials 0.000 description 1
- 229910020922 Sn-Pb Inorganic materials 0.000 description 1
- 229910008783 Sn—Pb Inorganic materials 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
Landscapes
- Coils Or Transformers For Communication (AREA)
Abstract
Description
【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、積層構造のチップ
内にコイルを埋設した積層インダクタに関するものであ
る。
【０００２】
【従来の技術】図６には従来の積層インダクタの概略断
面図を示してある。
【０００３】同図において、１１は磁性体材料から成る
直方体形状のチップ、１２はチップ１１内に埋設された
螺旋状のコイル、１３はチップ１１の長手方向端部に設
けられた一対の端子電極である。コイル１２の周回中心
線Ｙは端子電極１３を結ぶ方向（チップ長手方向）と直
交しており、該コイル１２の端部はチップ端面まで導出
され各端子電極１３に接続している。
【０００４】この積層インダクタは、スクリーン印刷等
の手法によりコ字状，Ｌ字状等のコイル用導体を形成し
た複数の磁性体グリーンシートを導体非形成のシートと
共に所定の順序で積み重ねて圧着し、これを焼成した後
に端子電極用の導体ペーストをチップ端部に塗布して焼
き付けることで製造されている。シートを介して隣接す
るコイル用導体は、導体形成前に予め該シートに形成し
たスルーホール部分を通じて相互に接続され螺旋状のコ
イル１２となる。最上層及び最下層のコイル用導体はシ
ート端に延びる導出部分を有しており、チップ両端に露
出する該導出端が端子電極１３と接続している。
【０００５】
【発明が解決しようとする課題】ところで、上記従来の
積層インダクタでは、端子電極１３の４面を夫々搭載面
として利用できることから、これを基板Ｚの導体パター
ンＺａ上に搭載する際に図７と図８に示す２通りの向
き、即ちコイル１２の周回中心線Ｙが基板面と直角とな
る向き（図７参照）とコイル１２の周回中心線Ｙが基板
面と平行となる向き（図８参照）とが発生する。
【０００６】図７の搭載向きと図８の搭載向きでは、コ
イル１２と基板Ｚとの位置関係が異なることに起因して
チップ外部の磁束に対する磁気抵抗に差が生じ、これが
インダクタンスの差となって現れることになる。特に、
チップ材料として比透磁率の低いものを使用した積層イ
ンダクタでは、搭載向きによる磁気抵抗に大きな差が生
じてインダクタンスにかなりの差が現れる。
【０００７】本発明は上記問題点に鑑みてなされたもの
で、その目的とするところは、端子電極の形態及び位置
によって部品搭載向きが変わるような場合でも安定した
特性を得ることができる積層インダクタを提供すること
にある。
【０００８】
【課題を解決するための手段】上記目的を達成するた
め、本発明は、直方体形状を成す積層構造のチップと、
チップ内に埋設されたコイルと、チップの相対する端部
に設けられた一対の端子電極と、コイル端と各端子電極
とを接続する一対の引出部分を備えた積層インダクタで
あって、各端子電極はチップの積層方向両端部に形成さ
れ、該各端子電極はチップ側面に回り込む部分を有して
いてその４面を搭載面として利用できるように構成され
ており、コイルは積層方向に並ぶ多数のコイル用導体を
導体充填スルーホールを通じ接続することによって所定
周回数を有する螺旋状に構成され、該コイルの周回中心
線は端子電極を結ぶ方向と平行であり、コイルの一端と
一方の端子電極とを接続する一方の引出部分は積層方向
に並ぶ多数の引出用導体を導体充填スルーホールを通じ
接続することにより前記回り込み部分以上の所定長さを
有する直線状に構成され、該引出部分の向きは端子電極
を結ぶ方向と平行であり、コイルの他端と他方の端子電
極とを接続する他方の引出部分は積層方向に並ぶ多数の
引出用導体を導体充填スルーホールを通じ接続すること
により前記回り込み部分以上の所定長さを有する直線状
に構成され、該引出部分の向きは端子電極を結ぶ方向と
平行である、ことをその特徴とする。
【０００９】この積層インダクタによれば、コイルの周
回中心線を端子電極を結ぶ方向と平行にしてあるので、
複数の搭載向きが可能な場合又は端子電極の形態及び位
置が変更され搭載向きが変わるような場合でも、基板面
に対するコイルの周回中心線の向きが変わることがな
い。
【００１０】
【発明の実施の形態】図１には本発明に係る積層インダ
クタの概略断面図を示してある。
【００１１】同図において、１は磁性体材料或いは非磁
性材料（絶縁材料）から成る直方体形状のチップ、２は
チップ１内に埋設された螺旋状のコイル、３はチップ１
の長手方向端部に設けられた一対の端子電極である。コ
イル２の周回中心線Ｙは端子電極３を結ぶ方向（チップ
長手方向）と平行であり、該コイル２の端部はチップ端
面まで導出され各端子電極３に接続している。
【００１２】上記の積層インダクタでも端子電極３の４
面を夫々搭載面として利用できることから、基板Ｚの導
体パターンＺａ上に搭載する際に図２に示す向きとこれ
と９０度異なる向きとが発生することになる。しかし、
コイル２の周回中心線Ｙが端子電極３を結ぶ方向（チッ
プ長手方向）と平行であるため、搭載向きが変わっても
基板面に対するコイル２の周回中心線Ｙの向きは変わる
ことがない。
【００１３】従って、搭載向きに拘らずコイル２と基板
Ｚとの位置関係を一定に維持することができ、チップ外
部の磁束に対する磁気抵抗に差が生じることを防止して
安定したインダクタンスを得ることができる。
【００１４】ここで、図３乃至図５を参照して図１に示
した積層インダクタの製造方法について説明する。
【００１５】製造に際しては、まず上層用シートＡとコ
イル層用シートＢ１〜Ｂ４と下層用シートＣを夫々用意
する（図３参照）。尚、図面には一部品に対応するもの
を示してあるが、実際の各シートは多数個取りが可能な
大きさを有しており、積層，圧着後に部品寸法に切断さ
れる。
【００１６】上層用シートＡは、Ｆｅ2Ｏ3，ＮｉＯ，Ｚ
ｎＯ又はＣｕＯ等を主成分とするフェライトグリーンシ
ートの所定位置に所定径のスルーホールｈを形成した
後、該スルーホールｈと重なるように矩形状の引出用導
体Ｐａを形成することにより作成されている。
【００１７】コイル層用シートＢ１〜Ｂ４は、上記同様
のフェライトグリーンシートの所定位置にスルーホール
ｈを形成した後、該スルーホールｈにその端部が重なる
ように４種類のコ字状のコイル用導体Ｐｂ１〜Ｐｂ４を
夫々形成することにより作成されている。このコイル用
導体Ｐｂ１〜Ｐｂ４の形状はコ字状以外にもＬ字状等の
非環状のものが種々採用できる。
【００１８】下層用シートＣは、上層用シートＡと同
様、フェライトグリーンシートの所定位置に所定径のス
ルーホールｈを形成した後、該スルーホールｈと重なる
ように矩形状の引出用導体Ｐｃを形成することにより作
成されている。
【００１９】上記のスルーホールｈはフェライトグリー
ンシートがフィルムで支持されている場合にはレーザ光
照射によって、またフィルムで支持されていない場合に
は金型打ち抜きによって夫々形成される。また、導体Ｐ
ａ，Ｐｂ１〜Ｐｂ４，ＰｃはＡｇ等の金属粉末を含有し
た導体ペーストをスクリーン印刷等の手法によって厚膜
印刷することで形成され、スルーホールｈには印刷時に
印刷ペーストの一部が充填される。
【００２０】次いで、用意した各シートＡ，Ｂ１〜Ｂ
４，Ｃをフィルム付きの場合にはこれを剥しながら図３
に示す順序で積層し、これを５００ｋｇ／ｃｍ2 前後の
圧力で圧着する。ちなみに上・下層用シートＡ，Ｃは層
厚みに相当する枚数が、またコイル層用シートＢ１〜Ｂ
４はコイル周回数に相当する枚数が夫々用いられる。
【００２１】次いで、各シートＡ，Ｂ１〜Ｂ４，Ｃの積
層体（図４参照）を導体に含まれる金属成分に応じた温
度、例えばＡｇの場合には９００℃前後の温度で焼成す
る。これにより、各シートＡ，Ｂ１〜Ｂ４，Ｃを介して
隣接する導体Ｐａ，Ｐｂ１〜Ｐｂ４，Ｐｃがスルーホー
ル充填部分を通じて相互に接続され積層方向の螺旋状コ
イル２となる。
【００２２】次いで、焼成後のチップ１の積層方向端部
に上記同様の導体ペーストＰをディップ法等の手法によ
って塗布し（図５参照）、これを焼成温度温度よりも低
い温度で焼き付けて端子電極３を形成し、必要に応じて
これにＳｎ−Ｐｂ等のメッキ処理を施す。コイル２の端
部（引出用導体Ｐａ，Ｐｃ）はチップ端面に導出され露
出しているので、該露出部分が端子電極３と接続する。
【００２３】
【発明の効果】以上詳述したように、本発明によれば、
コイルの周回中心線が端子電極を結ぶ方向（チップ長手
方向）と平行であるため、搭載向きが変わっても基板面
に対するコイルの周回中心線の向きは変わることがな
い。従って、搭載向きに拘らずコイルと基板との位置関
係を一定に維持することができ、チップ外部の磁束に対
する磁気抵抗に差が生じることを防止して安定したイン
ダクタンスを得ることができる。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated inductor in which a coil is embedded in a chip having a laminated structure. 2. Description of the Related Art FIG. 6 is a schematic sectional view of a conventional laminated inductor. In FIG. 1, reference numeral 11 denotes a rectangular chip made of a magnetic material, 12 denotes a spiral coil embedded in the chip 11, and 13 denotes a pair of terminal electrodes provided at the longitudinal end of the chip 11. It is. The circling center line Y of the coil 12 is orthogonal to the direction connecting the terminal electrodes 13 (chip longitudinal direction), and the end of the coil 12 is led out to the chip end face and connected to each terminal electrode 13. In this laminated inductor, a plurality of magnetic green sheets formed with a coil-shaped or L-shaped coil conductor by a method such as screen printing are stacked and crimped together with a sheet without a conductor in a predetermined order. After baking this, a conductor paste for a terminal electrode is applied to the end of the chip and baked. The coil conductors adjacent to each other via the sheet are connected to each other through a through-hole portion formed in the sheet before the conductor is formed to form a spiral coil 12. The coil conductors of the uppermost layer and the lowermost layer have lead-out portions extending to sheet ends, and the lead-out ends exposed at both ends of the chip are connected to the terminal electrodes 13. In the above-mentioned conventional laminated inductor, since the four surfaces of the terminal electrode 13 can be used as mounting surfaces, respectively, when mounting the terminal electrode 13 on the conductive pattern Za of the substrate Z, The two directions shown in FIGS. 7 and 8, that is, the direction in which the circling center line Y of the coil 12 is perpendicular to the substrate surface (see FIG. 7) and the direction in which the circulating center line Y of the coil 12 is parallel to the substrate surface ( 8) occurs. In the mounting direction shown in FIG. 7 and the mounting direction shown in FIG. 8, there is a difference in magnetic resistance with respect to the magnetic flux outside the chip due to the difference in the positional relationship between the coil 12 and the substrate Z. This results in a difference in inductance. Will appear. In particular,
In a multilayer inductor using a material having a low relative magnetic permeability as a chip material, a large difference occurs in magnetic resistance depending on the mounting direction, and a considerable difference appears in inductance. SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a multilayer inductor capable of obtaining stable characteristics even when the component mounting direction changes depending on the form and position of a terminal electrode. Is to provide. In order to achieve the above object, the present invention provides a chip having a laminated structure having a rectangular parallelepiped shape,
A laminated inductor comprising a coil embedded in a chip, a pair of terminal electrodes provided at opposite ends of the chip, and a pair of lead portions connecting a coil end and each terminal electrode. Electrodes are formed at both ends of the chip in the stacking direction, and each terminal electrode has a portion that goes around the chip side surface, and is configured so that four surfaces thereof can be used as a mounting surface. Is formed in a spiral shape having a predetermined number of turns by connecting the coil conductors through the conductor-filled through-holes, and the center line of the coil is parallel to the direction connecting the terminal electrodes. Is connected to a large number of extraction conductors arranged in the stacking direction through conductor-filled through holes to form a straight line having a predetermined length equal to or longer than the wraparound portion. The direction of the lead portion is parallel to the direction connecting the terminal electrodes, and the other lead portion connecting the other end of the coil and the other terminal electrode has a large number of lead conductors lined up in the laminating direction with conductor filled through holes. Through the connection, a straight line having a predetermined length equal to or longer than the wraparound portion is formed, and the direction of the extraction portion is parallel to the direction connecting the terminal electrodes. According to this laminated inductor, since the center line of the coil is parallel to the direction connecting the terminal electrodes,
Even when a plurality of mounting directions are possible or when the mounting direction changes due to a change in the form and position of the terminal electrode, the direction of the coil center line with respect to the substrate surface does not change. FIG. 1 is a schematic sectional view of a laminated inductor according to the present invention. In FIG. 1, 1 is a rectangular chip made of a magnetic material or a non-magnetic material (insulating material), 2 is a spiral coil embedded in the chip 1, and 3 is a chip 1
Are a pair of terminal electrodes provided at the longitudinal ends of the pair. The circling center line Y of the coil 2 is parallel to the direction connecting the terminal electrodes 3 (chip longitudinal direction), and the end of the coil 2 is led out to the chip end face and connected to each terminal electrode 3. In the above-described multilayer inductor, the terminal electrode 3
Since each surface can be used as a mounting surface, the direction shown in FIG. 2 and the direction different from this by 90 degrees occur when mounting on the conductor pattern Za of the substrate Z. But,
Since the circling center line Y of the coil 2 is parallel to the direction connecting the terminal electrodes 3 (chip longitudinal direction), the direction of the circulating center line Y of the coil 2 with respect to the substrate surface does not change even if the mounting direction changes. Accordingly, the positional relationship between the coil 2 and the substrate Z can be kept constant regardless of the mounting direction, and a stable inductance can be obtained by preventing a difference in magnetic resistance with respect to magnetic flux outside the chip. Can be. Here, a method of manufacturing the multilayer inductor shown in FIG. 1 will be described with reference to FIGS. At the time of production, first, an upper layer sheet A, coil layer sheets B1 to B4, and lower layer sheet C are prepared (see FIG. 3). It should be noted that although the drawing shows a part corresponding to one part, each actual sheet has a size capable of taking a large number of pieces, and is cut into parts dimensions after lamination and pressure bonding. The upper layer sheet A is made of Fe 2 O 3 , NiO, Z
After forming a through hole h of a predetermined diameter at a predetermined position of a ferrite green sheet containing nO or CuO as a main component, a rectangular lead conductor Pa is formed so as to overlap the through hole h. I have. The coil layer sheets B1 to B4 are formed by forming a through hole h at a predetermined position of the same ferrite green sheet as described above, and then forming four types of U-shaped coils so that the ends thereof overlap the through hole h. It is created by forming the respective conductors Pb1 to Pb4. As the shape of the coil conductors Pb1 to Pb4, various non-annular shapes such as an L-shape can be adopted other than the U-shape. As in the case of the upper layer sheet A, the lower layer sheet C is formed with a through hole h having a predetermined diameter at a predetermined position of the ferrite green sheet, and then a rectangular lead conductor Pc is overlapped with the through hole h. It is created by forming. The above-mentioned through hole h is formed by laser beam irradiation when the ferrite green sheet is supported by a film, and is formed by punching out a die when the ferrite green sheet is not supported by a film. The conductor P
a, Pb1 to Pb4, and Pc are formed by thick-film printing of a conductive paste containing a metal powder such as Ag by screen printing or the like, and a part of the printing paste is filled in the through-hole h at the time of printing. . Next, the prepared sheets A, B1 to B1
4 and C are peeled off when a film is attached.
And then pressure-bonded at a pressure of about 500 kg / cm 2 . The number of sheets A and C for the upper and lower layers is equal to the layer thickness, and the sheets B1 to B for the coil layers
4 is a number corresponding to the number of coil turns. Next, the laminate of the sheets A, B1 to B4, and C (see FIG. 4) is fired at a temperature corresponding to the metal component contained in the conductor, for example, about 900 ° C. in the case of Ag. As a result, the conductors Pa, Pb1 to Pb4, and Pc adjacent to each other via the sheets A, B1 to B4, and C are connected to each other through the through-hole filling portion to form the spiral coil 2 in the stacking direction. Next, the same conductive paste P as described above is applied to the end of the fired chip 1 in the stacking direction by a technique such as dipping (see FIG. 5), and this is baked at a temperature lower than the firing temperature. The electrode 3 is formed, and if necessary, a plating process such as Sn-Pb is performed. Since the ends (leading conductors Pa and Pc) of the coil 2 are led out to the chip end surfaces and are exposed, the exposed portions are connected to the terminal electrodes 3. As described in detail above, according to the present invention,
Since the center line of the coil is parallel to the direction connecting the terminal electrodes (the longitudinal direction of the chip), the direction of the center line of the coil relative to the substrate surface does not change even if the mounting direction changes. Therefore, the positional relationship between the coil and the substrate can be maintained constant regardless of the mounting direction, and a stable inductance can be obtained by preventing a difference in magnetic resistance with respect to magnetic flux outside the chip.
【図面の簡単な説明】
【図１】本発明に係る積層インダクタの概略断面図
【図２】本発明に係る積層インダクタの概略斜視図
【図３】図１に示した積層インダクタの製造方法を示す
図
【図４】積層，圧着工程を示す斜視図
【図５】端子電極形成工程を示す斜視図
【図６】従来の積層インダクタの概略断面図
【図７】従来の積層インダクタの搭載例を示す図
【図８】従来の積層インダクタの搭載例を示す図
【符号の説明】
１…チップ、２…コイル、３…端子電極、Ｙ…コイルの
周回中心線、Ａ…上層用シート、Ｐａ…引出用導体、Ｂ
１〜Ｂ４…コイル層用シート、Ｐｂ１〜Ｐｂ４…コイル
用導体、Ｃ…下層用シート、Ｐｃ…引出用導体。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view of a laminated inductor according to the present invention. FIG. 2 is a schematic perspective view of a laminated inductor according to the present invention. FIG. 3 shows a method of manufacturing the laminated inductor shown in FIG. FIG. 4 is a perspective view showing a laminating and crimping process. FIG. 5 is a perspective view showing a terminal electrode forming process. FIG. 6 is a schematic sectional view of a conventional laminated inductor. FIG. 7 is a mounting example of a conventional laminated inductor. FIG. 8 shows an example of mounting a conventional laminated inductor. [Description of References] 1 ... Chip, 2 ... Coils, 3 ... Terminal electrodes, Y ... Circumferential center line, A ... Sheet for upper layer, Pa ... Leader, B
1 to B4: sheet for coil layer, Pb1 to Pb4: conductor for coil, C: sheet for lower layer, Pc: conductor for extraction.
Claims (1)
チップ内に埋設されたコイルと、チップの相対する端部
に設けられた一対の端子電極と、コイル端と各端子電極
とを接続する一対の引出部分を備えた積層インダクタで
あって、 各端子電極はチップの積層方向両端部に形成され、該各
端子電極はチップ側面に回り込む部分を有していてその
４面を搭載面として利用できるように構成されており、 コイルは積層方向に並ぶ多数のコイル用導体を導体充填
スルーホールを通じ接続することによって所定周回数を
有する螺旋状に構成され、該コイルの周回中心線は端子
電極を結ぶ方向と平行であり、 コイルの一端と一方の端子電極とを接続する一方の引出
部分は積層方向に並ぶ多数の引出用導体を導体充填スル
ーホールを通じ接続することにより前記回り込み部分以
上の所定長さを有する直線状に構成され、該引出部分の
向きは端子電極を結ぶ方向と平行であり、 コイルの他端と他方の端子電極とを接続する他方の引出
部分は積層方向に並ぶ多数の引出用導体を導体充填スル
ーホールを通じ接続することにより前記回り込み部分以
上の所定長さを有する直線状に構成され、該引出部分の
向きは端子電極を結ぶ方向と平行である、 ことを特徴とする積層インダクタ。Claims: 1. A chip having a laminated structure having a rectangular parallelepiped shape,
A laminated inductor comprising a coil embedded in a chip, a pair of terminal electrodes provided at opposing ends of the chip, and a pair of lead-out portions connecting the coil end and each terminal electrode. Electrodes are formed at both ends of the chip in the stacking direction. Each of the terminal electrodes has a portion which goes around the chip side surface, and is configured so that four surfaces thereof can be used as a mounting surface. The coil conductors are connected through conductor-filled through holes to form a spiral having a predetermined number of rounds, and the circumferential center line of the coil is parallel to the direction connecting the terminal electrodes. Is connected to a large number of extraction conductors arranged in the stacking direction through conductor-filled through holes to form a straight line having a predetermined length equal to or greater than the wraparound portion. The direction of the lead portion is parallel to the direction connecting the terminal electrodes, and the other lead portion connecting the other end of the coil and the other terminal electrode passes through a plurality of lead conductors arranged in the laminating direction through a conductor filling through. A laminated inductor, wherein the inductor is formed in a linear shape having a predetermined length equal to or longer than the wraparound portion by connecting through a hole, and the direction of the lead portion is parallel to a direction connecting the terminal electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002206936A JP2003077728A (en) | 2002-07-16 | 2002-07-16 | Lamination inductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002206936A JP2003077728A (en) | 2002-07-16 | 2002-07-16 | Lamination inductor |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6188158A Division JPH0855726A (en) | 1994-08-10 | 1994-08-10 | Laminated electronic part and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003077728A true JP2003077728A (en) | 2003-03-14 |
Family
ID=19195801
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002206936A Withdrawn JP2003077728A (en) | 2002-07-16 | 2002-07-16 | Lamination inductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003077728A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013005482A1 (en) * | 2011-07-06 | 2013-01-10 | 株式会社村田製作所 | Electronic component |
| KR20160000164A (en) | 2014-06-24 | 2016-01-04 | 삼성전기주식회사 | Multi-layered electronic part and board having the same mounted thereon |
| KR20160123676A (en) | 2015-04-16 | 2016-10-26 | 삼성전기주식회사 | Coil electronic component |
| JP2017022304A (en) * | 2015-07-14 | 2017-01-26 | 太陽誘電株式会社 | Inductor and printed board |
-
2002
- 2002-07-16 JP JP2002206936A patent/JP2003077728A/en not_active Withdrawn
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013005482A1 (en) * | 2011-07-06 | 2013-01-10 | 株式会社村田製作所 | Electronic component |
| JPWO2013005482A1 (en) * | 2011-07-06 | 2015-02-23 | 株式会社村田製作所 | Electronic components |
| US9123465B2 (en) | 2011-07-06 | 2015-09-01 | Murata Manufacturing Co., Ltd. | Electronic component |
| KR20160000164A (en) | 2014-06-24 | 2016-01-04 | 삼성전기주식회사 | Multi-layered electronic part and board having the same mounted thereon |
| US9412509B2 (en) | 2014-06-24 | 2016-08-09 | Samsung Electro-Mechanics Co., Ltd. | Multilayer electronic component having conductive patterns and board having the same |
| KR20160123676A (en) | 2015-04-16 | 2016-10-26 | 삼성전기주식회사 | Coil electronic component |
| US10957476B2 (en) | 2015-04-16 | 2021-03-23 | Samsung Electro-Mechanics Co., Ltd. | Coil electronic component |
| JP2017022304A (en) * | 2015-07-14 | 2017-01-26 | 太陽誘電株式会社 | Inductor and printed board |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0855726A (en) | Laminated electronic part and its manufacture | |
| US6871391B2 (en) | Method of manufacturing laminated ceramic electronic component and laminated ceramic electronic component | |
| JP5482554B2 (en) | Multilayer coil | |
| KR100552010B1 (en) | Multilayer Electronic Components and Manufacturing Method Thereof | |
| CN104021913B (en) | Multilayer coil and manufacturing method thereof | |
| JP2004128506A (en) | Stacked coil component and its manufacturing method | |
| US20120062348A1 (en) | Laminated coil | |
| JPH0582350A (en) | Transformer | |
| JP3201309B2 (en) | Laminated coil and method of manufacturing the same | |
| JP4831101B2 (en) | Multilayer transformer component and manufacturing method thereof | |
| JP2002367833A (en) | Multilayer chip inductor | |
| US20080005890A1 (en) | Transformer and associated method of making using liquid crystal polymer (lcp) material | |
| JP2001044038A (en) | Laminated electronic component | |
| JP6784183B2 (en) | Multilayer coil parts | |
| JPH11265823A (en) | Laminated inductor and manufacture of the same | |
| JP2003077728A (en) | Lamination inductor | |
| JP2012204475A (en) | Multilayer electronic component | |
| JP2003217935A (en) | Layered inductor array | |
| JPH0732908U (en) | electromagnet | |
| JP2539613Y2 (en) | Chip inductor | |
| JP2006066829A (en) | Multi-layered electronic component and its manufacturing method | |
| JP2003037014A (en) | Laminated inductor mounted structure | |
| JP2016171160A (en) | Laminated impedance element | |
| JPH02256214A (en) | Chip inductor and its manufacture | |
| JP2000003827A (en) | Manufacture of laminated electronic component |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20040129 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20040224 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20040426 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20040622 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20040823 |
|
| A911 | Transfer of reconsideration by examiner before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20040908 |
|
| A912 | Removal of reconsideration by examiner before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20041001 |
|
| A761 | Written withdrawal of application |
Free format text: JAPANESE INTERMEDIATE CODE: A761 Effective date: 20060510 |