JP2003051757A - Wireless circuit - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To enable a normal carrier monitoring operation in a radio circuit using an ultra-high-speed frequency synthesizer and prevent deterioration of transmission performance. A control unit manages the timing of each slot period of a transmission slot, a ramp down, a guard bit, a ramp up, and a reception slot, and turns on / off a reception power supply.
It controls generation of the F signal 210, the PLL control signal 211, and the switch control signal 212. In the case where the local frequency is switched between the transmission slot and the reception slot, the control unit performs a ramp-up period in which the frequency of the local signal 213 generated by the frequency synthesizer sufficiently converges to the corresponding frequency of the next slot, the reception slot. The receiving power ON / OFF signal 210 is set to the H level to start the receiving operation of the receiving unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio circuit provided with an ultrahigh-speed frequency synthesizer for performing high-speed switching of local frequencies in radio communication.

[0002]

2. Description of the Related Art In recent mobile communication, a system capable of large-capacity data communication is desired. For example, in the PHS (registered trademark) system, PIA
64kb of FS (PHS Internet Access Forum Standard)
When performing ps data communication, a high transmission rate data communication is realized by using multiple slots. In this case, the transmission slot and the reception slot may be adjacent to each other in a plurality of slots assigned to one system of data communication. Therefore, the local frequency is assigned to each slot during the guard bit period between the slots. It is necessary to switch to the frequency to be used at high speed. Therefore, recently, a wireless circuit using an ultrahigh-speed frequency synthesizer capable of switching the local frequency at high speed has been developed.

A configuration example of a radio circuit using such an ultrahigh-speed frequency synthesizer will be shown. FIG. 7 is a block diagram showing a configuration example of a conventional wireless circuit, and FIG. 8 is a time chart explaining the operation of the conventional wireless circuit shown in FIG.

As shown in FIG. 7, the radio circuit includes a transmission / reception input / output terminal 502 to which an antenna 501 is connected, a transmission / reception changeover switch 503, a reception section 504, and a reception power source 505.
A level detection circuit 506, a transmission unit 507, and an ultrahigh-speed frequency synthesizer 508 which is a local unit.

The receiving power source 505 is a receiving power source ON / OFF.
When the signal 510 is at a high level (hereinafter referred to as “H level”), the ON operation is performed to supply power to the receiving unit 504. Further, when it is at a low level (hereinafter referred to as “L level”), the OFF operation is performed and the power supply to the receiving unit 504 is stopped. As a result, the receiving unit 504 performs the intermittent receiving operation.

The frequency synthesizer 508 is a VCO 52.
1 and a PLL circuit 522. The frequency synthesizer 508 generates a local signal 513 to be supplied to the receiving unit 504 and the transmitting unit 507 according to the PLL control signal 511, and switches the frequency within a guard bit period between the transmission slot and the reception slot. It is like this.

The transmission / reception changeover switch 503 has a receiving section 504 when the switch control signal 512 is, for example, H level.
And a transmission / reception input / output terminal 502 are connected, and a reception signal 514 received by the antenna 501 is transmitted to the reception unit 504.
The level detection circuit 506 generates and outputs a reception level detection signal (hereinafter referred to as “RSSI signal”) 516 for carrier monitoring from the reception IF signal 515 output from the reception unit 504.

Further, the transmission / reception changeover switch 503 connects the transmission unit 507 and the transmission / reception input / output terminal 502 when the switch control signal 512 is, for example, L level, and the transmission unit 50.
7, the transmission signal 518 generated and output according to the transmission IF signal 517 is transmitted to the antenna 501.

Next, the operation of the radio circuit will be described with reference to FIG. As shown in the upper part of FIG. 8, guard bits are provided between the slots, such as between the transmission slot and the reception slot, as a buffer period during which no signal is transmitted. Further, before and after the guard bit, a ramp-up period and a ramp-down period are provided as a preparatory period defined for suppressing the steepness of the fall and rise of the burst signal. By a control unit (not shown), a transmission slot, a ramp down, a guard bit, a ramp up,
And managing the timing of each period of the receiving slot, receiving power ON / OFF signal 510 to the receiving power source 505,
PLL control signal 51 for frequency synthesizer 508
1. Controls the generation of the switch control signal 512 for the transmission / reception changeover switch 503.

The PLL control signal 511 is output in the period (input period) extending from the vicinity of the end of the transmission slot to the ramp-down period. Frequency synthesizer 50
8 starts the operation of generating a local signal by the PLL control signal 511, and continues the guard bit period (transition period:
In the unlocked state), the frequency of the local signal is switched between the transmission slot and the reception slot. And
During the next ramp-up period, the frequency is locked, and a local signal with a stable frequency is received by the receiving unit 504 and the transmitting unit 5.
07 to one (the receiving unit 504 in the illustrated example).

The reception power ON / OFF signal 510 changes from the L level to the H level during the period from the SS (start symbol) signal to the CRC (error checking bit) signal of the transmission slot.
Switch to level. The reception unit 504 turns on the reception power ON /
When the OFF signal 510 becomes H level, power is supplied from the reception power supply 505 to start the reception operation.

The switch control signal 512 is at the L level during the period of the transmission slot, and the transmission / reception changeover switch 5
Reference numeral 03 connects the transmission / reception input / output terminal 502 and the transmission unit 507. Therefore, the transmission unit 507 transmits the transmission IF signal 5 of the intermediate frequency (IF) during the transmission slot period.
17 is frequency-converted by the local signal 513 to generate and output a radio frequency (RF) transmission signal 518, which is sent to the antenna 501 through the transmission / reception changeover switch 503 and the transmission / reception input / output terminal 502.

The leading edge detection timing of the RSSI signal 516 for carrier monitoring is set during the ramp-up period before the reception slot. For this reason,
The switch control signal 512 is a guard bit, which is a period from after ramp down to before ramp up,
It rises from L level to H level. In the example of FIG. 8, it is shown that the switch control signal 512 becomes the H level after the guard bit period starts, and the transmission / reception changeover switch 503 switches to the connection between the transmission / reception input / output terminal 502 and the reception unit 504. There is. At this time, the receiving unit 504 is in the state of starting the receiving operation before the switching of the transmission / reception changeover switch 503.

Received signal 51 received by antenna 501
Reference numeral 4 denotes a transmission / reception input / output terminal 502 and a transmission / reception changeover switch 503.
And is input to the receiving unit 504 through. In the reception unit 504, the reception signal 514 is converted into the reception IF signal 515 of the intermediate frequency by the local signal 213 and is sent to the level detection circuit 506 and the like.

Reception level detection circuit 506 outputs RSSI signal 516 in accordance with the signal level of reception IF signal 515. At the above leading edge detection timing, RSSI
When the signal level of the signal 516 is higher than the threshold value for determining the presence / absence of a carrier, it is determined that there is a carrier in the corresponding slot, and when the signal level is low, it is determined that there is no carrier in the corresponding slot.

[0016]

However, in the radio circuit of the above-mentioned conventional example, since the receiving section 504 is made operable for reception in the period of the transmission slot before the reception slot, the frequency of the local signal generated by the frequency synthesizer 508 is reduced. A guard bit that switches to the frequency of the local signal in the corresponding slot (transition period: unlocked state)
During the period of, the receiving unit 50 in which the interference signal has started to operate
When input to 4, the interfering signal may be converted into the IF frequency band of the received IF signal by the local signal during the transition period and may be detected by the level detection circuit 506.

When the signal level of the interfering signal is high,
As shown in FIG. 8, the signal level of the RSSI signal increases. In such a case, at the leading edge detection timing of the RSSI signal, the signal level of the RSSI signal becomes a level higher than the threshold value for determining the presence / absence of a carrier, which causes a problem that normal carrier monitoring cannot be performed.

Further, when the reception power ON / OFF signal is switched during the period of the transmission slot to start the reception operation of the reception unit 504, the frequency fluctuation of the local signal occurs due to the load fluctuation and power fluctuation of the reception unit 504, and the transmission is performed. There is a problem that the modulation accuracy characteristic, which is the performance, is deteriorated.

Also, a PLL control signal (DATA) for setting the frequency of the local signal during the transmission slot is used.
Signal, CLOCK signal, etc.) frequency synthesizer 50
Since it is input to the PLL circuit 522 of No. 8, there is a problem that the frequency variation of the local signal occurs due to the load variation and the power source variation of the PLL circuit 522, and the modulation accuracy characteristic that is the transmission performance deteriorates.

The present invention has been made in view of the above circumstances, and in a radio circuit using an ultrahigh-speed frequency synthesizer, a radio circuit capable of performing a normal carrier monitoring operation without being affected by an interfering signal. The purpose is to provide.

It is another object of the present invention to provide a radio circuit using an ultrahigh-speed frequency synthesizer, which can prevent deterioration of transmission performance.

[0022]

SUMMARY OF THE INVENTION A radio circuit of the present invention comprises, firstly, a frequency synthesizer for generating a local signal having a frequency corresponding to each slot of a time-divided communication signal, and a receiving operation for the communication signal. And a receiving unit
When switching the frequency of the local signal between slots, control for starting the receiving operation of the receiving unit when the frequency of the local signal generated by the frequency synthesizer is sufficiently converged to the corresponding frequency of the next slot And a section.

In the above configuration, for example, when the frequency of the local signal is switched between the transmission slot and the reception slot, a ramp-up among the ramp-down, guard bit and ramp-up provided between the transmission slot and the reception slot. The state of the local signal generated by the frequency synthesizer, such as the period of, is sufficiently converged to the corresponding frequency of the next slot (reception slot) (lock state)
By starting the reception operation of the receiving unit during the period, the local frequency is stabilized because the receiving unit is not operating even if an interfering signal is input to the receiving unit during the transition period of the local frequency. Even without being converted to the IF frequency band and output, normal carrier monitoring is possible.

Secondly, the radio circuit of the present invention includes a frequency synthesizer for generating a local signal having a frequency corresponding to each slot of the time-divided communication signal, and a receiver for performing a receiving operation for the communication signal. A changeover switch unit for connecting the receiving unit and the antenna side by switching,
When switching the frequency of the local signal between slots, when the frequency of the local signal generated by the frequency synthesizer is sufficiently converged to the corresponding frequency of the next slot, the changeover switch unit causes the receiving unit and the And a control unit for connecting to the antenna.

In the above configuration, for example, when the frequency of the local signal is switched between the transmission slot and the reception slot, a ramp-up among the ramp-down, guard bit and ramp-up provided between the transmission slot and the reception slot. The state of the local signal generated by the frequency synthesizer, such as the period of, is sufficiently converged to the corresponding frequency of the next slot (reception slot) (lock state)
During this period, by switching the signal path in the changeover switch section and connecting the receiving section and the antenna, even if an interfering signal is input during the transition period of the local frequency, the local frequency remains in the receiving section. Since it is not input and processed until it becomes stable, normal carrier monitoring is possible without being converted to the IF frequency band and output.

Thirdly, the wireless circuit of the present invention comprises a frequency synthesizer for generating a local signal having a frequency corresponding to each slot of the time-divided communication signal, and a receiver for performing a receiving operation for the communication signal. When the frequency of the local signal is switched between a transmission section that performs a transmission operation related to the communication signal and the slot, the reception operation of the reception section is started before or after a transmission slot in which the transmission section operates. And a control unit for performing the same.

In the above configuration, for example, when the frequency of the local signal is switched between the transmission slot and the reception slot, a guard bit among ramp down, guard bit, and ramp up provided between the transmission slot and the reception slot. By starting the receiving operation of the receiving unit outside the transmission slot period, such as during the ramp-up period or ramp-up period, fluctuations in the local frequency caused by load fluctuations and power supply fluctuations in the receiving unit that occur when the receiving unit starts operating are Will occur outside the period, and deterioration of the transmission performance will be prevented.

Fourthly, the radio circuit of the present invention comprises a frequency synthesizer for generating a local signal having a frequency corresponding to each slot of the time-divided communication signal, and a receiver for performing a receiving operation for the communication signal. When a frequency of the local signal is switched between slots and a transmitter that performs a transmission operation related to the communication signal, a PLL control signal that controls the frequency synthesizer is input before a transmission slot in which the transmitter operates. And a control unit which is performed in a later period.

In the above configuration, for example, when the frequency of the local signal is switched between the transmission slot and the reception slot, the ramp down, guard bit, or ramp up of the ramp down provided between the transmission slot and the reception slot. PLL outside the transmission slot period, such as
By inputting the control signal to the frequency synthesizer,
The fluctuation of the local frequency caused by the fluctuation of the load and the fluctuation of the power supply of the PLL circuit which occurs when the PLL control signal is input,
This occurs outside the period of the transmission slot, and deterioration of transmission performance is prevented.

Fifthly, the radio circuit of the present invention comprises a frequency synthesizer for generating a local signal having a frequency corresponding to each slot of the time-divided communication signal, and a receiver for performing a receiving operation for the communication signal. A transmitting unit that performs a transmitting operation related to the communication signal, a changeover switch unit that switches and connects the receiving unit and the antenna side, and the frequency when the frequency of the local signal is switched between a transmitting slot and a receiving slot. When the frequency of the local signal generated by the synthesizer is sufficiently converged to the corresponding frequency of the next slot, the receiving operation of the receiving section is started, and the receiving section and the antenna are switched by the changeover switch section. Connect and start the receiving operation of the receiver before or after the transmission slot in which the transmitter operates. It comprises a control unit for the period, the.

In the above configuration, the frequency of the local signal generated by the frequency synthesizer, such as the ramp-down period of the ramp-down, guard bit, and ramp-up provided between the transmission slot and the reception slot, is the next slot (reception slot). ) In the period in which the frequency is sufficiently converged to the corresponding frequency (locked state), the receiving operation of the receiving section is started and the receiving section and the antenna are connected by the changeover switch section, so that they are affected by the interference signal. Instead, normal carrier monitoring operation becomes possible.
Also, by starting the receiving operation of the receiving unit outside the transmission slot period, such as the guard bit or ramp-up period, fluctuations in the local frequency caused by load fluctuations and power supply fluctuations at the start of the operation of the receiving unit are Since it occurs outside the period, deterioration of transmission performance is prevented.

The radio circuit of the present invention, sixthly, a frequency synthesizer for generating a local signal having a frequency corresponding to each slot of the time-divided communication signal, and a receiver for performing a receiving operation for the communication signal. A transmitting unit that performs a transmitting operation related to the communication signal, a changeover switch unit that switches and connects the receiving unit and the antenna side, and the frequency when the frequency of the local signal is switched between a transmitting slot and a receiving slot. When the frequency of the local signal generated by the synthesizer is sufficiently converged to the corresponding frequency of the next slot, the receiving operation of the receiving section is started, and the receiving section and the antenna are switched by the changeover switch section. The transmitter operates by inputting a PLL control signal for connecting and controlling the frequency synthesizer. And and a control unit for performing the period before or after the transmission slot.

In the above configuration, the frequency of the local signal generated by the frequency synthesizer such as the ramp-down period of the ramp-down, guard bit, and ramp-up provided between the transmission slot and the reception slot is the next slot (reception slot). ) In the period in which the frequency is sufficiently converged to the corresponding frequency (locked state), the receiving operation of the receiving section is started and the receiving section and the antenna are connected by the changeover switch section, so that they are affected by the interference signal. Instead, normal carrier monitoring operation becomes possible.
Further, by inputting the PLL control signal to the frequency synthesizer outside the transmission slot period, such as a ramp-down period, fluctuations in the local frequency caused by load fluctuations and power supply fluctuations in the PLL circuit at the time of inputting the PLL control signal are Since it occurs outside the period of, the deterioration of the transmission performance is prevented.

[0034]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a block diagram showing the configuration of a radio circuit according to an embodiment of the present invention, and FIG. 2 is a time chart for explaining the operation of the radio circuit according to the first embodiment of the present invention.

The radio circuit of this embodiment is provided with an antenna 101.
, A transmission / reception input / output terminal 102, a transmission / reception changeover switch 103, a reception unit 104, a reception power source 105, a level detection circuit 106, a transmission unit 107, and an ultra-high-speed frequency synthesizer 108 that is a local unit, The control unit 109 controls each unit.

The reception power supply 105 is ON / OFF for the reception power supply.
When the signal 210 is at a high level (hereinafter referred to as “H level”), the ON operation is performed to supply power to the receiving unit 104. When the reception power ON / OFF signal 210 is at a low level (hereinafter referred to as “L level”), the OFF operation is performed and the power supply to the reception unit 104 is stopped. As a result, the reception unit 104 performs the intermittent reception operation, and the reception IF signal 215 obtained by frequency-converting the radio frequency (RF) to the intermediate frequency (IF) is detected by the level detection circuit 106 and a demodulation circuit, a decoding circuit, etc. in the subsequent stage (not shown). Output to.

The frequency synthesizer 108 includes a VCO 12
1 and a PLL circuit 122. The frequency synthesizer 108 generates a local signal 213 to be supplied to the receiving unit 104 and the transmitting unit 107 according to the PLL control signal 211, and switches the frequency within a guard bit period between the transmission slot and the reception slot. It is like this.

The transmitting section 107 includes an encoding circuit (not shown),
An intermediate frequency (IF) transmission IF signal 217 generated by a modulation circuit or the like is frequency-converted, amplified, and the like, and a radio frequency (RF) transmission IF signal 217 is output.

Transmission / reception changeover switch 1 which is a changeover switch section
03 connects the receiving unit 104 and the transmission / reception input / output terminal 102 when the switch control signal 212 is at H level, for example, and transmits the reception signal 214 received by the antenna 101 to the receiving unit 104. The level detection circuit 106 generates a reception level detection signal (hereinafter referred to as “RSSI signal”) 216 for carrier monitoring from the reception IF signal 215 output from the reception unit 104 and outputs it to the control unit 109 and the like.

The transmission / reception change-over switch 103 connects the transmission unit 107 and the transmission / reception input / output terminal 102 when the switch control signal 212 is, for example, L level, and the transmission unit 10 is connected.
7, the transmission signal 218 generated and output according to the transmission IF signal 217 is transmitted to the antenna 101.

Next, the operation of the radio circuit according to the first embodiment will be described with reference to FIG. The control unit 109 manages the timing of each period of the transmission slot, the ramp down, the guard bit, the ramp up, and the reception slot shown in FIG. 2, the reception power ON / OFF signal 210 for the reception power supply 105, and the PLL for the frequency synthesizer 108. It controls the generation of the control signal 211 and the switch control signal 212 for the transmission / reception changeover switch 103, respectively. Here, the ramp-down and ramp-up periods before and after the guard bit are defined in order to suppress the steepness of the fall and rise of the burst signal.

The control unit 109 generates the PLL control signal 211 at a timing (input period) extending from the vicinity of the end of the transmission slot to the ramp-down period. The frequency synthesizer 108 starts the operation of generating the local signal of the local frequency set by the PLL control signal 211, and in the following guard bit period (transition period: unlocked state), the local signal in the transmission slot and the reception slot. Switch the frequency of. Then, in the next ramp-up period, the frequency is locked, and a local signal having a stable frequency is output to one of the receiving unit 104 and the transmitting unit 107 (the receiving unit 104 in the illustrated example).

Further, the control unit 109 controls the reception power ON / O.
The FF signal 210 is set to the L level from the period of the transmission slot (SS (start symbol) signal to the CRC (error check bit) signal) to the period of the guard bit, and when the next ramp-up period starts, the L level is changed to the H level. Switch to. That is, during the ramp-up period in which the frequency of the local signal 213 is sufficiently converged (locked) to the corresponding frequency in the relevant slot (here, the receiving slot which is the next slot), the reception power ON / OFF signal 2
Set 10 to H level. As a result, the reception unit 104 receives power from the reception power supply 105 and starts operating.

The control unit 109 sets the switch control signal 212 to the L level during the transmission slot period, and the transmission / reception changeover switch 103 connects the transmission / reception input / output terminal 102 and the transmission unit 107. Therefore, in the transmission section 107, during this transmission slot period, the transmission IF signal 217 of the intermediate frequency (IF) is frequency-converted by the local signal 213 to generate and output the transmission signal 218 of the radio frequency (RF), and the transmission / reception changeover switch. 10
3. It is transmitted to the antenna 101 through the transmission / reception input / output terminal 102.

Then, as shown in FIG. 2, the leading edge detection timing of the RSSI signal 216 for carrier monitoring is
It is set during the ramp-up period before the receive slot. Therefore, the control unit 109 changes the switch control signal 212 from the L level to the H level in the guard bit which is a period after the ramp down and before the ramp up. For example, the switch control signal 212 is switched from the L level to the H level when the guard bit period starts. As a result, when the guard bit period starts, the transmission / reception changeover switch 103 is switched to the connection between the transmission / reception input / output terminal 102 and the reception unit 104. At this point, the receiving unit 104 is in the receiving operation stopped state.

After that, when the ramp-up period starts and the receiving unit 104 starts operating, the reception signal 214 received by the antenna 101 is input to the receiving unit 104 through the transmission / reception input / output terminal 102 and the transmission / reception changeover switch 103. To be done. In the receiving unit 104, the received signal 214 is converted into the received IF signal 21 of the intermediate frequency (IF) by the local signal 213.
5 and outputs to the level detection circuit 106.

The level detection circuit 106 receives the received IF signal 2
The RSSI signal 216 is generated according to the signal level of 15 and output to the control unit 109. When the signal level of the RSSI signal 216 is higher than the threshold value for determining the presence / absence of a carrier at the leading edge detection timing, the control unit 109 determines that there is a carrier in the corresponding slot, and if the signal level is low, , It is determined that there is no carrier in the corresponding slot.

As described above, in the radio circuit according to the first embodiment, when the transmission slot is shifted to the reception slot, the guard bit is in a state (lock state) in which the frequency of the local signal is sufficiently converged to the corresponding frequency for each slot. During the later ramp-up period (before the reception slot), the operation of the reception unit is started. Therefore, even if an interfering signal is input to the receiving unit during the transition period of the local frequency, the receiving unit does not operate and is not converted to the IF frequency band and output until the local frequency stabilizes. , Normal carrier monitoring can be performed at the leading edge detection timing in ramp-up.

[Second Embodiment] FIG. 3 is a time chart for explaining the operation of the radio circuit according to the second embodiment of the present invention. The second embodiment is an example in which the operation of the control unit 109 in the above-described first embodiment is changed. Since the device configuration is the same as that of the first embodiment shown in FIG. 1, the configuration description is omitted here, and only the operation will be described based on FIG.

The control unit 109, as in the first embodiment, has a P
The LL control signal 211 is generated at a timing (input period) extending from the vicinity of the end of the transmission slot to the ramp-down period. The frequency synthesizer 108 starts the operation of generating the local signal of the local frequency set by the PLL control signal 211, and switches the frequency of the local signal between the transmission slot and the reception slot during the subsequent guard bit period. Then, in the next ramp-up period, the frequency is locked, and a local signal having a stable frequency is output to one of the receiving unit 104 and the transmitting unit 107 (the receiving unit 104 in the illustrated example).

Further, the control unit 109 turns the reception power ON / O.
The FF signal 210 is switched from the L level to the H level during the period of the transmission slot (SS (start symbol) signal to CRC (error check bit) signal). As a result, the reception unit 104 receives power from the reception power supply 105 and starts operating during the transmission slot period.

Further, the control unit 109 sets the switch control signal 212 to the L level during the period of the transmission slot, and the transmission / reception changeover switch 103 connects the transmission / reception input / output terminal 102 and the transmission unit 107. Therefore, in the transmission unit 107, the transmission IF signal 217 is frequency-converted by the local signal 213 to generate and output the transmission signal 218 during the period of the transmission slot, and the antenna 101 is passed through the transmission / reception changeover switch 103 and the transmission / reception input / output terminal 102. Sent to.

Since the leading edge detection timing of the RSSI signal 216 for carrier monitoring is set during the ramp-up period before the reception slot, the control section 109 starts the ramp-up period. The switch control signal 212 is changed from L level to H level. That is, when the ramp-up period in which the frequency of the local signal 213 is sufficiently converged (locked) to the corresponding frequency in the relevant slot (here, the receiving slot) is started, the switch control signal 212 is changed from the L level to the low level. Switch to H level. As a result, the transmission / reception change-over switch 103 is switched to the connection between the transmission / reception input / output terminal 102 and the reception unit 104.

When the receiving section 104 is connected to the transmission / reception input / output terminal 102 by the transmission / reception changeover switch 103, the antenna 1
The reception signal 214 received at 01 is the transmission / reception input / output terminal 1
02, and input to the receiving unit 104 through the transmission / reception changeover switch 103. In the receiving unit 104, the received signal 214 is converted into the received IF signal 215 by the local signal 213,
Output to the level detection circuit 106.

The level detection circuit 106 receives the received IF signal 2
The RSSI signal 216 is generated according to the signal level of 15 and output to the control unit 109. When the signal level of the RSSI signal 216 is higher than the threshold value for determining the presence / absence of a carrier at the leading edge detection timing, the control unit 109 determines that there is a carrier in the corresponding slot, and if the signal level is low, , It is determined that there is no carrier in the corresponding slot.

As described above, in the radio circuit according to the second embodiment, the receiving section is in the reception operable state during the transmission slot, but the signal path is switched by the transmission / reception changeover switch when the frequency of the local signal is changed by each slot. Is performed during the ramp-up period in which the frequency is sufficiently converged (locked state). Therefore, even if an interfering signal is input during the transition period of the local frequency, it is not input and processed until the local frequency stabilizes in the receiving unit, so that it is not converted to the IF frequency band and output. Normal carrier monitoring can be performed at the leading edge detection timing during ramp-up.

[Third Embodiment] FIG. 4 is a time chart for explaining the operation of the wireless circuit according to the third embodiment of the present invention. The third embodiment is an example in which the operation of the control unit 109 in the above-described first embodiment is changed. Since the device configuration is the same as that of the first embodiment shown in FIG. 1, the configuration description is omitted here, and only the operation will be described based on FIG.

As in the first embodiment, the control unit 109 controls the P
The LL control signal 211 is generated at a timing (input period) extending from the vicinity of the end of the transmission slot to the ramp-down period. The frequency synthesizer 108 starts the operation of generating the local signal of the local frequency set by the PLL control signal 211, and in the following guard bit period (transition period: unlocked state), the local signal in the transmission slot and the reception slot. Switch the frequency of. Then, in the next ramp-up period, the frequency lock state is set, and the local signal having a stable frequency is received by the receiving unit 10.
4 and one of the transmission units 107 (the reception unit 104 in the illustrated example).

Although not shown in the third embodiment, the switch control signal 212 is at the L level during the transmission slot period, and the transmission / reception changeover switch 103 causes the transmission / reception input / output terminal 102 and the transmission unit 107 to operate. Connected. Therefore, in the transmission unit 107, the frequency of the transmission IF signal 217 is converted by the local signal 213 to generate and output the transmission signal 218 during the period of the transmission slot, and the transmission / reception changeover switch 103 and the transmission / reception input / output terminal 1 are output.
It is sent to the antenna 101 through 02. Then, the switch control signal 212 switches from the L level to the H level when the guard bit period starts, for example, during the guard bit period after the ramp down and before the ramp up, and the transmission / reception changeover switch 103. Switches to the connection between the transmission / reception input / output terminal 102 and the reception unit 104. At this point in time, the receiving unit 104 is in the receiving operation stopped state.

Further, the control unit 109 turns the reception power ON / O.
The FF signal 210 is sent to the RSS after the period of the transmission slot.
During the period before the leading edge detection timing of the I signal 216, the L level is changed to the H level. In the example of FIG. 4, the L level is switched to the H level near the end of the guard bit period. That is, the frequency of the local signal 213 is sufficiently converged (locked) to the corresponding frequency in the slot (here, the receiving slot), and before the leading edge detection timing of the RSSI signal 216 in the ramp-up period, The reception unit 104 receives power from the reception power supply 105 and starts operation.

As a result, the reception signal 214 received by the antenna 101 is input to the reception unit 104 through the transmission / reception input / output terminal 102 and the transmission / reception changeover switch 103, and the reception unit 104 transmits the reception signal 214 by the local signal 213. The received IF signal 215 is converted into the level detection circuit 10
Output to 6. The level detection circuit 106 generates the RSSI signal 216 according to the signal level of the reception IF signal 215 and outputs it to the control unit 109.

As described above, in the radio circuit according to the third embodiment, the operation of the receiving section is started during the period after the transmission slot period and before the leading edge detection timing of the RSSI signal, and outside the transmission slot period. I am trying to do it. Therefore, the fluctuation of the local frequency caused by the load fluctuation and the power fluctuation of the receiving unit when the receiving unit starts the operation occurs outside the period of the transmission slot, and the deterioration of the transmission performance such as the modulation accuracy characteristic can be prevented. .

[Fourth Embodiment] FIG. 5 is a time chart for explaining the operation of the radio circuit according to the fourth embodiment of the present invention. The fourth embodiment is an example in which the operation of the control unit 109 in the above-described first embodiment is changed. Since the device configuration is the same as that of the first embodiment shown in FIG. 1, the configuration description is omitted here, and only the operation will be described based on FIG.

Control section 109 generates PLL control signal 211 during the ramp-down period (input period) from after the transmission slot period to before the guard bit period. The frequency synthesizer 108 starts the operation of generating the local signal of the local frequency set by the PLL control signal 211, and switches the frequency of the local signal between the transmission slot and the reception slot during the subsequent guard bit period. Then, in the next ramp-up period, the frequency is locked, and a local signal having a stable frequency is output to one of the receiving unit 104 and the transmitting unit 107 (the receiving unit 104 in the illustrated example).

Although not shown in the third embodiment, the switch control signal 212 is at the L level during the transmission slot period, and the transmission / reception changeover switch 103 causes the transmission / reception input / output terminal 102 and the transmission unit 107 to operate. Connected. Therefore, in the transmission unit 107, the frequency of the transmission IF signal 217 is converted by the local signal 213 to generate and output the transmission signal 218 during the period of the transmission slot, and the transmission / reception changeover switch 103 and the transmission / reception input / output terminal 1 are output.
It is sent to the antenna 101 through 02.

The switch control signal 212 is, for example, the RSS signal after ramp down and ramp up.
In the period before the leading edge detection timing of the I signal 216, when the ramp-up period starts, the L level is switched to the H level, and the transmission / reception changeover switch 103
Switches to the connection between the transmission / reception input / output terminal 102 and the reception unit 104. As a result, the reception signal 214 received by the antenna 101 is input to the reception unit 104 through the transmission / reception input / output terminal 102 and the transmission / reception changeover switch 103, and the reception unit 10
In 4, the received signal 214 is converted into the received IF signal 215 by the local signal 213 and output to the level detection circuit 106. The level detection circuit 106 receives the received IF signal 21.
The RSSI signal 216 is generated according to the signal level of 5 and output to the control unit 109.

As described above, in the radio circuit according to the fourth embodiment, the PLL control signal is input to the PLL circuit of the frequency synthesizer outside the transmission slot period.
The fluctuation of the local frequency caused by the fluctuation of the load and the fluctuation of the power supply of the PLL circuit which occurs when the PLL control signal is input,
This occurs outside the period of the transmission slot, and deterioration of transmission performance such as modulation accuracy characteristics can be prevented.

[Fifth Embodiment] FIG. 6 is a time chart for explaining the operation of a radio circuit according to the fifth embodiment of the present invention. The fifth embodiment is an example in which the operation of the control unit 109 in the first embodiment described above is changed, and the first to fourth embodiments are described.
It is a combination of the features of the embodiments. Since the device configuration is the same as that of the first embodiment shown in FIG. 1, the configuration description is omitted here, and only the operation will be described based on FIG.

As in the fourth embodiment, the control unit 109 controls the P
The LL control signal 211 is generated in the ramp-down period (input period) from after the transmission slot period to before the guard bit period. The frequency synthesizer 108
In the period of the following guard bit (transition period: unlocked state), the operation of generating the local signal of the local frequency set by the PLL control signal 211 is started,
The frequency of the local signal is switched between the transmission slot and the reception slot. Then, in the next ramp-up period, the frequency is locked, and a local signal having a stable frequency is output to one of the receiving unit 104 and the transmitting unit 107 (the receiving unit 104 in the illustrated example).

Further, the control unit 109 turns the reception power ON / O.
The FF signal 210 is set to the L level from the period of the transmission slot (SS (start symbol) signal to the CRC (error check bit) signal) to the period of the guard bit, and when the next ramp-up period starts, the L level is changed to the H level. Switch to. That is, the reception power ON / OFF signal 210 is set to the H level during the ramp-up period in which the frequency of the local signal 213 is sufficiently converged (locked) to the corresponding frequency in the slot (here, the reception slot). . As a result, the reception unit 104 receives power from the reception power supply 105 and starts operating.

The control unit 109 sets the switch control signal 212 to the L level during the transmission slot period, and the transmission / reception changeover switch 103 connects the transmission / reception input / output terminal 102 and the transmission unit 107. Therefore, in the transmission section 107, during this transmission slot period, the transmission IF signal 217 of the intermediate frequency (IF) is frequency-converted by the local signal 213 to generate and output the transmission signal 218 of the radio frequency (RF), and the transmission / reception changeover switch. 10
3. It is transmitted to the antenna 101 through the transmission / reception input / output terminal 102.

Since the leading edge detection timing of the RSSI signal 216 for carrier monitoring is set during the ramp-up period before the reception slot, the control unit 109 starts the ramp-up period. The switch control signal 212 is changed from L level to H level. That is, when the ramp-up period in which the frequency of the local signal 213 is sufficiently converged (locked) to the corresponding frequency in the relevant slot (here, the receiving slot) is started, the switch control signal 212 is changed from the L level to the low level. Switch to H level. As a result, the transmission / reception change-over switch 103 is switched to the connection between the transmission / reception input / output terminal 102 and the reception unit 104.

The ramp-up period starts, and the receiving unit 10
4 starts operating, and the receiving unit 104 is connected to the transmission / reception input / output terminal 102 by the transmission / reception changeover switch 103,
The reception signal 214 received by the antenna 101 is input to the reception unit 104 through the transmission / reception input / output terminal 102 and the transmission / reception changeover switch 103. In the receiving unit 104, the received signal 2
14 is received by the local signal 213. IF signal 215
To the level detection circuit 106.

The level detection circuit 106 receives the received IF signal 2
The RSSI signal 216 is generated according to the signal level of 15 and output to the control unit 109. When the signal level of the RSSI signal 216 is higher than the threshold value for determining the presence / absence of a carrier at the leading edge detection timing, the control unit 109 determines that there is a carrier in the corresponding slot, and if the signal level is low, , It is determined that there is no carrier in the corresponding slot.

As described above, in the radio circuit according to the fifth embodiment, when the transmission slot is shifted to the reception slot, the guard bit becomes a state (lock state) in which the frequency of the local signal is sufficiently converged to the corresponding frequency for each slot. During the later ramp-up period (before the reception slot), the operation of the reception unit is started. Therefore, even if an interfering signal is input during the transition period of the local frequency, it is not converted to the IF frequency band and then output because the receiving unit is not operating, and the leading edge detection timing in ramp-up is used. Normal carrier monitoring can be performed.

Also, during the ramp-up period in which the frequency of the local signal is sufficiently converged to the corresponding frequency for each slot (locked state), the signal path is switched by the transmission / reception changeover switch, and the antenna side and the reception side. I am trying to connect with. Therefore, even if an interfering signal is input during the transition period of the local frequency, it is not input and processed until the local frequency stabilizes in the receiving unit, so that it is not converted to the IF frequency band and output. Normal carrier monitoring can be performed at the leading edge detection timing during ramp-up.

Furthermore, by performing the timing of starting the operation of the receiving unit outside the transmission slot period, the fluctuation of the local frequency caused by the load fluctuation and the power supply fluctuation of the receiving unit which occurs when the receiving unit starts the operation, This occurs outside the period of, and deterioration of transmission performance such as modulation accuracy characteristics can be prevented.

In addition, since the PLL control signal is inputted to the PLL circuit of the frequency synthesizer outside the transmission slot period, the fluctuation of the local frequency caused by the fluctuation of the load of the PLL circuit and the fluctuation of the power supply which occur at the time of inputting the PLL control signal is prevented. , Which occurs outside the period of the transmission slot, and deterioration of transmission performance such as modulation accuracy characteristics can be prevented.

[0079]

As described above, according to the present invention, it is possible to perform a normal carrier monitoring operation without being affected by an interfering signal in a radio circuit using an ultrahigh-speed frequency synthesizer. Is obtained. In addition, in a radio circuit using an ultrahigh-speed frequency synthesizer, it is possible to prevent deterioration of transmission performance.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a wireless circuit according to an embodiment of the present invention.

FIG. 2 is a time chart explaining the operation of the wireless circuit according to the first embodiment of the present invention.

FIG. 3 is a time chart explaining the operation of the wireless circuit according to the second embodiment of the present invention.

FIG. 4 is a time chart explaining the operation of the wireless circuit according to the third embodiment of the present invention.

FIG. 5 is a time chart explaining the operation of the wireless circuit according to the fourth embodiment of the present invention.

FIG. 6 is a time chart explaining the operation of the wireless circuit according to the fifth embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration example of a conventional wireless circuit.

FIG. 8 is a time chart explaining the operation of a conventional wireless circuit.

[Explanation of symbols]

101 antenna 102 Transmission / reception input / output terminal 103 Transfer switch 104 receiver 105 Receive power supply 106 Level detection circuit 107 transmitter 108 Frequency Synthesizer 109 control unit 121 VCO 122 PLL circuit 210 Reception power ON / OFF signal 211 PLL control signal 212 Switch control signal 213 Local signal 216 RSSI signal

Continued front page    F-term (reference) 5K011 BA03 DA07 DA21 FA01 GA02                       JA01 KA05                 5K020 DD01 GG01 KK08

Claims (6)

[Claims] 1. A frequency synthesizer that generates a local signal having a frequency corresponding to each slot of a time-division communication signal, a receiver that performs a receiving operation relating to the communication signal, and a frequency of the local signal is switched between slots. In this case, the control unit starts the receiving operation of the receiving unit when the frequency of the local signal generated by the frequency synthesizer is sufficiently converged to the corresponding frequency of the next slot, and Wireless circuit to do. 2. A frequency synthesizer that generates a local signal having a frequency corresponding to each slot of a time-division communication signal, a receiver that performs a reception operation related to the communication signal, and the connection between the receiver and the antenna side. And a changeover switch unit for switching the frequency of the local signal between slots when the frequency of the local signal generated by the frequency synthesizer is sufficiently converged to the corresponding frequency of the next slot. And a control unit that connects the receiving unit and the antenna to each other. 3. A frequency synthesizer that generates a local signal having a frequency corresponding to each slot of a time-division communication signal, a receiver that performs a reception operation related to the communication signal, and a transmitter that performs a transmission operation related to the communication signal. And a control unit that, when switching the frequency of the local signal between slots, starts a receiving operation of the receiving unit during a period before or after a transmission slot in which the transmitting unit operates. Characteristic wireless circuit. 4. A frequency synthesizer that generates a local signal having a frequency corresponding to each slot of a time-division communication signal, a receiver that performs a reception operation related to the communication signal, and a transmitter that performs a transmission operation related to the communication signal. And a control unit for inputting a PLL control signal for controlling the frequency synthesizer in a period before or after a transmission slot in which the transmission unit operates, when the frequency of the local signal is switched between slots. A wireless circuit characterized by that. 5. A frequency synthesizer that generates a local signal having a frequency corresponding to each slot of a time-division communication signal, a receiver that performs a reception operation related to the communication signal, and a transmitter that performs a transmission operation related to the communication signal. A changeover switch unit for switching and connecting the receiving unit and the antenna side, and when switching the frequency of the local signal between a transmission slot and a receiving slot, the frequency of the local signal generated by the frequency synthesizer is the next slot. When the frequency is sufficiently converged to the corresponding frequency, the receiving operation of the receiving section is started, the receiving section and the antenna are connected by the changeover switch section, and the receiving operation of the receiving section A control unit for performing start during a period before or after a transmission slot in which the transmitting unit operates, Radio circuit characterized by and. 6. A frequency synthesizer that generates a local signal having a frequency corresponding to each slot of a time-division communication signal, a receiver that performs a reception operation related to the communication signal, and a transmitter that performs a transmission operation related to the communication signal. A changeover switch unit for switching and connecting the receiving unit and the antenna side, and when switching the frequency of the local signal between a transmission slot and a receiving slot, the frequency of the local signal generated by the frequency synthesizer is the next slot. The PLL for starting the receiving operation of the receiving section when the frequency is sufficiently converged to the corresponding frequency, connecting the receiving section and the antenna with the changeover switch section, and controlling the frequency synthesizer. The control signal should be input before or after the transmission slot in which the transmitter operates. Radio circuit, characterized in that it comprises a control unit, a performed.