JP2003051597A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) Abstract: A method for manufacturing a semiconductor device capable of suppressing an increase in reverse leakage current is provided. When forming an active region such as an n-type diffusion layer, a gate electrode, and an emitter electrode on the front side of a wafer, a contact flaw formed on the back side of the wafer is formed at the end of the process. By forming the p-type diffusion layer 3 which is a collector layer, partial omission of the back surface collector layer is prevented, and an increase in reverse leakage current is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor), and more particularly to a method of manufacturing a collector region.

[0002]

2. Description of the Related Art A power semiconductor device such as an IGBT has a back surface impurity diffusion layer such as a collector region, and there is an opportunity to contact both the front and back surfaces of a wafer with a supporting base of a device such as an etching device in a manufacturing process. . When contacting with such a support, contact scratches may occur on the contact surface of the wafer, that is, the impurity diffusion layer. If these scratches penetrate the thin collector layer, the performance of the semiconductor device will deteriorate,
This is a factor that reduces the rate of non-defective products.

FIG. 7 shows a conventional IGBT manufacturing process, and FIGS. 7A to 7C are cross-sectional views of the essential part in the order of processes. The process shown here is a manufacturing process of the back surface impurity layer. The drawings shown below are cross-sectional views of the essential steps of the IGBT cells formed in large numbers on the wafer. First, in the beginning of the process, boron ion implantation 52 is performed on a wafer 51 (n-type silicon substrate), and heat treatment is performed at a high temperature of about 1150 ° C. to form a p-type diffusion layer 5 to be a thin collector region of about 1 μm.
3 (back surface collector layer) is formed (FIG. 9A).

Next, on the surface of the wafer 1, the P-well
P-type diffusion layer 55 to be an n-type diffusion layer 5 to be an emitter layer
4 is formed. In addition, the gate electrode 5 is made of polysilicon.
6 is formed on the gate insulating film 61, the interlayer insulating film 57 is made of boron phosphorous glass, and the emitter electrode 58 is made of aluminum / silicon (FIG. 7B). Next, a collector electrode 59 is formed on the back surface of the wafer 1 to complete the product. In the chipped portion of the p-type diffusion layer 53, which is the back surface collector layer, the collector electrode 59 and the n-type drift layer 60 are shown in FIG.
As shown in the enlarged view of the I portion of (c) (FIG. 8), they come into direct contact ((c) of the same figure).

As described above, the finished product lacking the back surface collector layer has a large reverse leakage current and becomes a defective product.

[0006]

As described above, in the above manufacturing method, the emitter layer 54, the gate electrode 56, and the emitter electrode 58 are formed on the front surface of the wafer 51 after forming the p-type diffusion layer 53 which is the back surface collector layer. As a result of the various steps for forming the above, the back surface of the wafer 1 comes into contact with the support arm 62 such as the transfer arm of the etching apparatus or the holding rod of the asher, and a contact scratch 64 is formed. Due to the contact scratch 64, a part of the p-type diffusion layer 53, which is the back surface collector layer, is chipped off, and at this chipped-off portion, the collector electrode 59 becomes the n-type drift layer 6.
In direct contact with 0, the reverse leakage current increases. This increase in reverse leakage current reduces the yield rate of semiconductor devices.

An object of the present invention is to solve the above problems and provide a method of manufacturing a semiconductor device capable of suppressing an increase in reverse leakage current.

[0008]

In order to achieve the above object, a semiconductor region formed on a surface layer of a first main surface of a semiconductor substrate, and a first main electrode formed on the semiconductor region,
A method of manufacturing a semiconductor device, comprising: a semiconductor diffusion layer of an opposite conductivity type formed on a surface layer of a second main surface of the semiconductor substrate; and a second main electrode formed on the semiconductor diffusion layer, After the step of forming the semiconductor region and the first main electrode on the surface, impurity implantation and 420 are performed on the second main surface.
The manufacturing method includes a step of forming the semiconductor diffusion layer by low temperature annealing at a temperature equal to or lower than 0 ° C., and forming the second main electrode on the semiconductor diffusion layer.

Further, the dose amount of the ion implantation is 1 × 1.
It is preferable that it is 0 ¹⁴ cm ⁻² or more and 1 × 10 ¹⁶ or less. Also, a semiconductor region formed on the surface layer of the first main surface of the semiconductor substrate, a first main electrode formed on the semiconductor region, and a reverse region formed on the surface layer of the second main surface of the semiconductor substrate. A conductive type semiconductor diffusion layer, and a second layer formed on the semiconductor diffusion layer
A method for manufacturing a semiconductor device having a main electrode, comprising:
Before the step of forming the semiconductor region and the first main electrode on the main surface, there is provided a first semiconductor diffusion layer forming step of forming the semiconductor diffusion layer on the surface layer of the second main surface. And a second semiconductor diffusion layer forming step of forming the semiconductor diffusion layer on the surface layer of the second main surface after the step of forming the semiconductor region and the first main electrode.

Further, the second semiconductor diffusion layer forming step includes
The semiconductor diffusion layer may be formed by ion implantation of impurities and low temperature annealing at 420 ° C. or lower. Further, the dose of the ion implantation is preferably 1 × 10 ¹² cm ⁻² or more and 1 × 10 ¹⁶ or less. Thus, the feature of the present invention is that the implantation and activation of the impurity ions for forming the back surface impurity diffusion layer are performed after the front surface electrode made of the aluminum / silicon film, which is the final stage of the manufacturing process. This reduces the number of contacts between the back surface of the wafer and the manufacturing apparatus after forming the back surface impurity diffusion layer, and reduces scratches entering the back surface of the wafer.

Further, the back surface impurity diffusion layer is formed once in the early stage of the manufacturing process, and thereafter, impurity ions are implanted and activated again in the final stage of the manufacturing process for the purpose of compensating for a portion of the back surface impurity diffusion layer which is missing in the manufacturing process. The same effect can be obtained by performing.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a method of manufacturing a semiconductor device according to a first embodiment of the present invention, and FIGS. 1A to 1C are sectional views showing the essential steps in the order of steps. . The drawings shown below are cross-sectional views of the essential steps of the IGBT cells formed in large numbers on the wafer. On the front surface side of the wafer 1 (n-type silicon substrate), an n-type diffusion layer 4 serving as an emitter layer, P-wel
A p-type diffusion layer 5 to be 1 is formed, a gate electrode 6 is formed of polysilicon on the gate insulating film 11, an interlayer insulating film 7 is formed of boron phosphorus glass, and an emitter electrode 8 is formed of aluminum / silicon. (N-type diffusion layer 4, p-type diffusion layer 5
Together with the semiconductor region).

Formation of each of these portions (semiconductor region formation)
Is performed on the front surface side of the wafer 1, and the back surface of the wafer is in contact with a support 12 such as a transfer arm of an etching apparatus or a holding rod of an ashing apparatus. Contact scratches 14 are introduced by the protrusions 13 on the surface 12 (FIG. 8A). Next, at the end of the process, the wafer 1
On the back side of the dose amount 1 × 10 ¹⁴ cm ^-2 to 1 × 10 ¹⁶ c
Boron ion implantation 2 is performed in the range of m ⁻² , and low-temperature annealing at 420 ° C. or lower is performed to form the p-type diffusion layer 3 (back surface collector layer).

If high temperature annealing is performed here, there arises a problem that aluminum and silicon are softened or melted. Therefore, annealing is performed at a low temperature of 420 ° C. or lower (FIG. 2B). Next, the collector electrode 9 is formed on the back surface of the wafer 1 (FIG. 7C). Thus, after the contact scratches 14 are introduced, the p-type diffusion layer 3 serving as the back surface collector layer is formed by the ion implantation 2 and the heat treatment, so that the contact scratches 14 can be almost covered with the p-type diffusion layer 3. As a result, a part of the p-type diffusion layer 3 which is the back surface collector layer is less likely to be chipped. Since the p-type diffusion layer 3 is less likely to be partly chipped, the collector electrode 9 and the n-type drift layer 1 are reduced.
The number of points where 0 directly contacts decreases, and the increase of reverse leakage current is suppressed. Therefore, the non-defective rate is significantly increased.

However, when the portion A having the contact scratch 14 in FIG. 1B is enlarged, it is shown in FIG.
As shown in FIG. 5A, if the cross-sectional shape of the contact scratch 14 is concave like the portion E, the boron 21 is not injected at this portion, and after the heat treatment, after the heat treatment, as shown in FIG. A part of the p-type diffusion layer 3 is not formed, such as the F part, and the collector electrode 9 and the n-type drift layer 10 form the F part.
It comes to contact at a portion (a portion where the p-type diffusion layer 3 is missing). Therefore, the reverse leakage current is increased, and the non-defective rate is reduced. Of course, the non-defective rate is greatly improved compared to the conventional method. Next, a measure for solving this will be described.

FIG. 2 shows a method of manufacturing a semiconductor device according to a second embodiment of the present invention, and FIGS. 2A to 2D are sectional views showing the essential steps in the order of steps. The drawings shown below are cross-sectional views of the essential steps of the IGBT cells formed in large numbers on the wafer. First, in the beginning of the process, boron ion implantation 2a with a dose of 3.80 × 10 ¹² cm ⁻² is performed on the back surface of the wafer 1, and then heat treatment is performed at a high temperature of about 1150 ° C. for 1 μm.
A p-type diffusion layer 3a to be a collector region of about m is formed. The impurity ions implanted are fully activated by annealing at a high temperature (FIG. 7A).

Next, on the front surface side of the wafer 1 (n-type silicon substrate), the n-type diffusion layer 4 serving as an emitter layer and the P-wel.
A p-type diffusion layer 5 to be 1 is formed, a gate electrode 6 is formed of polysilicon on the gate insulating film 11, an interlayer insulating film 7 is formed of boron phosphorus glass, and an emitter electrode 8 is formed of aluminum / silicon. . The formation of each of these parts is performed on the front surface side of the wafer 1, and the back surface of the wafer is in contact with the support base 12 such as the transfer arm of the etching apparatus or the holding rod of the ashing apparatus, and the back surface of the wafer 1 is formed. This support 1
Contact scratches 14 are introduced by the protrusions 13 at 2. However, when enlarging the portion C where the introduction scratch 14 is present, the result shown in FIG.
As shown in (a), the concave portion (G portion) of the contact scratch 14 is p
It is covered with the mold diffusion layer 3a ((b) of the same figure).

Next, at the end of the process, a second boron ion is applied to the back surface of the wafer from a dose of 1 × 10 ¹² cm ^-2 to 1
The p-type diffusion layer 3b is formed by implanting in the range of × 10 ¹⁶ cm ^-2 and performing low temperature annealing at 420 ° C. or lower. FIG. 6 is an enlarged view of a portion (D portion) having the contact scratch 14 in FIG. 2C.
As shown in (b), the portion where the p-type diffusion layer 3a is missing at the tip portion (H portion) of the contact scratch 14 is covered with the p-type diffusion layer 3b. Therefore, even if the contact scratch 14 has a concave cross-sectional shape, the p-type diffusion layer 3 serving as the back surface collector layer does not have a missing portion (FIG. 7C).

Next, the collector electrode 9 is formed on the back surface of the wafer (FIG. 3 (d)). By thus forming the p-type diffusion layer 3a for the first time and the p-type diffusion layer 3b for the second time, a part of the p-type diffusion layer 3 serving as the back surface collector layer is eliminated. Therefore, the increase of the reverse leakage current is further suppressed and the non-defective rate is further increased, as compared with the first embodiment.

Incidentally, in FIG. 2A, the p-type diffusion layer 5 may be formed before the p-type diffusion layer 3a is formed. Figure 3
FIG. 6 is a diagram showing a distribution (ratio) of reverse leakage current values of the semiconductor device of the present invention. This semiconductor device is the IGBT (invention product) shown in the second embodiment, and the second dose amount is 1 × 1.
It is 0 ¹⁴ cm ^-2 . For comparison, the reverse leakage current of the IGBT manufactured by the conventional method (conventional product) is also shown.

The invention product and the conventional product each have 6 lots (9
(6 pieces) of data. Applied reverse voltage is 6V
Then, the reverse leakage current product having a current of 200 mA or less was determined to be a good product. In the figure, non-defective products are shown surrounded by a thick frame. In the conventional product, the non-defective rate was 10% (the defective rate was 90%), but in the present invention, it was improved to 90% (the defective rate was 10%). As described above, it can be seen that the present invention is a very effective method for suppressing an increase in reverse leakage current.

FIG. 4 is a diagram showing the relationship between the dose amount and the reverse leakage current. In this figure, boron ion implantation and activation for forming the back surface collector layer (p-type diffusion layer 3) of the IGBT are performed only once at the end of the manufacturing process (corresponding to the first embodiment), and the beginning. (Dose amount: 3.80 x
10 ¹² cm ^-2 ) and the final stage are performed twice in total (corresponding to the second embodiment). The dose amount on the horizontal axis is the dose amount in the final stage.

The number of samples is 96 under each condition, and the measured value is the distribution of reverse leakage current, which is a non-defective standard.
The ratio of 0 mA or less (non-defective product rate) is shown as a value of 90%. It can be seen from FIG. 4 that the reverse leakage current is smaller when the ion implantation is performed twice (corresponding to the second embodiment) than when only once (corresponding to the first embodiment).

As described above, when the contact scratch 14 has a concave cross-sectional shape, the p-type diffusion layer 3a is formed so as to cover the concave portion in the first ion implantation. This is because the p-type diffusion layer 3 that is the collector layer is less likely to be missing. However, as the dose amount is increased, even in the case of the first embodiment in which the ion implantation is carried out only once, the diffusion depth of the p-type diffusion layer 3 becomes deeper and the influence of the recesses becomes smaller, so that the second embodiment. The difference in the reverse leakage current from the case of 1 becomes small.

From FIG. 4, the value of the reverse leakage current is 200 m.
If it is judged to be non-defective if it is A or less, 1 × 10 ¹⁴ cm ^-2
With the above dose amount, boron ion implantation is performed only once in the final stage (invention product of the first embodiment) to sufficiently suppress the increase of the reverse leakage current and to make the non-defective product rate 90% or more. be able to. Further, in the case where the boron ion implantation is performed twice in the early stage and the final stage (second embodiment), if the dose amount of the ion implantation in the final stage is 1 × 10 ¹² cm ⁻² or more, the reverse leakage current is sufficiently increased. And the non-defective rate can be set to 90% or more.

However, if the dose exceeds 1 × 10 ¹⁶ cm ^-2 , it becomes difficult to recover the defects introduced by ion implantation. Further, the carrier concentration does not change due to the low temperature annealing. Therefore, the dose amount is preferably 1 × 10 ¹⁶ or less. From this, in the case of the first embodiment, the dose amount of boron at the time of ion implantation in the final stage is 1 × 10 ¹⁴ cm ⁻² or more and 1 × 10 ¹⁶ cm ⁻² or less, and in the second embodiment. In this case, 1 × 10 ¹² cm ⁻² or more and 1 × 10 ¹⁶ cm ⁻² or less can sufficiently suppress an increase in reverse leakage current.

[0027]

According to the present invention, the semiconductor region on the back surface (back surface collector layer) is formed at the end of the process, and it is possible to prevent the semiconductor region on the back surface from being partly cut off. It is possible to suppress the increase and increase the yield rate. Also, at the beginning of the process, the semiconductor area on the back side of the first time,
By additionally forming the backside semiconductor region for the second time in the final stage, it is possible to more reliably prevent the backside semiconductor region from being partially lost, and thus to further suppress an increase in reverse leakage current and reduce the yield rate. Can be higher.

The dose amount at the time of ion implantation for forming the semiconductor region on the back surface is set to a predetermined value (1 × 10 ¹² cm ^{−2
Alternatively} , by setting the value in the range of 1 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² ), it is possible to suppress the increase of the reverse leakage current and increase the non-defective rate.

[Brief description of drawings]

FIG. 1 is a method of manufacturing a semiconductor device according to a first embodiment of the present invention, in which (a) to (c) are process cross-sectional views of essential parts shown in the order of processes.

FIGS. 2A to 2D are sectional views of a main part showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention, in which FIGS.

FIG. 3 is a diagram showing a distribution (ratio) of reverse leakage current values of the semiconductor device of the present invention.

FIG. 4 is a diagram showing a relationship between a dose amount and a reverse leakage current.

5 is an enlarged view of FIG. 1, in which (a) is an enlarged view of part A in FIG. 1 (b), and (b) is an enlarged view of part B in FIG. 1 (c).

FIG. 6 is an enlarged view of FIG. 2, in which (a) is an enlarged view of portion C in FIG. 2 (b), and (b) is an enlarged view of portion D in FIG. 2 (c).

FIG. 7 is a cross-sectional view of a main part of a conventional IGBT manufacturing process, in which (a) to (c) are shown in the order of processes.

FIG. 8 is an enlarged view of part I of FIG. 7 (c).

[Explanation of symbols]

1 wafer 2 ion implantation 2a 1st ion implantation 2b 2nd ion implantation 3 p-type diffusion layer (back surface collector layer) 3a p-type diffusion layer (first time) 3b p-type diffusion layer (second time) 4 n-type diffusion layer (emitter layer) 5 p-type diffusion layer (p-Well layer) 6 Gate electrode 7 Interlayer insulation film 8 Emitter electrode 9 Collector electrode 10 n-type drift layer 11 Gate insulating film 12 Support 13 Protrusion 14 Contact scratches

Claims (5)

[Claims] 1. A semiconductor region formed on a surface layer of a first main surface of a semiconductor substrate, a first main electrode formed on the semiconductor region, and a surface layer of a second main surface of the semiconductor substrate. And a second main electrode formed on the semiconductor diffusion layer, wherein the semiconductor region and the first main electrode are formed on a first main surface. And the ion implantation of impurities is performed on the second main surface.
A method of manufacturing a semiconductor device, comprising the step of forming the semiconductor diffusion layer by low temperature annealing at 0 ° C. or lower, and forming the second main electrode thereon. 2. A dose amount of the ion implantation is 1 × 10 ¹⁴ c
The method for manufacturing a semiconductor device according to claim 1, wherein the value is not less than m ^{−2 and not} more than 1 × 10 ¹⁶ . 3. A semiconductor region formed on a surface layer of a first main surface of a semiconductor substrate, a first main electrode formed on the semiconductor region, and a surface layer of a second main surface of the semiconductor substrate. And a second main electrode formed on the semiconductor diffusion layer, wherein the semiconductor region and the first main electrode are formed on a first main surface. Prior to the step of forming, a first semiconductor diffusion layer forming step of forming the semiconductor diffusion layer on the surface layer of the second main surface, and a step of forming the semiconductor region and the first main electrode on the first main surface After the above, there is a second semiconductor diffusion layer forming step of forming the semiconductor diffusion layer on the surface layer of the second main surface, which is a method for manufacturing a semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 3, wherein in the second semiconductor diffusion layer forming step, the semiconductor diffusion layer is formed by ion implantation of impurities and low temperature annealing at 420 ° C. or lower. 5. A dose amount of the ion implantation is 1 × 10 ¹² c
^{5. The} method for manufacturing a semiconductor device according to claim 4, wherein m ⁻² or more and 1 × 10 ¹⁶ or less.