JP2003043124A - Testing device and calibration method - Google Patents

Abstract

(57) Abstract: A test apparatus and a calibration method for a test apparatus such as an electronic device that can efficiently perform calibration of a driver, a comparator, and the like. A method of calibrating a test apparatus including a first input / output unit having a plurality of first drivers and a second input / output unit having a plurality of driver comparators, the method comprising: Calibrating a predetermined reference comparator among the comparators, calibrating each of the plurality of first drivers based on the reference comparator, and determining a predetermined reference driver among the plurality of first drivers And calibrating each of the second drivers corresponding to the plurality of comparators.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a calibration method for calibrating a test apparatus and a test apparatus for testing an electronic device. In particular, it relates to a calibration method for a driver of a test device and a comparator.

[0002]

2. Description of the Related Art Conventionally, a test apparatus for testing an electronic device includes a plurality of drivers corresponding to a plurality of pins of the electronic device, a plurality of comparators, and the like. In order to accurately test the electronic device, it is necessary to calibrate the plurality of drivers and the plurality of comparators.

In the conventional calibration method, a calibration reference comparator is prepared separately from the device test comparator, and a plurality of test drivers are sequentially connected to the reference comparator to calibrate the test driver. I was going. Further, the reference voltage is supplied to each of the plurality of comparators to calibrate the comparators.

[0004]

As described above, in the conventional calibration method, since a plurality of drivers and the reference comparator are connected and the plurality of drivers are calibrated sequentially based on the reference comparator, This was a time-consuming method for calibration. Further, it is necessary to supply the reference voltage to each of the plurality of comparators, which is troublesome.

Therefore, an object of the present invention is to provide a test apparatus and a calibration method that can solve the above problems. This object is achieved by a combination of features described in independent claims of the invention. The dependent claims define further advantageous specific examples of the present invention.

[0006]

In order to solve the above problems, in the first aspect of the present invention, a test apparatus for testing an electronic device, which generates a test pattern for testing the electronic device. A pattern generating section, a waveform shaping section for shaping the test pattern, a first input / output section having a plurality of first drivers for supplying the test pattern shaped by the waveform shaping section to the electronic device, and a test shaped by the waveform shaping section A plurality of second drivers that supply a pattern to the electronic device, and a plurality of comparators that are provided corresponding to the plurality of second drivers and that receive output signals that the electronic device outputs based on the test pattern; A second input / output unit having a driver / comparator, and a first input / output unit and a second input / output unit. Provided between the first relay A and the first relay B, which select whether or not to electrically connect, and the first relay A and the first relay B, and among a plurality of comparators, a predetermined reference comparator, The second input / output unit includes a second relay that selects whether to supply a predetermined reference voltage, and a determination unit that determines whether the electronic device is good or bad based on the output signal received by the comparator. Is provided between the first driver and the first relay A corresponding to each of the plurality of first drivers to determine whether or not the plurality of first drivers and the first relay A are electrically connected. A plurality of third relays to be selected are provided, and the second input / output unit is provided between the plurality of driver comparators and the first relay B so as to correspond to each of the plurality of driver comparators. Comparator and first Providing a test apparatus characterized by a fourth relay to select whether to electrically connect the relay B.

The first input / output unit is provided between the first relay A and the plurality of third relays, and whether or not each electrically connects at least one third relay and the first relay A. The second input / output unit is provided between the first relay B and the plurality of fourth relays, and each has at least one fourth relay and a first relay.
It may further include a plurality of sixth relays for selecting whether or not to electrically connect with the relay B.

Each third relay is connected in series with the fifth relay, and each third relay is provided in parallel with another third relay, and each fifth relay is the first relay. A is connected in series, and each fifth relay is provided in parallel with another fifth relay, each fourth relay is connected in series with a sixth relay, and each sixth relay is It may be connected in series with the first relay B, and each sixth relay may be provided in parallel with another sixth relay.

Further, the delay amounts of signal transmission between the first relay A and each of the plurality of first drivers are substantially the same, and between the first relay B and each of the plurality of driver comparators. It is preferable that the delay amounts of signal transmission are substantially the same. Further, the lengths of the paths electrically connecting the first relay A and each of the plurality of first drivers are substantially the same, and the first relay B and each of the plurality of driver comparators are electrically connected. The lengths of the connecting paths may be substantially the same.

Further, it is preferable that the delay amount of signal transmission between the first relay A and the first driver and the delay amount of signal transmission between the first relay B and the driver comparator are substantially the same. . Also, the first relay A and the first
The length of the path electrically connecting the driver and the length of the path electrically connecting the first relay B and the driver comparator may be substantially the same. Further, the first input / output unit may further include a plurality of comparators corresponding to the plurality of first drivers, respectively.

In the second aspect of the present invention, a first input / output unit having a plurality of first drivers for supplying a test pattern for testing the electronic device to the electronic device and a test pattern for supplying the test pattern to the electronic device. A second driver comparator including a plurality of second drivers and a plurality of comparators provided corresponding to the plurality of second drivers and receiving output signals output by the electronic device based on a test pattern. A method of calibrating a test apparatus including an input / output unit, comprising: a step of calibrating a reference comparator by applying a reference voltage to a predetermined reference comparator among a plurality of comparators; One driver is connected in sequence, and one of the plurality of first drivers is connected based on the reference comparator. A step of calibrating this, a step of sequentially connecting a predetermined reference driver and a plurality of comparators among the plurality of first drivers, and calibrating each of the plurality of comparators based on the reference driver; Calibrating each of the second drivers corresponding to the plurality of comparators based on the plurality of calibrated comparators.

The second aspect of the present invention may further include the step of calibrating the signal output timing of the first driver and the signal output timing of the second driver.

The above summary of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments are not intended to limit the invention according to the scope of claims and are described in the embodiments. Not all of the combinations of features described above are essential to the solution of the invention.

FIG. 1 shows an example of the configuration of a test apparatus 100 according to the present invention. The test apparatus 100 includes the pattern generator 1
0, waveform shaping section 20, signal input / output section 50, and determination section 4
Equipped with 0. The pattern generation unit 10 uses the electronic device 30.
Generate a test pattern for testing. It is preferable that the pattern generation unit 10 generate various test patterns according to test items for testing the electronic device 30.
For example, when the electronic device 30 is a semiconductor memory,
The pattern generation unit 10 generates a test pattern for testing whether or not normal writing is possible for all addresses of the semiconductor memory.

The waveform shaping section 20 shapes the test pattern generated by the pattern generating section 10 and supplies the shaped test pattern to the signal input / output section 50. The waveform shaping section 20 may supply the shaped test pattern to the signal input / output section 50 at a desired timing. For example, the waveform shaping unit 20 has a variable delay circuit that delays and outputs the test pattern by a desired time.

The signal input / output unit 50 exchanges signals with the electronic device 30. For example, the signal input / output unit 50 receives the test pattern from the waveform shaping unit 20 and supplies the test pattern to a desired pin of the electronic device 30. The signal input / output unit 50 may include a plurality of drivers provided corresponding to a plurality of pins of the electronic device 30 and supplying a test pattern to the corresponding pins. When the electronic device 30 is, for example, a semiconductor memory, the signal input / output unit 50 may receive, as a test pattern, data to be written to a predetermined address of the semiconductor memory and supply the data to a predetermined pin of the semiconductor memory. .

The signal input / output unit 50 also receives an output signal output from the electronic device 30 based on the test pattern. The signal input / output unit 50 may include a plurality of comparators that are provided corresponding to the plurality of pins of the electronic device 30 and that receive output signals from the corresponding pins. Further, the signal input / output unit 50 may include a unit that reads data stored at a predetermined address of the semiconductor memory when the electronic device 30 is a semiconductor memory. The signal input / output unit 50 supplies the output signal or data received from the electronic device 30 to the determination unit 40.

The determination section 40 is based on the output signal or data received from the signal input / output section 50 and the electronic device 30.
The quality of is judged. The determination unit 40 compares the output signal to be output by the electronic device 30 based on the test pattern or the expected value signal of the data to be stored by the electronic device 30 with the output signal or data received from the signal input / output unit 50. The quality of the electronic device 30 may be determined. In this case, the pattern generating section 10 may generate the expected value signal based on the generated test pattern and supply the expected value signal to the signal input / output section 50.

FIG. 2 shows an example of the configuration of the signal input / output unit 50. The signal input / output unit 50 includes a first input / output unit 70, a second input / output unit 80, a first relay A64, a first relay B66, a second relay 68, and a seventh relay 86. The first input / output unit 70 includes a plurality of first drivers 52 that supply the test pattern shaped by the waveform shaping unit 20 (see FIG. 1) to the electronic device 30. The second input / output unit 80 also has a plurality of driver comparators 54. Each of the driver comparators 54 supplies the test pattern shaped by the waveform shaping section 20 to the electronic device 30.
6 and a comparator 58 that is provided corresponding to the second driver 56 and that receives an output signal that the electronic device 30 outputs based on the test pattern. First relay A64
The first relay B66 electrically connects the first input / output unit 70 and the second input / output unit 80.

The plurality of first drivers 52 respectively receive the test pattern and supply the test pattern to the electronic device 30 via the relay 72. That is, when testing the electronic device 30, the relay 72 corresponding to the pin to be tested of the electronic device 30 is brought into the conductive state, and the test pattern is supplied to the pin of the electronic device 30. In addition, when calibrating the first driver 52, the relay 72
Is opened.

Similarly, the plurality of second drivers 54 respectively receive the test pattern and supply the test pattern to the electronic device 30 via the relay 72. Further, the plurality of comparators 58 receive the output signal or data from the electronic device 30 via the relay 72, and supply the received output signal or data to the determination unit 40. In the present example, the comparator 58 is provided with a determination voltage, compares the determination voltage with the signal level of the output signal or the data, and supplies the comparison result to the determination unit 40.

The first input / output unit 70 includes a plurality of fifth relays 8
2 and a plurality of third relays 60. The plurality of fifth relays 82 includes the first relay A64 and the plurality of third relays 60.
And each of which selects whether or not to electrically connect at least one third relay 60 and the first relay A64. Each fifth relay is connected in series with the first relay A, and each fifth relay is provided in parallel with another fifth relay. That is, one end of each of the fifth relays 82 is connected to one or more third relays 60, and the other end thereof is connected to the first relay A64.

The plurality of third relays 60 are provided between the plurality of first drivers 52 and the fifth relay 82 so as to correspond to the plurality of first drivers 52, respectively. Whether to electrically connect to the fifth relay 82 is selected. Further, each third relay 60 is connected in series with the fifth relay 82, and each third relay 60 is provided in parallel with another third relay 60.
As shown in FIG. 2, the plurality of third relays 60 may be connected to the second relay 64 via another relay.

As shown in FIG. 2, the first input / output section 70 may further include another relay between the fifth relay 82 and the plurality of third relays 60. For example, the first input / output unit 7
0, one end is connected to the path connecting the predetermined third relay 60 and another third relay 60, and the other end is further connected to the fifth relay 82 and a relay connected via another relay. You can do it. In this case, the other end of the relay may be directly connected to the fifth relay 82. For example, as shown in FIG. 2, the first input / output unit 70 is provided between the lower two relays and the upper relay 1 to electrically connect the lower two relays and the upper relay 1 to each other. It may further have a plurality of relays for selecting whether or not. Since the first input / output unit 70 has the relay configuration as shown in FIG. 2, it is possible to select the electrical connection between the first relay A64 and the arbitrary first driver 52.

The second input / output unit 80 includes a plurality of fourth relays 6
2 and a plurality of sixth relays 84. The plurality of sixth relays 84 includes the first relay B66 and the plurality of fourth relays 62.
And each of which selects whether or not to electrically connect at least one fourth relay 62 and the first relay B66. Each 6th relay 84 is connected in series with the 1st relay B66, and each 6th relay 84 is provided in parallel with the other 6th relay 84. That is, one end of each of the sixth relays 84 is connected to one or a plurality of fourth relays 62 and the other end thereof is connected to the first relay B66.
Connected to.

The plurality of fourth relays 62 are provided between the plurality of driver comparators 54 and the first relay B66 in correspondence with the plurality of driver comparators 54, respectively. B
It is selected whether or not to be electrically connected to 66. Further, each fourth relay 62 is connected in series with the sixth relay 84, and each fourth relay 62 is provided in parallel with the other fourth relay 62. As shown in FIG. 2, the plurality of fourth relays 62 may be connected to the first relay B66 via another relay.

As shown in FIG. 2, the second input / output section 80 may further include another relay between the sixth relay 84 and the plurality of fourth relays 62. For example, the second input / output unit 8
0, one end is connected to a path connecting the predetermined fourth relay 62 and another fourth relay 62, and the other end is further connected to a sixth relay 84 and a relay connected via another relay. You can do it. In this case, the other end of the relay may be directly connected to the sixth relay 84. For example, as shown in FIG. 2, the second input / output unit 80 is provided between two lower relays and one upper relay so as to electrically connect the two lower relays and one upper relay. It may further have a plurality of relays for selecting whether or not. Since the second input / output unit 80 has the relay configuration as shown in FIG. 2, the first relay B66 and the optional driver comparator 5
The electrical connection with 4 can be selected.

According to the signal input / output unit 50 described in this example, by setting a predetermined relay in a conductive state, a predetermined first driver 52 of the first input / output unit 70 and a second input / output unit 80 are provided. It can be electrically connected to a predetermined driver comparator 54.

Further, in this example, the first relay A64
It is preferable that the delay amounts of signal transmission between the first and second drivers 52 are substantially the same. Similarly, it is preferable that the delay amounts of signal transmission between the first relay B66 and each of the plurality of driver comparators 54 are substantially the same. In addition, a delay amount of signal transmission between the first relay A64 and the first driver 52,
The delay amount of signal transmission between the first relay B66 and the driver comparator 54 is preferably substantially the same.

For example, the first relay A64 and a plurality of first relays A64
The lengths of the paths electrically connecting each of the drivers 52 may be substantially the same. Similarly, the first relay B66
And the length of the path electrically connecting each of the plurality of driver comparators 54 may be substantially the same. Further, the length of the path electrically connecting the first relay A64 and the first driver 52 and the length of the path electrically connecting the first relay B66 and the driver comparator 54 are
It may be substantially the same. Further, in the present example, the first input / output unit 70 has the plurality of first drivers 52, but in another example, the first input / output unit 70 corresponds to each of the plurality of first drivers 52. It may further include a plurality of comparators. That is, the first input / output unit 70 may have the same or similar configuration as the second input / output unit 80.

The second relay 68 is provided between the first relay A 64 and the first relay B 66, and whether or not to supply a predetermined reference voltage to a predetermined reference comparator among the plurality of comparators 58. Select. The second relay 68 has one end connected to a path connecting the first relay A64 and the first relay B66, and receives the reference voltage from the other end. For example, a reference voltage generator that generates the reference voltage is connected to the other end of the second relay 68. Further, the seventh relay 86 is the signal input / output unit 50 in this example.
And a signal input / output unit of another test apparatus may be connected. For example, the seventh relay 86 is provided with the signal input / output unit 50 in this example via the calibration board 150 described later.
And a signal input / output unit of another test apparatus may be connected. Further, the first relay A64 and the first relay B66 may connect the signal input / output unit 50 in the present example and the signal input / output unit of another test apparatus.

With the relay configuration of the signal input / output unit 50 described above, calibration in the signal input / output unit 50 of the test apparatus 100 can be easily performed. Less than,
A method of calibrating the signal input / output unit 50 will be described.

FIG. 3 shows a flow chart of an example of a calibration method of the signal input / output unit 50. First, in the reference comparator calibration stage, among the plurality of comparators 58 (see FIG. 2), the predetermined reference comparator is the second relay 68, the first relay B66, the sixth relay 84, the sixth relay 84, and the sixth relay 84. A reference voltage is applied through a relay provided between the fourth relay 62 and the fourth relay 62 to calibrate the reference comparator (S100). For example, the reference comparator is calibrated so that the reference voltage is correctly measured. In S100, the plurality of fourth relays 62 shown in FIG. 2 other than the fourth relay 62 corresponding to the reference comparator are preferably in the open state. Further, it is preferable that the first relay A64 is also in the open state.

Next, in the first driver calibration stage, the reference comparator and the plurality of first drivers 52 (see FIG. 2) are sequentially connected, and each of the plurality of first drivers 52 is calibrated based on the reference comparator. (S102). For example, each first driver 52 is calibrated so that the first driver 52 outputs the reference voltage correctly. In this case, the first driver 52 may be provided with a test pattern for calibration.

In S102, among the relays shown in FIG. 2, the fourth relay 62, the sixth relay 84, the first relay B66, and the fourth relay 62 corresponding to the reference comparator.
Corresponding to the first driver 52 to be calibrated by putting the relay between the sixth relay 84 and the sixth relay 84 into a conductive state,
The third relay 60, the fifth relay 82, the first relay A64,
Also, the relays between the third relay 60 and the fifth relay 82 are brought into conduction, and the respective first drivers 52 are sequentially calibrated. By sequentially connecting the first drivers 52 to be calibrated and opening the relays corresponding to the other first drivers 52, the first drivers can be accurately calibrated.

Next, in the comparator calibration stage, among the plurality of first drivers 52, a predetermined reference driver and a plurality of comparators 58 are sequentially connected, and a plurality of comparators 5 based on the reference driver are connected.
Each of 8 is calibrated (S104).
For example, each of the plurality of comparators 58 is calibrated so that the reference voltage output by the reference driver is correctly measured.

In S104, as in S102, the third relay 60, the fifth relay 82, which correspond to the reference driver,
First relay A64, and third relay 60 and fifth relay 8
The fourth relay 6 corresponding to the comparator 58 to be calibrated by bringing the relay between the second relay 6 and the relay into a conductive state.
The second and sixth relays 84, the first relay B66, and the relays between the fourth relay 62 and the sixth relay 84 are brought into conduction, and the respective comparators 58 are calibrated sequentially. Comparator 5 to be calibrated
By sequentially connecting 8 and opening the relays corresponding to the other comparators 58, the comparators can be calibrated accurately.

Next, in the second driver calibration stage, a plurality of calibrated comparators 5
The second corresponding to the plurality of comparators 58 based on 8
Each of the drivers 56 (see FIG. 2) is calibrated (S106). For example, each second driver 56 is calibrated so that each second driver 56 outputs the reference voltage correctly. In this case, it is preferable that the plurality of fourth relays 62 be in an open state.

Further, a step of calibrating the signal output timing of the first driver 52 and the signal output timing of the second driver 56 may be further provided. At this stage, the timing at which the test patterns supplied by the respective first drivers 52 to the electronic device 30 reach the electronic device 30 and the test patterns supplied by the respective second drivers 56 to the electronic device 30 are the electronic devices 30.
The calibration is performed so that the timing of reaching the time is almost the same. A delay amount of signal transmission in the path from each first driver 52 to the electronic device 30, each second driver 56 to the electronic device 30
Of the signal transmission delay in the path up to and the delay amount of the signal transmission in the path from each first driver 52 to each second driver 56, and based on the measured values, the waveform shaping unit 20 (FIG. 1) adjusts the timing of supplying the test pattern to each driver. As described above, when the waveform shaping unit 20 has the variable delay circuit, the delay amount in the variable delay circuit may be adjusted based on the measured value.

The delay amounts of signal transmission on the paths from the first drivers 52 to the electronic devices 30 are substantially the same, and the delay amounts of signal transmission on the paths from the second drivers 56 to the electronic device 30 are also the same. It is preferable that they are substantially the same. If the reference first driver 52 and the second driver 56 are calibrated by making the delay amounts substantially the same, the signal output timing of each driver can be adjusted.

According to the calibration method described in this example, all drivers and comparators can be calibrated without externally connecting the reference comparator, and efficient calibration can be performed. Further, according to the test apparatus 100,
Since it is possible to select whether or not the first input / output unit 70 and the second input / output unit 80 are electrically connected by the first relay A64 and the first relay B66, a predetermined comparator among the plurality of comparators 58 is a reference comparator. As a result, all drivers can be calibrated without using an external reference comparator. In this example, the first
Although the case where the input / output unit 70 has the plurality of first drivers 52 has been described, the case where the second input / output unit 70 has the plurality of driver comparators 54 can be easily performed by the same method as the above-described calibration method. Obviously, it can be calibrated.

FIG. 4 shows a calibration board 150 for calibrating a plurality of test devices 100.
An example of the configuration will be shown. Calibration board 150
Has a relay configuration similar to that of the signal input / output unit 50 described with reference to FIG. Calibration board 150
Has a plurality of eighth relays 74, a plurality of ninth relays 76, and a tenth relay 78. 7th relay 74 and 8th
Each of the relays 76 is electrically connected to the first relay 68 (see FIG. 2) of the signal input / output unit 50 of the test apparatus 100. The tenth relay 78 is one of the test devices 100.
Select whether to supply the reference voltage to the reference comparator of. The tenth relay 78 is connected to a reference voltage generator that generates the reference voltage, as shown in FIG. Each test apparatus 100 may be provided on one substrate. The test apparatus 100 has the same or similar function and configuration as the test apparatus 100 described with reference to FIG. The test apparatus 100 may include a CPU and / or a power supply that controls the operation of each test apparatus 100. Each C
The PU may receive instructions from a host computer (not shown) and control the operation of the test apparatus 100.

The calibration board 150 is shown in FIG.
The respective drivers and comparators of the test apparatus 100 are calibrated by the same method as the calibration method described in relation to. For example, the signal input / output unit 50 connected to the eighth relay 74 has a plurality of first drivers 52 (see FIG. 2), and the signal input / output unit 50 connected to the ninth relay 76 has a plurality of drivers. It may include a comparator 54 (see FIG. 2). An arbitrary test apparatus 1 is configured by the relay configuration of the signal input / output unit 50 and the relay configuration of the calibration board 150 described with reference to FIG.
It is possible to select whether to electrically connect the first driver 00 and 52 of No. 00 and the comparator 58 of the other test apparatus 100, and each driver and comparator can be easily calibrated. When performing the calibration described in this example, the reference voltage generator that generates the reference voltage is connected to the tenth relay 78, so that each test apparatus 100 has the second relay described with reference to FIG. It is not necessary to have 68.

Although the present invention has been described above with reference to the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. Various changes or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

[0046]

As is apparent from the above description, according to the present invention, the test apparatus can be easily calibrated without using an external reference comparator.

[Brief description of drawings]

FIG. 1 shows an example of the configuration of a test apparatus 100 according to the present invention.

FIG. 2 shows an example of the configuration of a signal input / output unit 50.

FIG. 3 shows a flowchart of an example of a calibration method of the signal input / output unit 50.

FIG. 4 shows an example of the configuration of a calibration board 150 for calibrating a plurality of test apparatuses 100.

[Explanation of symbols]

10: pattern generating section, 20: waveform shaping section, 3
0 ... Electronic device, 40 ... Judgment unit, 50 ...
Signal input / output unit, 52 ... First driver, 54 ... Driver comparator, 56 ... Second driver, 58 ...
..Comparator, 60 ... Third relay, 62 ...
4th relay, 64 ... 1st relay A, 66 ... 1st
Relay B, 68 ... second relay, 70 ... first input / output unit, 72 ... relay, 74 ... eighth relay, 76
... 9th relay, 78 ... 10th relay, 80 ...
Second input / output unit, 82 ... Fifth relay, 84 ... Sixth relay, 86 ... Seventh relay, 100 ... Testing device, 150 ... Calibration board

Claims (10)

[Claims] 1. A test apparatus for testing an electronic device, comprising: a pattern generating section for generating a test pattern for testing the electronic device; a waveform shaping section for shaping the test pattern; and a waveform shaping section. A first input / output unit having a plurality of first drivers for supplying the shaped test pattern to the electronic device; a plurality of second drivers for supplying the test pattern shaped by the waveform shaping unit to the electronic device; Second
A second input / output unit having a plurality of driver comparators, which is provided corresponding to each of the drivers and includes a plurality of comparators that receive the output signals output by the electronic device based on the test pattern; A first relay A and a first relay that are provided between an output unit and the second input / output unit and select whether or not to electrically connect the first input / output unit and the second input / output unit. B is provided between the first relay A and the first relay B,
A second relay that selects whether or not to supply a predetermined reference voltage to a predetermined reference comparator among the plurality of comparators, and a quality of the electronic device based on the output signal received by the comparator. A determination section for determining, wherein the first input / output section is provided between the plurality of first drivers and the first relay A in correspondence with each of the plurality of first drivers, A plurality of first drivers and a plurality of third relays for selecting whether or not to electrically connect the first relays A, the second input / output unit includes the plurality of driver comparators; First relay B
And a fourth relay that is provided corresponding to each of the plurality of driver comparators and that selects whether or not to electrically connect the plurality of driver comparators to the first relay B. Test equipment characterized by. 2. The first input / output unit includes the first relay A.
And a plurality of third relays, each of which is at least one of the third relay and the first relay A.
And a plurality of fifth relays for selecting whether or not to be electrically connected, the second input / output unit is provided between the first relay B and the plurality of fourth relays, The test apparatus according to claim 1, further comprising a plurality of sixth relays each selecting whether or not to electrically connect at least one of the fourth relay and the first relay B. . 3. Each of the third relays is connected to the fifth relay.
Relays are connected in series, and each third relay is provided in parallel with another third relay, each fifth relay is connected in series with the first relay A, and each The fifth relay is provided in parallel with another fifth relay, each fourth relay is connected in series with the sixth relay, and each sixth relay is the first relay.
The test apparatus according to claim 2, wherein the sixth relay is connected in series with a relay B, and each of the sixth relays is provided in parallel with another of the sixth relays. 4. The delay amount of signal transmission between the first relay A and each of the plurality of first drivers is
The test apparatus according to claim 3, wherein the delay amounts of signal transmission between the first relay B and each of the plurality of driver comparators are substantially the same, and are substantially the same. 5. The length of a path electrically connecting the first relay A and each of the plurality of first drivers is:
The test device according to claim 4, wherein the paths that are substantially the same and that electrically connect the first relay B and each of the plurality of driver comparators are substantially the same. 6. The delay amount of signal transmission between the first relay A and the first driver and the delay amount of signal transmission between the first relay B and the driver comparator are substantially the same. The test apparatus according to claim 5, wherein the test apparatus is provided. 7. The length of a path electrically connecting the first relay A and the first driver and the length of a path electrically connecting the first relay B and the driver comparator are substantially equal to each other. The test device according to claim 6, wherein the test device is the same. 8. The test apparatus according to claim 1, wherein the first input / output unit further includes a plurality of comparators corresponding to the plurality of first drivers, respectively. 9. A first input / output unit having a plurality of first drivers for supplying a test pattern for testing an electronic device to the electronic device, and a plurality of second drivers for supplying the test pattern to the electronic device. And a plurality of comparators provided corresponding to each of the plurality of second drivers and receiving an output signal output from the electronic device based on the test pattern, the second input / output having a plurality of driver comparators. And a step of calibrating the reference comparator by applying a reference voltage to a predetermined reference comparator among the plurality of comparators, the method comprising: The first driver of the Calibrating each of the first drivers, a predetermined reference driver of the plurality of first drivers, and the plurality of comparators are sequentially connected, and the plurality of comparators are connected based on the reference driver. And a step of calibrating each of the second drivers corresponding to the plurality of comparators based on the plurality of calibrated comparators. . 10. The calibration method according to claim 9, further comprising the step of calibrating the signal output timing of the first driver and the signal output timing of the second driver.