JP2003032301A - Clad device and cell disassembling method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CLAD(cell assembly and disassembly) that is provided with a CBR(constant bit rate) interface with a plurality of ports with respect to an ATM interface of one port and can reduce number of memories. SOLUTION: The CLAD device is provided with a single storage means 16 that stores data of a plurality of ports of a CBR interface and with a conversion means 18 that converts a discontinuous parallel data by each port read in time division from the storage means 16 into parallel data corresponding to each bit stream from each port of the CBR interface. Thus, it is not required to mount CDV(cell delay variation) absorption buffers and bit buffers by the same number of the ports of the CBR interfaces.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CLAD device and a cell disassembling method, and more particularly to an ATM (Asynchronous Tracing).
nsfer Mode: AAL1-, which is a component of IWFs defined to provide the Unsturalctured Service of CES introduced in the forum.
The present invention relates to a CLAD device and a cell disassembling method for realizing a CLAD function.

[0002]

2. Description of the Related Art Conventionally, a CLA having the above cell disassembly function
The D device is, for example, as disclosed in Japanese Patent Laid-Open No. 10-23026, an ATM access interface of a single transmission path (hereinafter, simply referred to as "ATM interface").
And a single-port CBR (Constant Bit Rate) service interface (hereinafter simply referred to as
"CBR interface").

FIG. 9 shows a conventional AAL1-CLAD device (hereinafter simply referred to as "CLAD device" when connecting an ATM access interface of a single transmission line and a CBR service interface of a single port and network dependent synchronization). Is a block diagram showing an example of a circuit to which the ".

As a function realizing circuit of AAL1, an AAL1 processing circuit 2 for processing and measuring cell loss and the like, and a cell for arriving asynchronously are stored in a buffer to store CDV (Cell Delay).
Variation: Cell delay variation), the CDV absorption buffer 4, the timing generator 8 that generates the output timing of the CBR interface, and the non-continuous parallel data read from the CDV absorption buffer 4 as the data of the CBR interface. A bit buffer 6 for converting to a format.

FIG. 10 shows the input / output data format of each block having the configuration described with reference to FIG. 9 and the memory map of the CDV absorption buffer 4. In the ATM interface format, ATM is placed in the first 5 octets of the cell.
A cell header is added and the remaining 48 octets are SAR
-PDU (Segmentation And Reassembly-Protocol Dat
a Unit) area. The first 1 byte of the SAR-PDU is assigned to the SAR-PDU header, and the remaining 47 octets are assigned to the information area. CD
The memory map of the V absorption buffer secures the storage area of the SAR-PDU payload corresponding to the SN values 0 to 7. The output format of the CDV absorption buffer is non-continuous data in byte units in parallel format. On the other hand, the CBR interface format is serial continuous data.

In the CLAD device, since processing is performed for each cell that arrives, it is efficient to allocate the data area of the CDV absorption buffer in cell units and write and read data in parallel. In this case, the data format output from the buffer is parallel signal non-continuous data. On the other hand, since the data format of the CBR interface is continuous data of serial format, it is necessary to provide a parallel / serial conversion function in order to interface between them. This conversion function is generally composed of a bit buffer, and reads the next data when the buffer becomes empty.

The format conversion operation at the time of cell disassembly of this commonly used CLAD device will be described with reference to FIG.

When the ATM cell 1 (signal 1) arrives, the AAL1 processing circuit 2 carries out the processing relating to AAL1, and C
Cell N corresponding to SN value of PDU of DV absorption buffer 4
Write the payload area of the SAR-PDU to the address of o. The timing generator 8 includes a bit buffer 6
The timing at which a vacancy of 1 octet occurs is counted, and when the vacancy occurs, the next address read last time and the read enable (signal 11) are output to the CDV absorption buffer 4, and the bit buffer 6 outputs them. , Write enable (signal 12) is output. Bit buffer 6
Then, the read one octet data (signal 5) is written, and the timing data of CBR_CLK (signal 10) is output bit by bit.

In the above-mentioned conventional method, when the CBR interface is a single port, it is possible to process absorption of CDV and conversion of non-continuous data into continuous data with a single buffer. When the CBR interface is expanded to a multi-port, the output is continuous data, and since it is a plurality of ports, it is necessary to read data of a plurality of addresses from the buffer at the same timing. However, since a single buffer cannot read data at a plurality of addresses at the same time, the same number of buffers as the number of ports is required. As described above, when the conventional method is expanded to multiport, it is necessary to mount the CDV absorption buffer and the bit buffer in the same number as the number of ports, which causes a problem that the number of memories increases.

FIG. 11 shows an example of the configuration when the CBR interface is multiported by the conventional method.

The parallel / serial conversion block 14 is
As many bit buffers 6 as the number of ports are mounted. Also,
The AAL1 processing block 13 includes an AAL1 processing circuit 2 and
It is composed of the output selector 15 and the CDV absorption buffers 4, and the CDV absorption buffers 4 are mounted as many as the number of ports. The AAL1 processing circuit 2 is a single circuit for performing processing on a cell-by-cell basis.

Next, the operation of the CLAD device having the above structure will be described with reference to FIGS. 11 and 12.

The same number of CDV absorption buffers 4 as ports are prepared, and each buffer secures an area corresponding to SN values 0 to 7. For data (signal 18) that has been processed by the AAL1 processing circuit 2, VPI (Virtual Path I)
dentifier) / VCI (Virtual Channel Identifier)
The corresponding port is determined from the value, and the data is output from the output selector 15 to the CDV absorption buffer 4 of the corresponding port.

The CDV absorption buffer 4 determines the cell number from the SN value and writes the payload area of the SAR-PDU at the corresponding address. Timing generator 8
Counts the timing at which an empty space of 1 octet is generated in the bit buffer 6 for each port.
The next address value read last time and the read enable (signal 11) are output to the CDV absorption buffer 4 of the corresponding port, and the write enable (signal 12) is output to the bit buffer 6 of the corresponding port. , 1-octet data (signal 5) is written in the bit buffer 6. The bit buffer 6 is CBR_CLK (signal 1
Data is output bit by bit at the timing of 0). As an example, in the case of supporting a 84-port CBR interface, 84 CDV absorption buffers 4 and 84 bit buffers 6 are required.

[0015]

As described above,
When the conventional CLAD device is configured to have a multi-port CBR interface for a single-port ATM interface, it is necessary to mount CDV absorption buffers and bit buffers in the same number as the number of ports. There was a problem that was increased.

Therefore, the present invention has been made in view of the problems in the above-mentioned conventional CLAD device, and it has a plurality of CBs for one ATM interface.
Even if the R interface is provided, it is not necessary to mount the CDV absorption buffer and the bit buffer in the same number as the number of ports, and the CLAD can reduce the number of memories.
An object is to provide an apparatus and a cell disassembly method.

[0017]

In order to achieve the above object, the invention according to claim 1 is a CLAD device having a CBR interface of a plurality of ports with respect to an ATM interface of a one port, and a plurality of ports of the CBR interface are provided. A single storage means for storing data and the same number of ports as the CBR interface are provided to convert non-continuous parallel data for each port read out from the storage means in a time division manner into continuous data. Second
And storage means of

The invention according to claim 2 is a one-port ATM.
In a CLAD device having a CBR interface with a plurality of ports for the interface, a single storage means for storing data of the plurality of ports of the CBR interface, and non-contiguous for each of the ports read from the storage means in a time division manner Of parallel data of each of the CBR service interfaces is converted into parallel data corresponding to each bit string.

The invention according to claim 3 is a one-port ATM.
A cell disassembling method in a CLAD device having a CBR interface of a plurality of ports with respect to an interface, wherein data of a plurality of ports of the CBR interface is stored in a single storage means, and the stored data is time-divided for each port. Read out, and the second storage means of the same number as the number of ports of the CBR interface are used to convert the data which is discontinuous due to the time division into continuous data which is synchronized with the CBR interface.

The invention according to claim 4 is a one-port ATM.
A cell disassembling method in a CLAD device having a CBR interface of a plurality of ports with respect to an interface, wherein data of a plurality of ports of the CBR interface is stored in a single storage means, and the data is read from the storage means in a time division manner. The non-continuous parallel data for each port is converted into parallel data corresponding to each bit string by each port of the CBR interface, and the parallel data is converted into continuous data synchronized with the CBR interface.

According to the first or third aspect of the invention, the data of a plurality of ports of the CBR interface is stored by a single storage means, and the data for each port is read out in a time division manner. It is possible to reduce the number of storage units required to be the same as the number of interface ports to one.

According to the invention of claim 2 or 4, C
By converting parallel data composed of data of a plurality of ports of the BR interface into parallel data corresponding to each bit string, a single storage means collectively stores ports for the number of parallel ports in the CBR.
Since it can be synchronized with the interface clock, the number of storage means required to synchronize non-contiguous data with the CBR interface clock has conventionally been the same as the number of ports. In the present invention, this storage is required. The number of means can be reduced to the same number as the total number of ports divided by the parallel number of input / output data of each storage means.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a specific example of an embodiment of a CLAD device according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a CLAD device according to the present invention. In the following, the same components as those of the conventional CLAD device shown in FIGS. 9 to 12 are designated by the same reference numerals, and detailed description thereof will be omitted.

The CLAD device according to this embodiment is AAL
As a function realizing circuit of the one processing block 13, there is an AAL1 processing circuit 2 for performing processing such as cell loss processing and measurement, and a CDV absorption buffer 16 for accumulating cells that arrive asynchronously in a buffer and performing CDV absorption processing.

When an ATM cell arrives, the AAL1 processing circuit 2 and the CDV absorption buffer 16 perform processing such as performance measurement and data restoration, and the CDV absorption buffer 1
The process of writing the PDU information field of the ATM cell in 6 is performed. The parallel / serial conversion block 14 has a bit buffer 6 as a function realizing circuit. The bit buffer 6 converts parallel data into serial data and outputs data in synchronization with the CBR interface clock. The bit buffer 6 is arranged for each port. The timing generator 8 is C
Data read control from the DV absorption buffer 16 (signal 1
1), write control of the bit buffer 6 (signal 12) is performed.

FIG. 2 is a block diagram showing the configuration of the bit buffer 6 in this embodiment.

The bit buffer 6 has a two-sided structure and 4
It has a structure of octet (32 bits) x 2 (plane). One side is read side by the 0/1 side switching control circuit,
The other side is selectively controlled to the write side, and the read side and the write side are switched at the timing when the bit buffer on the read side becomes empty.

FIG. 3 is a diagram for explaining the data format in this embodiment.

The format of the ATM interface is
It corresponds to the signal 1 in FIG. The port number is calculated from the header of the ATM cell in this signal 1, and the cell number is calculated from the SN value of the SAR-PDU header. Also, the SAR-PDU payload is a CD
According to the V absorption buffer memory map, it is stored in the area corresponding to the port number and the cell number.

The CDV absorption buffer memory map is shown in FIG.
8 shows a memory map of the CDV absorption buffer 16 in FIG. 1, and secures an area for 8 cells corresponding to the cell number for each port, and secures a capacity for storing 47 octets of SAR-PDU payload in the area for 1 cell. ing.

The format of the CDV absorption buffer output corresponds to the signal 3 in FIG. In the signal 3, the data is divided into data units of 48 octets, and one data unit includes data for 12 ports, each port having 4 octets. The first data unit is composed of data of octets 1 to 4 of ports 1 to 12. The next data unit is composed of data of octets 1 to 4 of 13 to 24 ports, and thereafter, the data unit of the final port has the same structure. When the data unit of the final port is reached, the next data unit returns to ports 1 to 12 and is composed of data of octets 5 to 8. After that, the last port has the same configuration up to 40 to 44 octets. However, since 45 to 47 octets are data of 3 bytes, in this data unit, dummy data is inserted in an area corresponding to 48 octets to form a data unit. When the data unit of 45 to 47 octets of the final port is reached, the data unit of the octets 1 to 4 of the ports 1 to 12 is formed again.

The format of the bit buffer input port 1 corresponds to the input of the bit buffer 6 port 1 in FIG. During the output of the CDV absorption buffer 16, only the data of the port 1 is extracted, and the octets 1 to 4 to 3 are extracted.
The data unit is divided into 2 bits, 40 to 44
It has the same structure up to the octet. However, only 45 to 47 octets are constituted by a 24-bit data unit.
When a data unit of 45 to 47 octets is reached, it becomes a data unit composed of octets 1 to 4 again. The data of the other ports are configured similarly to the port 1.

The format of the CBR interface is
It corresponds to the signal 7 in FIG. This signal 7 is a serial signal for each port. Signal 7 is C
It is continuously output to the transmission line at a timing synchronized with the BR interface clock.

Next, the operation of the CLAD device having the above configuration will be described in detail with reference to FIGS. 1 to 4.

In FIG. 1, when an ATM cell is input from the ATM access interface, the AAL1 processing circuit 2
After performing processing such as performance monitoring and reproduction of abnormal cells, the SAR-P is stored in the CDV absorption buffer 16.
Stores the DU payload. AAL1 processing circuit 2 and C
The data writing to the DV absorption buffer 16 operates based on the cell arrival timing, whereas the data reading from the CDV absorption buffer 16 and the parallel / serial conversion block 14 use the timing generated by the timing generator 8. It works according to the standard.

The timing generator 8 is the CD of FIG.
According to the V absorption buffer format, the enable control and the addressing control are performed so that the data stored in the CDV absorption buffer 16 is read out in units of 4 octets per port for 12 ports. Input control to However, the data of octet 45 to octet 47 is read in units of 3 octets for each port, and the data corresponding to the 48th octet is undefined.

The data (signal 3) read out from the CDV absorption buffer 16 is discontinuous data in units of 8 para × 48 octets, and the port is switched every 4 octets. Therefore, the port outputting the write enable signal is switched every 4 octets (signal 12), and the data is stored in the bit buffer of the corresponding port. However, if the octets 45 to 47 are applicable, no port is selected for the last 1 octet of the 4 octets. In addition, no port is selected for the division between data units.

When the read / input control of all the ports is completed in this way, the read operation is stopped until the free space of the bit buffer 6 becomes free enough to write the next data. When the capacity becomes available, the next 4-octet data reading is performed in the same manner. Note that the free time of the bit buffer 6 for writing the next data is 32 bits of data in the case of 4 octets of data.
The CBR interface has 32 clock times, and in the case of 3-octet data, it has 24 clock times.

In the bit buffer 6, 4 octet data or 3 octet data (signal 3) is inputted according to the write enable control (signal 12), and as shown in FIG. Write the data to the buffer on the side where is selected. When the data input is completed, the data input surface and the output surface are switched, and the data input surface is in a data input standby state. From the data output side, data is always read at the CBR interface clock timing.
The time from the arrival of 4 octets of data to the arrival of the next data is 32 clock hours with the CBR interface clock, and when the data of 3 octets arrives, the time until the next data arrives. Time is 2
It is 4 clock hours. In this way, the next data arrives when the memory on the read side becomes empty,
Since the planes are switched, the capacity of the memory is 32 bits per port × 2 planes.

As an example, in the case of supporting a 84-port CBR interface, 168 32-bit bit buffers (2 sides × 84 ports) and 8 bits ×
One CDV absorption memory of 31584 addresses (47 octets x 8 cells x 84 ports) is required.

Next, the second CLAD device according to the present invention will be described.
Examples will be described with reference to FIGS. 5 to 8.

FIG. 5 is a block diagram of a second embodiment in which a vertical / horizontal conversion circuit is added to the configuration of the first embodiment and a clock transfer memory is used instead of the bit buffer.

The AAL1 processing block 13 is, as a function realizing circuit, an AAL1 processing circuit 2 for performing processing such as cell loss processing and measurement, and a CDV absorption buffer 16 for accumulating cells arriving asynchronously in a buffer and performing CDV absorption processing. Have and. When an ATM cell arrives, the AAL1 processing block 13 performs processing such as performance measurement and data restoration, and writes the PDU information field of the ATM cell in the CDV absorption buffer 16.

The parallel / serial conversion block 14 is
A vertical / horizontal conversion circuit 18 and a clock transfer memory 17 are provided as function realizing circuits. Clock replacement memory 1
7 has the same number as the number of ports divided by the number of memory input / output signal parallels.

The vertical / horizontal conversion circuit 18 converts data in units of 4 octets × 12 ports divided into 4 octets into data in units of 12 bits (corresponding to 12 ports) × 32 words. .

The clock transfer memory 17 is composed of a dual port memory of 12 bits × 64 words (32 words × 2 faces), and one memory has data for 12 ports, one port for each pit. Is stored. 12 bits (corresponding to 12 ports) x 32 using this memory
The data in units of words is converted into constant-speed data synchronized with the CBR interface clock. The timing generator 8 controls data reading from the CDV absorption buffer 4 (signal 11), data writing control of the vertical / horizontal conversion circuit 18 (signal 16), and data writing control of the clock transfer memory 17 (signal 12).

FIG. 6 is a block diagram showing the details of the clock transfer memory 17. Clock replacement memory 1
7 is composed of a dual port memory of 12 bits × 64 words (32 words × 2 faces).

FIG. 7 is a diagram for explaining the data format in this embodiment.

The format of the ATM interface is
It corresponds to the signal 1 in FIG. The port number is calculated from the header of the ATM cell in this signal 1, and the cell number is calculated from the SN value of the SAR-PDU header. Also, the SAR-PDU payload is a CD
According to the V absorption buffer memory map, it is stored in the area corresponding to the port number and the cell number.

The CDV absorption buffer memory map is shown in FIG.
8 shows a memory map of the CDV absorption buffer 16 in FIG. 1, and secures an area for 8 cells corresponding to the cell number for each port, and secures a capacity for storing 47 octets of SAR-PDU payload in the area for 1 cell. ing.

The format of the CDV absorption buffer output corresponds to the signal 3 in FIG. In this signal 3, the data is divided into data units of 48 octets, and one data unit includes data for 12 ports and each port is composed of 4 bytes. The first data unit is composed of data of octets 1 to 4 of ports 1 to 12. The next data unit is from 13 ports to 24
It is composed of the data of octets 1 to 4 of the port.
The data structure of the final port is the same. When the data unit of the final port is reached, the next data unit returns to ports 1 to 12 and is composed of data of octets 5 to 8. After that, the last port has the same configuration up to 40 to 44 octets. However, since 45 to 47 octets are 3-byte data, dummy data is inserted in an area corresponding to 48 octets in this data unit to form a data unit. When the data unit of 45 to 47 octets of the last port is reached, octet 1 of ports 1 to 12 is re-established.
A data unit is composed of data of 4 to 4.

The format of the output of the vertical / horizontal conversion circuit is a 12-bit parallel signal in which each bit and port are in a one-to-one correspondence. In the data unit of ports 1 to 12, the port 1 is stored in the LSB column, thereafter the ports are stored in order for each pit column, and the data of the port 12 is stored in the MSB bit column. Also, one data unit is
It has a structure of 12 bits x 32 words, 3 for each port.
2-bit data is stored. In addition, octet 45
The data unit of octet 47 has a structure of 12 bits × 24 words, and 24 bits of data are stored for each port.

The No. 1 input format of the clock transfer memory is the ports 1 to 1 of the output data of the vertical / horizontal conversion circuit.
The data is extracted from the data unit of 2.

The format of the CBR interface is
It corresponds to the signal 7 in FIG. This signal 7 is C
It is continuously output to the transmission line at a timing synchronized with the BR interface clock. Clock replacement memory 1
From 7 it is output as parallel data, but since 1 bit corresponds to 1 port, it is serial signal data when viewed for each bit.

Next, the operation of the CLAD device having the above configuration will be described in detail with reference to FIGS.

In FIG. 5, when an ATM cell is input from the ATM access interface, the AAL1 processing circuit 2
After performing processing such as performance monitoring and reproduction of abnormal cells, the SAR-P is stored in the CDV absorption buffer 16.
Stores the DU payload. This AAL1 processing and CD
The data writing in the V absorption buffer 16 operates based on the cell arrival timing, whereas the data reading from the CDV absorption buffer 16 and the parallel / serial conversion block 14 use the timing generated by the timing generator 8. It works according to the standard.

The timing generator 8 is the CD of FIG.
According to the output format of the V absorption buffer, the enable control and the addressing control are performed so that the data stored in the CDV absorption buffer 16 is read out as data of 12 ports by 4 octets per port at the same time. , Input enable control to the vertical / horizontal conversion circuit 18 is performed. In this way, the data for 12 ports and the data of 8 para × 48 octets are converted into the vertical / horizontal conversion circuit 1.
8 is input, the reading / input control of the next data unit is stopped until the data processing is completed in the vertical / horizontal conversion circuit 18. In this way, when the read / input control of all ports is completed, the read is stopped until the free space of the clock transfer memory 17 becomes free enough to write the next data.

When there is a free space, the next 4-octet data is read in the same manner. However, the data of the 45th octet to the 47th octet is read in units of 3 octets for each port, and the data corresponding to the 48th octet is undefined. Incidentally, the time for which the free space of the clock transfer memory 17 is free to write the next data is 32 bits in the case of the data of 4 octets.
It becomes a clock time, and in the case of 3-octet data, it becomes 24 clock time.

The vertical-to-horizontal conversion circuit 18 outputs 1 of the input data.
~ 4th byte is bit1, 5th-8th byte is bit2,
Thereafter, the 45th to 48th bytes are sequentially allocated to bit12 and converted into a 32 × 12 bit data unit. The converted data (signal 17) is output to the timing generator 8
By the write control signal (signal 12) output from, the data is written in the clock transfer memory 17 that stores the corresponding port.

The timing generator 8 receives the data (signal 17) read from the vertical / horizontal conversion circuit 18,
The control signal (signal 12) controls data storage in the corresponding clock transfer memory 17. However, when it corresponds to the octet 45 to the octet 47, the last 1 octet of the 4 octets does not select any memory. In addition, no memory is selected at the division between data units.

The clock transfer memory 17 is a dual port, and writes data of 12 para × 32 words or 12 para × 24 words of data (signal 17) in accordance with a control signal (signal 12) from the timing generator 8. From the data output port, data of 12 parameters is constantly read at the CBR interface clock timing. This data (signal 7) is serial continuous data for every 12 para bits.

As an example, in the case of supporting a CBR interface of 84 ports, 7 bit buffers of 12 bits × 64 addresses (84 ports / 12 paras).
And 8 bits x 31584 addresses (47 octets x
One CDV absorption memory (8 cells x 84 ports) is required.

[0064]

As described above, according to the present invention,
Even if a multi-port CBR interface is provided for a 1-port ATM interface, it is not necessary to mount the same number of CDV absorption buffers and bit buffers as the number of ports, and the CL can reduce the number of memories.
An AD device and a cell disassembly method can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining a first embodiment of a CLAD device according to the present invention.

FIG. 2 is a diagram for explaining a configuration of a bit buffer in the CLAD device in FIG.

FIG. 3 is a diagram for explaining the configuration of a data format in the CLAD device in FIG.

FIG. 4 is a diagram for explaining a time chart of a bit buffer in the CLAD device in FIG.

FIG. 5 is a block diagram for explaining a second embodiment of the CLAD device according to the present invention.

6 is a diagram for explaining a configuration of a bit buffer in the CLAD device in FIG.

FIG. 7 is a diagram for explaining the configuration of a data format in the CLAD device in FIG.

8 is a diagram for explaining a time chart of a bit buffer in the CLAD device of FIG.

FIG. 9 is a block diagram for explaining an example of the configuration of a conventional CLAD device.

10 is a diagram for explaining the configuration of the data format of the CLAD device in FIG. 9.

11 is a block diagram for explaining a case where the configuration of the CLAD device in FIG. 9 is expanded to a multiport.

12 is a diagram for explaining the configuration of the data format of the CLAD device in FIG. 11. FIG.

[Explanation of symbols]

2 AAL1 processing circuit 4 CDV absorption buffer 6-bit buffer 8 Timing generator 13 AAL1 processing block 14 Parallel / serial conversion block 15 Output selector 16 CDV absorption buffer 17 clock replacement memory 18 Vertical-to-horizontal conversion circuit

Claims (4)

[Claims] 1. A CLAD device having a multi-port CBR service interface for a 1-port ATM access interface, wherein a single storage means for storing data of the multi-port CBR service interface and a time from the storage means are provided. In order to convert the non-continuous parallel data for each port read in division into continuous data, the CL is provided with the second storage means provided in the same number as the number of ports of the CBR service interface.
AD device. 2. A CLAD device having a multi-port CBR service interface with respect to a 1-port ATM access interface, wherein a single storage means for storing data of the multi-port CBR service interface and time from the storage means are provided. CL comprising: a conversion unit for converting the non-continuous parallel data read by division for each port into parallel data corresponding to each bit string of each port of the CBR service interface.
AD device. 3. A cell disassembling method in a CLAD device having a CBR service interface of a plurality of ports with respect to an ATM access interface of a one port, wherein data of a plurality of ports of the CBR service interface is stored in a single storage means. Reading the stored data for each port in a time division manner and synchronizing the data discontinuous by the time division with the CBR service interface by using the same number of second storage means as the number of ports of the CBR service interface. A cell decomposition method characterized by converting to continuous data. 4. A cell disassembling method in a CLAD device having a CBR service interface of a plurality of ports with respect to an ATM access interface of a one port, wherein data of a plurality of ports of the CBR service interface is stored in a single storage means. Converting non-continuous parallel data for each port read out from the storage means in a time division manner into parallel data corresponding to each bit string of each port of the CBR service interface, and converting the parallel data to the CBR service interface. A cell decomposition method characterized by converting to continuous data synchronized with.