JP2003032228A - Error correction circuit and error correction method - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To continuously viterbi-decode data encoded by one convolutional encoder over different modulation multi-level numbers, the data remains in the path metric when the transmission mode is switched. The data error rate is not affected by the transmission mode after switching. SOLUTION: A Viterbi decoder control circuit has a transmission mode A
Recognizing the switching timing of B, turns on the switching control signal from the time (J) when the last symbol of the transmission mode A is input to the path memory to the time (1) when it is output, and outputs the signal to the ACS circuit. While the switching control signal is ON, the ACS circuit outputs the Viterbi decoded symbol of the transmission mode A from the path memory with reference to the result of the minimum path metric determination of the last symbol of the transmission mode A. All path memories are in transmission mode B
After the time point is satisfied, the switching control signal is turned off.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction circuit for performing error correction coding and decoding digitally transmitted data, and a method thereof.

[0002]

2. Description of the Related Art In recent years, digitalization of TV broadcasting has been rapidly progressing in cable, satellite and terrestrial media in Japan, Europe and America. In Japan, digital CA
The standard system of TV was announced in the official gazette at the end of 1996, and the standard system of terrestrial broadcasting is being studied with the aim of starting broadcasting around 2000. On the other hand, for satellite broadcasting, C
S (Communication Satellite) digital broadcasting 199
Starting from 6 years, BS (Broadcasting Satellite) digital broadcasting is being studied by the Telecommunications Technology Council, the Radio Industries Association, etc. with the aim of starting broadcasting in 2000.

By the way, in BS digital broadcasting,
Since the transponder power can be doubled compared to CS digital broadcasting, TC-8PSK (Trellis
Adoption of Coded-8-ary Phase Shift Keying: trellis coded 8-phase PSK) is under study. As a result, more transmission capacity can be obtained than in CS digital broadcasting that uses QPSK (Quarternary PSK: four-phase PSK), and one transponder enables HDTV (High Definit
2 channels of ion TV) can be transmitted. Or HDTV
SDTV (Standard Definitio
n TV) can be transmitted for 3 channels. However, since the modulation multi-level number (phase number) is large and the inter-code distance is small, the service time rate is reduced due to rain attenuation, that is, the unviewable time is increased to some extent.

As a countermeasure against this, adoption of layered transmission is being studied (Kato et al .: "Study on satellite ISDB system", Technical Report of the Institute of Image Information and Television Engineers, BCS97-12 (Mar. 1997)).
). This is TC-8P for high resolution video (higher layer).
Images transmitted at SK, and images with the same contents as those dropped to a low bit rate (low layer) are QPSK or BPS.
K (Binary PSK: two-phase PSK) is used for time-division multiplexing transmission in the same transmission frame as in the higher layer. On the receiver side, all modulated data (TC-8P) in the transmission frame
SK, QPSK, BPSK) is subjected to PSK demodulation, and normally, a high-level image of TC-8PSK is MPEG-decoded and the image is output to the monitor. On the other hand, due to heavy rain, the C / N ratio (Ca
If the rrier to Noise ratio decreases, QPSK
And MPEG-decodes a low-layer image of BPSK or the like and outputs the image to the monitor.

By performing such layered transmission,
Although the image has a low resolution during heavy rain, it is possible to prevent the service time rate from decreasing. The standard system of BS digital broadcasting currently under discussion will be described below with reference to the drawings.

FIG. 76 shows an error correction coding device 10 on the transmission side.
It is a block diagram which shows the structural example of 001. The error correction coding apparatus 10001 shown in this figure is a TS multiplexing circuit 1000.
2, an RS (Reed-Solomon) encoding circuit 10003,
Randomize circuit 10004 and interleave circuit 1
0005, a byte / symbol conversion circuit 10006,
Convolutional encoder 10007 and mapping circuit 10
008 and a transmission control information generation circuit 10009.

The error correction coding apparatus 10 having such a configuration
The operation of 001 will be described. Multiple types of MPEG transport streams (TS: Transport Stream)
Is input to the error correction coding apparatus 10001, the TS
The multiplexing circuit 10002 multiplexes a plurality of types of TS, and FIG.
A multiplexed TS is generated as shown in (a) (two types of TS are assumed in this case).

[0008] Such a multiple TS multiplex system allows each broadcaster to have physical independence so that each broadcaster has a TS.
Is assigned and multiplexed in a frame. That is, one transponder has one TS in CS digital broadcasting, but one transponder in BS digital broadcasting has a feature that a plurality of TSs (8 at maximum) can be included.

The RS encoding circuit 10003 in FIG. 76 uses RS (204,
188) is encoded, 16 bytes of parity is added to TS188 bytes of MPEG, and
The data sequence shown in (b) is output. One frame is made up of 48 MPEG packets, and one superframe is made up of 8 frames. The randomizing circuit 10004 is shown in FIG.
One superframe (4
Randomization is performed at a cycle of (8 MPEG packets × 8 frames) and output to the interleave circuit 10005.
As shown in FIG. 77C, the randomizing circuit 1000
The PN generator in 4 is reset at the second byte of the first frame of each superframe and multiplies the input data using the generator polynomial. However, each MPEG packet 20
First byte of 4 bytes (MPEG sync byte: 47h)
During the period, the PN generator is free-run and the data is not multiplied.

In addition, PN (Pseudo-r
Andom Noise) sequence, the generating polynomial as 1 + x ¹⁴ + x ^15, the initial value (100,101,010,000,000).

FIG. 77 (d) is a structural diagram of a transmission frame. The 204 bytes after randomization are 1 slot, 1 frame is 48 slots, and 1 superframe is 8 frames. The first byte of each slot is
After interleaving, it is replaced with transmission control information including various information of superframe.

The randomized data sequence is interleaved in an interleave circuit 10005,
It is output to the byte / symbol conversion circuit 10006. Interleave is 20 excluding the first byte of each slot.
For 3 bytes, a block with a depth of 8 per slot
Interleaving is performed for 48 slots. That is, FIG.
As shown in, the interleave is 8 × 203 bytes. And each slot has a depth of 8 in the superframe direction.
Block interleave of Next, the i-th slot of the 1st to 8th frames is collectively interleaved and returned to the i-th slot every 1/8 (1 ≦ i ≦ 4
8).

The interleaving as described above is performed. Here, when the actual read address value for the i-th slot is shown (the number indicates the frame-byte), it becomes as follows. Start 2 Bytes 203 Bytes 1st frame: 1-1 2-1 ... 3-26 2nd frame: 4-26 5-26 ... 6-51 3rd frame: 7-51 8 -51 ... 1-77 4th frame: 2-77 3-77 ... 4-102 5th frame: 5-102 6-102 ... 7-127 6th frame: 8-127 1-128 ... 2- 153 7th frame: 3-153 4-153 ... 5-178 8th frame: 6-178 7-178 ... 8-203 For example, the access sequence for the 1st frame will be described in detail below. . 1-1, 2-1, 3-1, ... 8-1 1-2, 2-2, 3-2, ... 8-2 ... ... ... 1-24, 2- 24, 3-24, ... 8-24 1-25, 2-25, 3-25, ... 8-25 1-26, 2-26, 3-26

As described above, the interleave circuit 100
In 05, block interleaving with a depth of 8 is performed for each slot for 48 slots. Assuming that the coding rate is r, TC-8PSK (r = 2/3) and QPSK are included in the superframe for hierarchical transmission as described above.
There are data of (r = 3/4, 1/2) and BPSK (r = 1/2). One frame consists of 48 slots, and one super frame consists of 48 × 8 slots. When all slots are transmitted by TC-8PSK (r = 2/3), 48 slots of data are transmitted in full. It is possible. On the other hand, QPSK (r = 3/4), QPSK (r
= 1/2), BPSK (r = 1/2) is TC-8PS
Compared with K (r = 2/3), the transmission efficiency is 3 /
It is reduced to 4, 1/2 and 1/4.

Since the transmission time of one super frame is constant, as shown in FIG. 79 (a), QPSK (r = 1 /
When transmitting the slots of 2), the interleave circuit 1 is used as a dummy slot for every two slots.
Although it will be input to 0005, at the time of output, only one effective slot out of two slots becomes 1 at the time of input.
It is read at a speed of / 2. Similarly, FIG.
As shown in (b) and (c), QPSK (r = 3/4)
Is 1 slot per 4 slots, BPSK (r = 1 /
In 2), 3 slots per 4 slots are dummy.
It becomes a slot.

As described above, the first byte (MPEG synchronization byte: 47h) of each slot is interleaved, and then the transmission control information (TMCC: Transmission Multiplexing Configuratio) including various information of the superframe.
n Control). FIG. 80 shows a configuration example of the transmission control information generation circuit 10009. As shown in the figure, the transmission control information generation circuit 10009 includes a control information generation unit 10010, an RS encoding circuit 10011, and a TAB.
Signal inserting section 10012 and randomizing circuit 10013
And have.

TMCC has 48 slots × 8 frames =
The first byte of each slot in the 384 slots is replaced with the 384 bytes obtained by collecting one superframe, and is generated in units of superframes. Since TMCC is important information, BPS is added at the beginning of each frame before the main signal.
Transmission is performed at K (r = 1/2). Therefore, since the transmission efficiency is 1/4 of TC-8PSK (r = 2/3),
The data actually transmitted is 96 bytes (= 384 bytes / 4).

The operation of the transmission control information generation circuit 10009 will be described below. In FIG. 80, the control information generator 10
010 generates TMCC 48 bytes as transmission control information of the superframe after two, and the RS encoding circuit 10
Output to 011. Further, the control information generator 10010 uses the modulation parameters as the byte / symbol conversion circuit 10 of FIG.
006, the convolutional encoder 10007, and the mapping circuit 10008.

FIG. 81 shows an example of the contents of TMCC 48 bytes (384 bits). In BS digital broadcasting, a transmission frame configuration consisting of 48 slots, that is, 1 superframe = 8 frames, is adopted in order to enable the adoption of multiple TSs within one modulated wave and the switching of operation of multiple modulation systems by the broadcaster. . These are control information newly added for broadcasting to the control information of the MPEG2 System. It is necessary to transmit such transmission control information (TMCC) as information for clarifying the transmission mode of each slot and the relationship with the TS. Furthermore, TMCC
Is also a signal for transmitting information related to modulation / demodulation, and therefore information regarding transmission / reception control is included here. Figure 8
In 1, the version information is an instruction to change the contents of the TMCC, and is incremented by 1 each time the contents are changed. The receiver can recognize the timing of changing the contents of the TMCC by monitoring this information.

FIG. 82 shows an example of the structure of transmission mode / slot information. The transmission mode is an item indicating a combination of a modulation method to be used and an inner code (convolutional code). In the figure, the number of assigned slots indicates the number of slots per frame assigned to the immediately preceding transmission mode (including the above-mentioned dummy slots). The unused transmission mode is identified by the number of assigned slots immediately after that being 0. In the main signal, as shown in FIG. 82, the slots are arranged in the order of the transmission modes of the modulation method having the larger number of phases and the inner coding method having the higher coding rate.

FIG. 83 shows an example of the structure of relative TS / slot information. Since multiple TSs are transmitted in one modulated wave, it is necessary to clearly indicate in which slot in the transmission frame each TS is arranged. Since TS_ID used in MPEG2 System is 16 bits, it is not preferable to use it as it is in terms of transmission efficiency. Instead, the 3-bit relative TS / slot information indicates the TS transmitted in each slot using the relative TS number for each slot in order from slot 1. Relative T
By setting the S number to 3 bits, a maximum of 8 TS can be transmitted within one modulated wave.

FIG. 84 shows an example of the structure of the relative TS / TS correspondence table. By having a correspondence table of TS_ID (16 bits) for each relative TS number, the use of the relative TS number is completed only by the modulator / demodulator.

FIG. 85 and FIG. 86 show examples of the structures of transmission / reception control information and extension information, respectively. In the transmission / reception control information, a signal for receiver activation control in emergency alert broadcasting and a control signal for switching uplink stations are transmitted.
The extension information is a field used for future TMCC extension.

When the 48 bytes of TMCC shown above are output from the control information generator 10010 of FIG. 80, the RS encoding circuit 10011 performs RS (64, 48) encoding, and the parity of 16 bytes is applied to the 48 bytes of TMCC. Is added and output. The TAB signal insertion unit 10012 is
As shown in FIG. 87, the RS-encoded 64-byte data series is divided into 8 frames, and the divided 8
Two bytes of TAB signals are inserted before and after each byte, and a TMCC of 96 bytes per superframe (12 bytes per frame) is randomized.
Output to 013. Here, among the TAB signals, W1 (=
1B95h) is for frame synchronization, and W2 (= A340h) is for superframe identification. Regarding the TAB signal, in the following description, a signal before convolutional coding is represented by an uppercase letter W, and a signal after convolutional encoding is represented by a lowercase letter w.

The randomizing circuit 10013 shown in FIG.
The data sequence output from the TAB signal insertion unit 10012 is randomized at a cycle of TMCC1 superframe (96 bytes) and output to the byte / symbol conversion circuit 10006 in FIG. The PN generator of the randomizing circuit 10004 is reset at the third byte of the first frame of each superframe as shown in FIG. 88, and the input data is multiplied. However, the data is not multiplied as a free run during the period of each TAB signal (W1, W2, W3).

As described above, the transmission control information generation circuit 10
009 is a TM of 96 bytes per super frame
The CC is output to the byte / symbol conversion circuit 10006, and the modulation parameters (phase number, coding rate) of the data sequence in the superframe are displayed in the byte / symbol conversion circuit 10006 and the convolutional encoder 1000 in FIG.
7 and the mapping circuit 10008.

FIG. 87 shows the TMCC of 12 bytes per frame output from the transmission control information generation circuit 10009 and the main signal of 203 × 48 bytes converted into TC-8PSK per frame output from the interleave circuit 10005. It is input to the byte / symbol conversion circuit 10006 in a superframe structure. That is, the first 12 bytes of each frame are TMCC, and the subsequent 203 × 4
8 bytes are the main signal, and a structure of 1 superframe is formed by collecting 8 frames. As shown in FIG. 89,
In each frame, the main signals are arranged in order from the one having the largest modulation multi-value number (phase number). However, for QPSK, the coding rates are arranged in descending order such as coding rate r = 3/4 → r = 1/2.

The byte / symbol conversion circuit 10006 has
According to the modulation parameter output from the transmission control information generation circuit 10009, the input byte data sequence of the superframe structure is converted into
Convert to a symbol data sequence corresponding to the coding rate. The symbol output shown in FIG. 90 is TC-8PSK (r =
2/3) is parallel 2 bits, QPSK (r = 3/4, 1 /
2), BPSK (r = 1/2) is 1 bit.

The superframe structure symbol data sequence output from the byte / symbol conversion circuit 10006 is input to a convolutional encoder 10007. Figure 9
FIG. 1 is a block diagram showing a configuration example of a convolutional encoder 10007. This convolutional encoder 10007 is
A convolution circuit 10014 shown by a dotted line portion and a punctured P / S (Parallel to Serial) circuit 10015 are included.

When the symbol data sequence D [2: 1] is input to the convolution circuit 10014, the convolution circuit 100
14 is LSB D [1] = D1 is constraint length 7, coding rate 1 /
The convolutional coding is performed by 2, and the 2-bit symbol C
1, C0 is output to the punctured P / S circuit 10015. Also, the MSB of the symbol data series is D [2] = D
For 2, the convolutional encoding is not performed, and the MSB C2 of the encoded symbol (C2, C1, C0) is output to the punctured P / S circuit 10015.

The punctured P / S circuit 10015 is
According to the modulation parameters output from the transmission control information generation circuit 10009, punctured processing and P / S conversion are performed as shown in FIGS. 92 to 95, and encoded symbol data corresponding to each phase number / encoding rate is obtained. Mapping circuit 10
Output to 008. However, TC-8PSK (r = 2 /
Nothing is processed in 3) and QPSK (r = 1/2). In this manner, convolutional coding of the symbol data sequence is continuously performed by one convolution circuit 10014 over the different modulation schemes (number of phases) and coding rates.

FIG. 92 shows an operation example in the case of TC-8PSK (r = 2/3). In this case, the convolutional encoder 1
The symbol data D [2: 1] input to 0007 is LS
The D [1] of B is subjected to convolutional coding in the convolutional circuit 10014 to become 2-bit coded symbols C1 and C0. Further, D [2] of the MSB is not convolutionally coded but becomes C2 of the MSB of the coded symbol. These symbols C0 to C2 are output to the punctured P / S circuit 10015. The punctured P / S circuit 10015 is
The mapping circuit 1000 converts the 8PSK symbol data C2, C1, C0 of 1 symbol = 3 bits without any processing.
Output to 8. In this case, the convolutional encoder 1000
1 symbol (2 bits) input to 7 is encoded,
One symbol (3 bits) is output. Therefore, the coding rate of the convolutional encoder 10007 as a whole is r = 2.
/ 3.

FIG. 93 shows an operation example in the case of QPSK (r = 3/4). The symbol data D [2: 1] (however, D [2] of the MSB is invalid) input to the convolutional encoder 10007 is the convolution circuit 10014 of the D [1] of the LSB.
The convolutional coding is performed to obtain 2 bits of C1 and C0, which are output to the punctured P / S circuit 10015. In the punctured P / S circuit 10015, as shown in FIG. 93, 2 bits are regularly discarded from the data of 3 symbols = 6 bits, that is, punctured, and 1 symbol = 2 from the remaining 4 bits of data. QPS of bits
The K symbol data C1 and C0 are generated and output to the mapping circuit 10008. The MSB symbol C2 is invalid. In this case, 3 symbols (3 bits) input to the convolutional encoder 10007 are encoded and 2 symbols (4 bits) are output. Therefore, the coding rate of the convolutional encoder 10007 as a whole is r = 3/4.

FIG. 94 shows an operation example in the case of QPSK (r = 1/2). The symbol data D [2: 1] (however, D [2] of the MSB is invalid) input to the convolutional encoder 10007 is the convolution circuit 10014 of the D [1] of the LSB.
The convolutional coding is performed to obtain 2 bits of C1 and C0, which are output to the punctured P / S circuit 10015. The punctured P / S circuit 10015 outputs 1-symbol = 2-bit QPSK symbol data C1 and C0 to the mapping circuit 10008 without any processing.
However, the MSB symbol C2 is invalidated. In this case, 1 symbol (1 bit) input to the convolutional encoder 10007 is encoded and 1 symbol (2 bits) is output. Therefore, the coding rate of the convolutional encoder 10007 as a whole is r = 1/2.

FIG. 95 shows an operation example in the case of BPSK (r = 1/2). The symbol data D [2: 1] (however, D [2] of the MSB is invalid) input to the convolutional encoder 10007 is the convolution circuit 10014 of the D [1] of the LSB.
The convolutional coding is performed to obtain 2 bits of C1 and C0, which are output to the punctured P / S circuit 10015. As shown in FIG. 95, the punctured P / S circuit 10015 performs 2-bit P / S conversion of each symbol C1 and C0, and in the order of C0 → C1, 1 symbol = 1 bit of B.
The PSK symbol data (C0 / C1) is output to the mapping circuit 10008. However, 2 bits are invalid from the MSB. In this case, 1 symbol (1 bit) input to the convolutional encoder 10007 is encoded and 2 symbols (2 bits) are output. Therefore, the coding rate of the convolutional encoder 10007 as a whole is r = 1/2.

As shown in FIGS. 92 to 95, the symbol data output from the convolutional encoder 10007 is
Mapping circuit 1000 of FIG. 76 at a constant symbol rate.
8 is output. The mapping circuit 10008, according to the modulation parameter output from the transmission control information generation circuit 10009, as shown in FIG. 96, BPSK, QPSK,
TC-8PSK mapping is performed, and the mapped I (In-Phase) axis and Q (Quadrature Phase) axis data is output to a quadrature modulator (not shown).

The error correction coding apparatus 100 described above
The flow of signals from 01 input to output is summarized per frame as shown in FIG. Here TS1
It is assumed that two kinds of TSs, TS and TS2, are transmitted by one modulated wave, and TS1: <higher layer image> TC-8PSK: 22 slots <lower layer image> QPSK (r = 1/2): 2 slots (of which, dummy 1 slot) TS2: <higher layer image> TC-8PSK: 20 slots <lower layer image> BPSK (r = 1/2): 4 slots (of dummy 3) Slot) shall be transmitted.

TS1 and TS2 as shown in FIG. 97 (a)
Is input to the error correction coding apparatus 10001 of FIG. 76, the TS multiplexing circuit 10002 multiplexes two TSs. Then, the RS encoding circuit 10003 uses the RS (204,
188) Encode. And randomizing circuit 100
04 performs randomization, and outputs a data sequence of 48 slots (1 slot = 204 bytes) per frame as shown in FIG. 97 (b). However, among the 48 slots, the hatched 4 slots are dummy slots. Here, the data series are arranged in order from the largest modulation multi-value number (phase number), and for QPSK, the coding rate r = 3/4 →
It arranges from the one with a high coding rate like r = 1/2.

The interleave circuit 10005 has a head byte (MPEG sync byte: 47h) in each slot.
The block interleaving with a depth of 8 is performed in the superframe direction for each slot for the 203 bytes excluding. In addition, the transmission control information generation circuit 100
09 generates a TMCC and replaces it with the MPEG synchronization byte: 47h which is the head byte of each slot. As a result, as shown in FIG. 97 (c), the byte / symbol conversion circuit 10006 has a byte data sequence consisting of a main signal of 203 bytes × 44 slots following the TMCC 12 bytes including the TAB signal for each frame. Is entered.

The byte / symbol conversion circuit 10006 has
The input byte data series is converted into a symbol data series corresponding to the transmission mode (phase number / coding rate) of each slot. The convolutional encoder 10007 performs convolutional encoding corresponding to the transmission mode of each slot.
The mapping circuit 10008 performs mapping according to the number of phases of each slot, and outputs the data sequence shown in FIG. 97 (d) to a quadrature modulator (not shown). Note that FIG.
As shown in (d), 12 bytes of TMCC, that is, 96 bits per frame are 192 symbols (1 symbol = 1) because BPSK (r = 1/2) encoding is performed.
Bit).

In addition, in the main signal, 1 of TC-8PSK
A slot (203 bytes), that is, 1624 bits becomes 812 symbols (1 symbol = 3 bits) as a result of encoding. 1 slot of QPSK (r = 1/2) (203 bytes: 2 slots including dummy), that is, 1624
The bits are 1624 symbols (1 symbol = 2 bits) as a result of encoding. One slot of BPSK (r = 1/2) (203 bytes: four slots including dummy), that is, 1624 bits, becomes 3248 symbols (1 symbol = 1 bit) as a result of encoding. From the above, one frame consists of TMCC192 symbols and main signal 38976.
It is composed of a symbol (812 × 48).

Next, the error correction coding device 1 shown above
A circuit that performs error correction decoding on a data sequence that has been error correction coded by 0001 will be described below as an error correction circuit that has been studied so far (hereinafter referred to as a conventional error correction circuit) with reference to the drawings. .

FIG. 98 shows a conventional error correction circuit 20001.
3 is a block diagram showing a configuration example of FIG. This error correction circuit 2
0001 is a Viterbi decoder 20002, a high / low hierarchy selection signal generation circuit 20003, a symbol / byte conversion circuit 20004, and a de-interleave circuit 20005.
And MPEG sync byte / dummy slot insertion circuit 2
0006, de-randomizing circuit 20007, RS
Decoding circuit 20008, speed conversion circuit 20009, transmission control information decoding circuit 20010, and tuning circuit 20011
And have.

The error correction circuit 20001 having such a configuration.
The operation will be described below. A data sequence error-correction coded by the error-correction coding device 10001 of FIG. 76 is orthogonally modulated by an orthogonal modulator (not shown) and transmitted through a satellite transmission line including a transponder. This signal is PSK demodulated by a PSK demodulator on the receiving side (not shown). The constraint length of the convolution circuit 10014 described in FIG. 91 is 7, and the TAB signal section is transmitted by BPSK.
Therefore, the TAB signals (w1, w2, w) before Viterbi decoding
3) are 32 symbols (1
Of the 6 × 2 = 32 bits, the first 12 symbols (6 bits × 2) are indeterminate. However, the remaining 32-12 =
20 symbols are w1 (= xxxECD28h), w2 (= xxx0B6)
77h) or w3 (= xxxF4988h). When the channel selection is switched by the channel selection information, the PSK demodulator first demodulates by differential detection, w1, w2,
Superframe synchronization and absolute phase are detected by detecting w3. After detection, synchronous detection is performed and PSK
The demodulated data and the superframe synchronization signal are output to the error correction circuit 20001.

The transmission control information decoding circuit 20010 in the error correction circuit 20001 receives the TMCC of each frame according to the superframe synchronization signal output from the PSK demodulator.
A control signal (transmission mode) is generated for the 192 symbol section and output to the Viterbi decoder 20002. The Viterbi decoder 20002 uses the T of each frame shown in FIG.
For the MCC192 symbol section, B according to the control signal
Viterbi decoding of PSK (r = 1/2) is performed. And 19
The Viterbi decoded data of 2 symbols × 1/2 = 96 symbols (96 bits) is output to the transmission control information decoding circuit 20010. The details of the Viterbi decoder 20002 will be described later.

FIG. 99 shows a configuration example of the transmission control information decoding circuit 20010. This transmission control information decoding circuit 20010
Is a randomizing circuit 20012, a symbol / byte conversion circuit 20013, and an RS decoding circuit 20014.
And a TMCC decoding circuit 20015.

In the transmission control information decoding circuit 20010, the de-randomizing circuit 20012 is a Viterbi decoder 2000.
96 symbols (96
TM) of 768 bits (96 bytes) per superframe, as shown in FIG.
De-codes at a cycle of CC1 super frame (96 bytes)
Randomize and perform symbol / byte conversion circuit 200
It outputs to 13. As shown in FIG. 88, the PN generator in the de-randomization circuit 20012 is reset at the 3rd byte of the first frame of each superframe, and the input data and multiplication are performed, as in the randomization circuit 10004 of FIG. Done. However, each TAB signal (W1, W2,
During the period of W3), the PN generator is in the free-run state and no multiplication is performed on the data.

The symbol / byte conversion circuit 200 of FIG.
13 converts the input 768-symbol (768-bit) data series per superframe into a 96-byte byte data series and outputs it to the RS decoding circuit 20014. As shown in FIG. 87, the TAB signal (W1, W2, or W3) is included in each of the 12 bytes in each frame, 2 bytes before and after, so that the net TMCC signal is 8 bytes per frame (64 bytes per superframe). ). The RS decoding circuit 20014 of FIG. 99 uses RS (64, 4) for 64 bytes of the net TMCC signal.
Decode 8) and send the corrected TMCC of 48 bytes to T
It is output to the MCC decoding circuit 20015.

The TMCC decoding circuit 20055 decodes the contents of the 48-byte corrected TMCC by collating them with the signal arrangement diagrams shown in FIGS. 81 to 86, and outputting various transmission control information such as transmission mode and dummy slot information. Then, the TS_ID of MPEG and the relative TS number are referred to. As described above, the TMCC decoded by the transmission control information decoding circuit 20010 is various kinds of transmission control information applied to the next superframe. As shown in FIG. 87,
The TMCC is arranged at the beginning of the 1st to 8th frames in the superframe. Transmission control information decoding circuit 20010
Decoding of TMCC is not completed until TMCC (parity 2) of the 8th frame is input to. However, as shown in FIG. 87, the main signal of the 8th frame is TC-
When converted into 8PSK, there are 203 × 48 bytes, and when converted into symbols, there are 812 × 48 symbols as shown in FIG. 97 (d), and there is a time margin of 1 superframe.
Decoding of TMCC can be completed sufficiently in this period.

When the symbol data series (I / Q axis) of the superframe structure output from the PSK demodulator is input to the Viterbi decoder 20002, the Viterbi decoder 2
0002 performs Viterbi decoding, and outputs the decoded data to the high / low hierarchy selection signal generation circuit 20003 and the symbol / byte conversion circuit 20004.

FIG. 100 shows a Viterbi decoder 20002 and high / low.
FIG. 16 is a block diagram showing a configuration example of a low hierarchy selection signal generation circuit 20003. Viterbi decoder 2000 shown by the lower broken line
2 is De Punctured S / P (Serial to Paralle)
l) It has a circuit 20066 and a Viterbi decoding circuit 20017 shown by a dotted line portion. Viterbi decoding circuit 2001
7 is a branch metric calculation circuit 20018 and ACS
(Add, Compare, Select) circuit 20019, path metric memory 20020, and path memory 20021
And have. Further, the high / low hierarchy selection signal generation circuit 20003 shown by the upper broken line portion is the 8PSK hard decision circuit 200.
22, M stage delay circuit 20023, and BER (Bit Erro
r Rate) measuring circuit 20024 and convolution circuit 200
25 and.

When the PSK demodulated symbol data sequence (I / Q axis) is input to the Viterbi decoder 20002, the de-punctured S / P circuit 20066 follows the transmission mode output from the transmission control information decoding circuit 20010. 101 to 104, de-punctured processing corresponding to the transmission mode of each slot and S / P conversion are performed and output to the Viterbi decoding circuit 20017. The data subjected to the de-punctured processing and the S / P conversion is shown in FIG.
According to the transmission mode output from the transmission control information decoding circuit 20010, the Viterbi decoding circuit 20017 performs Viterbi decoding corresponding to the transmission mode of each slot. Then, the Viterbi decoded symbol is output to the symbol / byte conversion circuit 20004. Error correction coding device 10
Since the convolutional coding in 001 is continuously performed in one convolutional circuit 10014 as shown in FIG. 91, the Viterbi decoding in the error correction circuit 20001 in FIG. 98 is continuously performed in one Viterbi decoder 20002. It can be decrypted.

FIG. 101 shows TC-8PSK (r = 2/3)
FIG. 6 is an explanatory diagram showing an example of a decoding operation in the case of. The 8PSK demodulated symbol data (I / Q axis) input to the Viterbi decoder 20002 is depunctured S / P circuit 200.
No processing is performed in 16 and the Viterbi decoding circuit 2001
It is directly output to 7. Viterbi decoding circuit 20017
Then, the branch metric calculation circuit 20018 is shown in FIG.
A branch metric with eight code points of 8PSK shown in 6, for example, Euclidean distance is calculated. Based on the branch metric calculated here, the ACS circuit 2001
9, Viterbi decoding is performed by the path metric memory 20020 and the path memory 20021. Then, 1 symbol = 2-bit Viterbi decoded symbol (D in FIG.
(Corresponding to [2: 1]) is output to the symbol / byte conversion circuit 20004 in FIG.

FIG. 102 is an explanatory diagram showing a decoding operation example in the case of QPSK (r = 3/4). Viterbi decoder 200
QPSK demodulated symbol data (I / Q
Axis) is input to the de-punctured S / P circuit 20016, the punctured P / S circuit 100 of FIG.
The de-punctured S / P circuit 20066 inserts a null symbol for the symbol that has been punctured and discarded in 15 to convert 2 symbols into 3 symbols. The null symbol is an intermediate value between two types of code points obtained on the Q axis or an intermediate value between two types of code points obtained on the I axis. These symbols are output to the Viterbi decoding circuit 20017 in FIG. In the Viterbi decoding circuit 20017, the branch metric calculation circuit 20
018 calculates a branch metric with four code points of QPSK shown in FIG. 96. Then, based on the calculated branch metric, the ACS circuit 20019, the path metric memory 20020, and the path memory 20021 perform Viterbi decoding. Thus 1 symbol = 1
Bit Viterbi decoded symbol (corresponding to D [1] in FIG. 93:
The MSB D [2] is invalid) is output to the symbol / byte conversion circuit 20004 in FIG.

FIG. 103 is an explanatory diagram showing a decoding operation example in the case of QPSK (r = 1/2). Viterbi decoder 200
QPSK demodulated symbol data (I / Q
The (axis) is directly output to the Viterbi decoding circuit 20017 without any processing in the de-punctured S / P circuit 20066. In the Viterbi decoding circuit 20017, the branch metric calculation circuit 20018 calculates the branch metric with four code points of QPSK shown in FIG. Then, based on the calculated branch metric, A
CS circuit 20019, path metric memory 2002
Viterbi decoding is performed by 0 and the path memory 20021. Thus, the 1-bit = 1-bit Viterbi decoded symbol (corresponding to D [1] in FIG. 94, and D [2] in the MSB is invalid) is the symbol / byte conversion circuit 20 in FIG.
It is output to 004.

FIG. 104 is an explanatory diagram showing an example of the decoding operation in the case of BPSK (r = 1/2). Viterbi decoder 200
The I-axis (Q-axis data is invalid) of the BPSK demodulated symbol data input to 02 is input (I, Q) for every two input symbols in the de-punctured S / P circuit 20066.
S / P conversion is performed on one symbol of the above and is output to the Viterbi decoding circuit 20017. Viterbi decoding circuit 20017
Then, the branch metric calculation circuit 20018 is shown in FIG.
A branch metric with four code points of QPSK shown in 6 is calculated. Then, based on the calculated branch metric, the ACS circuit 20019 and the path metric memory 2
Viterbi decoding is performed by the 0020 and the path memory 20021. Thus, 1 symbol = 1-bit Viterbi decoded symbol (corresponding to D [1] in FIG.
[2] is invalid), but the symbol / byte conversion circuit 20
It is output to 004.

FIG. 105 shows TC-8PSK (r = 2/3)
FIG. 6 is a trellis diagram showing the operation of the Viterbi decoding circuit 20017 in the case of. As shown in FIG. 91, in the convolutional encoder 10007 of the error correction encoder 10001, D [2] (= D2) of MSB is not encoded.
Therefore, D [2: 1] = (D2, D1) is (0,0) and (1,0), and D [2: 1] is (0,1) and (1,1).
Are considered to be in the same state in the trellis diagram of FIG. Therefore, there are two branches that are output from one state at time t and input to the same state at time (t + 1). Therefore, as shown in FIG. 105, at time (t + 1), the number of branches input to the state S is 4
The Viterbi decoding circuit 20017 sets the branch having the smallest path metric among them as the surviving path as shown by the bold line in FIG. The decoded symbol corresponding to each branch is 2 bits, and the 2-bit decoded symbol corresponding to the branch of the maximum likelihood path is output from the path memory 20021 to the symbol / byte conversion circuit 20004 in FIG.

On the other hand, FIG. 106 shows that QPSK (r = 3/4,
FIG. 6 is a trellis diagram showing the operation of the Viterbi decoding circuit 20017 in the case of 1/2) and BPSK (r = 1/2).
As shown in FIG. 91, in the convolutional encoder 10007 of the error correction encoder 10001, the MSB D [2]
Is invalid. Therefore, one branch is output from one state at time t and is input to the same state at time (t + 1). As shown in FIG. 106, at time (t + 1), the number of branches input to the state S is 2
Therefore, the Viterbi decoding circuit 20017 sets the branch having the smallest path metric among them as the surviving path as indicated by the bold line in FIG. 106, for example. The decoded symbol corresponding to each branch is 1 bit, and the path memory 2002
From 1, the 1-bit decoded symbol corresponding to the branch of the maximum likelihood path is output to the symbol / byte conversion circuit 20004.

As shown in FIG. 91, convolution circuit 10014 is provided with six registers. Therefore, the number of states in both trellis diagrams of FIGS. 105 and 106 is 64. That is, state “000000” to state “11”
It is one of 1111 ”.

On the other hand, when the PSK demodulated symbol data sequence is input to the high / low hierarchy selection signal generation circuit 20003,
As shown in FIG. 100, the 8PSK hard decision circuit 20022
96 makes a hard decision on the TC-8PSK (r = 2/3) slot as the code point of TC-8PSK shown in FIG. 96 according to the transmission mode output from the transmission control information decoding circuit 20010, and 1 symbol = 3 bits. The hard decision result of is output. The M-stage delay circuit 20023 is a Viterbi decoder 20002.
The processing delay (M stages) is delayed and the timing is adjusted and output to the BER measuring circuit 20024. Further, each symbol (1 symbol = 2 bits) of the Viterbi decoded data of the TC-8PSK slot output from the Viterbi decoder 20002 is input to the convolution circuit 20025. This convolution circuit 20025 is the convolution circuit 1 of FIG.
It has the same configuration as 0014. The data of each symbol (1 symbol = 3 bits) reconvolutionally encoded here is output to the BER measuring circuit 20024.

The BER measuring circuit 20024 is TC-8PS.
BER is measured by comparing each symbol (1 symbol = 3 bits) of K slots, and a high / low layer selection signal ('H' = high layer, 'L' = low layer) is generated based on the result. , To an MPEG decoder (not shown) following the error correction circuit 20001. When the BER is low, the'H 'signal is output, and when the BER is high, the'L' signal is output. When the'H 'signal is input, the MPEG decoder MPEG-decodes the higher layer signal and outputs the image to the monitor, and then'L'.
When the signal is input, the lower layer signal is MPEG-decoded and the image is output to the monitor.

The symbol / byte conversion circuit 200 of FIG.
04 converts the input Viterbi decoded symbol data sequence into a byte data sequence corresponding to the transmission mode of each slot according to the transmission mode output from the transmission control information decoding circuit 20010. This state is shown in FIG.
In TC-8PSK (r = 2/3), 4 symbols (1 symbol = 2 bits) are collected and converted into byte data.
QPSK (r = 3/4, 1/2) and BPSK (r = 1
In / 2), 8 symbols (1 symbol = 1 bit) are collected and converted into byte data. Then, these converted data are output to the de-interleave circuit 20005.

Here, the data sequence per frame output from the error correction coding apparatus 10001 is shown in FIG.
As shown in, TS1: <higher layer image> TC-8PSK: 22 slots <lower layer image> QPSK (r = 1/2): 2 slots (including 1 dummy slot) TS2: <higher layer image Image> TC-8PSK: 20 slots <Lower layer image> BPSK (r = 1/2): 4 slots (3 dummy slots). As shown in FIG. 108A, the error correction circuit 2
The 1-frame (= 39168 symbols) symbol data sequence input to 0001 is a Viterbi decoder 20002.
Is Viterbi decoded. Then, as shown in FIG. 108 (b), the symbol / byte conversion circuit 20004 converts the data into a byte data sequence and outputs it.

De-interleaving circuit 20005 performs de-interleaving, and the de-interleaved data is output to MPEG sync byte / dummy slot inserting circuit 20006. In this de-interleaving process, for each 203-byte slot excluding the TMCC portion (48 bytes in terms of TC-8PSK), block-de-interleaving with a depth of 8 is performed for each slot for 48 slots. However, this is not done for dummy slots. As shown in FIG. 109, 8
When the de-interleaving of × 203 is performed, block de-interleaving with a depth of 8 is performed for each slot in the superframe direction. In this way, the i-th slot of the 1st to 8th frames is collectively deinterleaved,
Return to the i-th slot every time (1 ≦ i ≦ 48). The de-interleave processing as described above is opposite to the write / read direction of the interleave circuit 10005 on the transmission side.

FIG. 110 shows a de-interleave circuit 200.
It is a configuration example of 05. This de-interleave circuit 20
Reference numeral 005 denotes a write address generation circuit 20026, a read address generation circuit 20027, and the memory circuit 20.
And 028. Note that the memory circuit 200028 uses a memory area for two banks of one superframe (48 × 8 slots) to perform de-interleaving. Here, the actual write address value for the i-th slot is as follows. The numbers indicate frame-bytes. Start 2 Bytes 203 Bytes 1st frame: 1-1 2-1 ... 3-26 2nd frame: 4-26 5-26 ... 6-51 3rd frame: 7-51 8 -51 ... 1-77 4th frame: 2-77 3-77 ... 4-102 5th frame: 5-102 6-102 ... 7-127 6th frame: 8-127 1-128 ... 2- 153 7th frame: 3-153 4-153 ... 5-178 8th frame: 6-178 7-178 ... 8-203

As described above, the de-interleave circuit 2
In the case of 0005, a block de
Interleaving is performed for 48 slots. However, as shown in FIG. 108C, the TMCC section of each frame is used in the MPEG synchronization 48 byte (48 slot) period. Therefore, the de-interleave circuit 20005
Outputs each slot with a gap of 1 byte for MPEG synchronization at the beginning of each slot. Further, the de-interleave circuit 20005 has a space for dummy slots with a space of 48 per frame as shown in FIG. 108 (c).
Output slots (including dummy slots) at constant speed.

De-interleave circuit 2 shown in FIG.
The operation of 0005 is as follows. As shown in FIG. 109, the write address generation circuit 2 for each slot
A read address generation circuit 20027 generates a write address and a read address,
It is output to the memory circuit 200028. As shown in FIG. 108 (b), the byte data series output from the symbol / byte conversion circuit 20004 is read / written by the memory circuit 200028 in accordance with the write address and read address, and as shown in FIG. The interleaved byte data series is output to the MPEG sync byte / dummy slot insertion circuit 20006 of FIG. However, according to the dummy slot information output from the transmission control information decoding circuit 20010, the write address generation circuit 200026 and the read address generation circuit 2
The address 0027 skips dummy slot addresses and sequentially generates valid slot addresses.

The MPEG sync byte / dummy slot insertion circuit 20006 inserts an MPEG sync byte at the beginning of each slot. And the transmission control information decoding circuit 200
According to the dummy slot information output from 10, the MPEG null packet is inserted in the dummy slot section, and the byte data series as shown in FIG. 108 (d) is output to the de-randomizing circuit 20007.

FIG. 111 shows the de-randomizing circuit 2000.
7 shows a configuration example of No. 7. De-randomize circuit 20007
Is a PN generation circuit 20032, a P / S conversion circuit 20030, an S / P conversion circuit 20031, a gate signal generation circuit 20032, and an ex-or (exclusiv
e-or) circuit 20033. The de-randomizing circuit 20007 is a randomizing circuit 100 on the transmitting side.
As with 04, 1 for the data series in FIG. 108 (d)
De-randomize at the super frame cycle. As shown in FIG. 111, the PN generation circuit 20029 performs signal processing using a generator polynomial (1 + x ¹⁴ + x ¹⁵ ), is reset at the second byte of the first frame of each superframe, and has an initial value "100101010000000." Is substituted. Then, the multiplication with the input data converted into the bit series by the P / S conversion circuit 20030 is performed by the ex-or circuit 2003.
Done in 3. The multiplication result is converted into a byte data series by the S / P conversion circuit 20031 and output to the RS decoding circuit 20008 of FIG. However, as shown in FIG.
Due to the gate signal generated by the gate signal generation circuit 20032, the PN generation circuit 200029 is free-running during the period of the leading byte of each slot 204 bytes and the dummy slot, and data multiplication is not performed.

The RS decoding circuit 20008 decodes RS (204, 188) for each 204-byte slot output from the de-randomizing circuit 20007, and outputs it to the speed conversion circuit 20009. However, the RS decoding circuit 20008 does not decode the dummy slot based on the dummy slot information output from the transmission control information decoding circuit 20010.

The speed conversion circuit 20009 selects one selected TS from the data sequence of 48 slots per frame output from the RS decoding circuit 20008,
The speed conversion is performed as shown in FIG. 108 (e), and the error correction data series (TS) is output to an MPEG decoder (not shown).

FIG. 113 shows a configuration example of the speed conversion circuit 20009. The speed conversion circuit 20009 shown by a dotted line portion includes a write address generation circuit 20034, a read address generation circuit 20035, and a memory circuit 20036. In order to select the TS and convert the speed,
Memory circuit 20036 for one frame (48 slots)
Use the memory area of. Further, FIG. 113 also shows a transmission control information decoding circuit 20010 and a channel selection circuit 20011.

When channel selection information (16-bit TS_ID) is input to the channel selection circuit 20011 from an MPEG decoder (not shown), the channel selection circuit 20011 outputs TS_ID to the transmission control information decoding circuit 20010. The transmission control information decoding circuit 20010 uses the relative TS / T shown in FIG.
Referring to the S correspondence table, the relative TS number of the corresponding TS_ID is selected. Next, with reference to the relative TS / slot information shown in FIG. 83, the slot number information of the selected relative TS number is output to the channel selection circuit 20011. Channel selection circuit 2001
1 outputs a slot selection signal for selecting a TS to the speed conversion circuit 200009 based on the slot number information.

In the speed conversion circuit 20009, the data series for one frame (48 slots) is sequentially written in the memory circuit 20036 by the write address output from the write address generation circuit 20034. The read address generation circuit 20035 is a tuning circuit 2001.
The read address of only the selected N slot including the dummy slot is generated from the slot selection signal output from 1 and output to the memory circuit 20036.

Only the N slots selected by the memory circuit 20036 are subjected to speed conversion and output to the MPEG decoder (not shown) at the input N / 48 speed. Figure 108
In the case of (e), N = 24. In the read address generation circuit 20035, for each slot (204 bytes) output from the memory circuit 20036, the MPEG packet valid period (188 bytes) is an “H” signal, and the RS code parity period (16 bytes) is “L”. An enable signal, which is a signal ', is generated as shown in FIG. 108 (e) and is output to an MPEG decoder (not shown). This enable signal causes the MPEG decoder to receive the MPEG packet valid period (188
Only bytes) can be decrypted.

FIG. 1 output from the memory circuit 20036
For the output sequence of 08 (e), the memory circuit 20036
The state of writing / reading to / from is shown in FIGS. 114 to 117. A data series of 48 slots including dummy slots per frame is input to the memory circuit 20036 at a constant speed. FIG. 108 (e) shows two types of TS.
3 shows a state in which TS1 (24 slots per frame) is selected and is output at the speed of 1/2 (= 24/48) of the input.

FIG. 114 shows the two slots T at the beginning of the frame.
It shows the time when S1 (1) to S1 (2) are input to and written in the memory circuit 20036. Meanwhile, one slot TS1 (1) is read from the memory circuit 20036 and output.

FIG. 115 shows a time point at which 20 slots TS1 (3) to (22) following FIG. 114 are input to and written in the memory circuit 20036. Meanwhile, 10 slots TS1 (2) to TS1 (11) are connected to the memory circuit 20.
It is read from 036 and output.

FIG. 116 shows a time point at which 22 slots TS2 (1) to (20) and TS1 (23) following FIG. 115 and a dummy 1 slot are input to and written in the memory circuit 20036. 11 slots TS in the meantime
1 (12) to TS1 (22) are read from the memory circuit 20036 and output.

FIG. 117 shows the four slots following FIG.
That is, TS2 (21) and the dummy 3 slot are the memory circuit 2
It shows the time when it is input to 0036 and written.
In the meantime, 2 slots, that is, TS1 (23) and dummy 1 slot are read from the memory circuit 20036 and output.

As shown in FIGS. 114 to 117 described above, the rate conversion circuit 20009 receives N frames of the selected TS when a data sequence of one frame (48 slots: including dummy slots) is input. 114 to FIG.
In case of 7, select TS1: N = 24 and input N / 4
It is output to an MPEG decoder (not shown) at a speed of 8.

[0082]

The error correction circuit 20001 which has been studied in the past operates in the above-mentioned configuration,
The error correction data series (TS) was output to the MPEG decoder. By the way, in the Viterbi decoder 20002 of the error correction circuit 20001, even if the transmission mode (phase number / coding rate) changes between slots, control at the time of switching the transmission mode has not been considered.

FIG. 118 is a trellis diagram showing the state of the path memory 20021 (path memory length = J) in the Viterbi decoder 20002 when the transmission mode is switched. Figure 1
18 (a) shows up to the last symbol of transmission mode A in FIG.
00 indicates the time when the data is input to the path memory 20021.
FIG. 118 (b) shows the time when the first symbol of the next transmission mode B is input to the path memory 20021. Figure 11
8C shows the time when the next (J-2) symbol of the transmission mode B is input to the path memory 20021.

In the conventional error correction circuit 20001, from the state having the smallest path metric among all the states of the latest symbol input to the path memory 20021, that is, the J-th symbol in the path memory 20021, The surviving path input to the state is returned by (J-1) symbols, and the first symbol in the corresponding path memory 20021 is output as Viterbi decoded symbol data.

However, FIGS. 118 (b) and 118 (c)
In the trellis diagram shown in, transmission mode B after mode switching
The minimum path metric is determined in all the states of the input symbols of, and the Viterbi decoded data of the transmission mode A before the mode switching, that is, the path memory 2002 when the mode is switched.
This means that Viterbi decoded symbol data is output for the (J-1) symbols remaining in 1.

For example, as shown in FIG. 108 (a), BP
Consider a case where TC-8PSK (r = 2/3) is transmitted after TMCC192 symbols transmitted in SK (r = 1/2). In this case, in FIG. 118, the transmission mode A is BPSK (r = 1/2) and the transmission mode B is T
It is C-8PSK (r = 2/3). In the conventional Viterbi decoding method, the TMCC symbol of the (J-1) symbol remaining in the path memory 20021 at the time of mode switching is the minimum path in the symbol sequence of TC-8PSK (r = 2/3) having a small inter-code distance. It will be decoded according to the metric determination result. Therefore, this (J-1) symbol has a problem that it is worse than the original error rate of BPSK (r = 1/2).

Further, according to the conventional Viterbi decoding method, FIG.
As shown in, the TAB signal (w1, w2, w) which is a fixed sequence of 32 symbols before and after the TMCC192 symbol.
In 3), the PSK demodulated data sequence is directly used for the Viterbi decoder 2 even though the last 20 symbols are known.
I was typing in 0002. Therefore, there is also a problem that the feature of the fixed sequence of the TAB signal is not used.

Further, the conventional error correction circuit 20001 is
As shown in FIG. 110, the de-interleave circuit 2000
In FIG. 5, de-interleaving was performed using 2 superframes of the memory circuit 200028, that is, a byte data area of 48 slots × 8 frames × 2 banks. However, in digital BS broadcasting, a plurality of TSs are multiplexed and transmitted / received by one transponder, and the error correction circuit 20001 finally outputs only the data series of one TS. As shown in FIG. 108 (b), the data sequence input to the de-interleave circuit 20005 is TS1: <higher layer image> TC-8PSK: 22 slots <lower layer image> per frame (48 slots). QPSK (r = 1/2): 1 slot (including 1 dummy slot) TS2: <Higher layer image> TC-8PSK: 20 slots <Lower layer image> BPSK (r = 1/2): 1 slot ( 2 TSs (3 dummy slots) are input. In this case, TS1 or T
Whichever of S2 is selected, if all slots of one TS are transmitted by TC-8PSK, a maximum of 24 slots may be deinterleaved and output per frame. Therefore, the conventional de-interleave circuit 20005
Has a problem that de-interleaving is performed using an unnecessary memory area.

Further, the conventional error correction circuit 20001
In the speed conversion circuit 20009 shown in FIG.
The selection of the TS and the speed conversion are performed by using the memory area of one frame of the memory circuit 20036. However, one frame of 1TS, that is, a maximum of 2 in the above example
TS selection and speed conversion are possible only with a 4-slot memory area. Therefore, the conventional speed conversion circuit 20009
Had a problem that TS selection and speed conversion were performed using an unnecessary memory area.

Further, the de-interleave circuit 20005
Inherently has a memory, and as described above, when the TS is selected by the de-interleave circuit and the speed conversion is performed at the same time, the speed conversion circuit 20009 is unnecessary. Therefore,
From this point of view, the conventional error correction circuit 200
It can be said that 01 has an unnecessary speed conversion circuit 20009.

By the way, in this case, the data series input to the de-randomizing circuit 20007 is not continuous slots but data series of discrete slots. Therefore, when the conventional de-randomizing circuit 20007 is used, de-randomizing cannot be performed, so that the de-interleaving circuit 200
It is impossible to adopt a configuration in which TS is selected and speed is converted in 05. Therefore, the conventional de-randomizing circuit 20007 has a problem that the speed converting circuit 20009 cannot be made unnecessary.

The present invention has been made in view of such conventional problems. In the present invention, the symbols remaining in the path memory before switching the transmission mode are
An error correction circuit capable of Viterbi decoding that is not affected by the symbols in the transmission mode after switching is determined by determining the minimum path metric by the path metric accumulated up to the last symbol in the transmission mode before switching and output as Viterbi decoded data. The purpose is to provide.

Further, according to the invention of the present application, among all the states in the final symbol before the transmission mode is switched, only one state having the minimum path metric is made valid, and the other states are made invalid to output the Viterbi decoded data, and after the switching, It is an object of the present invention to provide an error correction circuit capable of Viterbi decoding that is not affected by the symbols of the transmission mode of.

Further, according to the invention of the present application, among all the states in the final symbol before the transmission mode switching, the minimum value that can take only the path metric of one state having the minimum path metric is set to the maximum value that can take the other states. An object of the present invention is to provide an error correction circuit capable of Viterbi decoding which is not affected by the symbols of the transmission mode after switching by resetting the value.

The invention of the present application is that the transmission mode after switching is changed only when the modulation multi-value number (phase number) after switching the transmission mode is larger than that before switching, or when the modulation multi-value number is the same and the coding rate is high. It is an object of the present invention to provide an error correction circuit that performs Viterbi decoding that is not affected by the symbols of.

Further, the invention of the present application provides an error correction circuit which does not perform switching control in Viterbi decoding according to any one of claims 1 to 4 when a fixed symbol sequence is included following the last symbol before transmission mode switching. The purpose is to

Further, according to the invention of the present application, when a fixed symbol sequence is included following the final symbol before the transmission mode is switched, the fixed symbol sequence is changed to the final symbol from the symbol in which the state of the convolutional encoder is determined. For fixed symbols, only one fixed state is valid and the other states are invalid, Viterbi decoded data is output, and a fixed symbol sequence is used to avoid the influence of the symbols in the transmission mode after switching. It is an object to provide an error correction circuit that can be decoded.

Further, according to the invention of the present application, in the input fixed symbol sequence, at least one symbol is defined as one fixed state in the section from the symbol in which the state of the convolutional encoder is fixed to the final fixed symbol. Output Viterbi-decoded data with only valid and other states invalid,
An object of the present invention is to provide an error correction circuit capable of Viterbi decoding that is not affected by symbols in a transmission mode after switching by using a fixed symbol sequence.

Further, according to the invention of the present application, when a fixed symbol sequence for termination is included following the final symbol before switching, the state of the convolutional encoder is determined in the input fixed symbol sequence. From the symbol to the final fixed symbol, the symbol in the transmission mode after switching is reset by resetting it to the minimum value that can take only the determined one-state path metric and the maximum value that can take the other states. It is an object of the present invention to provide an error correction circuit capable of Viterbi decoding that is not affected by.

Further, according to the invention of the present application, when a fixed symbol sequence for termination is included following the final symbol before switching, the state of the convolutional encoder is determined in the input fixed symbol sequence. From the symbol to the final fixed symbol, for at least one symbol,
An error that enables Viterbi decoding that is not affected by the symbols of the transmission mode after switching by resetting the minimum value that can take only one fixed path metric to the maximum value that can take the other status The purpose is to provide a correction circuit.

Further, according to the invention of the present application, when a fixed symbol sequence is included following the final symbol before the transmission mode switching, the fixed symbol sequence is changed from the symbol whose state of the encoder is fixed to the final fixed symbol in the fixed symbol sequence. For up to the fixed symbol sequence, of the branches output from each state in Viterbi decoding, only one branch corresponding to the fixed symbol sequence is valid, and the other branches are invalid and Viterbi decoded data is output. An object of the present invention is to provide an error correction circuit capable of Viterbi decoding that is not affected by symbols in a transmission mode after switching by using a fixed symbol sequence.

Further, according to the invention of the present application, when a fixed symbol sequence is included following the last symbol before the transmission mode switching, the state of the encoder is determined from the first symbol in the input fixed symbol sequence. For the symbols up to, the state corresponding to the input up to that symbol out of all the states in Viterbi decoding is made valid, and the other states are made invalid, and the state is reduced every time one symbol is input. After it is confirmed, only one state is valid, other states are invalid, Viterbi decoded data is output, and a fixed symbol sequence is used to enable Viterbi decoding that is not affected by the symbols of the transmission mode after switching. The purpose is to provide a correction circuit.

Further, according to the invention of the present application, when the fixed symbol sequence is included following the final symbol before the transmission mode switching, the state of the encoder is determined from the first symbol in the input fixed symbol sequence. Up to the symbols to be input, in the input fixed symbol sequence, from the symbol for which the convolutional encoder state is fixed to the final fixed symbol, up to that symbol among all the states in Viterbi decoding has been input. The minimum value that can take only the path metric of the corresponding state is reset to the maximum value that can take the other states, and after the one state is fixed, the minimum path metric that can only take the fixed one state is taken. To the value of
An object of the present invention is to provide an error correction circuit capable of Viterbi decoding which is not affected by the symbols of the transmission mode after switching by resetting to the maximum value that can take other states.

Further, according to the invention of the present application, the fixed symbol sequence is changed to the code point of the fixed symbol sequence and input to the Viterbi decoder, so that the Viterbi decoding uses the fixed symbol sequence by using a normal method. Thus, an object of the present invention is to provide an error correction circuit capable of Viterbi decoding that is not affected by the symbols of the transmission mode after switching.

According to the invention of the present application, in the input fixed symbol sequence, from the first symbol to the symbol in which the state of the encoder is fixed, the fixed symbol among the branches output from each state in Viterbi decoding is used. Only one branch corresponding to the sequence is enabled, the other branches are disabled, and the Viterbi decoded data is output. Using the fixed symbol sequence, Viterbi decoding that is not affected by the symbols of the transmission mode after switching can be performed. It is an object to provide an error correction circuit.

According to the invention of the present application, in the input fixed symbol sequence, from the first symbol to the symbol whose state of the encoder is fixed, all the states in Viterbi decoding are input. Only the state corresponding to the above is enabled, the other states are disabled, the state is reduced every time one symbol is input, the Viterbi decoded data is output, and the fixed symbol sequence is used to change the transmission mode after switching. An object of the present invention is to provide an error correction circuit capable of Viterbi decoding that is not affected by symbols.

Further, according to the invention of the present application, in the input fixed symbol sequence, from the first symbol to the symbol whose state of the encoder is fixed, among the branches output from each state in Viterbi decoding, Only one branch corresponding to the symbol sequence is valid, the other branches are invalid, and only the state corresponding to the input of that symbol is valid among all the states in Viterbi decoding, and the other states are invalid. As a result, the Viterbi decoded data is output every time one symbol is input, the Viterbi decoded data is output, and the characteristics of the fixed symbol sequence are utilized to the maximum, enabling Viterbi decoding that is not affected by the symbols of the transmission mode after switching. To provide a simple error correction circuit.

Further, according to the invention of the present application, in the input fixed symbol sequence, from the first symbol to the symbol whose convolutional encoder state is fixed, all the states in Viterbi decoding are up to that symbol. After resetting to the minimum value that can take only the path metric of the state corresponding to the input and the maximum value that can take the other states, only the confirmed path metric of the 1 state is taken after being set to the 1 state. An object of the present invention is to provide an error correction circuit capable of Viterbi decoding which is not affected by the symbols of the transmission mode after switching by resetting the obtained minimum value to the maximum value that can take other states.

Further, according to the invention of the present application, in the input fixed symbol sequence, from the first symbol to the symbol in which the state of the convolutional encoder is determined, among the branches output from each state in Viterbi decoding. , The fixed branch signal for validating only one branch corresponding to the fixed symbol sequence and invalidating the other branch, and the state corresponding to the input up to that symbol of all the states in Viterbi decoding. The minimum value that can take only the path metric is reset to the maximum value that can take other states, and after the one state is confirmed, the other value is set to the minimum value that can take only the confirmed one-state path metric. Provides an error correction circuit capable of Viterbi decoding that is not affected by the symbols of the transmission mode after switching by resetting to the maximum possible value For the purpose of Rukoto.

Further, according to the invention of the present application, a data sequence transmitted by performing interleaving of depth N for each slot in the superframe by M slots is transmitted as data of the L slot selected from the M slots of each frame. It is an object of the present invention to provide an error correction circuit that deinterleaves only data and outputs data.

Further, according to the invention of the present application, when the maximum number of slots per frame to be selected is Lmax, the area 2 banks of only the maximum (Lmax × N) slots of the memory circuit are used, and the minimum necessary memory area is used. It is an object of the present invention to provide an error correction circuit that performs de-interleaving only by using the above method.

The invention of the present application also provides an error correction circuit that deinterleaves only the data of the selected L slot among the M slots of each frame and continuously outputs at the L / M speed of the transmission format. The purpose is to do.

Further, according to the invention of the present application, in a transmission system in which a plurality of MPEG transport streams are multiplexed and transmitted in a transmission format, interleaving with a depth of N is performed for each M slots in a superframe. The data series that
An object of the present invention is to provide an error correction circuit that deinterleaves only data in a selected L slot among slots and outputs the data.

Further, according to the invention of the present application, assuming that the maximum number of slots per frame occupied by one type of transport stream is Lmax, the maximum of the memory circuit (Lmax x
N) An error correction circuit that uses two banks of areas only for slots and deinterleaves only one type of selected transport stream with only the minimum necessary memory area to output data The purpose is to

Further, according to the invention of the present application, assuming that the maximum number of slots occupied by one type of transport stream per frame is Lmax and K is an integer of 2 or more, the maximum (Lmax × N × K) slots of the memory circuit can be obtained. It is possible to provide an error correction circuit that uses only two memory areas and uses only the minimum necessary memory area to deinterleave only selected K or less transport streams and output data. To aim.

Further, according to the invention of the present application, in a transmission system for transmitting in a transmission format in which a plurality of MPEG transport streams are multiplexed, only data of a selected L slot among M slots of each frame is deinterleaved. It is an object of the present invention to provide an error correction circuit that continuously outputs at an L / M speed of a transmission format.

Further, according to the invention of the present application, in the transmission method in which a plurality of MPEG transport streams are transmitted in a transmission format, the selected J types of transport streams are L per frame.
1, L2, ..., Lj slots are occupied, a total of (L1 + L2 + ... + Lj) slots of data among M slots of each frame are de-interleaved to have a transmission format of (L1 + L2).
It is an object of the present invention to provide an error correction circuit that continuously outputs at a speed of + ... + Lj) / M.

Further, according to the invention of the present application, when 1 frame = M slots and 1 superframe = N frames, the data sequence transmitted by randomizing continuously in superframe units is transmitted in one superframe ( N ×
M) It has (N × M) kinds of initial values of de-randomized for each head data of the slot, and when the data of the L slot among the M slots of each already selected frame is input, each input slot It is an object of the present invention to provide an error correction circuit that performs de-randomization for each input slot from an initial value corresponding to.

Further, according to the invention of the present application, by reading and writing only the data of the selected L slot among the M slots of each frame to and from the memory circuit, the data of the selected L slot per frame is transferred in the L format of the transmission format. / M
It is an object of the present invention to provide an error correction circuit that continuously outputs at a speed of.

Further, according to the invention of the present application, when the maximum number of slots per frame to be selected is Lmax, an area corresponding to the maximum Lmax slots of the memory circuit is used, and only the minimum necessary memory area is selected. An object of the present invention is to provide an error correction circuit that performs speed conversion of data and continuously outputs the data.

Further, according to the invention of the present application, in a transmission system for transmitting in a transmission format in which a plurality of MPEG transport streams are multiplexed, only data of a selected L slot among M slots of each frame is read from and written to a memory circuit. By doing so, it is an object of the present invention to provide an error correction circuit that continuously outputs data of L slots per selected frame at an L / M speed of a transmission format.

Further, in the invention of the present application, assuming that the maximum number of slots per frame occupied by one type of transport stream is Lmax, an area corresponding to the maximum Lmax slots of the memory circuit is used, and the minimum necessary number is used. An object of the present invention is to provide an error correction circuit that performs speed conversion and continuously outputs one selected type of transport stream using only a memory area.

Further, according to the invention of the present application, assuming that the maximum number of slots per frame occupied by one type of transport stream is Lmax and K is an integer of 2 or more, the maximum (Lmax × K) slots of the memory circuit can be obtained. Only the minimum necessary memory area is used, and the selected K
It is an object of the present invention to provide an error correction circuit that performs speed conversion and continuously outputs a transport stream of a type or less.

Further, in the invention of the present application, assuming that the selected J types of transport streams occupy L1, L2, ..., Lj slots per frame, respectively, the J types of transport streams are assumed. , L1 / M, L2 / M, ..., Lj of the transmission format, respectively.
An object of the present invention is to provide an error correction circuit that continuously outputs in parallel at a speed of / M.

Further, the invention of the present application is an error correction in which de-interleaving is performed, a data sequence of L slots per frame that has already been selected is input, and a data sequence is continuously output at the L / M speed of the transmission format. The purpose is to provide a circuit.

Further, according to the invention of the present application, if de-interleaving is performed and the maximum number of slots selected per frame is Lmax, an area corresponding to the maximum Lmax slots of the memory circuit is used, and the minimum necessary memory area is used. It is an object of the present invention to provide an error correction circuit that performs speed conversion on selected data and outputs the data continuously.

Further, according to the invention of the present application, in a transmission method in which a plurality of MPEG transport streams are transmitted in a transmission format, deinterleaving is performed, and an already selected L slot data sequence per frame is input. It is an object of the present invention to provide an error correction circuit that continuously outputs a data sequence at a transmission format L / M speed.

The invention of the present application is one type of transport method in which a plurality of MPEG transport streams are transmitted in a transmission format which is multiplexed.
If the maximum number of slots per frame occupied by a stream is Lmax, de-interleaving is performed, an area corresponding to the maximum Lmax slots of the memory circuit is used, and the channel is selected by the minimum necessary memory area. It is an object of the present invention to provide an error correction circuit that performs speed conversion and continuously outputs various types of transport streams.

[0129] The invention of the present application is one type of transport method in a transmission method for transmitting in a transmission format in which a plurality of MPEG transport streams are multiplexed.
If the maximum number of slots per frame occupied by the stream is Lmax and K is an integer of 2 or more, de-interleaving is performed and the area of the maximum (Lmax × K) slots of the memory circuit is used, and the minimum required It is an object of the present invention to provide an error correction circuit that performs speed conversion and continuously outputs the selected K or less kinds of transport streams only by the memory area of the above.

Further, according to the invention of the present application, in the transmission method in which a plurality of MPEG transport streams are transmitted in a transmission format, the selected J types of transport streams are L per frame.
1, L2, ..., Lj slots are occupied, de-interleaving is performed, and J types of transport streams are respectively transferred to L1 / L1 of the transmission format.
It is an object of the present invention to provide an error correction circuit that continuously outputs in parallel at a speed of M, L2 / M, ..., Lj / M.

It is another object of the present invention to realize a signal processing method for realizing the function of the error correction circuit according to each of claims 1 to 9.

[0132]

The invention according to claim 1 of the present application is constituted by symbols of a plurality of modulation schemes and a plurality of coding rates, and the symbols of different modulation schemes and coding rates are continuous. A data sequence transmitted by convolutionally encoded in, is an error correction circuit for Viterbi decoding, based on a known modulation method and coding rate between transmission and reception,
A Viterbi decoder for performing Viterbi decoding of each of the symbols using a path metric, and determining the switching time of the modulation scheme and the coding rate of the symbols, when Viterbi decoding performed by the Viterbi decoder, A Viterbi decoder control circuit for controlling the presence / absence of a reset setting to a predetermined value of the path metric performed at the time of switching based on the modulation multi-value number and the coding rate before and after switching. To do.

According to a second aspect of the present invention, in the error correction circuit according to the first aspect, the Viterbi decoder control circuit is configured such that when the number of modulation levels after switching is greater than that before switching, or when the number of modulation levels before and after switching is higher. Only when the number of values is the same and the coding rate is large, the control for resetting the path metric to a predetermined value is performed.

According to a third aspect of the present invention, in the error / error correction circuit according to the first aspect, the Viterbi decoder control circuit is:
With respect to the predetermined value to be reset and set, the path metric of one state having the smallest path metric of all states is set as the minimum path metric value, and the other state is set as the maximum path metric value. It is characterized by controlling the decoder.

According to a fourth aspect of the present invention, in the error correction circuit according to the first aspect, the data sequence is subjected to convolutional coding with a constraint length n, and further, the modulation method and the coding rate. Has a case where a fixed symbol sequence is included between the symbols to be switched, the Viterbi decoder control circuit,
When the number of modulation levels after switching is larger than that before switching, or when the number of modulation levels before and after switching is the same and the coding rate is large, the last fixed symbol from the nth fixed symbol in the fixed symbol sequence is selected. The reset control is performed only for the path metric up to the fixed symbol.

According to a fifth aspect of the present invention, in the error correction circuit according to the first aspect, the data sequence is subjected to convolutional coding with a constraint length n, and further, the modulation method and the coding rate. Has a case where a fixed symbol sequence is included between the symbols to be switched, the Viterbi decoder control circuit,
When the number of modulation levels after switching is larger than that before switching, or when the number of modulation levels before and after switching is the same and the coding rate is large, the last fixed symbol from the nth fixed symbol in the fixed symbol sequence is selected. At least 1 in the interval up to the fixed symbol
The reset setting is performed only for the path metric of the symbol.

The invention of claim 6 of the present application is the same as claim 4 or 5
In the error correction circuit described above, the Viterbi decoder control circuit sets a path metric of one fixed state as a minimum path metric value and sets the other path to a maximum path metric value with respect to the predetermined value reset and set. It is characterized by setting as.

According to a seventh aspect of the present invention, in the error correction circuit according to any one of the first to sixth aspects, the data sequence further includes transmission control information regarding a modulation scheme and a coding rate of each symbol. The Viterbi decoder is characterized by performing Viterbi decoding of the symbol based on the modulation scheme and the coding rate of each symbol included in the transmission control information.

The invention of claim 8 of the present application may be constituted by symbols of a plurality of modulation schemes and a plurality of coding rates, and may include a fixed symbol sequence between the symbols of which the modulation schemes and the coding rates are switched. An error correction circuit that Viterbi-decodes a data sequence in which the symbols of different modulation schemes and coding rates are continuously convolutionally coded and transmitted, and a fixed symbol sequence according to a symbol coordinate conversion signal. For the section of, the input symbol is changed to the code point of the fixed symbol series, and for the section other than the fixed symbol series, the input symbol is output without changing the input symbol, and the output from the input symbol conversion circuit. For each symbol, using the path metric based on the known modulation method and coding rate between transmission and reception, And a Viterbi decoder control circuit that determines the section of the fixed symbol sequence to generate the symbol coordinate conversion signal and supplies it to the input symbol conversion circuit. To do.

According to a ninth aspect of the present invention, in the error correction circuit according to the eighth aspect, the data sequence further includes transmission control information regarding a modulation scheme and a coding rate of each symbol, and the Viterbi decoder. Is characterized by performing Viterbi decoding of the symbol based on the modulation scheme and the coding rate of each symbol included in the transmission control information.

The invention according to claim 10 of the present application is constituted by symbols of a plurality of modulation schemes and a plurality of coding rates, and the respective symbols of the different modulation schemes and the coding rates are continuously convolutionally coded. A data sequence transmitted as a Viterbi decoding error correction method, based on a known modulation scheme and coding rate between transmission and reception, when performing Viterbi decoding of each symbol using a path metric, the symbol The presence or absence of reset setting to a predetermined value of the path metric, which is performed at the time of switching the modulation method and the coding rate, is controlled based on the modulation multi-value number and the coding rate before and after the switching. It is a thing.

The invention according to claim 11 of the present application is the error correction method according to claim 10, wherein the reset setting is performed when the number of modulation levels after switching is greater than that before switching, or the number of modulation levels before and after switching. Are the same and the coding rate is large, the coding is performed only.

According to a twelfth aspect of the present invention, in the error correction method according to the eleventh aspect, a one-state path having a minimum path metric of all states with respect to the predetermined value set by the reset setting is provided. The metric is set as the minimum path metric value, and the other states are set as the maximum path metric value.

According to a thirteenth aspect of the present invention, in the error correction method according to the tenth aspect, the data sequence is subjected to convolutional coding with a constraint length n, and further, the modulation method and the coding rate. There is a case where a fixed symbol sequence is included between the symbols that are switched, and the reset setting is
When the number of modulation levels after switching is larger than that before switching, or when the number of modulation levels before and after switching is the same and the coding rate is large, the last fixed symbol from the nth fixed symbol in the fixed symbol sequence is selected. It is characterized in that it is performed only for a path metric up to a fixed symbol.

According to a fourteenth aspect of the present invention, in the error correction method according to the tenth aspect, the data sequence is subjected to convolutional coding with a constraint length n, and further, the modulation method and the coding rate. Has a case where a fixed symbol sequence is included between the symbols to be switched, and the reset setting is such that the number of modulation multi-values after switching is larger than that before switching, or the number of modulation multi-values before and after switching is the same and the coding rate. Is large, the reset setting is performed only for the path metric of at least one symbol in the section from the n-th fixed symbol to the final fixed symbol in the fixed symbol sequence. .

According to a fifteenth aspect of the present invention, in the error correction method according to the thirteenth or fourteenth aspects, the determined one-state path metric is a minimum path metric with respect to the predetermined value set by the reset setting. Set as a value,
It is characterized in that another state is set as the maximum path metric value.

The invention of claim 16 of the present application is the same as claims 10 to 10.
15. In the error correction method according to any one of 15 items, the data sequence further includes transmission control information regarding a modulation scheme and a coding rate of each symbol, and Viterbi decoding of each symbol is included in the transmission control information. It is performed based on the modulation method and the coding rate of the symbol.

[0148] The invention of claim 17 of the present application may be constituted by symbols of a plurality of modulation schemes and a plurality of coding rates, and may include a fixed symbol sequence between the symbols of which the modulation schemes and the coding rates are switched. However, it is an error correction method for Viterbi decoding a data sequence in which each of the symbols having different modulation schemes and coding rates is continuously convolutionally coded and transmitted, and a fixed symbol sequence according to a symbol coordinate conversion signal. For the section of, the input symbol is changed to the code point of the fixed symbol series, and for the section other than the section of the fixed symbol series, the input symbol is output without changing the input symbol and the output of the input symbol conversion processing. , Viterbi decoding of each symbol is performed using path metrics based on a known modulation method and coding rate between transmission and reception. A Viterbi decoding process, to determine the interval of the fixed symbol sequence to generate the symbol coordinate transformation signals, is characterized in that it has a, a determination process of outputting to the input symbol conversion process.

The invention according to claim 18 of the present application is the error correction method according to claim 17, wherein the data sequence further includes transmission control information relating to the modulation scheme and coding rate of each symbol, The Viterbi decoding is performed based on the modulation scheme and the coding rate of the symbol included in the transmission control information.

[0150]

(First Embodiment) An error correction circuit according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the error correction circuit 101 according to the present embodiment. In the error correction circuit 101 shown in FIG. 1, the block shown by a thick solid line is different from the conventional example, and the error correction circuit 2000 shown in FIG.
It is characterized in that a Viterbi decoder 102 controlled by a switching control signal is provided in place of the Viterbi decoder 200002 of No. 1 and a Viterbi decoder control circuit 103 for generating a switching control signal is added. The switching control signal is a signal for switching the symbol for determining the minimum path metric in the path memory when outputting the Viterbi decoded data when switching the modulation method and the coding rate. The other blocks, that is, the high / low hierarchy selection signal generation circuit 20003 to the channel selection circuit 20011 are provided, which is the same as that shown in FIG.

The error correction circuit 10 configured as described above.
Each block of No. 1 and its operation will be described below. However, since the operation after the output of the Viterbi decoder 102 is the same as the conventional example, the description thereof will be omitted.

FIG. 2 shows the Viterbi decoder 102 of this embodiment.
3 is a block diagram showing the configuration of the above, and also shows the Viterbi decoder control circuit 103. FIG. A block different from the conventional example is shown by a thick solid line, but such an illustration method is adopted in all block diagrams described below. The Viterbi decoder 102 of FIG. 2 has a de-punctured S / P circuit 20.
016 and a Viterbi decoding circuit 104 shown by a dotted line portion. The Viterbi decoding circuit 104 includes a branch metric calculation circuit 20018, an ACS circuit 105, a path metric memory 20020, and a path memory 20021.
And have. Viterbi decoder 102 according to the present embodiment
Is different from the Viterbi decoder 20002 of the conventional example shown in FIG. 100 only in the internal configuration of the ACS circuit 105.

A Viterbi decoding control method of the present embodiment at the time of switching the transmission mode will be described with respect to the problem to be solved by the invention described with reference to FIG. FIG. 3 shows the path memory 2 in the Viterbi decoder 102 when switching the transmission mode.
It is a trellis diagram showing a state of 0021 (path memory length = J). FIG. 3A is a trellis diagram at the time when the last symbol of the transmission mode A is input to the path memory 20021. FIG. 3B shows the first transmission mode B in the first mode.
FIG. 9 is a trellis diagram when a symbol is input to the path memory 20021. FIG. 3C is a trellis diagram at the time when the next (J-2) symbol in the transmission mode B is input to the path memory 20021.

As shown in FIG. 1, in the error correction circuit 101 of the present embodiment, the transmission control information decoding circuit 200
The transmission mode / slot information of FIG. 82 decoded in 10 is output to the Viterbi decoder control circuit 103. The Viterbi decoder control circuit 103 recognizes the transmission mode switching symbol based on the input transmission mode / slot information. In the Viterbi decoder control circuit 103, up to the last symbol of the transmission mode A in FIG.
3 to the time when the (J-1) symbol of the transmission mode B in FIG. 3C is input to the path memory 20021, the switching control signal is generated and output to the ACS circuit 105.

The ACS circuit 105 receives the switching control signal output from the Viterbi decoder control circuit 103 as follows.
021 is controlled. That is, as shown in FIG. 3A, at the time when the last symbol of the transmission mode A is input to the path memory 20021, as in normal Viterbi decoding,
The state having the smallest path metric is determined among all the states of the latest symbol input to the path memory 20021, that is, the Jth symbol in the path memory 20021. Enter the surviving path entered in that state (J-1)
Returning to the previous symbol, the first symbol in the corresponding path memory 20021 is output as Viterbi decoded symbol data.

Next, as shown in FIG. 3B, at the time when the first symbol of the transmission mode B is input to the path memory 20021, the normal ACS operation is performed to branch to generate the latest trellis diagram. Is extended by 1 symbol. However, the state determined to be the minimum path metric at the time of FIG. 3A, that is, the (J-th) in the path memory 20021.
1) Enter the survivor path (J)
-2) Go back by the symbol and return to the corresponding path memory 200.
The first symbol in 21 is output as Viterbi decoded symbol data.

Hereinafter, during the period when the non-output data of the transmission mode A remains in the path memory 20021, the transmission mode A
Of the last symbol, the first symbol in the corresponding path memory 20021 is output as the Viterbi decoded symbol data.

FIG. 3C shows a trellis diagram when the (J-2) symbol of the transmission mode B is input to the path memory 20021 as compared with FIG. 3B. At this point,
The final symbol of the transmission mode A corresponds to the first symbol in the path memory 20021, and the Viterbi decoded data corresponding to the state determined to have the minimum path metric is output from the path memory 20021.

When the next one symbol of the transmission mode B is input to the path memory 20021 from FIG. 3C,
Since all the data in the path memory 20021 are symbols of the transmission mode B, the normal Viterbi decoding output method is restarted. The state having the smallest path metric is determined among all the states of the latest symbol input to the path memory 20021, that is, the Jth symbol in the path memory 20021. Enter the survivor path (J
-1) Go back by one symbol and go to the corresponding path memory 200.
The first symbol in 21 is output as Viterbi decoded symbol data. Further, the Viterbi decoder 102 outputs the Viterbi decoded data by performing the same operation as the Viterbi decoder 20002 shown in the conventional example, except for the control at the time of switching the transmission mode described above.

With the configuration described above, the error correction circuit 101 of the present embodiment completely cuts off the influence of the transmission mode B after the mode switching, and the mode remaining in the path memory 20021 when the transmission mode is switched. Transmission mode A before switching
The Viterbi decoded data of can be output.

Further, in the present embodiment, the Viterbi decoder control circuit 103 generates a switching control signal as shown below, and the ACS circuit 105 causes the Viterbi decoder control circuit 103.
According to the switching control signal output from the path metric memory 20020 and the path memory 2002, as shown in FIG.
The control of 1 may be performed. In this case, the Viterbi decoder control circuit 103 in FIG.
The switching symbol of the transmission mode is recognized based on the transmission mode / slot information output from. As shown in FIG. 4A, the switching control signal is generated and output to the ACS circuit 105 only when the last symbol of the transmission mode A is input to the path memory 20021.

As shown in FIG. 4A, at the time when the last symbol of the transmission mode A is input to the path memory 20021, the ACS circuit 105 is the latest input to the path memory 20021 like the normal Viterbi decoding. Of all symbols, ie, the Jth symbol in the path memory 20021, has the smallest path metric. Then, the path metric memory 200 is set so that only that state is valid and all other states are invalid.
20 and the path memory 20021 are controlled.

Others perform the same decoding as the Viterbi decoding shown in the conventional example. The state having the smallest path metric is determined among all the states of the latest inputted symbol, that is, the Jth symbol in the path memory 20021. The surviving path input in that state is moved back by (J-1) symbols, and the first path in the corresponding path memory 20021 is returned.
The th symbol is output as Viterbi decoded symbol data.

With the configuration shown above, the final symbol of the transmission mode A before the transmission mode switching is as shown in FIG.
In the trellis diagrams shown in (a) to (c), only one state having the minimum path metric is valid. Therefore,
The error correction circuit 101 of the present embodiment completely cuts off the influence of the transmission mode B after the mode switching, and the Viterbi decoded data of the transmission mode A before the mode switching which remains in the path memory 20021 when the transmission mode is switched. Can be output.

3A to 3C, or FIG.
At the time of (a), the Viterbi decoder control circuit 103 is assumed to generate the switching control signal. However, the switching control signal may be generated only when the number of modulation levels after switching the transmission mode is larger than that before switching the transmission mode, or when the number of modulation levels is the same and the coding rate is high. For example, in the transmission frame shown in FIG. 89, TMCC
(BPSK: r = 1/2) → next transmission mode (TC-8
Even if the Viterbi decoder control circuit 103 generates a switching control signal only when switching the transmission mode of PSK: r = 2/3, QPSK: r = 3/4, or QPSK: r = 1/2 Good. However, TMCC (BPSK:
Excluding the case of r = 1/2) → BPSK (r = 1/2).

By the switching control signal generated by the Viterbi decoder control circuit 103, the transmission mode A before transmission mode switching is set.
Is terminated and decoded at the final symbol as shown in FIG. However, for example, the main signal T
C-8PSK (r = 2/3) → QPSK (r = 3/4)
TC-8PSK (r =
QPSK (r = 3/4) following the last symbol of 2/3)
The symbol of TC-8PSK (r =
The distance between code points is larger than the distance between code points of 2/3). Therefore, when normal Viterbi decoding is performed without performing termination after the first symbol of QPSK (r = 3/4), a more probable branch metric that QPSK (r = 3/4) has is generated and termination is performed. TC-8PSK (r =
It can be expected that the BER for 2/3) (J-1) symbols is reduced.

As shown in FIG. 87, TMCC (BP
Before and after SK: r = 1/2), there are TAB signals (w1, w2, w3) each having a fixed symbol sequence of 2 bytes each and 20 symbols at the input of the Viterbi decoder 102. Therefore, the Viterbi decoder control circuit 103 may not generate a switching control signal when switching the transmission mode before and after TMCC (BPSK: r = 1/2). In this case, a Viterbi decoding control method using the property of the fixed symbol sequence can be considered. This will be described in the second and third embodiments.

(Embodiment 2) An error correction circuit according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 5 shows the error correction circuit 201 according to the present embodiment.
3 is a block diagram showing the configuration of FIG. In the error correction circuit 201 shown in FIG. 5, the block shown by a thick solid line is different from the conventional example, and instead of the Viterbi decoder 200002 of the error correction circuit 20001 shown in FIG. 98, a Viterbi decoder controlled by a definite state signal is used. A feature is that 202 is provided and a Viterbi decoder control circuit 203 for generating a definite state signal is added. The fixed state signal is a signal indicating a period during which the state of the convolutional encoder is fixed for a fixed symbol sequence. The other blocks, that is, the high / low hierarchy selection signal generation circuit 20003 to the channel selection circuit 20011 are provided, which is the same as that shown in FIG.

The error correction circuit 20 configured as described above
Each block of No. 1 and its operation will be described. However,
The operation after the output of the Viterbi decoder 202 is as shown in the conventional example, and thus the description thereof is omitted.

FIG. 6 shows the Viterbi decoder 202 of this embodiment.
FIG. 3 is a block diagram showing the configuration of the above, and also shows the Viterbi decoder control circuit 203. The Viterbi decoder 202
It has a de-punctured S / P circuit 20016 and a Viterbi decoding circuit 204 shown by a dotted line portion. The Viterbi decoding circuit 204 uses the branch metric calculation circuit 200.
18, ACS circuit 205, and path metric memory 2
0020 and a path memory 20021. The Viterbi decoder 202 of this embodiment is different from the Viterbi decoder 20002 of the conventional example shown in FIG. 100 only in the internal configuration of the ACS circuit 205.

With respect to the problem to be solved by the invention described with reference to FIG. 118, the Viterbi decoding control of the present embodiment at the time of switching the transmission mode, particularly the control method using the property of the fixed symbol sequence of the TAB signal, This will be described below. FIG. 7 shows, for example, TMCC (BP
SK: r = 1/2) → path memory 20021 (path memory length =) in the Viterbi decoder 202 in the transmission mode B
It is a trellis diagram which shows a mode of J).

In particular, FIG. 7A shows TMCC (BPSK:
32 symbols after the TAB signal of r = 1/2), for example, w2 = xxx0B677h or w3 = x shown in FIGS.
In the xxF4988h, the path memory 2 is the first symbol of the 20 symbols in which the state of the convolution circuit 10014 is determined.
It is a trellis diagram at the time of input to 0021. Among the above TAB signals, the convolutional circuit 10014
The 20 symbols that determine the state of
This corresponds to 10 symbols after S / P conversion by the S / P circuit 200616.

FIG. 7B is a trellis diagram when the next symbol (after S / P conversion) of the rear TAB signal is input to the path memory 20021. Further, FIG. 7 (c)
Follows the remaining symbols of the rear TAB signal (8 symbols after S / P conversion) and the first (J-1
0) is a trellis diagram when a symbol is input to the path memory 20021.

In the error correction circuit 201 of this embodiment, the transmission control information decoding circuit 2 is used as in the first embodiment.
The transmission mode / slot information decoded in 0010 is output to the Viterbi decoder control circuit 203.

The Viterbi decoder control circuit 203 recognizes the TAB signal (w1, w2, w3) which is a fixed sequence symbol based on the transmission mode / slot information output from the transmission control information decoding circuit 20010. As shown in FIG. 7A, from the time when the first symbol of each TAB signal after S / P conversion is input to the path memory 20021, the tenth symbol of each TAB signal is input to the path memory 200.
Until the time when it is input to 21, the fixed state signal is generated and A
Output to the CS circuit 205.

The ACS circuit 205 of FIG. 6 controls the path metric memory 20020 and the path memory 20021 as follows in accordance with the definite state signal output from the Viterbi decoder control circuit 203. That is, one TAB before the symbol in FIG. 7A and a TAB after the TMCC (BPSK: r = 1/2)
32 symbols of signal w2 = xxx0B677h or w3 = xx
Of the xF4988h, the path memory 20 is one symbol before the 20 symbols in which the state of the convolution circuit 10014 is determined.
Up to the time of being input to 021, the ACS circuit 205 is the smallest in all states of the latest symbol input to the path memory 20021, that is, the J-th symbol in the path memory 20021, as in the normal Viterbi decoding. The state having the path metric of is determined. Then, the surviving path input in this state is returned to (J-1) symbols ago,
The first symbol in the corresponding path memory 20021 is output as Viterbi decoded symbol data.

Next, when the first symbol of the 20 symbols in the rear TAB signal (w2 or w3) that determines the state of the convolution circuit 10014 is input to the path memory 20021, only the determined one state is valid. So that all other states are invalidated.
020 and the path memory 20021 are controlled.

As shown in FIG. 7B, the rear TAB signal (w
Similarly, even when the next symbol of 2 or w3) is input to the path memory 20021, the path metric memory 20020 and the path memory 20021 are set so that only one fixed state is valid and all other states are invalid. Control. Similar control is performed until the remaining symbols of the rear TAB signal are input.

Next, when the first symbol of the transmission mode B is input, the same decoding as the Viterbi decoding shown in the conventional example is performed. The latest input symbol, that is, the path memory 200
Of all the states of the Jth symbol in 21, the state with the smallest path metric is determined. The surviving path input in that state is returned by (J-1) symbols before, and the first symbol in the corresponding path memory 20021 is output as Viterbi decoded symbol data. It should be noted that FIG. 7C shows the first (J-10) of the transmission mode B.
The symbols up to the time point when they are input to the path memory 20021 are shown.

The above is the rear TAB signal (w2 or w3).
In the Viterbi decoding control method using the property of the fixed symbol sequence in, the similar control can be performed for the previous TAB signal (w1).

Further, the Viterbi decoder 202 performs the transmission mode switching described above, that is, TMCC (BPSK: r = 1).
/ 2) → Except for the control of the transmission mode B, the same operation as that of the Viterbi decoder 20002 shown in the conventional example is performed to output the Viterbi decoded data.

With the configuration described above, the Viterbi decoding control is performed using the property of the fixed symbol sequence in the TAB signal (w2 or w3) after the TMCC (BPSK: r = 1/2) before switching the transmission mode. ing. Therefore, the error correction circuit 201 of the present embodiment completely cuts off the influence of the transmission mode B after the mode switching, and the TMCC (BPSK: r) before the mode switching which remains in the path memory 20021 when the transmission mode is switched. = 1/2) Viterbi decoded data can be output.

With respect to the fixed symbol sequence 20 symbols (10 symbols after S / P conversion) of the rear TAB signal (w2 or w3), correct Viterbi decoded data is always selected by the above control method. As a result, as shown in FIG. 7A, when the first symbol of the rear TAB signal (w2 or w3) is input to the path memory 20021, the TMCC (BPSK: r remaining in the path memory is left.
= 1/2) (J-1) symbol error rate can be reduced.

TMCC (BPSK: r = 1/2) is also obtained by performing similar Viterbi decoding control on the fixed symbol sequence 20 symbols of the previous TAB signal (w1).
Transmission mode TC-8PSK (r = 2 /
3) or QPSK (r = 3/4, 1/2) or BPSK
The influence of (r = 1/2) can be cut off.

As described above, the error correction circuit 201 of the present embodiment has the front TAB signal (w1) and the rear TAB signal.
20 fixed symbol sequences for each signal (w2 or w3)
By performing the Viterbi decoding control method using symbols (10 symbols after S / P conversion), 128 symbols (S / P) of real symbol data of TMCC (BPSK: r = 1/2) shown in FIG. For 64 symbols after conversion, the influence of the symbols of the transmission modes before and after can be completely cut off, and the error correction capability of convolutional coding originally possessed by BPSK (r = 1/2) can be derived. .

In this embodiment, the Viterbi decoder control circuit 203 has 20 symbols of each TAB signal (w1, w2, w3) (10 symbols after S / P conversion) as shown in FIG. 7A. The first symbol of the path memory 2002
From the time of being input to 1, the 10th symbol (final symbol after S / P conversion) of each TAB signal is stored in the path memory 200.
A fixed state signal is generated until A
It is configured to output to the CS circuit 205. Instead,
The Viterbi decoder control circuit 203 uses, for example, each TAB signal 2
The definite state signal may be generated and output to the ACS circuit 205 only when the first symbol of 0 symbols (10 symbols after S / P conversion) is input to the path memory 20021. With this configuration, control of the Viterbi decoder control circuit 203 and the ACS circuit 205 can be simplified. The first symbol (S / P of each TAB signal
For the final symbol after conversion), in the trellis diagram shown in FIG. 7, only one confirmed state is valid,
All other states are invalid, so at least TMCC
It is possible to block the influence of symbols in the transmission mode before and after (BPSK: r = 1/2).

In the above, the Viterbi decoder control circuit 20 is used.
In No. 3, for example, the determinate state signal is generated and output to the ACS circuit 205 only when the first symbol of 20 symbols of each TAB signal is input to the path memory 20021. However, as shown in FIGS. 7A to 7C, after the S / P conversion, the symbol period for generating the fixed state signal is 1
It is possible to arbitrarily select between symbols and up to 10 symbols, and which symbol is selected is also arbitrary.

(Embodiment 3) An error correction circuit according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 8 shows an error correction circuit 301 according to this embodiment.
3 is a block diagram showing the configuration of FIG. In the error correction circuit 301 shown in FIG. 8, the block shown by a thick solid line is different from the conventional example, and instead of the Viterbi decoder 200002 of the error correction circuit 20001 of FIG. 98, a Viterbi decoder 302 controlled by a fixed branch signal is used. And a Viterbi decoder control circuit 303 for generating a fixed branch signal is added. The fixed branch signal is a signal that specifies a branch in the state transition of the trellis diagram for the fixed symbol sequence. Other blocks, that is, high / low hierarchy selection signal generation circuit 20003 to channel selection circuit 20011
Is the same as that shown in FIG. 98.

The error correction circuit 30 configured as described above
Each block of No. 1 and its operation will be described. However,
The operation after the output of the Viterbi decoder 302 is as described in the conventional example, and thus the description thereof is omitted.

FIG. 9 shows the Viterbi decoder 302 of this embodiment.
3 is a block diagram showing the configuration of the above, and also shows the Viterbi decoder control circuit 303. The Viterbi decoder 302
It has a de-punctured S / P circuit 20016 and a Viterbi decoding circuit 304 shown by a dotted line portion. The Viterbi decoding circuit 304 uses the branch metric calculation circuit 200.
18, ACS circuit 305, and path metric memory 2
0020 and a path memory 20021. The Viterbi decoder 302 of the present embodiment is different from the Viterbi decoder 20002 of the conventional example of FIG.
Only the internal structure of 5 has changed.

With respect to the problem to be solved by the invention described with reference to FIG. 118, a Viterbi decoding control method of the present embodiment at the time of switching a transmission mode, particularly a control method utilizing the property of a fixed symbol sequence of a TAB signal This will be described below.

FIG. 10 is a trellis diagram showing a branch output method in Viterbi decoding. Here, the Viterbi decoded symbol is 1 symbol = 1 bit QPSK (r = 3
/ 4, 1/2), or BPSK (r = 1/2). FIG. 10A is a trellis diagram showing a branch output method in conventional Viterbi decoding.
At time t, two branches corresponding to the decoded estimated symbols “1” and “0” are output from each state. Figure 10
As shown in (a), at time (t + 1), there are two branches input to the state S, and the Viterbi decoder 20002 shown in the conventional example has the branch having the smallest path metric (thick line). Was the survival path.

On the other hand, FIG. 10B is a trellis diagram showing a branch output method in the Viterbi decoding of the present embodiment for the TAB signal. For example, the rear TAB signal (w2 = xxx0B677h, decoded data W2 = A340h) is shown in FIG.
In the case of being input to the Viterbi decoder 302 of No. 1, it is known whether each of the decoded estimation symbols is “1” or “0” for a total of 16 decoded estimation symbols. For example, the first symbol = “1”. Therefore, FIG.
As shown in (b), for example, for the first symbol of the rear TAB signal (w2), at time t, only one branch corresponding to the decoded estimated symbol “1” is output from each state. At time (t + 1), only one branch is input to the state S, and the surviving path is automatically determined as indicated by the thick line in FIG. 10 (b).

Comparing FIG. 10 (a) and FIG. 10 (b), in FIG. 10 (b), for the TAB signal section, one branch from each state, for example, decoded estimated symbol =
Since only the branch corresponding to “1” is output, the branch input to each state at time (t + 1) is the branch corresponding to the decoded estimation symbol = “1”, which automatically determines the surviving path. . Therefore, an erroneous sequence in the TAB signal section is not set as a surviving path, the influence of the transmission mode B following TMCC (BPSK: r = 1/2) is blocked, and the residual remains in the path memory 20021 when the transmission mode is switched. It is possible to output the Viterbi-decoded data of the existing TMCC. On the other hand, in FIG.
There is two branches input to each state at time (t + 1) without utilizing the property of the fixed symbol sequence of the TAB signal, and the branch corresponding to the erroneously decoded estimated symbol can be selected as the surviving path. There is a nature.

The Viterbi decoding control method in the TAB signal section (fixed sequence section) shown in FIG. 10B will be described below. In the error correction circuit 301 of FIG. 8, the transmission control information decoding circuit 20010 is the same as in the first embodiment.
The transmission mode / slot information of FIG. 82, which is decoded in FIG. 82, is output to the Viterbi decoder control circuit 303. The Viterbi decoder control circuit 303 uses the transmission mode / slot information to determine a fixed sequence symbol (TAB signal: w1, w2, w).
Recognize 3). The fixed branch signal is generated from the time when the first symbol of 16 symbols of each TAB signal is input to the path memory 20021 to the time when the 16th symbol of each TAB signal is input to the path memory 20021 to generate ACS.
Output to the circuit 305.

The ACS circuit 305 outputs only one branch corresponding to the fixed sequence = “1” or “0” from each state of the trellis diagram by the fixed branch signal output from the Viterbi decoder control circuit 303. Path metric memory 20020 and path memory 2002
1 is controlled.

Further, the Viterbi decoder 302 performs the above-mentioned transmission mode switching, that is, TMCC (BPSK: r = 1).
/ 2) → Except for the control of the transmission mode B, the same operation as that of the Viterbi decoder 20002 shown in the conventional example is performed to output the Viterbi decoded data.

With the configuration described above, the Viterbi decoding control utilizing the property of the fixed symbol sequence of the TAB signals (w2, w3) after the TMCC (BPSK: r = 1/2) before the transmission mode switching is performed. Therefore, the error correction circuit 301 of the present embodiment blocks the influence of the transmission mode B after the mode switching, and the TMCC before the mode switching (BPSK: r =) that remains in the path memory 20021 when the transmission mode is switched.
It is possible to output Viterbi decoded data of 1/2).

As a result, assuming that the path memory length = J, the TMCC (BPSK: r = remaining in the path memory at the time when the first symbol of the rear TAB signal (w2, w3) is input to the path memory 20021. 1/2) (J-
1) It is possible to reduce the error rate of symbols. In addition, the same Viterbi decoding control is performed on the fixed symbol sequence of 16 symbols of the previous TAB signal (w1) to perform the transmission mode before the mode switching of TMCC (BPSK: r = 1/2), that is, TC-8PSK ( r = 2/3) or QPSK (r = 3/4, 1/2), or BPSK (r =
The effect of 1/2) can be blocked.

As described above, the error correction circuit 301 of the present embodiment has the front TAB signal (w1) and the rear TAB signal.
16 fixed symbol sequences of the signal (w2, w3) respectively
By performing the Viterbi decoding control method using symbols, the TMCC (BPSK:
For 128 symbols of the actual symbol data (r = 1/2) (64 symbols after S / P conversion), the influence of the symbols in the preceding and following transmission modes is cut off, and BPSK (r = 1 /
The error correction capability of convolutional coding originally possessed in 2) can be derived.

(Embodiment 4) An error correction circuit according to Embodiment 4 of the present invention will be described with reference to the drawings. FIG. 11 shows the error correction circuit 40 according to the present embodiment.
2 is a block diagram showing a configuration of No. 1. In the error correction circuit 401 shown in FIG. 11, the block shown by a thick solid line is different from the conventional example, and instead of the Viterbi decoder 200002 of the error correction circuit 20001 of FIG. 98, a Viterbi decoder 402 controlled by a state reduction signal is used. Is provided and a Viterbi decoder control circuit 403 for generating a state reduction signal is added. A state reduction signal is a signal that reduces the number of states in the trellis diagram for a fixed symbol sequence. Other blocks, that is, the high / low hierarchy selection signal generation circuit 200
No. 03-channel selection circuit 20011 is provided in FIG.
8 is the same as that shown in FIG.

The error correction circuit 40 configured as described above.
Each block of No. 1 and its operation will be described. However,
The operation after the output of the Viterbi decoder 402 is as described in the conventional example, and thus the description thereof is omitted.

FIG. 12 shows the Viterbi decoder 40 of this embodiment.
2 is a block diagram showing the configuration of No. 2, and a Viterbi decoder control circuit 403 is also shown. Viterbi decoder 402
Has a de-punctured S / P circuit 20066 and a Viterbi decoding circuit 404 indicated by a dotted line. The Viterbi decoding circuit 404 uses the branch metric calculation circuit 2
0018, ACS circuit 405, path metric memory 20020, and path memory 20021. The Viterbi decoder 402 of the present embodiment is different from the Viterbi decoder 20002 in the conventional example in that the ACS circuit 4
Only the internal structure of 05 has changed.

With respect to the problem to be solved by the invention described with reference to FIG. 118, a Viterbi decoding control method of the present embodiment at the time of switching a transmission mode, particularly a control method using the property of a fixed symbol sequence of a TAB signal explain. FIG. 13 is an explanatory diagram showing a trellis diagram state reduction method according to the present embodiment. □ in the figure indicates each register of the convolution circuit 10014 shown in FIG. 91, and as an example, the rear TAB signal (w2 = xxx0B677h, W2 = A340h)
Is input to each register.

In FIG. 13, the rear TAB signal w2 is 1
Until the 6 symbols are input to the Viterbi decoding circuit 404, the contents of all 6 registers of the convolution circuit 10014 are indefinite, so the number of states of the trellis diagram is as shown in FIG.
It is 64 as shown in FIG. When the first symbol of w2 is input to the Viterbi decoding circuit 404, the content of the first register is determined to be "1", so the number of states is shown in FIG. 13 (b).
Is reduced to 32. Next, when the second symbol of w2 is input to the Viterbi decoding circuit 404, the contents of the first two registers are determined to be "01", so the number of states is reduced to 16 as shown in FIG. 13 (c). It

[0206] Hereinafter, the Viterbi decoding circuit 4 symbol by symbol
The number of states is halved each time it is input to 04, and when up to the sixth symbol of w2 is input to the Viterbi decoding circuit 404, the contents of all six registers are determined to be “000101”. As shown in FIG. After that, w
Until the 2nd 16th symbol is input, only the determined 1 state is valid, and the Viterbi decoding circuit 404 performs Viterbi decoding.

By the way, in the second embodiment, as shown in FIG. 7, Viterbi decoding is performed by validating only one fixed state for only the last 10 symbols of w2. In comparison with this, in the present embodiment, for example, 10 after w2
Only the 1 state in which the symbol is confirmed is valid, and the top 6
Viterbi decoding circuit 4 for each symbol
Each time it is input to 04, the number of states is halved. Therefore, for all 16 symbols of the TAB signal (after S / P conversion), the Viterbi decoding control at the time of switching the transmission mode is performed by utilizing the property of the fixed sequence.

Now, a method of implementing Viterbi decoding control in the TAB signal section (fixed sequence section) shown in FIG. 13 will be described. In error correction circuit 401 of the present embodiment, the transmission mode / slot information decoded by transmission control information decoding circuit 20010 is output to Viterbi decoder control circuit 403 as in the first embodiment. The Viterbi decoder control circuit 403 determines the fixed sequence symbol (TAB signal: w1, w by the transmission mode / slot information).
2, w3) is recognized. From the time when the first symbol of each TAB signal 16 symbols is input to the path memory 20021, the 16th symbol of each TAB signal is the path memory 20.
A state reduction signal is generated until A
Output to the CS circuit 405.

The ACS circuit 405 halves the number of states by one symbol for each of the leading 6 symbols of each TAB signal as described above, by the state reduction signal output from the Viterbi decoder control circuit 403, and then for the subsequent 10 symbols. Controls the path metric memory 20020 and the path memory 20021 so that only one confirmed state is valid. Further, the Viterbi decoder 402 performs the above-mentioned transmission mode switching, that is, TMCC (BPSK: r = 1 /
2) The operation similar to that of the Viterbi decoder 20002 of the conventional example is performed except for the control of the transmission mode B, and Viterbi decoded data is output.

With the configuration described above, Viterbi decoding control is performed by utilizing the property of the fixed symbol sequence of the TAB signals (w2, w3) after the TMCC (BPSK: r = 1/2) before switching the transmission mode. Therefore, the error correction circuit 401 according to the present embodiment blocks the influence of the transmission mode B after the mode switching, and the TMCC before the mode switching (BPSK: r =) that remains in the path memory 20021 when the transmission mode is switched.
It is possible to output Viterbi decoded data of 1/2).

As a result, the rear TAB signal (w2, w3)
Of the TMCC (BP) remaining in the path memory when the first symbol of
It is possible to reduce the error rate of SK: r = 1/2) (J-1) symbols. In addition, the same Viterbi decoding control is performed on the 16 symbols of the fixed symbol sequence of the previous TAB signal (w1) to obtain TMCC (BPSK: r).
= 1/2) transmission mode before mode switching, that is, TC-8
PSK (r = 2/3) or QPSK (r = 3/4, 1 /
2) or the effect of BPSK (r = 1/2) can be blocked.

As described above, the error correction circuit 401 according to the present embodiment has the front TAB signal (w1) and the rear TAB signal.
By performing the Viterbi decoding control method using 16 symbols (after S / P conversion) of each fixed symbol sequence of the signals (w2, w3), the TMCC (B shown in FIG.
For 128 symbols of actual symbol data (PSK: r = 1/2) (64 symbols after S / P conversion), the influence of the symbols in the transmission mode before and after is cut off, and BPSK (r
= 1/2), the error correction capability of convolutional coding originally possessed can be derived.

Further, as shown in FIG. 13, the number of states is halved each time the first 6 symbols are input to the path memory 20021 one symbol at a time. Therefore, TAB
For all 16 symbols of the signal, the Viterbi decoding control at the time of switching the transmission mode is performed by using the property of the fixed sequence, and compared with the second and third embodiments, TMCC (BP
The error rate of the actual symbol data of SK: r = 1/2) can be further reduced.

(Fifth Embodiment) An error correction circuit according to a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 14 shows an error correction circuit 50 according to this embodiment.
2 is a block diagram showing a configuration of No. 1. This error correction circuit 5
01 is different from the conventional example in the block shown by the thick solid line, and the error correction circuit 20001 shown in FIG.
A feature is that a Viterbi decoder control circuit 503 for generating a symbol coordinate conversion signal and an input symbol conversion circuit 506 controlled by the symbol coordinate conversion signal are added. The symbol coordinate conversion signal is a signal converted into demodulated I / Q data corresponding to a fixed symbol. The other blocks, that is, the Viterbi decoder 20002, the high / low hierarchy selection signal generation circuit 20003 to the channel selection circuit 20011 are provided, which is the same as that shown in FIG.

Error correction circuit 50 configured as described above
Each block of No. 1 and its operation will be described. However,
Regarding the operation after the output of the Viterbi decoder 20002,
The description is omitted because it is as shown in the conventional example.

FIG. 15 is a block diagram showing the configuration of the Viterbi decoder 20002 and the connection relationship between the Viterbi decoder 20002 and Viterbi decoder control circuit 303 and the input symbol conversion circuit 506. Viterbi decoder 20 of the present embodiment
002 has the same configuration as the Viterbi decoder of the conventional example shown in FIG.

In order to solve the problem to be solved by the invention described with reference to FIG. 118, the Viterbi decoding control method of the present embodiment at the time of switching the transmission mode, particularly the control method using the property of the fixed symbol sequence of the TAB signal explain.
In the error correction circuit 501 of the present embodiment, the transmission mode / slot information decoded by the transmission control information decoding circuit 20010 is output to the Viterbi decoder control circuit 503, as in the first embodiment. Viterbi decoder control circuit 503
Recognizes the TAB signals (w1, w2, w3) which are fixed sequence symbols by this transmission mode / slot information. As shown in FIG. 87 or FIG. 108, TMCC (BP
32 symbols (w) after the TAB signal after SK: r = 1/2
2 = xxx0B677h, or w3 = xxxF4988h), in the section in which the rear 20 symbols in which the state of the convolution circuit 10014 is fixed is input to the input symbol conversion circuit 506, a symbol coordinate conversion signal is generated to generate the input symbol conversion circuit. Output to 506.

The input symbol conversion circuit 506 converts the rear 20 symbols, in which the state of the convolution circuit 10014 is fixed, into I / Q data of the code point according to the symbol coordinate conversion signal output from the Viterbi decoder control circuit 503. , I / for other input symbols
The Q data is output to the Viterbi decoder 20002.

As shown in FIG. 87 or FIG. 108, TMC
Convolution circuit 1001 of 32 symbols (w1 = xxxECD28h) of the previous TAB signal of C (BPSK: r = 1/2)
The input symbol conversion circuit 506 also performs similar I / Q coordinate conversion for the rear 20 symbols whose state 4 is fixed.

I / in the input symbol conversion circuit 506
FIG. 16 shows how the Q data is converted. The input symbol conversion circuit 506 sets the I / Q coordinates of the input symbol output from the PSK demodulator (not shown) to "0" for the rear 20 symbols of the TAB signal in which the state of the convolution circuit 10014 is determined. "Or" 1 "
It is converted into I / Q coordinate data of the code point of "0" or "1" as shown in FIG. Then, the Viterbi decoder 20002 performs Viterbi decoding as in the conventional example, and outputs the Viterbi decoded data to the symbol / byte conversion circuit 20004.

As described above, for the rear 20 symbols of the TAB signal in which the state of the convolution circuit 10014 is determined, the I / Q coordinates having the code point and the distance of 0 are input to the Viterbi decoder 20002. become. That is, in the trellis diagram of Viterbi decoding, the convolution circuit 100
For the last 20 symbols whose 14 states are fixed, the branch metric input to the correct 1 state of the transformed code point is 0, and all other states produce very large branch metrics. In such a decoding method, as shown in FIG.
It can be considered that the control equivalent to the Viterbi decoding control method of the second embodiment shown in (a) to (c) is performed. That is, the branch metric input to all other states is much larger than the branch metric input to the determined one state (the state of the converted code point), so the determined one state is It will be automatically determined as the minimum path metric.

As described above, the error correction circuit 501 of the present embodiment has the front TAB signal (w1) and the rear TAB signal.
20 fixed symbol sequences for each signal (w2 or w3)
By performing the Viterbi decoding control method using the symbols, the effect of the symbols of the transmission mode before and after the actual symbol data of TMCC (BPSK: r = 1/2), that is, 128 symbols shown in FIG. It is possible to cut off completely and bring out the error correction capability of convolutional coding originally possessed by BPSK (r = 1/2).

In this embodiment, the Viterbi decoder 2000 is used.
Since the input symbol conversion circuit 506 is provided in the preceding stage of 2, the Viterbi decoder 20002 of FIG. 14 can use the Viterbi decoder of the conventional example as it is.

The function (effect) of the error correction circuit 501 of this embodiment was examined by simulation. FIG. 17 is a configuration diagram of a transmission frame used in the simulation. FIG. 17A shows an input format to the input symbol conversion circuit 506, where TMCC is a signal before S / P conversion.
FIG. 17B shows an input format to the path memory 20021, and TMCC is a signal after S / P conversion. The path memory length is 64 and the main signal after TMCC is TC-8PSK.
(R = 2/3) Only 64 symbols were used. The path memory 20021 is TC-8PSK immediately before the first symbol of TMCC is input by the main signal of 64 symbols.
(R = 2/3) 64 symbols are filled.

FIG. 18 shows the BER of the decoding result simulated under the above conditions. C / N = -1 dB, and the rear TAB signal (w2 or w3) is stored in the path memory 20021.
The BER for each symbol is calculated for the 64 symbols remaining in the path memory 20021 at the time when the final symbol is input. The horizontal axis is the path memory 200.
It shows the remaining 64 symbols in 21 and the vertical axis is BER
Indicates. As is clear from this figure, the error rate of each symbol remaining in the path memory 20021 is improved in “with termination processing” of the present embodiment as compared with “without termination processing” in the conventional example. It is understood that there is.

(Embodiment 6) An error correction circuit according to Embodiment 6 of the present invention will be described with reference to the drawings. FIG. 19 shows an error correction circuit 60 according to this embodiment.
2 is a block diagram showing a configuration of No. 1. In the error correction circuit 601 shown in FIG. 19, the block shown by the thick solid line is different from the conventional example. That is, the error correction circuit 20 of FIG.
A Viterbi decoder 1 controlled by a fixed branch signal and a definite state signal instead of the Viterbi decoder 20001 of 001
02 is provided, and a Viterbi decoder control circuit 603 for generating a fixed branch signal and a fixed state signal is newly added. The other blocks, that is, the high / low hierarchy selection signal generation circuit 20003 to the channel selection circuit 20011 are provided, which is the same as that shown in FIG.

Error correction circuit 60 configured as described above
The operation of No. 1 will be described. However, the Viterbi decoder 60
Since the operation after the output of 2 is as shown in the conventional example, the description is omitted.

FIG. 20 is a block diagram showing the configuration of the Viterbi decoder 602, and also shows the Viterbi decoder control circuit 603. The Viterbi decoder 602 has a de-punctured S / P circuit 20066 and a Viterbi decoding circuit 604 shown by a dotted line portion. Viterbi decoding circuit 60
4 is a branch metric calculation circuit 20018 and AC
An S circuit 605, a path metric memory 20020,
And a path memory 20021. The Viterbi decoder 602 of the present embodiment is different from the Viterbi decoder 202 of the second embodiment shown in FIG. 6 only in the internal configuration of the ACS circuit 605.

With respect to the problem to be solved by the invention described with reference to FIG. 118, a Viterbi decoding control method of the present embodiment at the time of switching a transmission mode, particularly a control method utilizing the property of a fixed symbol sequence of a TAB signal explain. In the error correction circuit 601 of the present embodiment, the transmission control information decoding circuit 20010 is the same as in the first embodiment.
The transmission mode / slot information decoded at is output to the Viterbi decoder control circuit 603. The Viterbi decoder control circuit 603 uses the same TA as the fixed sequence symbol according to the transmission mode / slot information, as in the second embodiment.
Recognize B signals (w1, w2, w3). As shown in FIG. 7A, from the time when the first symbols of the last 10 symbols of each TAB signal are input to the path memory 20021,
The tenth symbol of each TAB signal is the path memory 20021.
Until it is input to the
Output to the circuit 605.

As shown in FIGS. 7 (a) to 7 (c), the ACS circuit 605 uses the definite state signal output from the Viterbi decoder control circuit 603 to pass the path metric memory 20020 and the path metric memory 20020 in the same manner as in the second embodiment. The memory 20021 is controlled. Further, the Viterbi decoder control circuit 603 uses the first 6 symbols of each TAB signal, that is, the convolution circuit 10.
The signal until the 014 is set to the 1 state is the path memory 20.
For the section input to 021, a fixed branch signal is generated and output to the ACS circuit 605.

As shown in FIG. 10B, the ACS circuit 605 uses the fixed branch signal output from the Viterbi decoder control circuit 603 to perform the same operation as in the third embodiment for the first 6 symbols of each TAB signal. The path metric memory 20020 and the path memory 20021 are controlled.
Further, the Viterbi decoder 602 is the Viterbi decoder 2 shown in the conventional example except for the above-mentioned transmission mode switching, that is, TMCC (BPSK: r = 1/2) → transmission mode B control.
The same operation as 0002 is performed to output the Viterbi decoded data.

With the configuration described above, as in the second embodiment, TMCC (BPSK: r =
Viterbi decoding control is performed using the property of the fixed symbol sequence of the (1/2) TAB signal (w1, w2, or w3). Therefore, the error correction circuit 601 of the present embodiment completely cuts off the influence of the transmission mode B after the mode switching, and the TMCC (BPSK: r before the mode switching) remaining in the path memory 20021 at the time of the transmission mode switching. = 1/2) Viterbi decoded data can be output. And TMCC (B
The influence of the transmission mode before PSK: r = 1/2) mode switching can be completely cut off.

Further, in this embodiment, each TAB is
Viterbi decoding control by a fixed branch signal is performed for the first 6 symbols of the signal. Therefore, for all 16 symbols of the TAB signal, the Viterbi decoding control at the time of switching the transmission mode is performed using the property of the fixed sequence.
Compared with the second embodiment, TMCC (BPSK: r = 1
It is possible to further reduce the error rate of the actual symbol data of / 2).

(Embodiment 7) An error correction circuit according to Embodiment 7 of the present invention will be described with reference to the drawings. FIG. 21 shows the error correction circuit 70 according to the present embodiment.
2 is a block diagram showing a configuration of No. 1. In the error correction circuit 701 shown in FIG. 21, the block shown by a thick solid line is different from the conventional example, and instead of the Viterbi decoder 200002 of the error correction circuit 20001 of FIG. 98, a Viterbi decoder 702 controlled by a fixed branch signal is used. Is provided, and a Viterbi decoder control circuit 703 for generating a fixed branch signal and a symbol coordinate conversion signal and an input symbol conversion circuit 506 controlled by the symbol coordinate conversion signal are newly added. The other blocks, that is, the high / low hierarchy selection signal generation circuit 20003 to the channel selection circuit 20011 are provided, which is the same as that shown in FIG.

The error correction circuit 70 configured as described above.
Each block of No. 1 and its operation will be described. However,
The operation after the output of the Viterbi decoder 702 is as described in the conventional example, and thus the description thereof is omitted.

FIG. 22 is a block diagram showing the configuration of the Viterbi decoder 702, which also shows the Viterbi decoder control circuit 703 and the input symbol conversion circuit 506. The Viterbi decoder 702 uses the de-punctured S / P circuit 20.
016 and a Viterbi decoding circuit 704 indicated by a dotted line portion. The Viterbi decoding circuit 704 includes a branch metric calculation circuit 20018, an ACS circuit 705, a path metric memory 20020, and a path memory 20021.
And have. Viterbi decoder 702 according to the present embodiment
Is a Viterbi decoder 2000 according to the fifth embodiment shown in FIG.
Compared to 2, only the internal configuration of the ACS circuit 705 is changed.

With respect to the problem to be solved by the invention described with reference to FIG. 118, a Viterbi decoding control method of the present embodiment at the time of switching a transmission mode, particularly a control method using the property of a fixed symbol sequence of a TAB signal explain. In the error correction circuit 701 of this embodiment, the transmission control information decoding circuit 20010 is the same as in the first embodiment.
The transmission mode / slot information decoded at is output to the Viterbi decoder control circuit 703. The Viterbi decoder control circuit 703 recognizes the TAB signals (w1, w2, w3) that are fixed sequence symbols based on the transmission mode / slot information. As shown in FIG. 87 or FIG. 108, TMCC
Of the 32 symbols (w2 = xxx0B677h or w3 = xxxF4988h) behind the TAB signal after (BPSK: r = 1/2),
With respect to the section in which the rear 20 symbols in which the state of the convolution circuit 10014 is fixed is input to the input symbol conversion circuit 506, a symbol coordinate conversion signal is generated and output to the input symbol conversion circuit 506.

Input symbol conversion circuit 506 performs the same operation as in the fifth embodiment and outputs I / Q data to Viterbi decoder 702. Also, the Viterbi decoder control circuit 70
3 is the top 6 symbols of each TAB signal, that is, the path memory 2 until the state of the convolution circuit 10014 is fixed to 1 state.
For the section input to 0021, a fixed branch signal is generated and output to the ACS circuit 705. And ACS
The circuit 705 controls the path metric memory 20020 and the path memory 20021 for the first 6 symbols of each TAB signal by the fixed branch signal output from the Viterbi decoder control circuit 703 in the same manner as in the third embodiment. . Further, the Viterbi decoder 702 performs the above-mentioned transmission mode switching, that is, TMCC (BPSK: r = 1 /
2) The operation similar to that of the Viterbi decoder 20002 shown in the conventional example is performed except for the control of the transmission mode B, and the Viterbi decoded data is output.

With the configuration described above, as in the fifth embodiment, TMCC (BPSK: r =
Viterbi decoding control is performed using the property of the fixed symbol sequence of the (1/2) TAB signal (w1, w2, or w3). Therefore, the error correction circuit 701 of the present embodiment blocks the influence of the transmission mode B after the mode switching, and the TMCC before the mode switching (BPSK: r = 1) remaining in the path memory 20021 at the time of the transmission mode switching. / 2) Viterbi decoded data can be output. And TMCC (BPS
The influence of the transmission mode before the mode switching of K: r = 1/2) can also be blocked.

Furthermore, in this embodiment, each TAB is
Viterbi decoding control by a fixed branch signal is performed for the first 6 symbols of the signal. Therefore, for all 16 symbols of the TAB signal, the Viterbi decoding control at the time of switching the transmission mode is performed by using the property of the fixed sequence, and compared with the fifth embodiment, TMCC (BPSK: r = 1 /
It is possible to further reduce the error rate of the real symbol data of 2).

(Embodiment 8) An error correction circuit according to Embodiment 8 of the present invention will be described with reference to the drawings. FIG. 23 shows an error correction circuit 80 according to this embodiment.
2 is a block diagram showing a configuration of No. 1. In the error correction circuit 801 shown in FIG. 23, the block shown by the thick solid line is different from the conventional example, and is controlled by a state reduction signal and a definite state signal instead of the Viterbi decoder 200002 of the error correction circuit 20001 of FIG. A Viterbi decoder 802 is provided,
The feature is that a Viterbi decoder control circuit 803 for generating a state reduction signal and a definite state signal is newly added. Each other block, that is, the high / low hierarchy selection signal generation circuit 2
The fact that the channel selection circuit 2001 to 0003 are provided is the same as that shown in FIG.

Error correction circuit 80 configured as described above
Each block of No. 1 and its operation will be described. However,
The operation after the output of the Viterbi decoder 802 is the same as that shown in the conventional example, and the description thereof is omitted.

FIG. 24 is a block diagram showing the configuration of the Viterbi decoder 802, and the Viterbi decoder control circuit 803 is also shown. The Viterbi decoder 802 has a de-punctured S / P circuit 20066 and a Viterbi decoding circuit 804 shown by a dotted line portion. Viterbi decoding circuit 8
Reference numeral 04 denotes a branch metric calculation circuit 20018 and A
CS circuit 805 and path metric memory 20020
And a path memory 20021. The Viterbi decoder 802 according to the present embodiment is different from the Viterbi decoder 202 according to the second embodiment shown in FIG.
Only the internal structure of 5 has changed.

With respect to the problem to be solved by the invention described with reference to FIG. 118, the Viterbi decoding control method of the present embodiment at the time of switching the transmission mode, particularly the control method utilizing the property of the fixed symbol sequence of the TAB signal explain. In the error correction circuit 801 of this embodiment, the transmission control information decoding circuit 20010 is the same as in the first embodiment.
The transmission mode / slot information decoded in (3) is output to the Viterbi decoder control circuit 803.

Like the second embodiment, the Viterbi decoder control circuit 803 uses the transmission mode / slot information output from the transmission control information decoding circuit 20010 to determine the TAB signals (w1, w2, w3) that are fixed sequence symbols. ) Is recognized. As shown in FIG. 7A, the first symbol of the last 10 symbols of each TAB signal is the path memory 2002.
The fixed state signal is generated and output to the ACS circuit 805 from the time of being input to 1 to the time of inputting the tenth symbol of each TAB signal to the path memory 20021.

The ACS circuit 805 is shown in FIGS.
As shown in FIG. 5, the path state memory 20020 and the path memory 20021 are used in the same manner as in the second embodiment by the definite state signal output from the Viterbi decoder control circuit 803.
Control. Further, the Viterbi decoder control circuit 803
The first 6 symbols of each TAB signal, that is, the convolution circuit 1
Is stored in the path memory 200 until 0014 is set to 1 state.
For the section input to 21, the state reduction signal is generated and output to the ACS circuit 805.

The ACS circuit 805 receives each TAB signal according to the state reduction signal output from the Viterbi decoder control circuit 803.
For the first 6 symbols of the signal, the path metric memory 20020 and the path memory 20021 are controlled in the same manner as in the fourth embodiment, and as shown in FIG. 13, the number of states until the convolution circuit 10014 is determined to be 1 state. Is cut in half. Further, the Viterbi decoder 802 performs the above-described transmission mode switching, that is, TMCC (BPSK:
Other than the control of the transmission mode B, the same operation as the Viterbi decoder 20002 of the conventional example is performed and Viterbi decoded data is output.

With the configuration described above, as in the second embodiment, TMCC (BPSK: r =
Viterbi decoding control is performed using the property of the fixed symbol sequence of the (1/2) TAB signal (w1, w2, or w3). Therefore, the error correction circuit 801 of the present embodiment completely cuts off the influence of the transmission mode B after the mode switching, and the TMCC (BPSK: r) before the mode switching remaining in the path memory 20021 at the time of the transmission mode switching. = 1/2) Viterbi decoded data can be output. And TMCC (B
The influence of the transmission mode before PSK: r = 1/2) mode switching is completely cut off.

Further, in this embodiment, each TAB is
Viterbi decoding control by the state reduction signal is performed for the first 6 symbols of the signal. Therefore, for all 16 symbols of the TAB signal, the Viterbi decoding control at the time of switching the transmission mode is performed by using the property of the fixed sequence, and compared to the second embodiment, TMCC (BPSK: r = 1). /
It is possible to further reduce the error rate of the real symbol data of 2).

(Ninth Embodiment) An error correction circuit according to a ninth embodiment of the present invention will be described with reference to the drawings. FIG. 25 shows an error correction circuit 90 according to this embodiment.
2 is a block diagram showing a configuration of No. 1. In the error correction circuit 901 shown in FIG. 25, the block shown by a thick solid line is different from the conventional example and is controlled by a state reduction signal and a fixed branch signal instead of the Viterbi decoder 200002 of the error correction circuit 20001 of FIG. The feature is that a Viterbi decoder 902 is provided and a Viterbi decoder control circuit 903 for generating a state reduction signal and a fixed branch signal is newly added. The other blocks, that is, the high / low hierarchy selection signal generation circuit 20003 to the channel selection circuit 20011 are provided, which is the same as that shown in FIG.

Error correction circuit 90 configured as described above
Each block of No. 1 and its operation will be described. However,
The operation after the output of the Viterbi decoder 902 is the same as that shown in the conventional example, and the description thereof is omitted.

FIG. 26 is a block diagram showing the configuration of the Viterbi decoder 902, and the Viterbi decoder control circuit 903 is also shown. The Viterbi decoder 902 includes a de-punctured S / P circuit 20066 and a Viterbi decoding circuit 904 shown by a dotted line portion. Viterbi decoding circuit 9
Reference numeral 04 denotes a branch metric calculation circuit 20018 and A
CS circuit 905 and path metric memory 20020
And a path memory 20021. The Viterbi decoder 902 of this embodiment is different from the Viterbi decoder 302 of the third embodiment shown in FIG.
Only the internal structure of 5 has changed.

With respect to the problem to be solved by the invention described with reference to FIG. 118, the Viterbi decoding control method of the present embodiment at the time of switching the transmission mode, particularly the control method utilizing the property of the fixed symbol sequence of the TAB signal explain. In the error correction circuit 901 of this embodiment, the transmission control information decoding circuit 20010 is the same as in the first embodiment.
The transmission mode / slot information decoded at is output to the Viterbi decoder control circuit 903. The Viterbi decoder control circuit 903 uses the same TA as the fixed sequence symbol according to the transmission mode / slot information as in the third embodiment.
Recognize B signals (w1, w2, w3). A fixed branch signal is generated and output to the ACS circuit 905 from the time when the first symbol of each 16-tab signal is input to the path memory 20021 to the time when the 16-th symbol of each TAB signal is input to the path memory 20021. To do.

As shown in FIG. 10, the ACS circuit 905 controls the path metric memory 20020 and the path memory 20021 by the fixed branch signal output from the Viterbi decoder control circuit 903 in the same manner as in the third embodiment. To do. Also, the Viterbi decoder control circuit 903 determines that each T
The first 6 symbols of the AB signal, that is, the convolution circuit 100
AC is generated by generating a state reduction signal for the section in which the path memory 20021 is input until 14 is set to 1 state.
Output to the S circuit 905.

As shown in FIG. 13, the ACS circuit 905 uses the state reduction signal output from the Viterbi decoder control circuit 903 to pass the first 6 symbols of each TAB signal in the same manner as in the fourth embodiment. The metric memory 20020 and the path memory 20021 are controlled, and the number of states is reduced by half until the convolution circuit 10014 is set to one state. Also, the Viterbi decoder 902
At the time of transmission mode switching shown above, that is, TMCC (BPS
K: r = 1/2) → Except for the control of the transmission mode B, the same operation as the Viterbi decoder 20002 of the conventional example is performed to output the Viterbi decoded data.

With the configuration described above, the TMCC (BPSK: r =
Viterbi decoding control using all the fixed symbol sequences of the (1/2) TAB signal (w1, w2, or w3) is performed. Therefore, the error correction circuit 901 according to the present embodiment blocks the influence of the transmission mode B after the mode switching, and the TMCC before the mode switching (BPSK: r = 1) remaining in the path memory 20021 at the time of the transmission mode switching. / 2) Viterbi decoded data can be output. And TMCC (BPSK:
The influence of the transmission mode before mode switching (r = 1/2) is completely cut off.

Further, in this embodiment, each TAB is
Viterbi decoding control by the state reduction signal is performed for the first 6 symbols of the signal. Therefore, for all 16 symbols of the TAB signal, it is possible to perform the Viterbi decoding control at the time of switching the transmission mode by double utilizing the property of the fixed sequence, such as fixed branch and state reduction. Therefore, as compared with the third embodiment, TMCC (BPSK: r = 1/2)
The error rate of the actual symbol data can be further reduced.

(Embodiment 10) Embodiment 1 of the present invention
The error correction circuit for 0 will be described with reference to the drawings. FIG. 27 is a block diagram showing the configuration of error correction circuit 1001 in the present embodiment. In the error correction circuit 1001 shown in FIG. 27, the block shown by the thick solid line is different from the conventional example, and the error correction circuit 2000 shown in FIG.
In place of the Viterbi decoder 20002 of No. 1, a Viterbi decoder 1002 controlled by a state reduction signal is provided, and a Viterbi decoder control circuit 1003 for generating a state reduction signal and a symbol coordinate conversion signal and a symbol coordinate conversion signal are used for control. The feature is that a new input symbol conversion circuit 506 is added. The other blocks, that is, the high / low hierarchy selection signal generation circuit 20003 to the channel selection circuit 20011 are provided, which is the same as that shown in FIG.

The error correction circuit 10 configured as described above.
Each block 01 and its operation will be described. However, the operation after the output of the Viterbi decoder 1002 is as described in the conventional example, and thus the description thereof is omitted.

FIG. 28 is a block diagram showing the configuration of the Viterbi decoder 1002, and the Viterbi decoder control circuit 1003 and the input symbol conversion circuit 506 are also shown.
The Viterbi decoder 1002 includes a de-punctured S / P circuit 20066 and a Viterbi decoding circuit 100 shown by a dotted line portion.
4 and. The Viterbi decoding circuit 1004 includes a branch metric calculation circuit 20018 and an ACS circuit 10.
05, a path metric memory 20020, and a path memory 20021. The Viterbi decoder 1002 according to the present embodiment is the Viterbi decoder 2 according to the fifth embodiment.
Compared with 0002, only the internal configuration of the ACS circuit 1005 has changed.

With respect to the problem to be solved by the invention described with reference to FIG. 118, the Viterbi decoding control method of the present embodiment at the time of switching the transmission mode, particularly the control method utilizing the property of the fixed symbol sequence of the TAB signal explain. In the error correction circuit 1001 of this embodiment,
Similar to the first embodiment, the transmission control information decoding circuit 2001
The transmission mode / slot information decoded at 0 is output to the Viterbi decoder control circuit 1003.

The Viterbi decoder control circuit 1003 is similar to the fifth embodiment in transmission control information decoding circuit 20010.
TAB signals (w1, w2, w3) that are fixed sequence symbols according to the transmission mode / slot information output from
Recognize. As shown in FIG. 87 or FIG. 108, TMC
After TAB signal of 32 symbols (w2 = xxx0B677h or w3 = xxxF4988h) after C (BPSK: r = 1/2), the rear 2 where the state of the convolution circuit 10014 is determined
For a section in which 0 symbol is input to the input symbol conversion circuit 506, a symbol coordinate conversion signal is generated and output to the input symbol conversion circuit 506. The input symbol conversion circuit 506 performs the same operation as in the fifth embodiment,
The I / Q data is output to the Viterbi decoder 1002.

Also, the Viterbi decoder control circuit 1003 is
The first 6 symbols of each TAB signal, that is, the convolution circuit 1
Path memory 2002 until 0014 is set to 1 state
For the section input to 1, the state reduction signal is generated and output to the ACS circuit 1005. ACS circuit 1005
The state reduction signal output from the Viterbi decoder control circuit 1003 controls the path metric memory 20020 and the path memory 20021 for the first 6 symbols of each TAB signal in the same manner as in the fourth embodiment. The number of states is reduced by half until the convolutional circuit 10014 is set to one state, as shown at 13. Further, the Viterbi decoder 1002 performs the same operation as the Viterbi decoder 20002 of the conventional example except for the above-mentioned transmission mode switching, that is, TMCC (BPSK: r = 1/2) → control of the transmission mode B. And outputs the Viterbi decoded data.

With the configuration shown above, as in the fifth embodiment, TMCC (BPSK: r =
Viterbi decoding control using a fixed symbol sequence of the (1/2) TAB signal (w1, w2, or w3) is performed. Therefore,
The error correction circuit 1001 of the present embodiment completely cuts off the influence of the transmission mode B after the mode switching, and the TMCC before the mode switching (BPSK: r = 1) remaining in the path memory 20021 at the time of the transmission mode switching. / 2) Viterbi decoded data can be output. And TMCC (BPS
The influence of the transmission mode before the mode switching of K: r = 1/2) is completely cut off.

Further, in this embodiment, each TAB is
Viterbi decoding control by the state reduction signal is performed for the first 6 symbols of the signal. Therefore, for all 16 symbols of the TAB signal, the Viterbi decoding control at the time of switching the transmission mode is performed using the property of the fixed sequence. Therefore, as compared with the fifth embodiment, TMCC (BPSK: r = 1
It is possible to further reduce the error rate of the actual symbol data of / 2).

(Embodiment 11) Embodiment 1 of the present invention
The error correction circuit in 1 will be described with reference to the drawings. FIG. 29 is a block diagram showing the structure of the error correction circuit 1101 in this embodiment. In the error correction circuit 1101 shown in FIG. 29, the block shown by a thick solid line is different from the conventional example, and the error correction circuit 2000 shown in FIG.
1 Viterbi decoder 20002 instead of the state reduction signal,
A Viterbi decoder 1102 controlled by a fixed branch signal and a definite state signal is provided, and a Viterbi decoder control circuit 1103 that generates a state reduction signal, a fixed branch signal, and a definite state signal is newly added. is there. Each other block, that is, the high / low hierarchy selection signal generation circuit 2
The fact that the channel selection circuit 2001 to 0003 are provided is the same as that shown in FIG.

Error correction circuit 11 configured as described above
Each block 01 and its operation will be described. However, the operation after the output of the Viterbi decoder 1102 is as described in the conventional example, and thus the description thereof is omitted.

FIG. 30 is a block diagram showing the configuration of the Viterbi decoder 1102, and also shows the Viterbi decoder control circuit 1103. As shown in FIG. 30, the Viterbi decoder 1102 includes a de-punctured S / P circuit 2001.
6 and a Viterbi decoding circuit 1104 shown by a dotted line portion. The Viterbi decoding circuit 1104 includes a branch metric calculation circuit 20018, an ACS circuit 1105, a path metric memory 20020, and a path memory 2002.
1 and. That is, the Viterbi decoder 1102 of the present embodiment is different from the Viterbi decoder 202 of the second embodiment only in the internal configuration of the ACS circuit 1105.

With respect to the problem to be solved by the invention described with reference to FIG. 118, the Viterbi decoding control method of the present embodiment at the time of switching the transmission mode, particularly the control method utilizing the property of the fixed symbol sequence of the TAB signal explain.

In error correction circuit 1101 of the present embodiment, the transmission mode / slot information of FIG. 82 decoded in transmission control information decoding circuit 20010 is output to Viterbi decoder control circuit 1103 as in the first embodiment. To be done. The Viterbi decoder control circuit 1103 recognizes the TAB signals (w1, w2, w3), which are fixed sequence symbols, based on the transmission mode / slot information, as in the second embodiment. As shown in FIG. 7 (a), one after each TAB signal
Since the first symbol of 0 symbol is input to the path memory 20021, the 10th symbol (S
The final state signal after the / P conversion) is input to the path memory 20021 and the definite state signal is generated to
Output to the CS circuit 1105.

The ACS circuit 1105 is shown in FIG.
As shown in (c), the determinate state signal output from the Viterbi decoder control circuit 1103 causes the path metric memory 20020 and the path memory 2 to operate in the same manner as in the second embodiment.
The control of 0021 is performed. Also, the Viterbi decoder control circuit 1
103 generates a fixed branch signal and a state reduction signal for the leading 6 symbols of each TAB signal, that is, a section in which the convolution circuit 10014 is input into the path memory 20021 until the state is determined to be 1 and generates an ACS circuit 1105.
Output to.

The ACS circuit 1105 uses the fixed branch signal output from the Viterbi decoder control circuit 1103, as shown in FIG. 10B, for the first 6 symbols of each TAB signal as in the third embodiment. The path metric memory 20020 and the path memory 20021 are controlled. Further, the ACS circuit 1105 receives each TA by the state reduction signal output from the Viterbi decoder control circuit 1103.
For the first 6 symbols of the B signal, the path metric memory 20020 and the path memory 20021 are controlled in the same manner as in the fourth embodiment, and the number of states is determined until the convolution circuit 10014 is set to one state as shown in FIG. Is cut in half. Also, the Viterbi decoder 1102 uses the above-mentioned transmission mode switching, that is, TMCC (BPS).
K: r = 1/2) → Except for the control of the transmission mode B, the same operation as the Viterbi decoder 20002 of the conventional example is performed to output the Viterbi decoded data.

With the configuration described above, as in the second embodiment, TMCC (BPSK: r =
Viterbi decoding control is performed using the property of the fixed symbol sequence of the (1/2) TAB signal (w1, w2, or w3). Therefore, the error correction circuit 1101 of the present embodiment completely cuts off the influence of the transmission mode B after the mode switching, and the TMCC (BPSK: r) before the mode switching remaining in the path memory 20021 at the time of the transmission mode switching. = 1/2) Viterbi decoded data can be output. And TMCC
The influence of the transmission mode before (BPSK: r = 1/2) mode switching can be completely cut off.

Further, in this embodiment, each TAB is
Viterbi decoding control by the fixed branch signal and the state reduction signal is performed for the first 6 symbols of the signal. Therefore, TA
For all 16 symbols of the B signal, it means that the Viterbi decoding control at the time of switching the transmission mode is performed using the property of the fixed sequence, and compared with the second and sixth embodiments, the TMC
It is possible to further reduce the error rate of C (BPSK: r = 1/2) real symbol data.

(Embodiment 12) Embodiment 1 of the present invention
The error correction circuit in 2 will be described with reference to the drawings. FIG. 31 is a block diagram showing the configuration of the error correction circuit 1201 in this embodiment. In the error correction circuit 1201 shown in FIG. 31, the block shown by the thick solid line is different from the conventional example, and the error correction circuit 2000 shown in FIG.
1 Viterbi decoder 20002 instead of 1 Viterbi decoder 1202 controlled by state reduction signal and fixed branch signal
And a Viterbi decoder control circuit 1 for generating a state reduction signal, a fixed branch signal, and a symbol coordinate conversion signal.
A feature is that 203 and an input symbol conversion circuit 506 controlled by a symbol coordinate conversion signal are newly added. The other blocks, that is, the high / low hierarchy selection signal generation circuit 20003 to the channel selection circuit 20011 are provided, which is the same as that shown in FIG.

Error correction circuit 12 configured as described above
Each block 01 and its operation will be described. However, the operation after the output of the Viterbi decoder 1202 is as shown in the conventional example, and the description thereof is omitted.

FIG. 32 is a block diagram showing the configuration of the Viterbi decoder 1202, and also shows the Viterbi decoder control circuit 1203 and the input symbol conversion circuit 506. The Viterbi decoder 1202 includes a de-punctured S / P circuit 20066 and a Viterbi decoding circuit 1204 indicated by a dotted line portion.
And have. The Viterbi decoding circuit 1204 includes a branch metric calculation circuit 20018 and an ACS circuit 120.
5, a path metric memory 20020, and a path memory 20021. That is, the Viterbi decoder 1202 of the present embodiment is the Viterbi decoder 20 of the fifth embodiment.
Compared with 002, only the internal configuration of the ACS circuit 1205 has changed.

With respect to the problem to be solved by the invention described with reference to FIG. 118, a Viterbi decoding control method of the present embodiment at the time of switching a transmission mode, particularly a control method utilizing the property of a fixed symbol sequence of a TAB signal explain.

In error correction circuit 1201 of the present embodiment, the transmission mode / slot information of FIG. 82 decoded by transmission control information decoding circuit 20010 is sent to Viterbi decoder control circuit 1203 as in the first embodiment. Is output. The Viterbi decoder control circuit 1203 recognizes the TAB signals (w1, w2, w3) which are fixed sequence symbols based on the transmission mode / slot information, as in the fifth embodiment. As shown in FIG. 87 or FIG. 108, TMCC
Of the 32 symbols (w2 = xxx0B677h or w3 = xxxF4988h) behind the TAB signal after (BPSK: r = 1/2),
For the section in which the rear 20 symbols in which the state of the convolution circuit 10014 is determined is input to the input symbol conversion circuit 506, a symbol coordinate conversion signal is generated and output to the input symbol conversion circuit 506.

The input symbol conversion circuit 506 performs the same operation as that of the fifth embodiment as shown in FIG.
The data is output to the Viterbi decoder 1202. Further, the Viterbi decoder control circuit 1203 outputs the fixed branch signal and the state reduction signal for the first 6 symbols of each TAB signal, that is, the section in which the convolution circuit 10014 is input to the path memory 20021 until the state is set to one. Generate A
Output to the CS circuit 1205. The ACS circuit 1205 is
As shown in FIG. 10B, the Viterbi decoder control circuit 12
The fixed branch signal output from the
For the first 6 symbols of the signal, the path metric memory 20020 and the path memory 20021 are controlled in the same manner as in the third embodiment. Further, the ACS circuit 1205
Is the Viterbi decoder control circuit 120, as shown in FIG.
In accordance with the state reduction signal output from No. 3, the leading 6 symbols of each TAB signal are processed in the same manner as in the fourth embodiment, the path metric memory 20020 and the path memory 20.
The control of 021 is performed, and the number of states is reduced by half until the convolutional circuit 10014 determines the one state.

The Viterbi decoder 1202 also performs the above-described transmission mode switching, that is, TMCC (BPSK: r =
1/2) → Except for the control of transmission mode B, the Viterbi decoder 20002 of the conventional example performs the same operation and outputs Viterbi decoded data.

With the configuration shown above, as in the fifth embodiment, TMCC (BPSK: r =
Viterbi decoding control is performed using the property of the fixed symbol sequence of the (1/2) TAB signal (w1, w2, or w3). Therefore, the error correction circuit 1201 according to the present embodiment blocks the influence of the transmission mode B after the mode switching, and the TMCC before the mode switching (BPSK: r = 1) remaining in the path memory 20021 at the time of the transmission mode switching. / 2) Viterbi decoded data can be output. And TMCC (BPS
The influence of the transmission mode before the mode switching of K: r = 1/2) can also be blocked.

Further, in this embodiment, each TAB is
Viterbi decoding control by the fixed branch signal and the state reduction signal is performed for the first 6 symbols of the signal. Therefore, TA
For all 16 symbols of the B signal, the Viterbi decoding control at the time of switching the transmission mode is performed by utilizing the property of the fixed sequence, and compared with the fifth or seventh embodiment, the TM
The error rate of CC (BPSK: r = 1/2) real symbol data can be further reduced.

(Embodiment 13) Embodiment 1 of the present invention
The error correction circuit in No. 3 will be described with reference to the drawings. FIG. 33 is a block diagram showing the configuration of the error correction circuit 1301 in this embodiment. In the error correction circuit 1301 shown in FIG. 33, the block shown by a thick solid line is different from the conventional example, and a de-interleave circuit 1302 and a channel selection circuit 1303 having different internal configurations are provided, and the de-interleave circuit 1302 is a channel selection circuit. It is characterized in that it is configured to be controlled by the slot selection signal output from 1303. Each of the other blocks, that is, the Viterbi decoder 20002 to the symbol / byte conversion circuit 20004,
MPEG sync byte / dummy slot insertion circuit 200
06 to each function of the transmission control information decoding circuit 20010 are the same as those shown in FIG.

Error correction circuit 13 configured as described above
Each block 01 and its operation will be described. However, the operation before the input of the de-interleave circuit 1302 and the operation after the output of the de-interleave circuit 1302 are as described in the conventional example, and thus the description thereof is omitted.

FIG. 34 shows the deinterleave circuit 1302.
3 is a block diagram showing a configuration example of FIG. The de-interleave circuit 1302 has a write address generation circuit 1304.
And a read address generation circuit 1305 and a memory circuit 1306. Note that the memory circuit 1306 according to the present embodiment has 24 units in order to perform de-interleaving.
It is assumed that a memory area for 2 banks of × 8 slots is used.

As described in the problem to be solved by the invention, the conventional de-interleave circuit 20005 performs de-interleaving by using an unnecessary memory area. The de-interleave circuit of the present embodiment is configured to solve this problem. The operation of this embodiment will be described below.

Similarly to the conventional example, the data sequence input to the de-interleave circuit 1302 is TS1: <higher layer image> TC-8PSK: 22 slots <lower layer per 1 frame (48 slots). Image> QPSK (r = 1/2): 2 slots (1 dummy slot) TS2: <Higher layer image> TC-8PSK: 20 slots <Lower layer image> BPSK (r = 1/2): 4 It is assumed that two kinds of TSs of slots (including 3 dummy slots) are input as shown in FIG. 108 (b).

In the conventional example, as shown in FIG. 109, the entire input data sequence of 48 slots per frame was written to and read from the memory circuit 20028 of FIG. 110. Therefore, the output data sequence from the de-interleave circuit 20005 is shown in FIG.
It was like (a).

On the other hand, in the de-interleave circuit 1302 of the present embodiment, 1TS selected by the slot selection signal output from the channel selection circuit 1303, in this example, a data sequence of only 24 slots / frame Are written in and read from the memory circuit 1306. Therefore, the write address generation circuit 1 of FIG.
The 304 and read address generation circuit 1305 generate only the addresses corresponding to the selected 1TS slots, and output them to the memory circuit 1306. The address of the slot corresponding to the unselected TS is free run. Therefore, the de-interleave circuit 130
The output data sequence from No. 2 is as shown in FIG.

With the above configuration, the interleave circuit 1302 of the present embodiment reduces the memory area to be used by half by writing and reading the input data sequence of only the selected 1TS in the memory circuit 1306. be able to.

In the present embodiment, TS1, TS2
Both of them occupy 24 slots per frame, but for example, if the maximum number of slots per frame occupied by one TS is determined in the BS digital broadcasting standard, the maximum number of slots × 8 slots It suffices to prepare a memory area for two banks, and the memory area used by the memory circuit 1306 is not limited to two banks of 24 × 8 slots as in this embodiment.

In the above embodiment, the data series input to the de-interleave circuit 1302 is two types of TS per frame (48 slots), and one type of TS is selected. Here, for example, TS1: <higher layer image> TC-8PSK: 14 slots <lower layer image> QPSK (r = 1/2): 2 slots (including 1 dummy slot) TS2: <higher layer image> TC-8PSK: 12 slots <Lower layer image> QPSK (r = 3/4): 4 slots (1 dummy slot) TS3: <Higher layer image> TC-8PSK: 12 slots <Lower layer image> BPSK (r = 1/2): Consider a case where three types of TS of 4 slots (including 3 dummy slots) are input. That is, 3TS is assigned to one transponder. When one type of TS is selected, only the selected 1TS may be written into and read from the memory circuit 1306 as described above. When two types of TS are selected, for example, when one 1TS is displayed on the monitor and the other 1TS is video-recorded, only the selected 2TS is stored in the memory circuit 130.
6 may be written to and read from. In this case,
1 occupied by 1TS in the BS digital broadcasting standard
If the maximum number of slots per frame is fixed,
It suffices to prepare a memory area for two banks of the maximum number of slots × 8 × 2 slots. Besides, for example, 8 types of TS
Is also input, and the same applies when four types of TS are selected.

(Embodiment 14) Embodiment 1 of the present invention
The error correction circuit in No. 4 will be described with reference to the drawings. FIG. 36 is a block diagram showing the configuration of error correction circuit 1401 in this embodiment. In the error correction circuit 1401 shown in FIG. 36, the block shown by a thick solid line is different from the conventional example, and a de-interleave circuit 1402, a de-randomize circuit 1407, and a channel selection circuit 1403 are provided, and the de-interleave circuit 1403 is provided. The circuit 1402 and the de-randomize circuit 1407 are channel selection circuits 1.
It is characterized in that it is configured to be controlled by the slot selection signal output by 403 and that the speed conversion circuit 20009 is deleted. Each other block, that is, the Viterbi decoder 20002 to the symbol / byte conversion circuit 2000
4. MPEG sync byte / dummy slot insertion circuit 2
The respective functions of the 0006, the RS decoding circuit 20008, and the transmission control information decoding circuit 20010 are the same as those shown in FIG.

The error correction circuit 14 configured as described above
Each block 01 and its operation will be described. However, the operation before the input of the de-interleave circuit 1402 and the operation after the output of the de-randomize circuit 1407 are as described in the conventional example, and thus the description thereof is omitted.

FIG. 37 shows the de-interleave circuit 1402.
3 is a block diagram showing a configuration example of FIG. The de-interleave circuit 1402 has a write address generation circuit 1404.
And a read address generation circuit 1405 and a memory circuit 1406. Note that the memory circuit 1406 of the present embodiment is provided with 24 units in order to perform de-interleaving.
It is assumed that a memory area for 2 banks of × 8 slots is used.

As described in the problem to be solved by the invention, the conventional error correction circuit 20001 has an unnecessary speed conversion circuit. The de-interleave circuit and the de-randomize circuit 1407 of this embodiment are configured to solve this problem.

As in the case of the conventional example, the data sequence input to the de-interleave circuit 1402 is shown in FIG.
As shown in (b), TS1: <higher layer image> TC-8PSK: 22 slots per 1 frame (48 slots) <lower layer image> QPSK (r = 1/2): 2 slots (of which: Dummy 1 slot) TS2: <Higher layer image> TC-8PSK: 20 slots <Lower layer image> BPSK (r = 1/2): 4 slots (including 3 dummy slots) are input. Shall be.

In the conventional example, the output data series from the deinterleave circuit 20005 is as shown in FIG. 38 (a). Further, in the above-described thirteenth embodiment, as the output data sequence from the de-interleave circuit 1302, slots corresponding to the TS selected as shown in FIG.

The thirteenth embodiment is the same as the thirteenth embodiment.
Similarly, the 1TS selected by the slot selection signal output from the tuning circuit 1403, in the case of this example, the data series of only 24 slots / frame is stored in the memory circuit 14
Control is performed so that writing is performed in 06. Therefore, the write address generation circuit 1404 generates only the address corresponding to the selected 1TS slot and outputs it to the memory circuit 1406. The address of the slot corresponding to the unselected TS is free run.

Also, the data sequence of only 1TS selected by the slot selection signal output from the channel selection circuit 1403 is not bursted from the memory circuit 1406,
Control is performed so that reading is performed continuously. Therefore, the read address generation circuit 1405 determines that the selected 1TS
Only the address corresponding to the slot of the memory circuit 140 is generated at a half speed (= 24/48) of the writing speed.
Output to 6. The address of the slot corresponding to the TS not selected is not generated and is skipped. The output data sequence from the de-interleave circuit 1402 in this case is as shown in FIG. 38 (b).

With the above configuration, the interleave circuit 1402 of the present embodiment reduces the memory area to be used by half by writing and reading the input data sequence of only the selected 1TS to the memory circuit 1406. be able to. Also, the interleave circuit 1402 performs speed conversion and outputs the deinterleaved data sequence to the MPEG sync byte / dummy slot insertion circuit 20006.

In the above embodiment, TS1, TS
Both 2 occupy 24 slots per frame, but if the maximum number of slots per frame occupied by one TS is determined in the BS digital broadcasting standard, for example, the maximum number of slots x 8 slots It is only necessary to prepare a memory area for two banks, and the memory area used by the memory circuit 1406 is not limited to two banks of 24 × 8 slots as in the above embodiment.

In the above embodiment, the data sequence input to the de-interleave circuit 1402 is composed of two types of TS per frame (48 slots), and one type of TS is selected. And Here, for example, TS1: <higher layer image> TC-8PSK: 14 slots <lower layer image> QPSK (r = 1/2): 2 slots (including 1 dummy slot) TS2: <higher layer image> TC-8PSK: 12 slots <Lower layer image> QPSK (r = 3/4): 4 slots (1 dummy slot) TS3: <Higher layer image> TC-8PSK: 12 slots <Lower layer image> BPSK (r = 1/2): Consider a case where three types of TS of 4 slots (including 3 dummy slots) are input. That is, one transponder is composed of 3TS. When one type of TS is selected, as described above, only the selected 1TS is written in the memory circuit 1406 to perform speed conversion,
Reading may be performed at a speed of 16/48 = 1/3. When two types of TS are selected, 1TS is displayed on the monitor and 1TS is video recorded, and only the selected 2TS is written in the memory circuit 1406.
Reading may be performed at a speed of 2/48 = 2/3. In this case, if the maximum number of slots per frame occupied by one TS is determined in the BS digital broadcasting standard, prepare a memory area for two banks of maximum number of slots × 8 × 2 slots. Good. Besides, for example, 8
The same applies to the case where four types of TS are input and four types of TS are selected.

As described in the problem to be solved by the invention, when the above-described de-interleave circuit 1402 is used, the data sequence input to the conventional de-randomize circuit 20007 is not a continuous slot but a skipped data sequence. The data series of the slot will be input. Therefore, when the conventional de-randomization circuit 20007 is used, de-randomization cannot be performed. The de-randomization circuit of this embodiment is configured to solve this problem. The operation of this point will be described below.

FIG. 39 is a block diagram showing the structure of the de-randomizing circuit 1407 in this embodiment. The de-randomization circuit 1407 includes a PN generation circuit 1408, a P / S conversion circuit 20030, an S / P circuit shown by a broken line portion.
Conversion circuit 20031 and gate signal generation circuit 20032
And an ex-or circuit 20033. The PN generation circuit 1408 includes an initial value generation circuit 1409 controlled by a slot selection signal. The de-randomizing circuit 1407 in this embodiment is different from the de-randomizing circuit 20007 in the conventional example shown in FIG.
A feature is that an initial value generation circuit 1409 is added.

As shown in FIG. 38B, the data sequence output from the de-interleave circuit 1402 is MP
EG sync byte / dummy slot insertion circuit 20006
At, the MPEG sync byte is inserted at the beginning of each slot. In addition, according to the dummy slot information output from the transmission control information decoding circuit 20010, an MPEG null packet is inserted in the dummy slot section and a byte data sequence as shown in FIG. 40 is output to the de-randomizing circuit 1407. .

The de-randomizing circuit 1407 is shown in FIG.
The de-randomization is performed on the data series in 1 superframe. PN generating circuit 1408, the characteristics are represented by the generator polynomial ^{(1 + x 14 + x 15} ), and is reset by the second byte of the first frame of each superframe. The initial value at this time is "100101010000000". The input data converted into the bit sequence by the P / S conversion circuit 20030 and the output value of the PN generation circuit 1408 are e
It is multiplied by the x-or circuit 20033. The multiplication result is converted into a byte data series in the S / P conversion circuit 20031 and output to the RS decoding circuit 20008 in FIG.

However, due to the gate signal generated by the gate signal generation circuit 20032, the PN generation circuit 1408 sets the ex-or circuit 20033 as a free run during the period of the leading byte of each slot 204 bytes and the dummy slot.
Does not multiply the data. Also, in FIG.
1 (1) to TS1 (22) are PN generation circuit 140
8 operates continuously. However, for the TS1 (23), the initial value generation circuit 1409 loads the initial value corresponding to the TS1 (23) by the slot selection signal at the second byte of the slot. This is shown in FIG. 108 (d).
This is because TS1 (22) and TS1 (23) are not continuously randomized as shown in FIG. Therefore, the initial value generation circuit 1409 in FIG. 39 may be configured to generate the initial values of the second bytes of all 48 × 8 slots by the slot selection signal.

With the above configuration, de-randomizing circuit 1407 of the present embodiment can perform de-randomizing corresponding to the case where de-interleaving circuit 1402 described above is used, and speed converting circuit 20009 is used. It can be unnecessary. In this case, an enable signal as shown in FIG. 108 (e), that is, a signal in which the 188-byte MPEG packet valid period becomes “H” and the 16-byte RS code parity period becomes “L”, is generated. The tuning circuit 1403 of FIG. 36 may be configured.

In this embodiment, the PN generation in the de-randomize circuit 1407 is bit serial, but it may be 8-bit parallel PN generation. In that case, the P / S conversion circuit 20030 of FIG.
And the S / P conversion circuit 20031 can be omitted.

(Embodiment 15) Embodiment 1 of the present invention
The error correction circuit in No. 5 will be described with reference to the drawings. FIG. 41 is a block diagram showing the structure of the error correction circuit 1501 in this embodiment. The error correction circuit 1501 shown in FIG. 41 has a different internal configuration as indicated by a thick solid line. Speed conversion circuit 1502 and tuning circuit 150
3 is newly provided, and the speed conversion circuit 1502 is configured to be controlled by the slot selection signal output from the channel selection circuit 1503. The functions of the other blocks, that is, the Viterbi decoder 20002 to RS decoding circuit 2008 and the transmission control information decoding circuit 20010 are the same as those shown in FIG.

Error correction circuit 15 configured as described above
Each block 01 and its operation will be described. However, the description before the input to the speed conversion circuit 1502 is omitted because it is as shown in the conventional example.

FIG. 42 is a block diagram showing a configuration example of the speed conversion circuit 1502. Speed conversion circuit 15 shown by the dotted line
02 has a write address generation circuit 1504, a read address generation circuit 1505, and a memory circuit 1506. Note that the memory circuit 1506 of this embodiment uses a memory area of 24 slots in order to select a TS and perform speed conversion. Note that FIG. 42 also shows a transmission control information decoding circuit 20010 and a channel selection circuit 1503.

As described in the problem to be solved by the invention, the conventional speed conversion circuit 20009 performs TS selection and speed conversion by using an unnecessary memory area. The speed conversion circuit 1502 of this embodiment is configured to solve this problem. Hereinafter, the operation of the speed conversion circuit 1502 of this embodiment will be described.

As in the case of the conventional example, the speed conversion circuit 1
As shown in FIG. 108 (d), the data sequence input to 502 is, per frame (48 slots), TS1: <higher layer image> TC-8PSK: 22 slots <lower layer image> QPSK (r = 1/2): 2 slots (internal dummy 1 slot) TS2: <Higher layer image> TC-8PSK: 20 slots <Lower layer image> BPSK (r = 1/2): 4 slots (internal dummy 2 slots (3 slots).

When channel selection information is input to the channel selection circuit 1503 of FIG. 42 from an MPEG decoder (not shown), the channel selection circuit 1503 is output from the transmission control information decoding circuit 20010 in the same manner as in the conventional example. Based on the slot number information, a slot selection signal for selecting a TS is output to the speed conversion circuit 1502. In the conventional example, as shown in FIGS. 114 to 117, the speed conversion circuit 20009 writes and reads all input data series of 48 slots into the memory circuit 20036 of FIG. 113.

On the other hand, in the present embodiment, the data sequence of only the selected 1TS, 24 slots / frame in this example, is written in the memory circuit 1506 by the slot selection signal output from the channel selection circuit 1503. Control to do. Therefore, the write address generation circuit 1504 generates only the address corresponding to the selected 1TS slot and outputs it to the memory circuit 1506. The address of the slot corresponding to the unselected TS is free run.

Also, by the slot selection signal output from the channel selection circuit 1503, the data series of only the selected 1TS is controlled to be continuously read from the memory circuit 1506. Therefore, the read address generation circuit 1505 sets only the address corresponding to the selected 1TS slot to half the write speed (= 24/48).
It is generated at the speed of, and is output to the memory circuit 1506. The address of the slot corresponding to the TS not selected is not generated and is skipped.

By the above operation, the speed conversion circuit 1502
The output data sequence from is the same as that of the conventional example as shown in FIG. In addition, the read address generation circuit 15
As shown in FIG. 108 (e), reference numeral 05 denotes a 188-byte MPEG packet valid period of “H” for each 204-byte slot output from the memory circuit 1506 as in the conventional example, and 16-byte RS code is used. Generates an enable signal that becomes “L” in the parity section of
Output to EG decoder.

With the above configuration, the speed conversion circuit 1502 of this embodiment reduces the memory area to be used by half by writing and reading the input data series of only the selected 1TS to the memory circuit 1506. can do.

In the above-mentioned embodiment, TS1, TS
Both 2 occupy 24 slots per frame, but for example, if the maximum number of slots per frame occupied by one TS is determined in the BS digital broadcasting standard, the memory of the maximum number of slots is set. It is only necessary to prepare an area, and the memory area used by the memory circuit 1506 is not limited to 24 slots as in the above embodiment.

In the above embodiment, the data sequence input to the speed conversion circuit 1502 is one frame (48
2 types of TS per slot) and 1 type of T
S was selected. Here, for example, TS1: <higher layer image> TC-8PSK: 14 slots <lower layer image> QPSK (r = 1/2): 2 slots (including 1 dummy slot) TS2: <higher layer image> TC-8PSK: 12 slots <Lower layer image> QPSK (r = 3/4): 4 slots (1 dummy slot) TS3: <Higher layer image> TC-8PSK: 12 slots <Lower layer image> BPSK (r = 1/2): Consider a case where three types of TS of 4 slots (including 3 dummy slots) are input.

When one type of TS is selected, as described above, only the selected 1TS is stored in the memory circuit 1506.
, And speed conversion is performed, and reading is performed at a speed of 16/48 = 1/3. When two types of TS are selected, for example, when one 1TS is displayed on the monitor and the other 1TS is video-recorded, the selected 2T is selected.
Only S is written in the memory circuit 1506, the speed is converted, and the reading is performed at a speed of 32/48 = 2/3. In this case, according to the BS digital broadcasting standard,
If the maximum number of slots per frame occupied by one TS is determined, a memory area of maximum number of slots × 2 slots may be prepared. Besides, for example, 8 types of T
The same applies when S is input and four types of TS are selected.

Further, as the speed conversion circuit, a structure in which a plurality of selected TSs are speed-converted and continuously output in parallel can be considered. FIG. 43 shows a parallel output speed conversion circuit 150.
8 is a block diagram showing the configuration of an error correction circuit 1507 having 8 bits. FIG. In the error correction circuit 1507 shown in FIG. 43, the internal configurations of the speed conversion circuit 1508 and the tuning circuit 1509 are the same as those of the speed conversion circuit 1502 and the tuning circuit 1 of FIG.
This is different from the internal configuration of 503. The other functions of each block, that is, the Viterbi decoder 20002 to RS decoding circuit 20008, and the transmission control information decoding circuit 20010 are the same as those shown in FIG.

FIG. 44 is a block diagram showing a configuration example of the speed conversion circuit 1508. Speed conversion circuit 15 shown by the dotted line
08 includes a write address generation circuit 1510, a read address generation circuit 1511, and a memory circuit 1512. Note that the memory circuit 1512 of this embodiment uses a memory area of 32 slots in order to select a TS and perform speed conversion. Further, FIG. 44 also shows a transmission control information decoding circuit 20010 and a channel selection circuit 1509.

Here, the data sequence input to the speed conversion circuit 1508 is TS1: <higher layer image> TC-8PSK: 14 slots <lower layer image> QPSK (r =) per frame (48 slots). 1/2): 2 slots (internal dummy 1 slot) TS2: <higher layer image> TC-8PSK: 12 slots <lower layer image> QPSK (r = 3/4): 4 slots (internal dummy 1) Slot) TS3: <Higher layer image> TC-8PSK: 12 slots <Lower layer image> BPSK (r = 1/2): 4 slots (including 3 dummy TSs) think of.

When two types of TS are selected, for example, when one 1TS is displayed on the monitor and the other 1TS is video recorded, only the selected 2TS is stored in the memory circuit 15.
12 is written, the speed is converted, and 1/3 (= 16 /
2TS may be read in parallel at the speed of 48). In addition, for example, the same applies when eight types of TS are input and four types of TS are selected.

Note that in the above embodiment, the speed conversion circuit 1502 or the speed conversion circuit 1508 sets 1 slot = 204 bytes, and 16 bytes of parity bytes are also read / written to / from the memory circuit 1506 or the memory circuit 1512.
It is configured to output with an enable signal. Not limited to this configuration, 16 bytes of parity bytes are used for the memory circuit 15.
It is also possible to consider a configuration in which speed conversion is performed without writing or reading data to or from the memory circuit 1512. In this case, the use area of the memory circuit 1506 or the memory circuit 1512 is further increased by 18.
It can be reduced to 8/204 = 47/51, and read address generation circuit 1505 or read address generation circuit 151
1 does not need to generate an enable signal. 47 /
The speed conversion of 51 is easy to realize by providing a counter circuit that outputs a ripple carry signal when the count value becomes 51 and inputting 47 to the counter circuit. In this case, the ripple carry signal is output at the speed of 47/51 of the input.

(Embodiment 16) Embodiment 1 of the present invention
The error correction circuit in 6 will be described with reference to the drawings. FIG. 45 is a block diagram showing the structure of the error correction circuit 1601 in this embodiment. In the error correction circuit 1601 shown in FIG. 45, as shown by the thick solid line,
The interleave circuit 1302, the speed conversion circuit 1602, and the channel selection circuit 1603 have different internal configurations, and the de-interleave circuit 1302 and the speed conversion circuit 1502 are configured to be controlled by the slot selection signal output from the channel selection circuit 1503. Is a feature. The other blocks, namely the Viterbi decoder 20002 to the symbol / byte conversion circuit 20004, the MPEG synchronization byte / dummy slot insertion circuit 20006 to RS decoding circuit 20008, and the transmission control information decoding circuit 20010 are the same as those shown in FIG. is there. The de-interleave circuit 1302 is the same as that shown in FIG.

The error correction circuit 16 configured as described above
Each block 01 and its operation will be described. However, the description before the input to the de-interleave circuit 1302 is omitted because it is as shown in the conventional example.

As described in the thirteenth embodiment, FIG.
The de-interleaved data shown in (b) is
It is output from the interleave circuit 1302. The number of effective slots per frame of 1TS is 24.

The byte data sequence output from the de-interleave circuit 1302 and shown in FIG. 35 (b) is the same as the conventional example, and the MPEG sync byte / dummy.
Slot insertion circuit 20006, de-randomization circuit 2
It is processed by the RS decoding circuit 20008 and output to the speed conversion circuit 1602. However, FIG. 108 (c)
As can be seen from a comparison between FIG. 35B and FIG. 35B, the number of effective slots per frame is 24 in the present embodiment.
Is. Therefore, the MPEG synchronization byte / dummy slot insertion circuit 20006 and the de-randomization circuit 2000
7 and the RS decoding circuit 20008 are processed in the same manner as in the conventional example, the same data sequence as in FIG. 108 is output for the effective slots.

FIG. 46 is a block diagram showing a configuration example of the speed conversion circuit 1602. Speed conversion circuit 16 shown by the dotted line
02 has a write address generation circuit 1604, a read address generation circuit 1605, and a memory circuit 1606. Note that the memory circuit 1606 of this embodiment uses a memory area of 24 slots in order to select a TS and perform speed conversion. Further, FIG. 46 shows a transmission control information decoding circuit 20010 and a channel selection circuit 1603.

When tuning information is input to the tuning circuit 1603 from an MPEG decoder (not shown), the tuning circuit 1603
Is similar to the conventional example, the transmission control information decoding circuit 2001
Based on the slot number information output from 0, a slot selection signal for selecting a TS is output to the speed conversion circuit 1602. A 1TS selected by the slot selection signal output from the tuning circuit 1603, in the case of this example, a data sequence of only 24 slots / frame effective slots is stored in the memory circuit 1606 in the same manner as in the fifteenth embodiment.
Control to write to. Therefore, the write address generation circuit 1604 generates only the address corresponding to the selected 1TS slot, and the memory circuit 16
It outputs to 06. In addition, TS not selected, that is, 2
The address of the slot corresponding to the invalid slot of 4 slots / frame is free run.

The data series of only 1TS selected by the slot selection signal is controlled so as to be continuously read from the memory circuit 1606 as in the fifteenth embodiment. Therefore, the read address generation circuit 16
05 generates only the address corresponding to the selected slot of 1TS at a write speed of 24/48 = 1/2 and outputs it to the memory circuit 1606. The address of the slot corresponding to the TS not selected is not generated and is skipped.

From the above, the output data series from the speed conversion circuit 1602 is the same as that of the conventional example as shown in FIG. 108 (e). In addition, the read address generation circuit 160
Similar to the conventional example, in No. 5, the 188-byte MPEG packet valid period as shown in FIG. 108E is'H 'for each 204-byte slot output from the memory circuit 1606, and the RS code of The 16-byte parity section generates an enable signal whose level is'L ', and MP (not shown)
Output to EG decoder.

With the above configuration, when the speed conversion circuit 1602 of this embodiment receives the input data series of only 1TS already selected by the de-interleave circuit 1302, it stores the data series of only 1TS in the memory. Circuit 16
By writing to and reading from 06, the memory area used can be reduced to half.

In the above embodiment, TS1, TS
Both 2 occupy 24 slots per frame, but for example, if the maximum number of slots per frame occupied by one TS is determined in the BS digital broadcasting standard, the memory of the maximum number of slots is set. An area may be prepared, and the memory area used by the memory circuit 1606 is not limited to 24 slots as in the above embodiment mode.

In the above embodiment, the data series input to the speed conversion circuit 1602 is one frame (48
2 types of TS per slot) and 1 type of T
S was selected. Here, for example, TS1: <higher layer image> TC-8PSK: 14 slots <lower layer image> QPSK (r = 1/2): 2 slots (including 1 dummy slot) TS2: <higher layer image> TC-8PSK: 12 slots <Lower layer image> QPSK (r = 3/4): 4 slots (1 dummy slot) TS3: <Higher layer image> TC-8PSK: 12 slots <Lower layer image> BPSK (r = 1/2): Consider a case where three types of TS of 4 slots (including 3 dummy slots) are input. One kind of T
When S is selected, 1T selected as described above
Only S is written in the memory circuit 1606, the speed is converted, and the reading is performed at a speed of 16/48 = 1/3. When two types of TS are selected, for example, one 1TS is displayed on the monitor and the other 1TS is video-recorded, only the selected 2TS is written in the memory circuit 1606 to perform speed conversion. , 32/48 = 2/3 at the speed of reading. In this case, if the maximum number of slots per frame occupied by one TS is determined in the BS digital broadcasting standard, a memory area of maximum number of slots × 2 slots may be prepared.
In addition, the same applies to the case where, for example, 8 types of TS are input and 4 types of TS are selected.

Further, as the speed conversion circuit, a structure in which a plurality of selected TSs are speed-converted and continuously output in parallel can be considered. FIG. 47 shows a parallel output speed conversion circuit 160.
8 is a block diagram showing a configuration of an error correction circuit 1607 having 8 bits. FIG. The speed conversion circuit 1608 is for performing speed conversion of a plurality of TSs already selected by the de-interleave circuit 1302 and continuously outputting in parallel. In the error correction circuit 1607 shown in FIG. 47, the de-interleave circuit 1302, the speed conversion circuit 1608, the channel selection circuit 1
The internal configuration of 609 is the de-interleave circuit 20005, the speed conversion circuit 1502, and the channel selection circuit 150 of FIG.
Compared with the internal structure of 3, it has changed. Other blocks, namely the Viterbi decoder 20002, the symbol / byte conversion circuit 20004, the MPEG synchronization byte / dummy slot insertion circuit 20006, the de-randomization circuit 20.
007, RS decoding circuit 20008, and transmission control information decoding circuit 20010 are the same as those shown in FIG.

FIG. 48 is a block diagram showing a configuration example of the speed conversion circuit 1608. Speed conversion circuit 16 shown by the dotted line
08 includes a write address generation circuit 1610, a read address generation circuit 1611, and a memory circuit 1612. Note that the memory circuit 1612 of this embodiment uses a memory area of 32 slots in order to select a TS and perform speed conversion. Further, FIG. 48 shows a transmission control information decoding circuit 20010 and a channel selection circuit 1609.

Here, the data sequence input to the speed conversion circuit 1608 is, per frame (48 slots), TS1: <higher layer image> TC-8PSK: 14 slots <lower layer image> QPSK (r = 1/2): 2 slots (internal dummy 1 slot) TS2: <higher layer image> TC-8PSK: 12 slots <lower layer image> QPSK (r = 3/4): 4 slots (internal dummy 1) Slot) TS3: <Higher layer image> TC-8PSK: 12 slots <Lower layer image> BPSK (r = 1/2): 4 slots (including 3 dummy TSs) think of.

When two types of TS are selected, for example, when one 1TS is displayed on the monitor and the other 1TS is video-recorded, only the 2TS already selected by the de-interleave circuit 1302 is stored in the memory circuit. Write to 1612, perform speed conversion and 2T at speed 16/48 = 1/3
S may be read in parallel. Besides, for example, 8 types of TS
Is also input, and the same applies when four types of TS are selected.

In the above embodiment, the speed conversion circuit 1602 or the speed conversion circuit 1608 reads / writes 16 bytes of parity bytes to / from the memory circuit 1606 or the memory circuit 1612 with 1 slot = 204 bytes and outputs them with an enable signal. It was configured to do. Not limited to this configuration, 16 bytes of parity bytes are used for the memory circuit 160.
6 or memory circuit 1612 may be configured to perform speed conversion without reading or writing. In this case, the use area of the memory circuit 1606 or the memory circuit 1612 is further increased by 18.
It can be reduced to 8/204 = 47/51, and read address generation circuit 1605 or read address generation circuit 161.
1 eliminates the need to generate an enable signal. 47
For speed conversion of / 51, for example, the count value is 51
In this case, it is easy to realize by providing a counter circuit that outputs a ripple carry signal and inputting 47 to this counter circuit. In this case, the ripple carry signal is output at the speed of 47/51 of the input.

(Embodiment 17) Embodiment 1 of the present invention
The error correction circuit in 7 will be described with reference to the drawings. In the embodiments described below,
“No TMCC”, that is, the case where the superframe structure is temporally constant is assumed. The error correction circuit according to the present embodiment is basically the same in operation as the error correction circuits described in the first to sixteenth embodiments, except that various control information is periodically generated. Therefore, the description of the same operation part is omitted.

FIG. 49 shows the error correction coding device 17 on the transmission side.
It is a block diagram which shows the structural example of 01. The error correction coding apparatus 1701 shown in this figure is based on the TS multiplexing circuit 10002.
, RS encoding circuit 10003, and randomizing circuit 1
0004, an interleave circuit 10005, a byte / symbol conversion circuit 10006, a convolutional encoder 10007, and a mapping circuit 10008. Instead of the conventional transmission control information generation circuit 10009 shown in FIG. The feature is that the data information generation circuit 1702 is provided. The TS multiplexing circuit 10002
~ Each function of the mapping circuit 10008 is the same as that shown in FIG.

FIG. 50 is a data layout diagram showing an output data series up to randomizing circuit 10004 in error correction coding apparatus 1701. The data arrangement here is exactly the same as the case of "with TMCC" shown in FIG. However, as shown in the superframe structure of FIG. 50 (d), the first byte of each slot is replaced with a signal of 12 bytes per frame instead of TMCC after interleaving. These 12-byte signals are the previous TAB signal 2 bytes W1, data other than video,
For example, it is W2 or W3 of 8 bytes of character multiplexed data and 2 bytes of rear TAB signal.

FIG. 51 shows the byte / symbol conversion circuit 10.
6 is a data layout diagram in a byte data series having a superframe structure input to 006. FIG. As shown in FIG. 87, as compared with the case of “with TMCC”, TMCC actual data, that is, 8 bytes per frame is characterized by being replaced by data other than video, for example, 8 bytes of character multiplexed data. Other than this, the superframe structure is the same as in FIG. That is, the TAB / data information generation circuit 1702 of FIG. 49 uses a 12-byte sync signal for each frame, a 2-byte front TAB signal (W1), 8-byte character multiplexed data other than video, and a rear TAB signal (W1).
2 or W3) Generate in the order of 2 bytes. Also, TAB /
The data information generation circuit 1702 periodically generates and outputs a constant modulation parameter.

FIG. 52 shows the byte / symbol conversion circuit 10.
FIG. 9 is an explanatory diagram showing an example of the number of slots in each transmission mode in the byte data series per frame of the superframe structure input to 006. As shown in this figure, TC-8PSK (r = 2/3): 42 slots QPSK (r = 3/4): 0 slot QPSK (r = 1/2): 2 slots (1 dummy slot) BPSK (R = 1/2): 4 slots (3 dummy slots), and the number of slots does not change with time.

FIG. 53 is a data layout diagram for one frame which summarizes the signal flow from the input to the output of the error correction coding device 1701. 97 (d), "TMCC"
53 (d) is different from the case of "Yes" 2 only in that the actual data of TMCC, that is, the portion of 128 symbols / frame is changed into a symbol in which 8 bytes of the character multiplex data is convolutionally encoded. The other parts are the same.

Next, an error correction circuit for performing error correction decoding on a data sequence that has been error correction coded by the error correction coding apparatus 1701 will be described below with reference to the drawings.

FIG. 54 shows the case of "without TMCC", that is, the error correction circuit 170 in the seventeenth embodiment, as compared with the case of "with TMCC" as described in the first embodiment.
It is a block diagram which shows the structural example of 3. In this error correction circuit 1703, the block shown by a thick solid line is different from the conventional example. In the error correction circuit 1703 of this embodiment,
A Viterbi decoder 102 controlled by the switching control signal and a Viterbi decoder control circuit 103 for generating the switching control signal are provided, and a control signal generation is performed instead of the transmission control information decoding circuit 20010 in the first to sixteenth embodiments. Circuit 1704
Is provided, and a channel selection circuit 1705 having an internal configuration different from those of Embodiments 1 to 16 is provided. The other blocks, that is, the high / low hierarchy selection signal generation circuit 20003 to the speed conversion circuit 20009 are provided, which is the same as that shown in FIG.

The operation of the error correction circuit 1703 having such a configuration will be described. The data sequence error-correction coded by the error correction coding device 1701 on the transmission side as shown in FIG. 49 is quadrature-modulated by a quadrature modulator (not shown) and transmitted through a satellite transmission path. The signal transmitted from the transponder is input to a PSK demodulator (not shown) on the receiving side and PSK demodulated. Since the convolution circuit 10014 shown in FIG. 91 has a constraint length of 7 and the TAB signal section is transmitted by BPSK, the TAB signals (w1, w2, w3) before Viterbi decoding are each 32 symbols (3.
Of the 2 bits), the first 12 symbols are uncertain,
The remaining 20 symbols are w1 (= xxxE as shown in FIG. 51.
CD28h), w2 (= xxx0B677h), w3 (= xxxF4988h)
) Is confirmed. The PSK demodulator performs demodulation by differential detection when the tuning is switched according to the tuning information.
Detect w1, w2, w3. In this way, the PSK demodulator detects superframe synchronization and absolute phase, and after detection, performs coherent detection and outputs PSK demodulated data and superframe synchronization signal to the error correction circuit 1703 of FIG.

In the error correction circuit 1703, the control signal generation circuit 1704 operates according to the superframe synchronization signal output from the PSK demodulator, and various control information, that is, transmission mode / slot information, transmission mode, dummy slot information, is sent. Generate and output at a fixed cycle. Further, the control signal generation circuit 1704 extracts and outputs only the portion of the 64-bit (64-symbol) character multiplexed data of each frame output from the Viterbi decoder 102.

The Viterbi decoder control circuit 103 generates a switching control signal according to the transmission mode / slot information output from the control signal generation circuit 1704 and outputs it to the Viterbi decoder 102, as in the first embodiment. . The Viterbi decoder 102 performs the same operation as that of the first embodiment shown in FIG.

The error correction capability of the error correction circuit 1703 described above is secured to the same extent as that of the error correction circuit of the first embodiment. As in the first embodiment, when the modulation multi-value number after switching the transmission mode is larger than that before switching the transmission mode,
Alternatively, the switching control signal may be generated only when the number of modulation levels is the same and the coding rate is large.

Also, as in the first embodiment, when switching the transmission mode before and after the super frame synchronization signal (BPSK: r = 1/2), the Viterbi decoder control circuit 103 is used.
May be configured not to generate the switching control signal.
In this case, a Viterbi decoding control method using the property of the fixed symbol sequence can be considered. This will be described in Embodiments 18 and 19.

(Embodiment 18) Embodiment 1 of the present invention
The error correction circuit in 8 will be described with reference to the drawings. Note that, also in the present embodiment, a case where the superframe structure is temporally constant and “without TMCC” will be described.

FIG. 55 shows "TM" described in the second embodiment.
It is a block diagram which shows the structural example of the error correction circuit 1801 in the case of "there is no CC" with respect to the case of "there is CC." This error correction circuit 1801 is different from the error correction circuit 201 of the second embodiment shown in FIG. 5 in that a tuning circuit 1705 having a different internal configuration is provided and that a control signal generation circuit is provided instead of the transmission control information decoding circuit 20010. 1704
It is characterized by the provision of. Other blocks,
That is, the Viterbi decoder 202 to the Viterbi decoder control circuit 20
3. The functions of the high / low hierarchy selection signal generation circuit 20003 to speed conversion circuit 20009 are the same as those shown in FIG.

In error correction circuit 1801 of this embodiment, as in the case of Embodiment 2, Viterbi decoder control circuit 203 outputs a fixed state signal according to the transmission mode / slot information output from control signal generation circuit 1704. Is generated and output to the Viterbi decoder 202 in FIG. The Viterbi decoder 202 performs the same operation as that of the second embodiment, as shown in FIG. In addition, the control signal generation circuit 1704 outputs 64 bits (6 bits) for each frame output from the Viterbi decoder 202.
(4 symbols) Only the character multiplex data portion is extracted and output.

The error correction capability of the error correction circuit 1801 shown above is secured to the same extent as that of the error correction circuit of the second embodiment. As in the second embodiment, the Viterbi decoder control circuit 203 can arbitrarily select the symbol period for generating the definite state signal from 1 symbol to a maximum of 10 symbols, and selects which symbol. It is also optional.

(Embodiment 19) Embodiment 1 of the present invention
The error correction circuit in 9 will be described with reference to the drawings. Note that, also in the present embodiment, a case where the superframe structure is temporally constant and “without TMCC” will be described.

FIG. 56 is a block diagram showing a configuration example of the error correction circuit 1901 in the case of “without TMCC” in contrast to “with TMCC” described in the third embodiment. This error correction circuit 1901 is different from the error correction circuit 301 of the third embodiment shown in FIG. 8 in that a channel selection circuit 1705 having a different internal configuration is provided and that a control signal generation circuit is provided instead of the transmission control information decoding circuit 20010. 1704
It is characterized by the provision of. Other blocks,
That is, the Viterbi decoder 302 to the Viterbi decoder control circuit 30
3. The functions of the high / low hierarchy selection signal generation circuit 20003 to the speed conversion circuit 20009 are the same as those shown in FIG.

In the error correction circuit 1901 of the present embodiment, the Viterbi decoder control circuit 303 performs a fixed branch according to the transmission mode / slot information output from the control signal generation circuit 1704, as in the case of the third embodiment. A signal is generated and output to the Viterbi decoder 302 in FIG.
The Viterbi decoder 302 performs the same operation as that of the third embodiment as shown in FIG. Further, the control signal generation circuit 170
4 is each frame 6 output from the Viterbi decoder 302
Only the 4-bit (64 symbol) character multiplex data portion is extracted and output.

The error correction capability of the error correction circuit 1901 described above is secured to the same extent as that of the error correction circuit of the third embodiment.

(Embodiment 20) Embodiment 2 of the present invention
The error correction circuit for 0 will be described with reference to the drawings. Note that, also in the present embodiment, a case where the superframe structure is temporally constant and “without TMCC” will be described.

FIG. 57 shows "TM" described in the fourth embodiment.
It is a block diagram which shows the structural example of the error correction circuit 2001 in the case of "there is no CC" with respect to "there is CC." This error correction circuit 2001 includes a channel selection circuit 1705 having a different internal configuration in the error correction circuit 401 of the fourth embodiment shown in FIG. 11, and a control signal generation instead of the transmission control information decoding circuit 20010. The feature is that the circuit 1704 is provided. Other blocks, namely the Viterbi decoder 402 to the Viterbi decoder control circuit 403, the high / low hierarchy selection signal generation circuit 20003 to the speed conversion circuit 2
Each function of 0009 is the same as that shown in FIG.

In the error correction circuit 2001 of this embodiment, the Viterbi decoder control circuit 403 outputs a state reduction signal based on the transmission mode / slot information output from the control signal generation circuit 1704, as in the fourth embodiment. It is generated and output to the Viterbi decoder 402 in FIG. The Viterbi decoder 402 performs the same operation as that of the third embodiment as shown in FIG. Further, the control signal generation circuit 1704 extracts and outputs only the portion of the character multiplexed data of 64 bits (64 symbols) of each frame output from the Viterbi decoder 402.

The error correction capability of the error correction circuit 2001 described above is secured to the same extent as that of the error correction circuit of the fourth embodiment.

(Embodiment 21) Embodiment 2 of the present invention
The error correction circuit in 1 will be described with reference to the drawings. Note that, also in the present embodiment, a case where the superframe structure is temporally constant and “without TMCC” will be described.

FIG. 58 shows "TM" described in the fifth embodiment.
It is a block diagram which shows the structural example of the error correction circuit 2101 in the case of "there is no CC" with respect to "there is CC." This error correction circuit 2001 includes a channel selection circuit 1705 having a different internal configuration in the error correction circuit 501 of the fifth embodiment shown in FIG. 14, and a control signal generation circuit instead of the transmission control information decoding circuit 20010. The feature is that 1704 is provided. Each of the other blocks, that is, the input symbol conversion circuit 506 and the Viterbi decoder control circuit 50.
3, Viterbi decoder 20002 to speed conversion circuit 20009
14 are the same as those shown in FIG.

In the error correction circuit 2101 of this embodiment, the Viterbi decoder control circuit 503 generates a symbol coordinate conversion signal based on the transmission mode / slot information output from the control signal generation circuit 1704, and FIG. Output to the input symbol conversion circuit 506 shown is the same as in the fifth embodiment. The input symbol conversion circuit 506 is
As shown in FIG. 16, the same operation as in the fifth embodiment is performed. Further, the control signal generation circuit 1704 extracts and outputs only the portion of the 64-bit (64-symbol) character multiplexed data of each frame output from the Viterbi decoder 502.

The error correction capability of the error correction circuit 2101 shown above is secured to the same extent as that of the error correction circuit of the fifth embodiment.

(Embodiment 22) Embodiment 2 of the present invention
The error correction circuit in 2 will be described with reference to the drawings. Note that, also in the present embodiment, a case where the superframe structure is temporally constant and “without TMCC” will be described.

FIG. 59 shows "TM" described in the sixth embodiment.
It is a block diagram which shows the structural example of the error correction circuit 2201 in the case of "there is no CC" with respect to "there is CC." This error correction circuit 2201 includes a channel selection circuit 1705 having a different internal configuration in the error correction circuit 601 of the sixth embodiment shown in FIG. 19, and a control signal generation instead of the transmission control information decoding circuit 20010. The feature is that the circuit 1704 is provided. Other blocks, that is, the Viterbi decoder 602 to the Viterbi decoder control circuit 603, the high / low hierarchy selection signal generation circuit 20003 to the speed conversion circuit 2
Each function of 0009 is the same as that shown in FIG.

In error correction circuit 2201 of the present embodiment, as in the sixth embodiment, Viterbi decoder control circuit 603 outputs a fixed state signal according to the transmission mode / slot information output from control signal generation circuit 1704. A fixed branch signal is generated and output to the Viterbi decoder 602 of FIG. The Viterbi decoder 602 operates similarly to the sixth embodiment. Further, the control signal generation circuit 1704 extracts and outputs only the portion of the 64-bit (64-symbol) character multiplexed data of each frame output from the Viterbi decoder 602.

The error correction capability of the error correction circuit 2201 shown above is secured to the same extent as that of the error correction circuit of the sixth embodiment.

(Embodiment 23) Embodiment 2 of the present invention
The error correction circuit in No. 3 will be described with reference to the drawings. Note that, also in the present embodiment, a case where the superframe structure is temporally constant and “without TMCC” will be described.

FIG. 60 shows "TM" described in the seventh embodiment.
FIG. 16 is a block diagram showing a configuration example of an error correction circuit 2301 in the case of “without CC” in contrast to “with CC”. This error correction circuit 2301 is different from the error correction circuit 701 according to the seventh embodiment shown in FIG. 21 in that a channel selection circuit 1705 having a different internal configuration is provided, and instead of the transmission control information decoding circuit 20010, a control signal generation is performed. The feature is that the circuit 1704 is provided. The other functions of the respective blocks, that is, the input symbol conversion circuit 506, the Viterbi decoder 702 to the Viterbi decoder control circuit 703, the high / low hierarchy selection signal generation circuit 20003 to the speed conversion circuit 20009 are the same as those shown in FIG. Is.

In error correction circuit 2301 of the present embodiment, as in the case of Embodiment 7, Viterbi decoder control circuit 703 uses the transmission mode / slot information output from control signal generation circuit 1704 to determine the symbol coordinates. The converted signal is generated and output to the input symbol conversion circuit 506, and the fixed branch signal is generated and output to the Viterbi decoder 702 of FIG. The input symbol conversion circuit 506 and the Viterbi decoder 702 perform the same operation as in the seventh embodiment. The control signal generation circuit 1704 extracts and outputs only the portion of the 64-bit (64-symbol) character multiplexed data of each frame output from the Viterbi decoder 702.

The error correction capability of the error correction circuit 2301 shown above is secured to the same extent as that of the error correction circuit of the seventh embodiment.

(Embodiment 24) Embodiment 2 of the present invention
The error correction circuit in No. 4 will be described with reference to the drawings. Note that, also in the present embodiment, a case where the superframe structure is temporally constant and “without TMCC” will be described.

FIG. 61 shows "TM" described in the eighth embodiment.
It is a block diagram which shows the structural example of the error correction circuit 2401 in the case of "there is no CC" with respect to "there is CC." This error correction circuit 2401 is different from the error correction circuit 801 according to the eighth embodiment shown in FIG. 23 in that a channel selection circuit 1705 having a different internal configuration is provided, and a control signal generation is performed instead of the transmission control information decoding circuit 20010. The feature is that the circuit 1704 is provided. Each of the other blocks, that is, the Viterbi decoder 802 to the Viterbi decoder control circuit 803, the high / low hierarchy selection signal generation circuit 20003 to the speed conversion circuit 2
Each function of 0009 is the same as that shown in FIG.

In the error correction circuit 2401 of the present embodiment, the Viterbi decoder control circuit 803 is in a definite state by the transmission mode / slot information output from the control signal generation circuit 1704, as in the case of the eighth embodiment. A Viterbi decoder 802 of FIG. 24 by generating a signal and a state reduction signal.
Output to. The Viterbi decoder 802 performs the same operation as in the eighth embodiment. Further, the control signal generation circuit 1704 is
Only the portion of the 64-bit (64-symbol) character multiplex data output from the Viterbi decoder 802 is extracted and output.

The error correction capability of the error correction circuit 2401 shown above is secured to the same extent as that of the error correction circuit of the eighth embodiment.

(Embodiment 25) Embodiment 2 of the present invention
The error correction circuit in No. 5 will be described with reference to the drawings. Note that, also in the present embodiment, a case where the superframe structure is temporally constant and “without TMCC” will be described.

FIG. 62 shows "TM" described in the ninth embodiment.
It is a block diagram which shows the structural example of the error correction circuit 2501 in the case of "there is no CC" with respect to "there is CC." This error correction circuit 2501 is different from the error correction circuit 901 of the ninth embodiment shown in FIG. 25 in that a channel selection circuit 1705 having a different internal configuration is provided, and instead of the transmission control information decoding circuit 20010, a control signal generation is performed. The feature is that the circuit 1704 is provided. Each of the other blocks, that is, the Viterbi decoder 902 to the Viterbi decoder control circuit 903, the high / low hierarchy selection signal generation circuit 20003 to the speed conversion circuit 2
Each function of 0009 is the same as that shown in FIG.

In error correction circuit 2501 of the present embodiment, similarly to the case of the ninth embodiment, Viterbi decoder control circuit 903 determines a fixed branch based on the transmission mode / slot information output from control signal generation circuit 1704. Signal and state reduction signal to generate the Viterbi decoder 9 of FIG.
Output to 02. The Viterbi decoder 902 operates similarly to the ninth embodiment. In addition, the control signal generation circuit 1704
Is each frame 64 output from the Viterbi decoder 902.
Only the bit (64 symbols) character multiplexed data portion is extracted and output.

The error correction capability of the error correction circuit 2501 described above is secured to the same extent as the error correction circuit of the ninth embodiment.

(Embodiment 26) Embodiment 2 of the present invention
The error correction circuit in 6 will be described with reference to the drawings. Also in the present embodiment, the case where “without TMCC” and the superframe structure is temporally constant will be described.

FIG. 63 shows "T" described in the tenth embodiment.
It is a block diagram which shows the structural example of the error correction circuit 2601 in the case of "there is no MCC" with respect to "there is MCC." This error correction circuit 2601 is the same as that of the first embodiment shown in FIG.
In the error correction circuit 1001 of 0, a channel selection circuit 1705 having a different internal configuration is provided, and instead of the transmission control information decoding circuit 20010, a control signal generation circuit 170 is provided.
The feature is that 4 is provided. Other blocks, that is, the input symbol conversion circuit 506 and the Viterbi decoder 1
The functions of 002 to Viterbi decoder control circuit 1003 and high / low hierarchy selection signal generation circuit 20003 to speed conversion circuit 20009 are the same as those shown in FIG.

In error correction circuit 2601 of the present embodiment, as in the case of the tenth embodiment, Viterbi decoder control circuit 1003 uses the transmission mode / slot information output from control signal generation circuit 1704 to determine the symbol coordinates. The converted signal is generated and output to the input symbol conversion circuit 506, and the state reduction signal is generated and output to the Viterbi decoder 1002 in FIG. The input symbol conversion circuit 506 and the Viterbi decoder 1002 perform the same operations as in the tenth embodiment. Further, the control signal generation circuit 1704 outputs 64 bits (6 bits) for each frame output from the Viterbi decoder 1002.
(4 symbols) Only the character multiplex data portion is extracted and output.

The error correction capability of the error correction circuit 2601 described above is secured to the same extent as that of the error correction circuit of the tenth embodiment.

(Embodiment 27) Embodiment 2 of the present invention
The error correction circuit in 7 will be described with reference to the drawings. Note that, also in the present embodiment, a case where the superframe structure is temporally constant and “without TMCC” will be described.

FIG. 64 shows "T" described in the eleventh embodiment.
It is a block diagram which shows the structural example of the error correction circuit 2701 at the time of "without TMCC" with respect to "with MCC." This error correction circuit 2701 is the same as that of the first embodiment shown in FIG.
In the error correction circuit 1101 of No. 1, the channel selection circuit 1705 having a different internal configuration is provided, and instead of the transmission control information decoding circuit 20010, the control signal generation circuit 170.
The feature is that 4 is provided. The other functions of the respective blocks, that is, the Viterbi decoder 1102 to the Viterbi decoder control circuit 1103 and the high / low hierarchy selection signal generation circuit 20003 to the speed conversion circuit 20009 are the same as those shown in FIG.

In error correction circuit 2701 of the present embodiment, Viterbi decoder control circuit 1103 is determined by the transmission mode / slot information output from control signal generation circuit 1704, as in the case of the eleventh embodiment. A state signal, a fixed branch signal, and a state reduction signal are generated and output to the Viterbi decoder 1102 in FIG. The Viterbi decoder 1102 performs the same operation as in the eleventh embodiment. Also,
The control signal generation circuit 1704 extracts and outputs only the portion of the 64-bit (64-symbol) character multiplexed data of each frame output from the Viterbi decoder 1102.

The error correction capability of error correction circuit 2701 shown above is secured to the same extent as the error correction circuit of the eleventh embodiment.

(Embodiment 28) Embodiment 2 of the present invention
The error correction circuit in 8 will be described with reference to the drawings. Note that, also in the present embodiment, a case where the superframe structure is temporally constant and “without TMCC” will be described.

FIG. 65 shows "T" described in the twelfth embodiment.
It is a block diagram which shows the structural example of the error correction circuit 2801 in the case of "there is no MCC" with respect to "there is MCC." This error correction circuit 2801 is the same as that of the first embodiment shown in FIG.
In the error correction circuit 1201 of No. 2, the channel selection circuit 1705 having a different internal configuration is provided, and instead of the transmission control information decoding circuit 20010, the control signal generation circuit 1701 is provided.
The feature is that 4 is provided. Other blocks, that is, the input symbol conversion circuit 506 and the Viterbi decoder 1
The functions of 202 to Viterbi decoder control circuit 1203 and high / low hierarchy selection signal generation circuit 20003 to speed conversion circuit 20009 are the same as those shown in FIG.

In error correction circuit 2801 of the present embodiment, as in the case of the twelfth embodiment, Viterbi decoder control circuit 1203 uses the transmission mode / slot information output from control signal generation circuit 1704 to determine the symbol coordinates. The converted signal is generated and output to the input symbol conversion circuit 506, and the fixed branch signal and the state reduction signal are generated and output to the Viterbi decoder 1202 in FIG. The input symbol conversion circuit 506 and the Viterbi decoder 1202 perform the same operation as in the twelfth embodiment. The control signal generation circuit 1704 extracts and outputs only the portion of the 64-bit (64-symbol) character multiplex data of each frame output from the Viterbi decoder 1202.

The error correction capability of error correction circuit 2801 described above is ensured to the same extent as the error correction circuit of the twelfth embodiment.

(Embodiment 29) Embodiment 2 of the present invention
The error correction circuit in 9 will be described with reference to the drawings. Note that, also in the present embodiment, a case where the superframe structure is temporally constant and “without TMCC” will be described.

FIG. 66 shows "T" described in the thirteenth embodiment.
It is a block diagram which shows the structural example of the error correction circuit 2901 in the case of "there is no MCC" with respect to "there is MCC." This error correction circuit 2901 is the same as that of the first embodiment shown in FIG.
In the error correction circuit 1301 of No. 3, the channel selection circuit 1705 having a different internal configuration is provided, and instead of the transmission control information decoding circuit 20010, the control signal generation circuit 170.
The feature is that 4 is provided. Each of the other blocks, that is, the de-interleave circuit 1302, the Viterbi decoder 20002 to the symbol / byte conversion circuit 20004,
MPEG sync byte / dummy slot insertion circuit 200
Each function of 06 to speed conversion circuit 20009 is the same as that shown in FIG.

In error correction circuit 2901 of the present embodiment, the relative TS / TS correspondence table shown in FIG. 84 and the relative TS / slot information shown in FIG. 83 are known and constant with time. Therefore, the channel selection circuit 1705 has a known relative TS / TS correspondence table and relative TS / slot information, generates a slot selection signal from these information, and outputs it to the de-interleave circuit 1302 in FIG. . The de-interleave circuit 1302 performs the same operation as that of the thirteenth embodiment, as shown in FIG.

The error correction capability of error correction circuit 2901 described above is ensured to the same extent as the error correction circuit of the thirteenth embodiment.

As in the thirteenth embodiment, for example, B
If the maximum number of slots per frame occupied by one TS is determined in the S digital broadcasting standard, it is sufficient to prepare a memory area for two banks of the maximum number of slots × 8 slots. The memory area used is not limited to two banks of 24 × 8 slots as in the thirteenth embodiment.

Further, as in the thirteenth embodiment, for example, TS1: <higher layer image> TC-8PSK: 14 slots <lower layer image> QPSK (r = 1/2): 2 slots (of which dummy 1 Slot) TS2: <Higher layer image> TC-8PSK: 12 slots <Lower layer image> QPSK (r = 3/4): 4 slots (1 dummy slot) TS3: <Higher layer image> TC- 8PSK: 12 slots <Lower layer image> BPSK (r = 1/2): 4 slots (including 3 dummy slots) Let us consider a case where three types of TS are input. That is, 3TS is assigned to one transponder. When one type of TS is selected, only the selected 1TS may be written in and read from the memory circuit 1306, as in the thirteenth embodiment. Also, when two types of TS are selected,
For example, when one 1TS is displayed on the monitor and the other 1TS is video-recorded, only the selected 2TS may be written in and read from the memory circuit 1306. In this case, if the maximum number of slots per frame occupied by one TS is determined in the BS digital broadcasting standard, prepare a memory area for two banks of maximum number of slots × 8 × 2 slots. Good. Besides, for example, 8
The same applies to the case where four types of TS are input and four types of TS are selected.

(Embodiment 30) Embodiment 3 of the present invention
The error correction circuit for 0 will be described with reference to the drawings. Note that, also in the present embodiment, a case where the superframe structure is temporally constant and “without TMCC” will be described.

FIG. 67 shows "T" described in the fourteenth embodiment.
FIG. 11 is a block diagram showing a configuration example of an error correction circuit 3001 in the case of “without MCC” with respect to “with MCC”. This error correction circuit 3001 is the same as that of the first embodiment shown in FIG.
In the error correction circuit 1401 of No. 4, the channel selection circuit 1705 having a different internal configuration is provided, and instead of the transmission control information decoding circuit 20010, the control signal generation circuit 170
The feature is that 4 is provided. Other blocks, namely de-interleave circuit 1402, de-randomize circuit 1407, Viterbi decoder 20002-symbol / byte conversion circuit 20004, MPEG sync byte /
Dummy slot insertion circuit 20006, RS decoding circuit 2
Each function of the speed conversion circuit 20009 is shown in FIG.
Is the same as that shown in.

In error correction circuit 3001 of the present embodiment, channel selection circuit 1705 generates a slot selection signal in the same manner as in the case of the twenty-ninth embodiment, and the data of FIG.
It outputs to the interleave circuit 1402 and the de-randomize circuit 1407 of FIG. The de-interleave circuit 1402 and the de-randomize circuit 1407 are shown in FIG.
As shown in (b) and FIG. 40, the same operation as that of the fourteenth embodiment is performed.

The error correction capability of error correction circuit 3001 described above is secured to the same extent as the error correction circuit of the fourteenth embodiment.

As in the fourteenth embodiment, for example, B
If the maximum number of slots per frame occupied by one TS is determined in the S digital broadcasting standard, it is sufficient to prepare a memory area for two banks of the maximum number of slots × 8 slots. The memory area used is not limited to two banks of 24 × 8 slots as in the fourteenth embodiment.

Further, similar to the fourteenth embodiment, for example, TS1: <higher layer image> TC-8PSK: 14 slots <lower layer image> QPSK (r = 1/2): 2 slots (of which dummy 1 Slot) TS2: <Higher layer image> TC-8PSK: 12 slots <Lower layer image> QPSK (r = 3/4): 4 slots (1 dummy slot) TS3: <Higher layer image> TC- 8PSK: 12 slots <Lower layer image> BPSK (r = 1/2): 4 slots (including 3 dummy slots) Let us consider a case where three types of TS are input. That is, 3TS is assigned to one transponder. When one kind of TS is selected, as in the fourteenth embodiment, only the selected 1TS is written in the memory circuit 1406, the speed is converted, and the TS is read at a speed of 16/48 = 1/3. Should be done. When two types of TS are selected, for example, when one TS is displayed on the monitor and the other 1TS is video-recorded, only the selected 2TS is stored in the memory circuit 14.
The data may be written in 06 and read at a speed of 32/48 = 2/3. In this case, if the maximum number of slots per frame occupied by one TS is determined in the BS digital broadcasting standard, the maximum number of slots × 8 × 2
It is sufficient to prepare a memory area for two banks of slots. In addition, for example, 8 types of TS are input and 4 types of T are input.
The same applies when S is selected.

In the case of this embodiment, the first embodiment
Similarly to FIG. 4, the enable signal as shown in FIG. 108 (e), that is, the signal in which the MPEG packet valid period of 188 bytes is “H” and the parity section of the RS code of 16 bytes is “L” is The channel selection circuit 1705 of 67 may generate it.

In this embodiment, the PN generation in the de-randomization circuit 1407 is bit serial, but it may be 8-bit parallel PN generation. In that case, the P / S conversion circuit 20030 and the S / P
The conversion circuit 20031 can be eliminated.

(Embodiment 31) Embodiment 3 of the present invention
The error correction circuit in 1 will be described with reference to the drawings. Note that, also in the present embodiment, a case where the superframe structure is temporally constant and “without TMCC” will be described.

FIG. 68 shows "T" described in the fifteenth embodiment.
It is a block diagram which shows the structural example of the error correction circuit 3101 in the case of "there is no MCC" with respect to "there is MCC." This error correction circuit 3101 is the same as that of the first embodiment shown in FIG.
The error correction circuit 1501 of No. 5 is provided with a channel selection circuit 1705 having a different internal configuration, and instead of the transmission control information decoding circuit 20010, the control signal generation circuit 170
The feature is that 4 is provided. Other blocks, that is, the speed conversion circuit 1502, the Viterbi decoder 2000
Each function of the 2-RS decoding circuit 20008 is the same as that shown in FIG.

In error correction circuit 3101 of the present embodiment, channel selection circuit 1705 generates a slot selection signal and outputs it to speed conversion circuit 1502 of FIG. 69, as in the case of the twenty-ninth embodiment. The speed conversion circuit 1502 performs the same operation as in the fifteenth embodiment.

The error correction capability of error correction circuit 3101 shown above is secured to the same extent as the error correction circuit of the fifteenth embodiment.

As in the fifteenth embodiment, for example, B
If the maximum number of slots per frame occupied by one TS is determined in the S digital broadcasting standard, a memory area for the maximum number of slots may be prepared.
The memory area used by the memory circuit 1506 is not limited to 24 slots as in the fifteenth embodiment.

Further, similar to the fifteenth embodiment, for example, TS1: <higher layer image> TC-8PSK: 14 slots <lower layer image> QPSK (r = 1/2): 2 slots (of which dummy 1 Slot) TS2: <Higher layer image> TC-8PSK: 12 slots <Lower layer image> QPSK (r = 3/4): 4 slots (1 dummy slot) TS3: <Higher layer image> TC- 8PSK: 12 slots <Lower layer image> BPSK (r = 1/2): 4 slots (including 3 dummy slots) Let us consider a case where three types of TS are input. That is, 3TS is assigned to one transponder. When one type of TS is selected, as in the fifteenth embodiment, only the selected 1TS is written into the memory circuit 1506, the speed is converted, and the TS is read at a speed of 16/48 = 1/3. Should be done. When two kinds of TSs are selected, for example, when one TS is displayed on the monitor and the other TS is video-recorded, only the selected 2TS is stored in the memory circuit 15.
Write to 06, speed conversion is performed and 32/48 = 2/3
The reading may be performed at the speed of. In this case, if the maximum number of slots per frame occupied by one TS is determined in the BS digital broadcasting standard, a memory area of maximum number of slots × 2 slots may be prepared. In addition, for example, 8 types of TS are input and 4 types of T are input.
The same applies when S is selected.

Further, as described in the fifteenth embodiment, the speed conversion circuit 1508 may have a structure in which the speed of a plurality of selected TSs is speed-converted and continuously output in parallel.

FIG. 70 shows "TMC" for the error correction circuit 1507 in the case of "with TMCC" shown in FIG.
It is a block diagram which shows the structural example of the error correction circuit 3102 which has the function of the parallel output in the case of "no C." This error correction circuit 3102 is different from the error correction circuit 1507 of the fifteenth embodiment shown in FIG. 43 in that a channel selection circuit 1705 having a different internal configuration is provided and that the transmission control information decoding circuit 2 is provided.
A characteristic is that a control signal generation circuit 1704 is provided instead of 0010. The other functions of each block, that is, the speed conversion circuit 1508 and the Viterbi decoder 20002 to RS decoding circuit 20008) are the same as those shown in FIG.

The speed conversion circuit 1508 is the tuning circuit 170.
71, the same operation as that of the fifteenth embodiment is performed in accordance with the slot selection signal output from No. 5.

The error correction capability of error correction circuit 3102 described above is secured to the same extent as the error correction circuit of the fifteenth embodiment.

A configuration may be considered in which 16 bytes of the parity bytes are not read from or written to the memory circuit 1506 or the memory circuit 1512, and speed conversion is performed. In this case, the memory circuit 1506 or the memory circuit 1512
Can be reduced to 188/204 = 47/51,
The read address generation circuit 1505 or the read address generation circuit 1511 does not need to generate the enable signal. The 47/51 speed conversion can be easily realized, for example, by providing a counter circuit that outputs a ripple carry (carry) signal when the count value becomes 51 and inputting 47 to the counter circuit. In this case, the ripple carry signal is output at the speed of 47/51 of the input.

(Embodiment 32) Embodiment 3 of the present invention
The error correction circuit in 2 will be described with reference to the drawings. Note that, also in the present embodiment, a case where the superframe structure is temporally constant and “without TMCC” will be described.

FIG. 72 is a block diagram showing a configuration example of the error correction circuit 3201 in the case of “without TMCC” with respect to the error correction circuit 1601 in the case of “with TMCC”. This error correction circuit 3201 is different from the error correction circuit 1601 of the sixteenth embodiment shown in FIG. 45 in that a channel selection circuit 1705 having a different internal configuration is provided, and instead of transmission control information decoding circuit 20010, a control signal generation circuit is generated. The feature is that the circuit 1704 is provided. Each of the other blocks, that is, the de-interleave circuit 1302, the speed conversion circuit 1602, the Viterbi decoder 20002-symbol /
Byte conversion circuit 20004, MPEG synchronization byte / dummy slot insertion circuit 20006 to RS decoding circuit 200
Each function of 08 is the same as that shown in FIG.

In the error correction circuit 3201 of this embodiment, as described in the twenty-ninth embodiment, FIG.
The de-interleaved data shown in (b) is
It is output from the interleave circuit 1302. The number of effective slots per frame in one TS is 24.

As shown in FIG. 35 (b), the byte data series output from the de-interleave circuit 1302 is an MPEG sync byte / dummy.
Slot insertion circuit 20006, de-randomization circuit 2
It is processed by the RS decoding circuit 20008 and output to the speed conversion circuit 1602. The channel selection circuit 1705 generates a slot selection signal and outputs it to the speed conversion circuit 1602 of FIG. 73, as in the twenty-ninth embodiment. The speed conversion circuit 1602 performs the same operation as in the sixteenth embodiment.

The error correction capability of error correction circuit 3201 shown above is secured to the same extent as the error correction circuit of the sixteenth embodiment.

As in the sixteenth embodiment, for example, B
If the maximum number of slots per frame occupied by one TS is determined in the S digital broadcasting standard, a memory area for the maximum number of slots may be prepared.
The memory area used by the memory circuit 1606 is not limited to 24 slots as in the sixteenth embodiment.

As in the sixteenth embodiment, for example, TS1: <higher layer image> TC-8PSK: 14 slots <lower layer image> QPSK (r = 1/2): 2 slots (of which dummy 1 Slot) TS2: <Higher layer image> TC-8PSK: 12 slots <Lower layer image> QPSK (r = 3/4): 4 slots (1 dummy slot) TS3: <Higher layer image> TC- 8PSK: 12 slots <Lower hierarchy image> BPSK (r = 1/2): 4 slots (3 dummy slots), where three kinds of TSs are input will be considered. That is, 3TS is assigned to one transponder. When one kind of TS is selected, as in the sixteenth embodiment, only the selected 1TS is written in the memory circuit 1606, the speed is converted, and the TS is read at a speed of 16/48 = 1/3. Should be done. When two kinds of TSs are selected, for example, when one TS is displayed on the monitor and the other TS is video-recorded, only the selected 2TS is stored in the memory circuit 16.
Write to 06, speed conversion is performed and 32/48 = 2/3
The reading may be performed at the speed of. In this case, if the maximum number of slots per frame occupied by one TS is determined in the BS digital broadcasting standard, a memory area of maximum number of slots × 2 slots may be prepared. In addition, for example, 8 types of TS are input and 4 types of T are input.
The same applies when S is selected.

As described in the sixteenth embodiment, the speed conversion circuit 1608 may have a structure in which a plurality of selected TSs are speed-converted and continuously output in parallel.

FIG. 74 is a block diagram showing a configuration example of the error correction circuit 3202 having a parallel output function in the case of “without TMCC” with respect to the error correction circuit 1607 in the case of “with TMCC”. This error correction circuit 3202
Is the error correction circuit 160 of the sixteenth embodiment shown in FIG.
7, the channel selection circuit 1705 having a different internal configuration is provided, and the control signal generation circuit 1704 is provided instead of the transmission control information decoding circuit 20010. Other blocks, namely de-interleave circuit 1302, speed conversion circuit 1608, Viterbi decoder 20002 to symbol / byte conversion circuit 20004, M
PEG sync byte / dummy slot insertion circuit 2000
Functions of the 6-RS decoding circuit 20008 are the same as those shown in FIG.

The speed conversion circuit 1608 performs the same operation as that of the sixteenth embodiment by the slot selection signal output from the channel selection circuit 1705 as shown in FIG.

The error correction capability of error correction circuit 3202 shown above is ensured to the same extent as the error correction circuit of the sixteenth embodiment.

As in the sixteenth embodiment, it is also possible to adopt a structure in which the 16-byte parity byte is subjected to speed conversion without being read from or written to the memory circuit 1606 or the memory circuit 1612. In this case, the memory circuit 1606
Alternatively, the use area of the memory circuit 1612 is set to 188/204 =
The read address generation circuit 16 can be reduced to 47/51.
05 or the read address generation circuit 1611 does not need to generate the enable signal. The 47/51 speed conversion can be easily realized, for example, by providing a counter circuit that outputs a ripple carry (carry) signal when the count value becomes 51 and inputting 47 to the counter circuit. In this case, the ripple carry signal is output at a speed of 47/51 of the input.

In the first embodiment, the error correction circuit 101 conforms to the BS digital broadcasting standard system currently under discussion, and the error correction coding apparatus 10001 shown in FIG.
The Viterbi decoding is performed on the data sequence encoded by the above method, the influence of the transmission mode B after the transmission mode switching is completely cut off, and the transmission mode A before the transmission mode switching that remains in the path memory 20021 when the transmission mode is switched. It is configured to output Viterbi decoded data.

However, the transmission frame is composed of symbols of a plurality of modulation schemes and a plurality of coding rates, and information about the modulation scheme / coding rate of each symbol is included as transmission control information for each frame, and the symbols of each frame are included. Performs Viterbi decoding on a data sequence that has been convolutionally encoded by one convolutional encoder and transmitted over different modulation schemes and encoding rates by the same configuration as in the first embodiment. It is obvious that the influence of the transmission mode B after the transmission mode switching can be completely cut off and the Viterbi decoded data of the transmission mode A before the transmission mode switching remaining in the path memory 20021 at the time of the transmission mode switching can be output.

Further, in the above second to twelfth embodiments,
Error correction circuits 201, 301, 401, 501, 60
1, 701, 801, 901, 1001, 1101, and 1201 comply with the BS digital broadcasting standard system currently under discussion, and Viterbi-decode the data sequence encoded by the error correction encoding device 10001 in FIG. . Then, by utilizing the property of the fixed symbol sequence of the TAB signal added before and after the TMCC, the influence of the transmission modes before and after the transmission mode switching of the TMCC is completely cut off, and the path memory 20021 when the transmission mode is switched. The remaining Viterbi decoded data of TMCC is output.

However, the transmission frame is composed of symbols of a plurality of modulation schemes and a plurality of coding rates, and when the modulation schemes and coding rates are switched, the final symbol before switching is followed by a fixed symbol sequence for termination. , The information regarding the modulation scheme and coding rate of each symbol is included as transmission control information for each frame, and the symbols of each frame exceed different modulation schemes and coding rates,
The data sequences which are convolutionally encoded by one convolutional encoder and transmitted are transmitted as in the above-mentioned Embodiments 2 to 1.
Viterbi decoding is performed with the same configuration as that of 2. Then, by utilizing the property of the fixed symbol sequence, the influence of the transmission mode B after the transmission mode switching is completely cut off, and the transmission mode A before the transmission mode switching remaining in the path memory 20021 at the time of the transmission mode switching. It is obvious that Viterbi decoded data can be output.

In the thirteenth embodiment, the error correction circuit 1301 conforms to the BS digital broadcasting standard system currently under discussion, and the error correction coding apparatus 100 of FIG.
The data series encoded in 01 is de-interleaved, and only the selected TS is read / written to / from the memory circuit 1306 to reduce the memory area used.

However, in the transmission method in which a plurality of MPEG transport streams are transmitted in a transmission format in which they are multiplexed, a data sequence of each packet unit of the MPEG transport stream is used as a slot.
When 1 frame = M slots and 1 superframe = N frames, the transport stream number information of each slot is included in the superframe as transmission control information, and the superframe has a depth of N in units of slots. A memory area to be used by deinterleaving a data sequence transmitted after interleaving M slots by the same configuration as in the thirteenth embodiment and reading and writing only the selected TS into the memory circuit 1306. It is clear that can be reduced.

In the fourteenth embodiment, error correction circuit 1401 conforms to the BS digital broadcasting standard system currently under discussion, and error correction coding apparatus 100 in FIG.
The data sequence encoded in 01 is de-interleaved, and only the selected TS is subjected to speed conversion and output.

However, in the transmission method in which a plurality of MPEG transport streams are transmitted in a transmission format in which they are multiplexed, a data sequence of each packet unit of the MPEG transport stream is used as a slot,
When 1 frame = M slots and 1 superframe = N frames, the transport stream number information of each slot is included in the superframe as transmission control information, and the superframe has a depth of N in units of slots. It is clear that the data sequence transmitted after M slots are transmitted by M slots can be deinterleaved by the configuration similar to that of Embodiment 14 and only the selected TS can be speed-converted and output.

In the fourteenth embodiment, error correction circuit 1401 conforms to the BS digital broadcasting standard system currently under discussion, and error correction coding apparatus 100 shown in FIG.
The data sequence encoded in 01 is de-interleaved, and the data sequence output by speed-converting only the selected TS is the second byte of all 48 × 8 slots (one superframe). An initial value generation circuit 1409 capable of generating an initial value is provided to perform de-randomization.

However, in the transmission method in which a plurality of MPEG transport streams are transmitted in a transmission format in which they are multiplexed, a data sequence of each packet unit of the MPEG transport stream is used as a slot,
When 1 frame = M slots and 1 superframe = N frames, transport stream number information of each slot is included in the superframe as transmission control information, and randomization is continuously performed in superframe units. It is obvious that the data sequence to be transmitted can be de-randomized by the same configuration as that of the fourteenth embodiment.

Further, in the fifteenth embodiment, the error correction circuit 1501 and the error correction circuit 1507 comply with the standard system of BS digital broadcasting under discussion and are coded by the error correction coding device 10001 of FIG. The speed of the selected data series is converted, and only the selected TS is read / written to / from the memory circuit 1506 or the memory circuit 1512 to reduce the memory area used.

However, in the transmission method in which a plurality of MPEG transport streams are transmitted in a transmission format in which they are multiplexed, a data sequence of each packet unit of the MPEG transport stream is used as a slot,
When 1 frame = M slots and 1 superframe = N frames, the transport stream number information of each slot is included in the superframe as transmission control information, and the data sequence transmitted is described in the first embodiment.
It is obvious that the memory area to be used can be reduced by performing speed conversion in the same configuration as in No. 5 and reading and writing only the selected TS into the memory circuit 1506 or the memory circuit 1512.

In the sixteenth embodiment, the error correction circuit 1601 and the error correction circuit 1607 are coded in the error correction coding device 10001 of FIG. The de-interleaved data sequence is output, and only the selected TS is output from the de-interleave circuit 1302. The speed conversion circuit 1602 or the speed conversion circuit 1608 speed-converts the data sequence, and only the selected TS is stored in the memory. Circuit 16
06 or the memory circuit 1612 is read / written to reduce the memory area used.

However, in the transmission system in which a plurality of MPEG transport streams are transmitted in the transmission format in which they are multiplexed, the data sequence of each packet unit of the MPEG transport stream is used as a slot,
When 1 frame = M slots and 1 superframe = N frames, the transport stream number information of each slot is included in the superframe as transmission control information, and the superframe has a depth of N in units of slots. The data sequence transmitted after M slots are interleaved is deinterleaved by the same configuration as in Embodiment 16 above, and only the TS selected by the deinterleave circuit 1302 is output, and the speed conversion circuit 1602 is output. Alternatively, the speed conversion circuit 1608 speed-converts the data sequence, and only the selected TS is stored in the memory circuit 16.
It is obvious that the memory area to be used can be reduced by reading / writing to the memory 06 or the memory circuit 1612.

Further, in the seventeenth embodiment, the error correction circuit 1703 is "no TMCC" in the standard system of BS digital broadcasting currently under discussion, that is, the error of FIG. 49 in which the superframe structure is constant over time. In the correction encoding device 1701, the data sequence encoded as shown in FIG. 53 is Viterbi-decoded to completely cut off the influence of the transmission mode B after the transmission mode is switched, and remains in the path memory 20021 when the transmission mode is switched. The Viterbi decoded data of the transmission mode A before the transmission mode switching is output.

However, the data sequence on the transmission side is composed of symbols of a plurality of modulation schemes and a plurality of coding rates, and each symbol exceeds one of the different modulation schemes and coding rates and is continuously convolutionally coded. A data sequence that has been convolutionally coded by a filter and transmitted is used in the first embodiment.
Viterbi decoding with the same configuration as in FIG. 7 completely cuts off the influence of the transmission mode B after the transmission mode switching, and the Viterbi decoding of the transmission mode A before the transmission mode switching that remains in the path memory 20021 when the transmission mode is switched. Obviously, the data can be output.

In the eighteenth to twenty-eighth embodiments, the error correction circuits 1801, 1901, 2001 and 21 are used.
01, 2201, 2301, 2401, 2501, 26
53, in the error correction coding device 1701 of FIG. 49 in which the superframe structure is temporally constant in the standard system of BS digital broadcasting currently under discussion, “no TMCC”. The effect of the transmission mode before and after the transmission mode switching of the character multiplex data is obtained by performing the Viterbi decoding of the data sequence encoded in the above and using the property of the fixed symbol sequence of the TAB signal added before and after the character multiplex data. Is completely cut off, and the Viterbi decoded data of the character multiplex data remaining in the path memory 20021 is output when the transmission mode is switched.

However, the data sequence on the transmission side is composed of symbols of a plurality of modulation schemes and a plurality of coding rates, and at the time of switching of the modulation schemes and coding rates, the final symbol before switching is followed by termination. In some cases, a fixed symbol sequence is included, and each symbol exceeds the different modulation schemes and coding rates, and is convolutionally coded by one convolutional encoder in succession, and then transmitted. In the same manner as in the forms 18 to 28
By utilizing the property of the fixed symbol sequence, the influence of the transmission mode B after the transmission mode switching is completely cut off, and the Viterbi decoding of the transmission mode A before the transmission mode switching remaining in the path memory 20021 at the time of the transmission mode switching is performed. Obviously, the data can be output.

Also, in the twenty-ninth embodiment, the error correction circuit 2901 has the error of FIG. 49 in which "no TMCC", that is, the superframe structure is constant over time, in the standard system of BS digital broadcasting currently under discussion. The correction coding device 1701 is configured to reduce the memory area to be used by de-interleaving the coded data sequence as shown in FIG. 97 and reading and writing only the selected slot in the memory circuit 1306. .

However, in the transmission format, when the fixed-length data sequence of the minimum unit is a slot and 1 frame = M slots and 1 super frame = N frames, interleaving of depth N in slot units within the super frame is performed. It is possible to reduce the memory area to be used by de-interleaving the data sequence transmitted for M slots and having the same configuration as that of the twenty-ninth embodiment, and reading and writing only the selected slot to the memory circuit 1306. Is clear.

Further, in the thirtieth embodiment, the error correction circuit 3001 has the error of FIG. 49 in which "no TMCC", that is, the superframe structure is constant in time, in the standard system of BS digital broadcasting currently under discussion. The correction coding device 1701 is configured to de-interleave the coded data sequence as shown in FIG. 97 and output the speed-converted only selected slots.

However, in the transmission format, when the fixed-length data sequence of the minimum unit is a slot and 1 frame = M slots and 1 super frame = N frames, interleaving of depth N in slot units within the super frame is performed. It is clear that the data sequence transmitted for M slots and transmitted can be de-interleaved by the same configuration as in Embodiment 30 and only the selected slot can be speed-converted and output.

Further, in the thirtieth embodiment, the error correction circuit 3001 has the error of FIG. 49 in which "no TMCC", that is, the superframe structure is temporally constant, in the standard system of BS digital broadcasting currently under discussion. In the correction encoding device 1701, the data sequence encoded as shown in FIG. 97 is de-interleaved, and the data sequence output by speed-converting only the selected slot is converted into 4
An initial value generation circuit 1409 capable of generating the initial value of the second byte for all 8 × 8 slots (for one superframe) is provided to perform derandomization.

However, in the transmission format, when the fixed length data sequence of the minimum unit is a slot and 1 frame = M slots and 1 superframe = N frames, randomization is continuously performed and transmitted in superframe units. It is obvious that the data sequence according to the present embodiment can be de-randomized by the same configuration as in the thirtieth embodiment.

Further, in the thirty-first embodiment, the error correction circuit 3101 and the error correction circuit 3102 are the "TMC" in the standard system of BS digital broadcasting currently under discussion.
C ", that is, in the error correction coding apparatus 1701 of FIG. 49 in which the superframe structure is constant over time, the data sequence coded as shown in FIG. 97 is subjected to speed conversion and only the selected slot is stored in the memory. By reading / writing the circuit 1506 or the memory circuit 1512, the memory area to be used is reduced.

However, in the transmission format, when the fixed length data sequence of the minimum unit is a slot and 1 frame = M slots and 1 super frame = N frames, the transmitted data sequence is the same as that in the above-mentioned thirty-first embodiment. With such a configuration, only the slot that has been subjected to speed conversion and has been tuned to is selected by the memory circuit 1506 or the memory circuit 1512.
It is clear that the memory area used can be reduced by reading and writing to.

[0466] In addition, in the above-mentioned thirty-second embodiment, in the standard system of BS digital broadcasting currently under discussion, "TM
No CC ”, that is, in the error correction coding device 1701 of FIG. 49 in which the superframe structure is temporally constant,
The data sequence encoded as shown in FIG. 97 is de-interleaved, only the selected slot is output from the de-interleave circuit 1302, and the speed conversion circuit 1602 or the speed conversion circuit 1608 speed-converts the data sequence, By reading and writing only the selected slot from the memory circuit 1606 or the memory circuit 1612, the memory area used is reduced.

However, in the transmission format, when the fixed-length data sequence of the minimum unit is a slot and 1 frame = M slots and 1 superframe = N frames, interleaving of depth N in slot units within the superframe is performed. The data sequence transmitted for M slots and transmitted is de-interleaved by the same configuration as in the above-described thirty-second embodiment, and only the selected slot is output from the de-interleave circuit 1302. It is obvious that the circuit 1608 can speed-convert the data sequence and read / write only the selected slot to / from the memory circuit 1606 or the memory circuit 1612 to reduce the memory area used.

Further, in the above-mentioned first embodiment, for the last symbol of the transmission mode A before the transmission mode switching, only one state having the minimum path metric in the trellis diagram is valid.

Instead, ACS circuit 105 of FIG.
However, the value of the path metric memory 20020 may be reset using a switching control signal output from the Viterbi decoder control circuit 103. That is, as shown in the trellis diagram of FIG. 119, the transmission mode A before the transmission mode switching
For the last symbol of, the one-state path metric (Path M
etric: PM) only, the smallest possible value, eg "
0 ". Then, the other states are reset to the maximum possible values. With this configuration, the influence of the transmission mode B after the mode switching is cut off and remains in the path memory 20021 when the transmission mode is switched. Transmission mode A before mode switching
The Viterbi decoded data of can be output. According to this configuration, since the value of the path metric memory 20020 is simply reset, there is an advantage that the control becomes simple.

In the second embodiment, the ACS circuit 205 of FIG. 6 uses the definite state signal output from the Viterbi decoder control circuit 203 to validate only one definite state and set the other states. The path metric memory 20020 and the path memory 20021 are controlled so as to invalidate all of them.

Instead, ACS circuit 205 of FIG.
However, using the definite state signal, the path metric memory 200
The value of 20 may be reset. That is, FIG.
As shown in the 0 trellis diagram, only the determined 1-state path metric is set to the minimum possible value, for example, “0”. Then, the other states are reset to the maximum possible values. With this configuration, the influence of the transmission mode B after the mode switching is blocked, and the path memory 200 is switched when the transmission mode is switched.
No. 21 remaining TMCC (BPS before mode switching)
Viterbi decoded data of K: r = 1/2) can be output. According to this configuration, the path metric memory 20
Since the value of 020 is simply reset, there is an advantage that control becomes simple.

Also in the above configuration, FIG.
As shown in (a), the Viterbi decoder control circuit 20 of FIG.
3 is the 10th symbol (S) of each TAB signal (w1, w2, w3) from the time when the first symbol of 20 symbols (10 symbols after S / P conversion) is input to the path memory 20021. It is not necessary to limit the configuration to generate the definite state signal and output the definite state signal to the ACS circuit 205 until the time when (the final symbol after / P conversion) is input to the path memory 20021. As shown in FIGS. 120 (a) to 120 (c), the period during which the definite state signal is generated is 1 symbol or more,
Up to 10 symbols can be arbitrarily selected, and which symbol is also selected arbitrarily.

By simulation, the effect of improving the BER by the above configuration was examined. FIG. 121 is a configuration diagram of a transmission frame used in the simulation. FIG. 121
FIG. 121 (b) is a signal arrangement diagram at the time of input to the Viterbi decoder 202 (TMCC is before S / P conversion).
[Fig. 6] is a signal layout diagram at the time of input to the path memory 20021 (TMCC is after S / P conversion). The path memory length is 64, and the main signal after TMCC is TC-8PSK (r = 2
/ 3) Only 64 symbols are used. Just before the first symbol of TMCC is input by the main signal of 64 symbols, the path memory 20021 has TC-8PSK (r = 2).
/ 3) The state is filled with 64 symbols.

FIG. 122 shows the above simulation result under the condition of C / N = -2 dB. Path memory 2
At the time when the last symbol of the rear TAB signal (w2 or w3) is input to 0021, the path memory 20021
The BER of each symbol was calculated for the remaining 64 symbols. The horizontal axis represents the 64 symbols remaining in the path memory 20021, and the vertical axis represents the BER value. FIG. 122 shows a case where the value of the path metric memory 20020 is reset at the first symbol or the last symbol of the rear TAB signal (w2 or w3).

As is clear from FIG. 122, the “with termination processing” of this embodiment has a higher error rate of each symbol remaining in the path memory 20021 than the “without termination processing” of the conventional example. You can see that it has been improved. In addition, the path metric memory 20 is defined by the first symbol of the rear TAB signal.
It can be said that resetting the value of 020 is more effective than resetting with the last symbol, because the BER of the net TMCC data shown by the 0th to 47th symbols in FIG. 122 is reduced.

In addition, in the above-mentioned fourth embodiment, FIG.
The ACS circuit 405 of the above uses the state reduction signal output from the Viterbi decoder control circuit 403 for each of the leading 6 symbols (after S / P conversion) of each TAB signal (after S / P conversion). The number of states is halved. For the subsequent 10 symbols (after S / P conversion), it is set to 1
Path metric memory 2 so that only the state is valid
0020 and the path memory 20021 are controlled.

Instead, the ACS circuit 405 of FIG.
Using the state reduction signal, the path metric memory 200
The value of 20 may be reset. That is, each T
For the first 6 symbols (after S / P conversion) of the AB signal,
Determined 32 for each symbol (after S / P conversion), 1
Only the path metrics of the states 6, 8, 4, 2, 1 are set to the minimum possible values, for example, “0”, and the other states are reset to the maximum possible values. With such a configuration, the influence of the transmission mode B after the mode switching is blocked, and the Viterbi decoded data of the TMCC (BPSK: r = 1/2) before the mode switching that remains in the path memory 20021 when the transmission mode is switched. Can be output. According to such a configuration, since the value of the path metric memory 20020 is simply reset, there is an advantage that the control becomes simple.

Further, in the above-mentioned sixth embodiment, FIG.
Similar to the second embodiment shown in (a) to (c), the ACS circuit 605 of FIG. 20 uses the definite state signal output from the Viterbi decoder control circuit 603 to validate only one definite state, The path metric memory 20020 and the path memory 20021 are controlled so as to invalidate all other states.

Instead, the ACS circuit 605 of FIG.
Is a path metric memory 2002 using the definite state signal.
The value of 0 may be reset. That is, the minimum value that can take only the determined one-state path metric,
For example, it is set to "0" and other states are reset to the maximum possible values. With this configuration, the influence of the transmission mode B after the mode switching is blocked, and the TMC before the mode switching that remains in the path memory 20021 when the transmission mode is switched.
Viterbi decoded data of C (BPSK: r = 1/2) can be output. According to such a configuration, since the value of the path metric memory 20020 is simply reset, there is an advantage that the control becomes simple.

[0480] Further, in the above-mentioned eighth embodiment, FIG.
Similar to the second embodiment shown in (a) to (c), the ACS circuit 805 in FIG. 24 uses the definite state signal output from the Viterbi decoder control circuit 803 to validate only one definite state. The path metric memory 20020 and the path memory 20021 are controlled so as to invalidate all other states. Further, similarly to the fourth embodiment shown in FIG. 13, the ACS circuit 805 is the Viterbi decoder control circuit 803.
The state reduction signal output from the TAB signal is used to control the path metric memory 20020 and the path memory 20021 for the first 6 symbols (after S / P conversion) of each TAB signal. The number of states is reduced by half until the convolution circuit 10014 is set to one state.

Instead, the ACS circuit 805 of FIG.
However, using the definite state signal, the path metric memory 200
The value of 20 may be reset. That is, only the determined path metric of one state is set to the minimum possible value, for example, “0”, and the other states are reset to the maximum possible values. Further, the ACS circuit 805 may be configured to reset the value of the path metric memory 20020 using the state reduction signal. That is, with respect to the first 6 symbols (after S / P conversion) of each TAB signal, the determined 32, 16, 8, 4, are determined for each symbol (after S / P conversion).
Only the path metric of the 2 and 1 states is set to the minimum possible value, for example, “0”, and the other states are reset to the maximum possible values. With such a configuration, the influence of the transmission mode B after the mode switching is blocked, and the T before the mode switching remaining in the path memory 20021 at the time of the transmission mode switching.
Viterbi decoded data of MCC (BPSK: r = 1/2) can be output. According to such a configuration, since the value of the path metric memory 20020 is simply reset, there is an advantage that the control becomes simple.

Further, in the above-mentioned eighth embodiment, FIG.
In the Viterbi decoder control circuit 803, the first symbol of 20 symbols (10 symbols after S / P conversion) of each TAB signal (w1, w2, w3) is stored in the path memory 20021 as shown in FIG. From the time when the TAB signal is input to the path memory 20021 to the time when the tenth symbol (the final symbol after S / P conversion) of each TAB signal is input to the ACS circuit 805. did.

Instead, the ACS circuit 805 of FIG.
However, the value of the path metric memory 20020 may be reset by using the definite state signal output from the Viterbi decoder control circuit 803. That is, as shown in FIG. 120, only the determined path metric of one state is set to the minimum possible value, for example, “0”, and the other states are reset to the maximum possible values. With such a configuration, the influence of the transmission mode B after the mode switching is blocked, and the Viterbi decoded data of the TMCC (BPSK: r = 1/2) before the mode switching that remains in the path memory 20021 when the transmission mode is switched. Can be output. According to such a configuration, since the value of the path metric memory 20020 is simply reset, there is an advantage that the control becomes simple.

In addition, in the ninth embodiment, as shown in FIG.
The ACS circuit 905 of FIG. 13 uses the state reduction signal output from the Viterbi decoder control circuit 903 in the same manner as in the fourth embodiment shown in FIG. 13 to start the first 6 symbols of each TAB signal (after S / P conversion). For the path metric memory 2
0020 and the path memory 20021 were controlled.
The number of states is reduced by half until the convolutional circuit 10014 is set to one state.

Instead, the ACS circuit 905 of FIG.
Using the state reduction signal 2002
The value of 0 may be reset. That is, each TA
1 for the first 6 symbols (after S / P conversion) of the B signal
For each symbol (after S / P conversion), confirmed 32, 16,
Only the path metric of the 8, 4, 2, 1 states is set to the minimum possible value, for example, “0”, and the other states are reset to the maximum possible values. With such a configuration, the influence of the transmission mode B after the mode switching is blocked, and the Viterbi decoded data of the TMCC (BPSK: r = 1/2) before the mode switching that remains in the path memory 20021 when the transmission mode is switched. Can be output. According to such a configuration, since the value of the path metric memory 20020 is simply reset, there is an advantage that the control becomes simple.

In addition, in the tenth embodiment, as shown in FIG.
8 is an ACS circuit 1005 according to the fourth embodiment shown in FIG.
In the same manner as described above, the state reduction signal output from the Viterbi decoder control circuit 1003 is used to control the path metric memory 20020 and the path memory 20021 for the first 6 symbols (after S / P conversion) of each TAB signal. I was going. The number of states is reduced by half until the convolutional circuit 10014 is set to one state.

Instead, ACS circuit 100 of FIG.
5 uses the state reduction signal to make the path metric memory 20
The value of 020 may be reset. That is, the top 6 symbols (after S / P conversion) of each TAB signal are determined for each symbol (after S / P conversion) 32,
Only the path metric of the 16, 8, 4, 2, 1 state is set to the minimum possible value, for example, “0”, and the other states are reset to the maximum possible values. With this configuration,
The influence of the transmission mode B after the mode switching can be blocked, and the Viterbi decoded data of the TMCC (BPSK: r = 1/2) before the mode switching remaining in the path memory 20021 at the time of the transmission mode switching can be output. . According to such a configuration, since the value of the path metric memory 20020 is simply reset, there is an advantage that the control becomes simple.

Further, in the above eleventh embodiment, FIG.
The ACS circuit 1105 of 0 is similar to the second embodiment shown in FIGS. 7A to 7C, and the Viterbi decoder control circuit 11
The confirmed state signal output from 03 is used to determine 1
The path metric memory 20020 and the path memory 20 are set so that only the states are valid and all other states are invalid.
021 was being controlled. In addition, the ACS circuit 1105
Is the same as in the fourth embodiment shown in FIG. 13, using the state reduction signal output from the Viterbi decoder control circuit 1103, the head 6 symbols of each TAB signal (after S / P conversion).
For the above, the path metric memory 20020 and the path memory 20021 were controlled. The number of states is reduced by half until the convolutional circuit 10014 is set to one state.

Instead, the ACS circuit 110 of FIG.
5 uses the deterministic state signal to determine the path metric memory 20.
The value of 020 may be reset. That is, only the determined path metric of one state is set to the minimum possible value, for example, “0”, and the other states are reset to the maximum possible values. Further, the ACS circuit 1105 may be configured to reset the value of the path metric memory 20020 using the state reduction signal. That is, with respect to the first 6 symbols (after S / P conversion) of each TAB signal, the determined 32, 16, 8, 4, are determined for each symbol (after S / P conversion).
Only the path metric of the 2 and 1 states is set to the minimum possible value, for example, “0”, and the other states are reset to the maximum possible values. With such a configuration, the influence of the transmission mode B after the mode switching is blocked, and the T before the mode switching remaining in the path memory 20021 at the time of the transmission mode switching.
Viterbi decoded data of MCC (BPSK: r = 1/2) can be output. According to such a configuration, since the value of the path metric memory 20020 is simply reset, there is an advantage that the control becomes simple.

In addition, in the eleventh embodiment, FIG.
As shown in FIG. 7A, the Viterbi decoder control circuit 1103 of 0 passes the first symbol of each TAB signal (w1, w2, w3) 20 symbols (10 symbols after S / P conversion) From the time of input to the memory 20021, each T
The fixed state signal is generated and output to the ACS circuit 205 until the 10th symbol of the AB signal (the final symbol after S / P conversion) is input to the path memory 20021.

Instead, ACS circuit 110 of FIG.
5 may be configured to reset the value of the path metric memory 20020 using the definite state signal output from the Viterbi decoder control circuit 1103. That is, as shown in FIG. 120, only the determined path metric of one state is set to the minimum possible value, for example, “0”, and the other states are reset to the maximum possible values. With this configuration,
The influence of the transmission mode B after the mode switching can be blocked, and the Viterbi decoded data of the TMCC (BPSK: r = 1/2) before the mode switching remaining in the path memory 20021 at the time of the transmission mode switching can be output. . According to such a configuration, since the value of the path metric memory 20020 is simply reset, there is an advantage that the control becomes simple.

Further, in the twelfth embodiment, FIG.
The ACS circuit 1205 of No. 2 is the fourth embodiment shown in FIG.
In the same manner as described above, the state reduction signal output from the Viterbi decoder control circuit 1203 is used to control the path metric memory 20020 and the path memory 20021 for the first 6 symbols (after S / P conversion) of each TAB signal. I was going. The number of states is reduced by half until the convolutional circuit 10014 is set to one state.

Instead, ACS circuit 120 of FIG.
5 uses the state reduction signal to make the path metric memory 20
The value of 020 may be reset. That is, the top 6 symbols (after S / P conversion) of each TAB signal are determined for each symbol (after S / P conversion) 32,
Only the path metric of the 16, 8, 4, 2, 1 state is set to the minimum possible value, for example, “0”, and the other states are reset to the maximum possible values. With this configuration,
The influence of the transmission mode B after the mode switching can be blocked, and the Viterbi decoded data of the TMCC (BPSK: r = 1/2) before the mode switching remaining in the path memory 20021 at the time of the transmission mode switching can be output. . According to such a configuration, since the value of the path metric memory 20020 is simply reset, there is an advantage that the control becomes simple.

[0494] Also, in the above-mentioned seventeenth embodiment, regarding the final symbol of transmission mode A before transmission mode switching,
In the trellis diagram, only one state having the minimum path metric is valid.

Instead, ACS circuit 105 of FIG.
However, the value of the path metric memory 20020 may be reset using a switching control signal output from the Viterbi decoder control circuit 103. That is, as shown in FIG. 119, regarding the final symbol of the transmission mode A before the transmission mode switching, only the path metric in one state having the minimum path metric in the trellis diagram is set to the minimum possible value, for example, “0”, Reset the other states to the maximum possible values. With such a configuration, the influence of the transmission mode B after the mode switching can be blocked, and the Viterbi decoded data of the transmission mode A before the mode switching that remains in the path memory 20021 at the time of the transmission mode switching can be output. According to such a configuration, the path metric memory 2
Since the value of 0020 is simply reset, there is an advantage that control becomes simple.

In the eighteenth embodiment, FIG.
Of the path metric memory 20020 and the path memory so that the ACS circuit 205 of FIG. 3 uses the fixed state signal output from the Viterbi decoder control circuit 203 to validate only one fixed state and invalidate all other states. The control of 20021 is performed.

Alternatively, the ACS circuit 205 may be configured to reset the value of the path metric memory 20020 using the definite state signal output from the Viterbi decoder control circuit 203. That is, as shown in FIG. 120, only the determined path metric of one state is set to the minimum possible value, for example, “0”, and the other states are reset to the maximum possible values. With such a configuration, the influence of the transmission mode B after the mode switching is blocked, and the Viterbi of the character multiplex data (BPSK: r = 1/2) before the mode switching remaining in the path memory 20021 at the time of the transmission mode switching. Decoded data can be output. According to such a configuration, since the value of the path metric memory 20020 is simply reset, there is an advantage that the control becomes simple.

Also in the above configuration, the Viterbi decoder control circuit 203 of FIG. 6 has 20 symbols (after S / P conversion) of each TAB signal (w1, w2, w3) as shown in FIG. 120 (a). Is 10 symbols), the first symbol is
Each TAB from the time of input to the path memory 20021
10th symbol of signal (final symbol after S / P conversion)
Can be configured to generate the definite state signal and output the definite state signal to the ACS circuit 205 until the time when is input to the path memory 20021. Further, as shown in FIGS. 120 (a) to 120 (c), the period during which the fixed state signal is generated can be arbitrarily selected from 1 symbol or more and up to 10 symbols, and which symbol is also arbitrarily selected. is there.

In addition, in the twentieth embodiment, as shown in FIG.
The second ACS circuit 405 is a Viterbi decoder control circuit 403.
The state reduction signal output from the TAB signal is used to halve the number of states for each of the first 6 symbols (after S / P conversion) of each TAB signal (after S / P conversion), and the subsequent 10
For the symbol (after S / P conversion), the path metric memory 200 is set so that only one fixed state is valid.
20 and the path memory 20021 are controlled.

Alternatively, the ACS circuit 405 may be configured to reset the value of the path metric memory 20020 using the state reduction signal. That is, with respect to the first 6 symbols (after S / P conversion) of each TAB signal, 32, 16, 8 are fixed for each symbol (after S / P conversion).
Only the path metrics of the 4, 2, and 1 states are set to the minimum possible values, for example, “0”, and the other states are reset to the maximum possible values. With such a configuration, the influence of the transmission mode B after the mode switching is blocked, and the Viterbi of the character multiplex data (BPSK: r = 1/2) before the mode switching remaining in the path memory 20021 at the time of the transmission mode switching. Decoded data can be output. According to such a configuration, since the value of the path metric memory 20020 is simply reset, there is an advantage that the control becomes simple.

In the twenty-second embodiment, the ACS circuit 605 of FIG. 20 is the same as that of the second embodiment shown in FIGS. 7A to 7C, and the Viterbi decoder control circuit 60.
Using the definite state signal output from 3, enable only one definite state and invalidate all other states.
Path metric memory 20020 and path memory 2002
1 was being controlled.

Alternatively, the ACS circuit 605 may be configured to reset the value of the path metric memory 20020 using the definite state signal. That is, only the determined path metric of one state is set to the minimum possible value, for example, “0”, and the other states are reset to the maximum possible values. With such a configuration, the influence of the transmission mode B after the mode switching is blocked, and the Viterbi of the character multiplex data (BPSK: r = 1/2) before the mode switching remaining in the path memory 20021 at the time of the transmission mode switching. Decoded data can be output. According to such a configuration, since the value of the path metric memory 20020 is simply reset, there is an advantage that the control becomes simple.

Further, in the twenty-fourth embodiment, FIG.
The ACS circuit 805 of No. 4 has a Viterbi decoder control circuit 803 in the same manner as in the second embodiment shown in FIGS.
The path metric memory 20020 and the path memory 20021 are used so that only one fixed state is made valid and all other states are made invalid by using the fixed state signal output from
Was being controlled. In addition, the ACS circuit 805 is shown in FIG.
In the same manner as in the fourth embodiment shown in FIG. 3, each TA is deleted using the state reduction signal output from the Viterbi decoder control circuit 803.
For the first 6 symbols of the B signal (after S / P conversion),
Path metric memory 20020 and path memory 2002
1 was being controlled. Then, the convolution circuit 100
The number of states is reduced by half until 14 is set to one state.

Alternatively, the ACS circuit 805 may be configured to reset the value of the path metric memory 20020 using the definite state signal. That is, only the determined path metric of one state is set to the minimum possible value, for example, “0”, and the other states are reset to the maximum possible values. Further, the ACS circuit 805 may be configured to reset the value of the path metric memory 20020 using the state reduction signal. That is, for the top 6 symbols (after S / P conversion) of each TAB signal, (S / P)
After P conversion), only the determined path metric of 32, 16, 8, 4, 2, 1 state is taken as the minimum value, for example, "
0 "and reset other states to the maximum possible values. With such a configuration, the influence of the transmission mode B after the mode switching is cut off, and the path memory 2 is switched when the transmission mode is switched.
It is possible to output the Viterbi decoded data of the character multiplexed data (BPSK: r = 1/2) before mode switching remaining in 0021. According to such a configuration, since the value of the path metric memory 20020 is simply reset, there is an advantage that the control becomes simple.

Further, in the twenty-fourth embodiment, FIG.
As shown in FIG. 7A, the Viterbi decoder control circuit 803 of No. 4 passes the first symbol of each TAB signal (w1, w2, w3) 20 symbols (10 symbols after S / P conversion) From the time of input to the memory 20021, each T
The fixed state signal is generated and output to the ACS circuit 205 until the 10th symbol of the AB signal (the final symbol after S / P conversion) is input to the path memory 20021.

Alternatively, the ACS circuit 805 may be configured to reset the value of the path metric memory 20020 using the definite state signal output from the Viterbi decoder control circuit 803. That is, as shown in FIG. 120, only the determined path metric of one state is set to the minimum possible value, for example, “0”, and the other states are reset to the maximum possible values. With such a configuration, the influence of the transmission mode B after the mode switching is blocked, and the T before the mode switching remaining in the path memory 20021 at the time of the transmission mode switching.
Viterbi decoded data of MCC (BPSK: r = 1/2) can be output. According to such a configuration, since the value of the path metric memory 20020 is simply reset, there is an advantage that the control becomes simple.

In addition, in the twenty-fifth embodiment, as shown in FIG.
The ACS circuit 905 of No. 6 uses the state reduction signal output from the Viterbi decoder control circuit 903 in the same manner as in Embodiment 4 shown in FIG. 13 to start the first 6 symbols of each TAB signal (after S / P conversion). ), The path metric memory 20020 and the path memory 20021 were controlled. The number of states is reduced by half until the convolutional circuit 10014 is set to one state.

Alternatively, the ACS circuit 905 may be configured to reset the value of the path metric memory 20020 using the state reduction signal. That is, with respect to the first 6 symbols (after S / P conversion) of each TAB signal, 32, 16, 8 are fixed for each symbol (after S / P conversion).
Only the path metrics of the 4, 2, and 1 states are set to the minimum possible values, for example, “0”, and the other states are reset to the maximum possible values. With such a configuration, the influence of the transmission mode B after the mode switching is blocked, and the Viterbi of the character multiplex data (BPSK: r = 1/2) before the mode switching remaining in the path memory 20021 at the time of the transmission mode switching. Decoded data can be output. According to such a configuration, since the value of the path metric memory 20020 is simply reset, there is an advantage that the control becomes simple.

Further, in the twenty-sixth embodiment, FIG.
8 is an ACS circuit 1005 according to the fourth embodiment shown in FIG.
In the same manner as described above, the state reduction signal output from the Viterbi decoder control circuit 1003 is used to control the path metric memory 20020 and the path memory 20021 for the first 6 symbols (after S / P conversion) of each TAB signal. I was going. The number of states is reduced by half until the convolutional circuit 10014 is set to one state.

Alternatively, the ACS circuit 1005 may be configured to reset the value of the path metric memory 20020 using the state reduction signal. That is, with respect to the first 6 symbols (after S / P conversion) of each TAB signal, 32, 16, 8 are fixed for each symbol (after S / P conversion).
Only the path metrics of the 4, 2, and 1 states are set to the minimum possible values, for example, “0”, and the other states are reset to the maximum possible values. With such a configuration, the influence of the transmission mode B after the mode switching is blocked, and the Viterbi of the character multiplex data (BPSK: r = 1/2) before the mode switching remaining in the path memory 20021 at the time of the transmission mode switching. Decoded data can be output. According to such a configuration, since the value of the path metric memory 20020 is simply reset, there is an advantage that the control becomes simple.

In the twenty-seventh embodiment, as shown in FIG.
The ACS circuit 1105 of 0 is similar to the second embodiment shown in FIGS. 7A to 7C, and the Viterbi decoder control circuit 11
The confirmed state signal output from 03 is used to determine 1
The path metric memory 20020 and the path memory 20 are set so that only the states are valid and all other states are invalid.
021 was being controlled. In addition, the ACS circuit 1105
Is the same as in the fourth embodiment shown in FIG. 13, using the state reduction signal output from the Viterbi decoder control circuit 1103, the head 6 symbols of each TAB signal (after S / P conversion).
For the above, the path metric memory 20020 and the path memory 20021 were controlled. The number of states is reduced by half until the convolutional circuit 10014 is set to one state.

Alternatively, the ACS circuit 1105 may be configured to reset the value of the path metric memory 20020 using the definite state signal. That is, the fixed 1
Only the path metric of the state is set to the minimum possible value, for example, "0", and the other states are reset to the maximum possible values. Further, the ACS circuit 1105 may be configured to reset the value of the path metric memory 20020 using the state reduction signal. That is, for the top 6 symbols (after S / P conversion) of each TAB signal, (S / P)
After P conversion), only the determined path metric of 32, 16, 8, 4, 2, 1 state is taken as the minimum value, for example, "
0 "and reset other states to the maximum possible values. With such a configuration, the influence of the transmission mode B after the mode switching is cut off, and the path memory 2 is switched when the transmission mode is switched.
It is possible to output the Viterbi decoded data of the character multiplexed data (BPSK: r = 1/2) before mode switching remaining in 0021. According to such a configuration, since the value of the path metric memory 20020 is simply reset, there is an advantage that the control becomes simple.

In addition, in the twenty-seventh embodiment, FIG.
As shown in FIG. 7A, the Viterbi decoder control circuit 1103 of 0 passes the first symbol of each TAB signal (w1, w2, w3) 20 symbols (10 symbols after S / P conversion) From the time of input to the memory 20021, each T
The fixed state signal is generated and output to the ACS circuit 1105 until the tenth symbol of the AB signal (the final symbol after S / P conversion) is input to the path memory 20021.

Alternatively, the ACS circuit 1105 may be configured to reset the value of the path metric memory 20020 using the definite state signal output from the Viterbi decoder control circuit 1103. That is, as shown in FIG. 120, only the determined path metric of one state is set to the minimum possible value, for example, “0”, and the other states are reset to the maximum possible values. With such a configuration, the influence of the transmission mode B after the mode switching is blocked, and the Viterbi decoded data of the TMCC (BPSK: r = 1/2) before the mode switching that remains in the path memory 20021 when the transmission mode is switched. Can be output. According to such a configuration, since the value of the path metric memory 20020 is simply reset, there is an advantage that the control becomes simple.

In the twenty-eighth embodiment described above, FIG.
The second ACS circuit 1205 is the same as the fourth embodiment shown in FIG.
In the same manner as described above, the state reduction signal output from the Viterbi decoder control circuit 1203 is used to control the path metric memory 20020 and the path memory 20021 for the first 6 symbols (after S / P conversion) of each TAB signal. I was going. The number of states is reduced by half until the convolutional circuit 10014 is set to one state.

Alternatively, the ACS circuit 1205 may be configured to reset the value of the path metric memory 20020 using the state reduction signal. That is, with respect to the first 6 symbols (after S / P conversion) of each TAB signal, 32, 16, 8 are fixed for each symbol (after S / P conversion).
Only the path metrics of the 4, 2, and 1 states are set to the minimum possible values, for example, “0”, and the other states are reset to the maximum possible values. With such a configuration, the influence of the transmission mode B after the mode switching is blocked, and the Viterbi of the character multiplex data (BPSK: r = 1/2) before the mode switching remaining in the path memory 20021 at the time of the transmission mode switching. Decoded data can be output. According to such a configuration, since the value of the path metric memory 20020 is simply reset, there is an advantage that the control becomes simple.

[0517]

As described above, according to the invention of the present application, with respect to the symbols before the transmission mode switching remaining in the path memory, the minimum path is determined by the path metric accumulated up to the final symbol of the transmission mode before the switching. It is possible to determine the metric, output it as Viterbi decoded data, and perform Viterbi decoding that is not affected by the symbols of the transmission mode after switching.

Further, according to the invention of the present application, in the case where the transmission control information is transmitted, the symbols remaining in the path memory before the transmission mode switching are accumulated in the path metric up to the final symbol of the transmission mode before the switching. Thus, the minimum path metric can be determined and output as Viterbi decoded data, and Viterbi decoding that is not affected by the symbols of the transmission mode after switching can be performed.

According to the invention of the present application, among all the states in the final symbol before the transmission mode switching, only one state having the minimum path metric is made valid, and the other states are made invalid to output Viterbi decoded data, Viterbi decoding that is not affected by the symbols of the transmission mode after switching can be performed.

Further, according to the invention of the present application, among all the states in the final symbol before the transmission mode switching, the minimum value that can take only the path metric of one state having the minimum path metric can take other states. By resetting to the maximum value and outputting the Viterbi decoded data, it is possible to perform Viterbi decoding that is not affected by the symbols of the transmission mode after switching and to simplify the control.

According to the invention of the present application, only when the modulation multi-value number (phase number) after switching the transmission mode is larger than that before the switching, or when the modulation multi-value number is the same and the coding rate is large, the switching By performing Viterbi decoding that is not affected by the symbols of the transmission mode, when the modulation multi-level number (phase number) after switching the transmission mode is smaller than before switching, or when the modulation multi-level number is the same and the coding rate is small. Ordinary Viterbi decoding can be continuously performed to improve the error rate.

Further, according to the invention of the present application, when a fixed symbol sequence is included following the final symbol before the transmission mode switching, the Viterbi decoding using the fixed symbol sequence is performed by not performing the switching control in the Viterbi decoding. Control can be enabled.

Further, according to the invention of the present application, when a fixed symbol sequence is included following the last symbol before the transmission mode switching, from the symbol in which the state of the convolutional encoder is determined in the fixed symbol sequence. Up to the final fixed symbol, only one fixed state is valid and the other states are invalid, Viterbi decoded data is output, and the fixed symbol sequence is used to receive the influence of the symbols of the transmission mode after switching. No Viterbi decoding can be performed.

Further, according to the invention of the present application, in the case where transmission control information is transmitted, when a fixed symbol sequence is included following the last symbol before transmission mode switching, convolution is performed in the fixed symbol sequence. From the symbol whose state of the encoder is fixed to the final fixed symbol, only one fixed state is valid and the other states are invalid, Viterbi decoded data is output, and the fixed symbol sequence is used to switch. It is possible to perform Viterbi decoding that is not affected by the symbols in the subsequent transmission mode.

According to the invention of the present application, in the fixed symbol sequence, from the symbol in which the state of the convolutional encoder is determined to the final symbol, at least one symbol has only one determined state. Is enabled, other states are disabled, Viterbi decoded data is output, and fixed symbol sequences are used to perform Viterbi decoding that is not affected by the symbols of the transmission mode after switching, and simplifies control. it can.

Further, according to the invention of the present application, when the fixed symbol sequence is included following the last symbol before the transmission mode switching, the state of the convolutional encoder is determined in the input fixed symbol sequence. From the symbol to the final fixed symbol, the Viterbi decoded data is output by resetting it to the minimum value that can take only the path metric of one fixed state and the maximum value that can take the other states, and outputting the Viterbi decoded data. Viterbi decoding that is not affected by the symbols of the transmission mode after switching using the fixed symbol sequence,
And control can be simplified.

According to the invention of the present application, in the input fixed symbol sequence, at least one symbol is fixed in the section from the symbol in which the state of the convolutional encoder is fixed to the final fixed symbol. In addition, the Viterbi-decoded data is output by resetting the minimum value that can take only one state path metric and the maximum value that can take other states, and using the fixed symbol sequence, the symbols of the transmission mode after switching. It is possible to perform Viterbi decoding which is not affected by and to simplify the control.

Further, according to the invention of the present application, when a fixed symbol sequence is included subsequent to the final symbol before the transmission mode switching, from the symbol in which the state of the convolutional encoder is determined in the fixed symbol sequence. For the fixed symbol sequence up to the final fixed symbol, of the branches output from each state in Viterbi decoding, only one branch corresponding to the fixed symbol sequence is valid,
Output the Viterbi decoded data with the other branches disabled,
By using the fixed symbol sequence, it is possible to perform Viterbi decoding that is not affected by the symbols of the transmission mode after switching.

Further, according to the invention of the present application, in the case where transmission control information is transmitted, when a fixed symbol sequence is included following the last symbol before transmission mode switching, convolution is performed in the fixed symbol sequence. For the symbol from which the state of the encoder is fixed to the final fixed symbol, for the fixed symbol sequence, only one branch corresponding to the fixed symbol sequence is valid among the branches output from each state in Viterbi decoding. , Viterbi-decoded data is output with other branches disabled, and Viterbi decoding that is not affected by symbols in the transmission mode after switching can be performed by using a fixed symbol sequence.

According to the invention of the present application, when the fixed symbol sequence is included following the final symbol before the transmission mode switching, the convolutional encoder starts from the first symbol in the input fixed symbol sequence. Up to the symbol whose state is confirmed, of all the states in Viterbi decoding,
Only the state corresponding to the input up to that symbol is valid, the other states are invalidated and the state is reduced each time one symbol is input, and after the state is fixed to one, only one state is valid and Viterbi-decoded data is output with the state disabled, and Viterbi decoding that is not affected by the symbols of the transmission mode after switching can be performed using the fixed symbol sequence.

[0531] According to the invention of the present application, in the case where transmission control information is transmitted, if a fixed symbol sequence is included following the last symbol before transmission mode switching, in the input fixed symbol sequence , From the first symbol to the symbol for which the convolutional encoder state is fixed, of all states in Viterbi decoding, only the state corresponding to the input up to that symbol is valid, and the other states are invalid. The state is reduced each time one symbol is input, and after the state is fixed to one, only one state is valid and the other states are invalid and Viterbi decoded data is output. Viterbi decoding that is not affected by the symbols of the transmission mode can be performed.

According to the invention of the present application, in the input fixed symbol sequence, from the first symbol to the symbol whose convolutional encoder state is fixed, that symbol is selected from all the states in Viterbi decoding. To the minimum value that can take only the path metric of the state corresponding to the input, and output the Viterbi decoded data by resetting it to the maximum value that can take other states, and switch using the fixed symbol sequence. It is possible to perform Viterbi decoding that is not affected by the symbols of the subsequent transmission mode and simplify the control.

According to the invention of the present application, the fixed symbol sequence is changed to the code point of the fixed symbol sequence and input to the Viterbi decoder, so that the fixed symbol sequence is converted into the fixed symbol sequence using the usual method. By utilizing this, it is possible to perform Viterbi decoding that is not affected by the symbols of the transmission mode after switching.

Further, according to the invention of the present application, when transmission control information is transmitted, the fixed symbol sequence is changed to the code point of the fixed symbol sequence and input to the Viterbi decoder, so that the Viterbi decoding is normally performed. Using the method described above, it is possible to perform Viterbi decoding that is not affected by the symbols of the transmission mode after switching by using a fixed symbol sequence.

According to the invention of the present application, in the input fixed symbol sequence, from the first symbol to the symbol whose encoder state is fixed, among the branches output from each state in Viterbi decoding. , Only one branch corresponding to the fixed symbol sequence is enabled, the other branches are disabled and Viterbi decoded data is output, and the fixed symbol sequence is used to avoid the influence of the symbols of the transmission mode after switching. It is possible to perform effective Viterbi decoding.

According to the invention of the present application, in the input fixed symbol sequence, from the first symbol to the symbol whose convolutional encoder state is fixed, that symbol is selected from all the states in Viterbi decoding. Are valid only in the states corresponding to the input, and the other states are invalid, the state is reduced every time one symbol is input, the Viterbi decoded data is output, and the fixed symbol sequence is used.
It is possible to perform more effective Viterbi decoding that is not affected by the symbols of the transmission mode after switching.

Further, according to the invention of the present application, in the input fixed symbol sequence, from the first symbol to the symbol whose convolutional encoder state is fixed, the branch output from each state in Viterbi decoding is performed. Of these, only one branch corresponding to the fixed symbol sequence is valid, the other branches are invalid, and only the state corresponding to the input up to that symbol is valid among all the states in Viterbi decoding. The state of is invalidated, the state is reduced every time one symbol is input, Viterbi decoded data is output, and the property of the fixed symbol sequence is utilized to the maximum
The most effective Viterbi decoding that is not affected by the symbols of the transmission mode after switching can be performed.

According to the invention of the present application, in the input fixed symbol sequence, from the first symbol to the symbol in which the state of the convolutional encoder is fixed, that symbol is selected from all states in Viterbi decoding. To the minimum value that can take only the path metric of the state corresponding to the input, and output the Viterbi decoded data by resetting it to the maximum value that can take other states, and switch using the fixed symbol sequence. It is possible to perform Viterbi decoding that is not affected by the symbols of the subsequent transmission mode and simplify the control.

Further, according to the invention of the present application, in the input fixed symbol sequence, from the first symbol to the symbol whose convolutional encoder state is fixed, the branch output from each state in Viterbi decoding is performed. Of these, only one branch corresponding to the fixed symbol sequence is valid, the other branches are invalid, and only the path metric of the state corresponding to the input of that symbol among all the states in Viterbi decoding is taken. The minimum value that can be obtained is reset to the maximum value that can take other states, Viterbi-decoded data is output, and the characteristics of the fixed symbol sequence are used to the maximum extent to be affected by the symbols of the transmission mode after switching. The most effective Viterbi decoding can be performed, and the control can be simplified.

Further, according to the invention of the present application, a data sequence transmitted by interleaving M slots in the superframe for a depth of N in a superframe is transmitted as a selected L slot among M slots of each frame. The data can be output by deinterleaving only the data of.

Further, according to the invention of the present application, when the maximum number of slots per frame to be selected is Lmax, the area 2 banks of only the maximum (Lmax × N) slots of the memory circuit are used, and the minimum necessary number is used. Deinterleaving can be performed only by the memory area.

Further, according to the invention of the present application, M of each frame is
Of the slots, only the data of the selected L slot can be deinterleaved and continuously output at the L / M speed of the transmission format.

Further, according to the present invention, a plurality of MPEG
In a transmission method in which a transport stream is multiplexed in a transmission format, in a superframe, interleaving with a depth of N is performed in slot units.
It is possible to deinterleave only the data of the selected L slot among the M slots of each frame, and output the data of the data sequence transmitted for the slots.

Further, according to the invention of the present application, assuming that the maximum number of slots occupied by one type of transport stream per frame is Lmax, a region 2 banks of only the maximum (Lmax × N) slots of the memory circuit. 1 selected using only the minimum required memory area
Only types of transport streams can be deinterleaved to output the data.

Further, according to the invention of the present application, if the maximum number of slots occupied by one type of transport stream per frame is Lmax and K is an integer of 2 or more,
Only the maximum (Lmax × N × K) slots of the memory circuit are used in the two banks, and only the minimum required memory area is used to de-interleave only the selected K or less transport streams. Data can be output.

Further, according to the present invention, a plurality of MPEG
In a transmission method in which a transport stream is multiplexed and transmitted in a transmission format, only data of a selected L slot among M slots of each frame is deinterleaved and continuously transmitted at a transmission format L / M speed. Can be output to.

Further, according to the present invention, a plurality of MPEG
In a transmission method in which the transport stream is multiplexed in a transmission format, it is assumed that the selected J types of transport streams occupy L1, L2, ..., Lj slots per frame, respectively. , Of the M slots of each frame, the data of a total of (L1 + L2 + ... + Lj) slots per frame is de-interleaved to obtain the transmission format (L1 +
It is possible to output continuously at a speed of L2 + ... + Lj) / M.

According to the invention of the present application, one frame = M
When a slot and one superframe = N frames, the data sequence that is continuously randomized and transmitted in superframe units is used to de-randomize each head data of (N × M) slots in one superframe. (N × M) types of initial values of, and when the data of the L slot in the M slots of each frame that has already been selected is input, the data is input from the initial value corresponding to each input slot. De-randomization can be performed for each slot.

Further, according to the invention of the present application, when transmission control information is transmitted, 1 frame = M slots, 1
When superframe = N frames, the data sequence transmitted by randomizing continuously in units of superframes is used to de-randomize (N × M) slots of each superframe in one superframe (N × M).
× M) When the data of the L slot among the M slots of each frame, which has the initial value of the type and is already selected, is input,
From the initial value corresponding to each input slot, it is possible to perform de-randomization for each input slot.

Further, according to the invention of the present application, M of each frame is
By reading and writing only the data of the selected L slot among the slots to the memory circuit, the data of the selected L slot per frame can be continuously output at the speed of L / M of the transmission format. .

Further, according to the invention of the present application, when the maximum number of slots per frame to be selected is Lmax, the area for the maximum Lmax slots of the memory circuit is used, and only the minimum necessary memory area is used for selection. The converted data can be subjected to speed conversion and continuously output.

Further, according to the present invention, a plurality of MPEG
In the transmission method in which the transport stream is transmitted in a multiplexed transmission format, by reading and writing only the data of the L slot selected from the M slots of each frame to the memory circuit, the L slots per selected frame Data of the transmission format L /
It is possible to output continuously at a speed of M.

According to the invention of the present application, assuming that the maximum number of slots per frame occupied by one type of transport stream is Lmax, the maximum L of the memory circuit is
By using the area for only max slots and only the minimum necessary memory area, it is possible to continuously output the selected one type of transport stream by performing speed conversion.

According to the invention of the present application, when the maximum number of slots occupied by one type of transport stream per frame is Lmax and K is an integer of 2 or more,
Uses only the maximum (Lmax × K) slots of the memory circuit, and outputs the K or less selected transport streams continuously by speed conversion using only the minimum required memory area. can do.

According to the invention of the present application, if the selected J types of transport streams occupy L1, L2, ..., Lj slots per frame, J types of transport streams are assumed.・ Stream
The transmission formats L1 / M, L2 / M, ...
..., Lj / M speed can be continuously output in parallel.

According to the invention of the present application, M of each frame is
Of the slots, only the data of the selected L slot is de-interleaved, and the data sequence of the already selected L slot per frame is continuously transmitted by the rate conversion circuit at the transmission format L / M rate. Can be output.

According to the invention of the present application, if the maximum number of slots per selected frame is Lmax, only the data in the selected slot is deinterleaved,
It is possible to continuously output the selected data by performing the speed conversion by using the area of the maximum Lmax slots of the memory circuit and using only the minimum necessary memory area.

Further, according to the present invention, a plurality of MPEG
In a transmission method in which a transport stream is transmitted in a transmission format, only data of a selected L slot among M slots of each frame is de-interleaved, and L is already selected for each frame.
The speed conversion circuit can continuously output the data series of the slot at the speed of L / M of the transmission format.

According to the invention of the present application, a plurality of MPEG
If the maximum number of slots per frame occupied by one type of transport stream is Lmax in the transmission method in which the transport stream is transmitted in a transmission format, only the data in the selected slot is Interleave, maximum L of memory circuit
It is possible to continuously output the selected one type of transport stream by performing speed conversion by using an area for only max slots and using only a minimum necessary memory area.

Further, according to the present invention, a plurality of MPEG
In a transmission method in which a transport stream is transmitted in a multiplexed transmission format, the maximum number of slots occupied by one type of transport stream is Lmax, and K is an integer of 2 or more. Deinterleave only the data in the slot,
The maximum (Lmax × K) slots of the memory circuit are used, and only the minimum required memory area is used to continuously output the selected K or less transport streams by speed conversion. can do.

Further, according to the present invention, a plurality of MPEG
In a transmission method in which the transport stream is multiplexed in a transmission format, it is assumed that the selected J types of transport streams occupy L1, L2, ..., Lj slots per frame, respectively. , De-interleave only the data of the selected slot, and J types of transport streams,
The transmission formats L1 / M, L2 / M, ...
..., Lj / M speed can be continuously output in parallel.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an error correction circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a Viterbi decoder according to the first embodiment.

FIG. 3 is an explanatory diagram showing a state (trellis diagram) of the path memory when switching the transmission mode in the first embodiment.

FIG. 4 is an explanatory diagram of another example showing a state (trellis diagram) of the path memory at the time of switching the transmission mode in the first embodiment.

FIG. 5 is a block diagram showing an overall configuration of an error correction circuit according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a Viterbi decoder according to the second embodiment.

FIG. 7 is an explanatory diagram showing a state (trellis diagram) of a path memory at the time of transmission mode switching in the second embodiment.

FIG. 8 is a block diagram showing an overall configuration of an error correction circuit according to a third embodiment of the present invention.

FIG. 9 is a block diagram showing the configuration of a Viterbi decoder according to the third embodiment.

FIG. 10 is an explanatory diagram showing a branch output method at the time of transmission mode switching in the third embodiment.

FIG. 11 is a block diagram showing an overall configuration of an error correction circuit according to a fourth embodiment of the present invention.

FIG. 12 is a block diagram showing the configuration of a Viterbi decoder according to the fourth embodiment.

FIG. 13 is an explanatory diagram showing a trellis diagram state reduction method at the time of transmission mode switching in the fourth embodiment.

FIG. 14 is a block diagram showing an overall configuration of an error correction circuit according to a fifth embodiment of the present invention.

FIG. 15 is a block diagram showing the configuration of a Viterbi decoder according to the fifth embodiment.

FIG. 16 is an explanatory diagram showing a conversion method of fixed series I / Q coordinates in the fifth embodiment.

FIG. 17 is an explanatory diagram showing a transmission frame configuration used for simulation in the fifth embodiment.

FIG. 18 is an explanatory diagram showing a simulation result in the fifth embodiment.

FIG. 19 is a block diagram showing an overall configuration of an error correction circuit according to a sixth embodiment of the present invention.

FIG. 20 is a block diagram showing the configuration of a Viterbi decoder according to the sixth embodiment.

FIG. 21 is a block diagram showing an overall configuration of an error correction circuit according to a seventh embodiment of the present invention.

FIG. 22 is a block diagram showing the configuration of a Viterbi decoder according to the seventh embodiment.

FIG. 23 is a block diagram showing an overall configuration of an error correction circuit according to an eighth embodiment of the present invention.

FIG. 24 is a block diagram showing the configuration of a Viterbi decoder according to the eighth embodiment.

FIG. 25 is a block diagram showing an overall configuration of an error correction circuit according to a ninth embodiment of the present invention.

FIG. 26 is a block diagram showing the configuration of a Viterbi decoder according to the ninth embodiment.

FIG. 27 is a block diagram showing an overall configuration of an error correction circuit according to a tenth embodiment of the present invention.

FIG. 28 is a block diagram showing the configuration of a Viterbi decoder according to the tenth embodiment.

FIG. 29 is a block diagram showing an overall configuration of an error correction circuit according to an eleventh embodiment of the present invention.

FIG. 30 is a block diagram showing the configuration of a Viterbi decoder according to the eleventh embodiment.

FIG. 31 is a block diagram showing an overall configuration of an error correction circuit according to a twelfth embodiment of the present invention.

FIG. 32 is a block diagram showing the configuration of a Viterbi decoder according to the twelfth embodiment.

FIG. 33 is a block diagram showing an overall configuration of an error correction circuit according to a thirteenth embodiment of the present invention.

FIG. 34 is a block diagram showing a configuration of a de-interleave circuit in the thirteenth embodiment.

FIG. 35 is an explanatory diagram showing an output data series from the de-interleave circuit in the thirteenth embodiment.

FIG. 36 is a block diagram showing an overall configuration of an error correction circuit according to a fourteenth embodiment of the present invention.

FIG. 37 is a block diagram showing the structure of the de-interleave circuit in the fourteenth embodiment.

FIG. 38 is an explanatory diagram showing an output data series from the de-interleave circuit in the fourteenth embodiment.

FIG. 39 is a block diagram showing a configuration of a de-randomizing circuit according to the fourteenth embodiment.

FIG. 40 is an explanatory diagram showing how gate signals and initial values are generated in the de-randomizing circuit of the fourteenth embodiment.

FIG. 41 is a block diagram showing an overall structure of an error correction circuit according to a fifteenth embodiment of the present invention.

FIG. 42 is a block diagram showing the structure of the speed conversion circuit according to the fifteenth embodiment.

FIG. 43 is a block diagram showing the overall configuration of another example of the error correction circuit according to the fifteenth embodiment of the present invention.

FIG. 44 is a block diagram showing the configuration of another example of the speed conversion circuit in the fifteenth embodiment.

FIG. 45 is a block diagram showing an overall structure of an error correction circuit according to a sixteenth embodiment of the present invention.

FIG. 46 is a block diagram showing a structure of a speed conversion circuit according to the sixteenth embodiment.

FIG. 47 is a block diagram showing the overall structure of another example of the error correction circuit according to the sixteenth embodiment of the present invention.

FIG. 48 is a block diagram showing the configuration of another example of the speed conversion circuit in the sixteenth embodiment.

FIG. 49 is a block diagram showing an overall configuration of an error correction coding apparatus according to Embodiments 17 to 32 of the present invention.

FIG. 50 is an explanatory diagram showing an output data series up to a randomizing circuit in the error correction coding apparatus according to the seventeenth to thirty-second embodiments.

FIG. 51 is an explanatory diagram showing a byte data sequence having a superframe structure, which is input to the byte / symbol circuit in the error correction encoding device according to the seventeenth to thirty-second embodiments.

52 is an explanatory diagram showing an example of the number of slots in each transmission mode of the superframe structure in Embodiments 17 to 32 of the present invention. FIG.

FIG. 53 is an explanatory diagram showing an output data sequence from input to output in the error correction coding apparatus according to any of Embodiments 17 to 32.

FIG. 54 is a block diagram showing an overall configuration of an error correction circuit according to a seventeenth embodiment of the present invention.

FIG. 55 is a block diagram showing an overall structure of an error correction circuit according to an eighteenth embodiment of the present invention.

FIG. 56 is a block diagram showing the overall structure of an error correction circuit according to the nineteenth embodiment of the present invention.

FIG. 57 is a block diagram showing an overall structure of an error correction circuit according to a twentieth embodiment of the present invention.

FIG. 58 is a block diagram showing an overall structure of an error correction circuit according to a twenty-first embodiment of the present invention.

FIG. 59 is a block diagram showing an overall structure of an error correction circuit according to a twenty-second embodiment of the present invention.

FIG. 60 is a block diagram showing an overall structure of an error correction circuit according to a twenty-third embodiment of the present invention.

FIG. 61 is a block diagram showing an overall configuration of an error correction circuit according to a twenty-fourth embodiment of the present invention.

62 is a block diagram showing an overall configuration of an error correction circuit according to a twenty-fifth embodiment of the present invention. FIG.

FIG. 63 is a block diagram showing an overall structure of an error correction circuit according to a twenty sixth embodiment of the present invention.

FIG. 64 is a block diagram showing the overall structure of an error correction circuit according to the twenty-seventh embodiment of the present invention.

FIG. 65 is a block diagram showing an overall structure of an error correction circuit according to a twenty-eighth embodiment of the present invention.

66 is a block diagram showing an overall configuration of an error correction circuit in the twenty-ninth embodiment of the present invention. FIG.

FIG. 67 is a block diagram showing an overall configuration of an error correction circuit in the thirtieth embodiment of the present invention.

FIG. 68 is a block diagram showing an overall configuration of an error correction circuit in the thirty-first embodiment of the present invention.

FIG. 69 is a block diagram showing the structure of the speed conversion circuit in the thirty-first embodiment.

FIG. 70 is a block diagram showing the overall structure of another example of the error correction circuit according to the thirty-first embodiment of the present invention.

71 is a block diagram showing the configuration of another example of the speed conversion circuit according to the thirty-first embodiment. FIG.

72 is a block diagram showing an overall structure of an error correction circuit according to a thirty-second embodiment of the present invention. FIG.

73 is a block diagram showing the structure of the speed conversion circuit in the thirty-second embodiment. FIG.

FIG. 74 is a block diagram showing the overall structure of another example of the error correction circuit according to the thirty-second embodiment of the present invention.

FIG. 75 is a block diagram showing the configuration of another example of the speed conversion circuit according to the thirty-second embodiment.

FIG. 76 is a block diagram showing the overall configuration of an error correction encoding device in a conventional example.

[Fig. 77] Fig. 77 is an explanatory diagram showing an output data sequence up to a randomizing circuit in the error correction encoding device in the conventional example.

[Fig. 78] Fig. 78 is an explanatory diagram showing how interleaving is performed in the error correction encoding device of the conventional example.

FIG. 79 is an explanatory diagram showing dummy slots in a conventional error correction encoding device.

FIG. 80 is a block diagram showing a configuration of a transmission control information generation circuit in a conventional example.

FIG. 81 is an explanatory diagram showing an example of the entire contents of the TMCC in the conventional example.

FIG. 82 is an explanatory diagram showing an example of contents of transmission mode / slot information in the conventional TMCC.

FIG. 83 is an explanatory diagram showing an example of the content of relative TS / slot information in the conventional TMCC.

FIG. 84 is a relative TS / TS in the conventional TMCC.
It is explanatory drawing which shows an example of the content of the number corresponding table.

FIG. 85 is an explanatory diagram showing an example of the contents of transmission / reception control information in the conventional TMCC.

[Fig. 86] Fig. 86 is an explanatory diagram showing an example of the contents of extended information in a conventional TMCC.

[Fig. 87] Fig. 87 is an explanatory diagram showing a byte data sequence having a superframe structure, which is input to a byte / symbol circuit in an error correction encoding device according to a conventional example.

FIG. 88 is an explanatory diagram showing how a gate signal is generated in a randomizing circuit of a conventional error correction encoding device.

FIG. 89 is an explanatory diagram showing an example of a superframe structure in a conventional example.

FIG. 90 is an explanatory diagram showing a state of bytes / symbols in a byte / symbol circuit in a conventional error correction encoding device.

[Fig. 91] Fig. 91 is a block diagram illustrating a configuration of a convolutional encoder in a conventional example.

FIG. 92 is an explanatory diagram showing how TC-8PSK (r = 2/3) convolutional coding, punctured processing, and P / S conversion are performed in the convolutional encoder of the error correction encoder of the conventional example. Is.

FIG. 93 is an explanatory view showing the manner of convolutional encoding, punctured processing, and P / S conversion in the case of QPSK (r = 3/4) in the convolutional encoder of the error correction encoding device of the conventional example. It is a figure.

[Fig. 94] Fig. 94 is a diagram illustrating the manner of convolutional encoding, punctured processing, and P / S conversion in the case of QPSK (r = 1/2) in the convolutional encoder of the error correction encoding device of the conventional example. It is a figure.

FIG. 95 is an explanatory view showing the manner of convolutional coding, punctured processing, and P / S conversion in the case of BPSK (r = 1/2) in the convolutional encoder of the error correction encoding device of the conventional example. It is a figure.

[Fig. 96] Fig. 96 is an explanatory diagram showing a state of mapping in a mapping circuit of a conventional error correction encoding device.

[Fig. 97] Fig. 97 is an explanatory diagram showing an output data sequence from input to output in the error correction encoding device in the conventional example.

FIG. 98 is a block diagram showing an overall configuration of an error correction circuit in a conventional example.

FIG. 99 is a block diagram showing a configuration of a transmission control information decoding circuit in a conventional example.

FIG. 100 is a block diagram showing a configuration of a Viterbi decoder and a high / low hierarchy selection signal generation circuit in a conventional example.

101 is a TC-8 in the Viterbi decoder of the conventional example.
It is explanatory drawing which shows the mode of Viterbi decoding in the case of PSK (r = 2/3), de-punctured processing, and S / P conversion.

FIG. 102 is a diagram showing a QPSK in the Viterbi decoder of the conventional example.
It is explanatory drawing which shows the mode of Viterbi decoding in the case of (r = 3/4), de-punctured processing, and S / P conversion.

[FIG. 103] FIG. 103 is a diagram showing a QPSK decoder in the Viterbi decoder of the conventional example.
It is explanatory drawing which shows the mode of Viterbi decoding in the case of (r = 1/2), de-punctured processing, and S / P conversion.

[FIG. 104] FIG. 104 is a schematic diagram illustrating a VPSK in a Viterbi decoder of a conventional example.
It is explanatory drawing which shows the mode of Viterbi decoding in the case of (r = 1/2), de-punctured processing, and S / P conversion.

FIG. 105 is a TC-8 in the Viterbi decoder of the conventional example.
It is explanatory drawing which shows the mode of the trellis diagram in case of PSK.

FIG. 106 is a schematic diagram showing a QPSK decoder in the Viterbi decoder of the conventional example.
It is an explanatory view showing the appearance of the trellis diagram in the case of and BPSK.

FIG. 107 is an explanatory diagram showing a state of symbol / byte conversion by a symbol / byte circuit in a conventional error correction circuit.

FIG. 108 is an explanatory diagram showing an output data series from input to output in the error correction circuit in the conventional example.

FIG. 109 is an explanatory diagram showing how de-interleaving is performed in the de-interleaving circuit of the conventional error correction circuit.

110 is a block diagram showing a configuration of a de-interleave circuit in a conventional example. FIG.

FIG. 111 is a block diagram showing a configuration of a de-randomizing circuit in a conventional example.

FIG. 112 is an explanatory diagram showing how gate signals are generated in the de-randomizing circuit in the conventional example.

FIG. 113 is a block diagram showing a configuration of a speed conversion circuit in a conventional example.

FIG. 114 is an explanatory diagram showing a state of speed conversion in the speed conversion circuit of the error correction circuit of the conventional example.

FIG. 115 is an explanatory diagram showing a manner of speed conversion in a speed conversion circuit of an error correction circuit of a conventional example.

FIG. 116 is an explanatory diagram showing a state of speed conversion in the speed conversion circuit of the error correction circuit of the conventional example.

FIG. 117 is an explanatory diagram showing a state of speed conversion in the speed conversion circuit of the error correction circuit of the conventional example.

FIG. 118 is an explanatory diagram showing a state (trellis diagram) of the path memory at the time of switching the transmission mode in the conventional example.

FIG. 119 is an explanatory diagram of an example showing a state (trellis diagram) of the path memory at the time of switching the transmission mode in the first embodiment.

FIG. 120 is an explanatory diagram of an example showing a state (trellis diagram) of the path memory at the time of switching the transmission mode in the second embodiment.

[FIG. 121] FIG. 121 is an explanatory diagram showing a structure of a transmission frame used for a simulation in Embodiment 2.

122 is an explanatory diagram showing simulation results in the second embodiment. FIG.

[Explanation of symbols]

101,201,301,401,501,601,7
01, 801, 901, 1001, 1101, 120
1,1301,1401,1501,1507,160
1,1607,1703,1801,1901,200
1,210,221,230,1,240,250
1,2601,2701,2801,2901,300
1,3101,3102,3201,3202,200
01 error correction circuits 102, 202, 302, 402, 602, 702, 8
02,902,1002,1102,1202,200
02 Viterbi decoder 103, 203, 303, 403, 503, 603, 7
03,803,903,1003,1103,1203
Viterbi decoder control circuit 104, 204, 304, 404, 604, 704, 8
04,904,1004,1104,1204,200
17 Viterbi Decoding Circuit 105, 205, 305, 405, 605, 705, 8
05,905,1005,1105,1205,200
19 ACS circuit 506 Input symbol conversion circuit 1302, 1402, 20005 De-interleave circuit 1303, 1403, 1503, 1509, 1603
1609, 1705, 20011 Channel selection circuits 1304, 1404, 1504, 1510, 1604
1610, 20026, 20034 write address generation circuits 1305, 1405, 1505, 1511, 1605
1611, 20027, 20035 read address generation circuits 1306, 1406, 1506, 1512, 1606
1612, 200028, 20036 Memory circuit 1407, 20007, 20012 De-randomize circuit 1408, 20029 PN generation circuit 1409 Initial value generation circuit 1502, 1508, 1602, 1608, 20009
Rate conversion circuit 1701, 10001 Error correction coding device 1702 TAB / data information generation circuit 1704 Control signal generation circuit 10002 TS multiplex circuit 10003, 10011 RS coding circuit 10004 Randomize circuit 10005 Interleave circuit 10006 Byte / symbol conversion circuit 10007 Convolutional code Optimizer 10008 Mapping circuit 10009 Transmission control information generation circuit 10010 Control information generation unit 10012 TAB signal insertion unit 10013 Randomization circuit 10014, 20025 Convolution circuit 10015 Punctured P / S circuit 20003 High / low hierarchy selection signal generation circuit 20004, 20013 Symbol / byte conversion circuit 20006 MPEG synchronization byte / dummy slot insertion circuit 20008,20014 RS decoding circuit 0010 Transmission control information decoding circuit 200515 TMCC decoding circuit 20066 De-punctured S / P circuit 20018 Branch metric calculation circuit 20020 Path metric memory 20021 Path memory 20022 8PSK hard decision circuit 20023 M stage delay circuit 20024 BER measurement circuit 20030 P / S Conversion circuit 20031 S / P conversion circuit 20032 Gate signal generation circuit 20033 ex-or circuit

Continued front page    (72) Inventor Ryosuke Mori             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Yoshikazu Hayashi             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Yasuhiro Nakakura             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Takehiro Kamata             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F-term (reference) 5C059 KK01 MA00 RB02 RF02 RF05                       SS02 UA02 UA05                 5J065 AA01 AB01 AC02 AD10 AE06                       AF03 AH06 AH09 AH23                 5K004 AA01 BA02 BB02 BB05 BD02                       FA05 FA06 FD02 FD05                 5K014 AA01 BA10 HA06

Claims (18)

[Claims] 1. A data sequence which is composed of symbols of a plurality of modulation schemes and a plurality of coding rates, and which is transmitted by convolutionally coding the symbols of the different modulation schemes and the coding rates successively. , A Viterbi decoding error correction circuit, based on a known modulation scheme and coding rate between transmission and reception, a Viterbi decoder that performs Viterbi decoding of each symbol using a path metric, and the modulation scheme of the symbol, In addition to determining the switching rate of the coding rate, the presence or absence of reset setting to the predetermined value of the path metric performed at the time of switching at the time of Viterbi decoding performed by the Viterbi decoder is determined by the modulation multi-value before and after switching. An error correction circuit, comprising: a Viterbi decoder control circuit for controlling based on the number of values and the coding rate. 2. The Viterbi decoder control circuit, if the modulation multi-value number after switching is larger than that before switching, or if the modulation multi-value number before and after switching is the same and the coding rate is large, The error correction circuit according to claim 1, wherein control is performed to reset and set the path metric to a predetermined value. 3. The Viterbi decoder control circuit sets, as a minimum path metric value, a path metric of one state having a minimum path metric of all states with respect to the predetermined value reset and set. 3. The error correction circuit according to claim 2, wherein the Viterbi decoder is controlled by setting ## EQU1 ## as a maximum path metric value. 4. The data sequence is convolutionally coded with a constraint length n, and further includes a case where a fixed symbol sequence is included between symbols for which the modulation scheme and the coding rate are switched, The decoder control circuit, when the number of modulation multi-values after switching is larger than that before switching, or when the number of modulation multi-values before and after switching is the same and the coding rate is large, the n-th fixed symbol sequence 2. The error correction circuit according to claim 1, wherein the reset setting control is performed only for the path metric from the fixed symbol to the final fixed symbol. 5. The data sequence may be subjected to convolutional coding with a constraint length n, and may further include a fixed symbol sequence between symbols at which the modulation scheme and the coding rate are switched, The decoder control circuit, when the number of modulation multi-values after switching is larger than that before switching, or when the number of modulation multi-values before and after switching is the same and the coding rate is large, the n-th fixed symbol sequence The error correction circuit according to claim 1, wherein the reset setting is performed only for a path metric of at least one symbol in a section from the fixed symbol to the final fixed symbol. 6. The Viterbi decoder control circuit sets, for the predetermined value reset and set, a path metric of one fixed state as a minimum path metric value, and sets another state as a maximum path metric value. The error correction circuit according to claim 4 or 5, wherein 7. The data sequence further includes transmission control information regarding the modulation scheme and coding rate of each symbol, and the Viterbi decoder includes the modulation scheme for each symbol included in the transmission control information and Based on the coding rate,
The error correction circuit according to any one of claims 1 to 6, wherein the symbol is subjected to Viterbi decoding. 8. A case where a fixed symbol sequence is included between symbols of a plurality of modulation schemes and a plurality of coding rates and the modulation schemes and the coding rates are switched, and different modulation schemes and An error correction circuit that Viterbi-decodes a data sequence in which each of the symbols of the coding rate is continuously convolutionally coded and transmitted, wherein an input symbol for a section of a fixed symbol sequence according to a symbol coordinate conversion signal. To the code point of the fixed symbol sequence, and except the section of the fixed symbol sequence,
An input symbol conversion circuit that outputs without changing the input symbol, and for each symbol output from the input symbol conversion circuit, using the path metric based on a known modulation method and coding rate between transmission and reception, A Viterbi decoder for performing Viterbi decoding of symbols, and a Viterbi decoder control circuit for determining the section of the fixed symbol sequence to generate the symbol coordinate conversion signal and giving it to the input symbol conversion circuit. Error correction circuit. 9. The data sequence further includes transmission control information regarding a modulation scheme and a coding rate of each symbol, and the Viterbi decoder includes the modulation scheme of each symbol included in the transmission control information and Based on the coding rate,
9. The error correction circuit according to claim 8, wherein the symbol is subjected to Viterbi decoding. 10. A data sequence that is composed of symbols of a plurality of modulation schemes and a plurality of coding rates, and that is transmitted by convolutionally coding the symbols of the different modulation schemes and the coding rates continuously. , An error correction method for Viterbi decoding, wherein when performing Viterbi decoding of each of the symbols using a path metric based on a known modulation method and coding rate between transmission and reception, the modulation method and the code of the symbol An error correction method, characterized in that the presence / absence of a reset setting to a predetermined value of the path metric performed at the time of switching the conversion rate is controlled based on the number of modulation levels and the coding rate before and after the switching. 11. The reset setting is performed only when the number of modulation levels after switching is larger than that before switching, or when the number of modulation levels before and after switching is the same and the coding rate is large. The error correction method according to claim 10. 12. A path metric of one state having the smallest path metric of all states with respect to the predetermined value set by the reset setting is set as a minimum path metric value, and another state is set to a maximum path metric. The error correction method according to claim 11, wherein the error correction method is set as a value. 13. The data sequence may be convolutionally coded with a constraint length n, and may further include a fixed symbol sequence between the symbols at which the modulation scheme and the coding rate are switched, The reset setting is the nth fixed symbol sequence in the fixed symbol sequence when the number of modulation levels after switching is greater than that before switching, or when the number of modulation levels before and after switching is the same and the coding rate is large. The error correction method according to claim 10, wherein the error correction method is performed only for a path metric from a symbol to a final fixed symbol. 14. The data sequence is convolutionally coded with a constraint length n, and further includes a case where a fixed symbol sequence is included between symbols at which the modulation scheme and the coding rate are switched, and the reset is performed. The setting is such that when the number of modulation multi-values after switching is larger than that before switching, or when the number of modulation multi-values before and after switching is the same and the coding rate is large, the n-th fixed symbol in the fixed symbol sequence. 11. The error correction method according to claim 10, wherein the reset setting is performed only for the path metric of at least one symbol in the section from the last fixed symbol to the last fixed symbol. 15. The fixed path metric of one state is set as a minimum path metric value, and the other state is set as a maximum path metric value with respect to the predetermined value set by the reset setting. Claim 1
The error correction method according to 3 or 14. 16. The data sequence further includes transmission control information regarding a modulation scheme and a coding rate of each symbol, and Viterbi decoding of each symbol includes the modulation scheme of the symbol included in the transmission control information. And the error correction method according to any one of claims 10 to 15, wherein the error correction method is performed based on the coding rate. 17. A case in which a fixed symbol sequence is included between symbols of a plurality of modulation schemes and a plurality of coding rates and the modulation schemes and the coding rates switch, and different modulation schemes and An error correction method for Viterbi decoding a data sequence in which each of the symbols of the coding rate is continuously convolutionally coded and transmitted, wherein an input symbol is input for a section of a fixed symbol sequence according to a symbol coordinate conversion signal. An input symbol conversion process that changes to the code point of the fixed symbol sequence and outputs without changing the input symbol except the section of the fixed symbol sequence, and a known modulation between transmission and reception for the output of the input symbol conversion process. A Viterbi decoding process for performing Viterbi decoding of each of the symbols using a path metric based on the scheme and the coding rate; An error correction method comprising: determining a section of a fixed symbol sequence, generating the symbol coordinate conversion signal, and outputting to the input symbol conversion processing. 18. The data sequence further includes transmission control information regarding a modulation scheme and a coding rate of each symbol, and Viterbi decoding of each symbol is performed by the modulation scheme of the symbol included in the transmission control information. 18. The error correction method according to claim 17, wherein the error correction method is performed based on the encoding rate.