JP2003017588A - Semiconductor storage device - Google Patents

Abstract

(57) [Problem] To provide a highly integrated semiconductor memory device with improved data retention characteristics. SOLUTION: An insulating layer 2 formed on a semiconductor substrate 1
And a semiconductor layer 3 formed on the insulating layer, a drain and source diffusion layers formed separately from each other in the semiconductor layer, and a gate formed on a gate insulating film formed on the semiconductor layer. A first data state having an electrode 5 and having a first threshold voltage in which majority carriers are injected into the semiconductor layer; and a second data state having a second threshold voltage in which majority carriers in the semiconductor layer are emitted to the drain diffusion layer. A MOS transistor that stores the data state and a first diffusion layer formed in the semiconductor layer, in contact with the semiconductor layer below the gate electrode and having a conductivity type opposite to the source diffusion layer, and formed in the semiconductor layer; The second diffusion layer 1 is in contact with the first diffusion layer and has the opposite conductivity type to the first diffusion layer.
2).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device for performing data read / write operations, and more particularly to a MO memory device.
The present invention relates to a semiconductor memory device that identifies data by changing the threshold of an S transistor.

[0002]

2. Description of the Related Art FIG. 8 shows an equivalent circuit of a conventional DRAM cell. Here, a data transfer transistor 40 having a word line WL connected to its gate and a bit line BL connected to its drain is provided. One end of a data storage capacitor 41 is connected to the source of the data transfer transistor 40. The other end of the data storage capacitor 41 is connected to the plate line PL. In this way, by controlling the potential of the word line WL, data writing and reading operations are performed in the data storage capacitor 41.

FIG. 9 is a sectional view showing the structure of a typical trench type DRAM cell. An N well (plate) 46 is formed on the semiconductor substrate 45. This N well 4
A P-well 47 is formed on top of 6. A plurality of trench capacitors 48 in which N-type polysilicon is buried are formed across the N well 46 and the P well. A collar oxide film 49 is formed around the upper portion of the trench capacitor 48.

A plurality of gate electrodes 50 are formed on the P well 47. An N type diffusion layer 51 is formed in the P well 47 below the side surface of the gate electrode 50. The N-type diffusion layer 51 on one side surface of the gate electrode 50 is electrically connected to the upper portion of the adjacent trench capacitor 48 by a buried strap 52. Further, the N-type diffusion layer 51 on the other side surface of the gate electrode 50 is connected to the bit line 5 by the bit line contact 53.
4 is connected.

The STI element isolation region 5 is formed on the upper surface of the P well 47 so as to separate the adjacent straps 52.
5 is formed.

[0006]

The conventional semiconductor memory device as described above has the following problems.

As the design size is reduced, it is necessary to increase the P well concentration in order to suppress the short channel effect of the transistor. It is known as a problem that PN junction leak increases along with it and the data retention characteristic deteriorates.

Regarding the leak current in such a fine DRAM, "On the Retention Time Distribu
tion of Dynamic Random Access Memory (DRAM) ”IEEE
Transactions on Electron Devices. Vol.45, No.6, Ju
ne 1998 ”. In this document,
Thermionic field emission (TFE) cu
rrent) is the cause of the PN junction leak.

P forming the P region of the PN junction
TFE increases as the concentration of boron in the well increases.
It has been confirmed. For example, the boron concentration is 7.0 ×
10 ¹⁶cm^-3So, in a 16M DRAM, 1 bit
4.3 × 10^-16A, the boron concentration is 2.0 ×
10¹⁷cm^-3, 16M DRAM, 1 bit warm
R, 9.0 x 10 cm^-16It is A. In this P-well
Data retention is due to increase in leakage current due to increase in boron concentration.
It will result in deterioration of characteristics.

As the well concentration increases, the junction leak current between the belly strap and the P well increases. If the leak current increases, the data stored in the memory cell will disappear with the passage of time. Therefore, it is preferable that the leak current be as small as possible.

As described above, as miniaturization of DRAM progresses, there is a problem that the data retention characteristic cannot be maintained due to an increase in junction leak.

An object of the present invention is to solve the above problems of the prior art.

A particular object of the present invention is to provide a highly integrated semiconductor memory device having improved data retention characteristics.

[0014]

To achieve the above object, the present invention is characterized by a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a floating potential state formed on the insulating layer. A semiconductor layer, and a drain and source diffusion layer formed in the semiconductor layer so as to be separated from each other,
The semiconductor device has a gate insulating film formed on the semiconductor layer between the drain and source diffusion layers and a gate electrode formed on the gate insulating film, the gate electrode being connected to a word line, and drain diffusion. The layers are connected to the bit lines,
The source diffusion layers are connected to fixed potential lines, respectively, and the first data state having a first threshold voltage in which majority carriers are injected into the semiconductor layer and the majority carriers in the semiconductor layer are released to the drain diffusion layer. A MOS transistor for storing a second data state having a threshold voltage of 2; a first diffusion layer formed in the semiconductor layer, in contact with the semiconductor layer under the gate electrode, and having a conductivity type opposite to that of the source diffusion layer; ,
A semiconductor memory device is formed in the semiconductor layer, is in contact with the first diffusion layer, and includes the first diffusion layer and a second diffusion layer having an opposite conductivity type.

Still another feature of the present invention is that a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a semiconductor layer formed on the insulating layer, and a semiconductor layer formed in the semiconductor layer. A conductive type first diffusion layer, a gate electrode formed in a comb shape on the first diffusion layer, to which a word line potential is applied, and the semiconductor layer on one side between comb-shaped portions of the gate electrode. A second conductivity type drain diffusion layer that is provided and is provided with a bit line potential, and a second conductivity type that is provided on the other side of the semiconductor layer between the comb-shaped portions of the gate electrode and is provided with a first common power source. Type source diffusion layer, the second diffusion type first diffusion layer connected to the first diffusion layer and formed on the semiconductor layer, and the second conduction type first diffusion layer, A second second conductive type formed on the semiconductor layer and supplied with a second common power source. A semiconductor memory device having a diffuser layer.

Still another feature of the present invention is that a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a semiconductor layer formed on the insulating layer, and a semiconductor layer formed in the semiconductor layer. A conductive type first diffusion layer, a gate electrode formed in a comb shape on the first diffusion layer, to which a word line potential is applied, and the semiconductor layer on one side between comb-shaped portions of the gate electrode. A second conductivity type drain diffusion layer that is provided and is provided with a bit line potential, and a second conductivity type that is provided on the other side of the semiconductor layer between the comb-shaped portions of the gate electrode and is provided with a first common power source. Type source diffusion layer and a second conductive type first conductive layer connected to the first diffused layer and penetrating through the semiconductor layer from above the semiconductor substrate, and the second conductive type first conductive layer. A second common power source connected to the layer and formed in the semiconductor substrate. A semiconductor memory device having a Erareru first diffusion layer of the second conductivity type.

Still another feature of the present invention is that a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a semiconductor layer formed on the insulating layer, and a semiconductor layer formed in the semiconductor layer. A conductive type first diffusion layer and a first conductive type first diffusion layer;
A first gate electrode formed in a comb shape on the diffusion layer to which a word line potential is applied, and the semiconductor layer provided on one side between the comb tooth-shaped portions of the first gate electrode and provided with a bit line potential. A first drain type diffusion layer of the second conductivity type and a second conductivity type first drain provided on the other side of the semiconductor layer between the comb-shaped portions of the first gate electrode. A source diffusion layer, a second diffusion type first diffusion layer which is connected to the first diffusion layer and is linearly formed on the semiconductor layer in parallel with the comb axis of the gate electrode; A second diffusion layer of a first conductivity type, which is connected to the first diffusion layer of a conductivity type and is linearly formed in parallel with the first diffusion layer on the semiconductor layer and to which a second common power source is applied; 1 conductivity type second
A second diffusion layer of the second conductivity type, which is connected to the diffusion layer and is linearly formed on the semiconductor layer in parallel with the second diffusion layer of the first conductivity type, and formed in the semiconductor layer. , A third diffusion layer of the first conductivity type, a second gate electrode formed in a comb shape on the third diffusion layer of the first conductivity type, to which a word line potential is applied, and comb teeth of the second gate electrode. Second drain diffusion layer of the second conductivity type, which is provided on the semiconductor layer on one side between the gate-shaped portions, and the semiconductor on the other side between the comb-shaped portions of the second gate electrode. Provided on a layer,
A semiconductor memory device having a second conductive type second source diffusion layer to which a first common power source is applied.

Another feature of the present invention is that a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a second conductivity type first electrode formed on the insulating layer and supplied with a first common power source. Region, a second region of the second conductivity type that is formed apart from the first region of the second conductivity type and is applied with a potential as a bit line, and a first region of the second conductivity type. A first region of the first conductivity type formed on the insulating layer between the second regions of the second conductivity type, and a first region of the first conductivity type.
In contact with the gate insulating film formed on the region, the gate electrode formed on the gate insulating film and given a potential as a word line, and the first region of the first conductivity type. A semiconductor memory device having a third region of the second conductivity type provided and a second region of the first conductivity type in contact with the third region of the second conductivity type.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) In this embodiment, the latch characteristic of a thyristor triggered by a change in substrate potential of a transistor having a floating substrate is used in a memory. This embodiment will be described with reference to FIGS. 1 to 5.

As shown in FIG. 2, the memory cell is SO
It is configured using an I-structured NMOS transistor. That is, an SOI substrate is used in which a silicon oxide film 2 is formed as an insulating film on a semiconductor substrate 1 made of silicon, and a P-type silicon layer 3 is formed on the silicon oxide film 2.

A gate electrode 5 is formed on the silicon layer 3 of this SOI substrate via a gate oxide film 4, and an N-type source diffusion layer 6 and a drain diffusion layer 7 are formed in self alignment with the gate electrode 5. . The gate electrode 5 is formed, for example, from a lower layer to an upper layer by a polysilicon layer, a WSi layer, a SiN layer.
The layers are sequentially stacked, and a gate sidewall made of a SiN layer is formed around the layers.

The source and drain diffusion layers 6 and 7 are formed to a depth reaching the silicon oxide film 2 at the bottom. In the bulk region made of the P-type silicon layer 3, when the isolation in the channel width direction is performed by the oxide film, the bottom surface and the side surface in the channel width direction are insulated and isolated from each other, and the channel length direction is in a floating state with the PN junction isolation. Become.

In this memory cell, the gate electrode 5 is connected to the word line, the source diffusion layer 6 is connected to the first common power supply line 9 via the polysilicon plug 8, and the drain diffusion layer 7 is connected.
Is connected to a bit line 10 made of tungsten or the like via a polysilicon plug 8. Here, the gate electrode 5, the source and drain diffusion layers 6 and 7 are covered with an interlayer insulating film (not shown) made of BPSG or the like.

Here, the gate length is, for example, about 0.175 μm.
The gate material can be formed by depositing WSi on polysilicon, and the gate insulating film can be formed with an oxide film of 60 Å and a contact diameter of 0.2 μm.

This memory cell of the NMOS transistor utilizes accumulation of holes which are majority carriers in the bulk region 3 (P-type silicon layer which is insulated and isolated from others) of the MOS transistor.

Next, a PNP bipolar transistor forming a thyristor for controlling the potential of the bulk region 3 of this memory cell will be described with reference to FIG.

In FIG. 1, two bulk regions 3 are provided on the left and right sides of the drawing. This is because the bulk potentials of the two memory cells are controlled simultaneously. In the thyristor portion shown in FIG. 1, separate thyristors are formed on the left and right sides of the central portion. That is, the P plus diffusion layer 12, which is a common power supply line, is commonly used by the left and right elements.

A gate electrode 5 is provided on the bulk region 3 on the silicon oxide film 2. Adjacent to the bulk region 3, the N-plus diffusion layer 11 is formed on the silicon oxide film 2.
Is provided above. Furthermore, this N-plus diffusion layer 11
A P plus diffusion layer 12 is provided on the silicon oxide film 2 adjacent to. The P-plus diffusion layer 12 is connected to the second common power supply line 13 via the polysilicon plug 8.

Here, the switching operation of the thyristor is performed by raising and lowering the hot carrier. The thyristor has three pn junctions, and the state is maintained unless the potential applied between the anode and the cathode exceeds the critical condition.

Next, FIG. 3 shows a top view of this embodiment. As shown in FIG. 3, the gate electrode 5 has a comb shape. The N-plus diffusion layer 11 is linearly formed along the longitudinal direction of the comb-shaped shaft-shaped portion of the gate electrode 5. Along the N-plus diffusion layer 11, the P-plus diffusion layer 12 is linearly formed.

N-plus diffusion layers are formed between the comb tooth-shaped portions of the comb-shaped gate electrode 5 to alternately serve as the source diffusion layers 6 and the drain diffusion layers 7. A source line 9 is linearly formed on the source diffusion layer 7 in parallel with the longitudinal direction of the gate electrode 5 in the comb tooth-shaped portion.

Further, on the drain diffusion layer 7, the bit line 10 is formed in a straight line in parallel with the longitudinal direction of the gate electrode 5 in the comb tooth-shaped portion.

The P-type silicon layer 3 is formed so that two gate electrodes 5 formed in a comb shape are formed below most of their existing portions. Here, the P-type diffusion layer 3 is not formed about halfway down along the longitudinal direction of the axial portion of the gate electrode 5.

Two gate electrodes 5 are formed above the same P-type silicon layer 3 with their comb teeth facing each other.

A plurality of P-type silicon layers 3 are formed at regular intervals. Two N-plus diffusion layers 11 are formed between the P-type silicon layers 3. Further, a second common power supply line 13 and a P plus diffusion layer 12 formed between the two N plus diffusion layers 11 are formed.

On each of the plurality of P-type silicons 3,
A gate electrode 5, a source diffusion layer 6 and a drain diffusion layer 7 having the same shape are formed.

Here, FIG. 2 is a sectional view taken along the line AB, and FIG. 1 is a sectional view taken along the line CD.

FIG. 4 is a sectional view taken along the line E--F in FIG. In FIG. 4, a source region is formed on the left side. That is, the silicon oxide film 2 is formed on the semiconductor substrate 1, and the N-type source diffusion layer 6 is formed thereon. A P-type silicon layer 3 is formed on the silicon oxide film 2 adjacent to the source diffusion layer 6. From the P-type silicon layer 3 to the source diffusion layer 6, the gate electrode 5 is formed on the source diffusion layer 6 with the gate insulating film 4 interposed therebetween.
Are formed.

An N plus diffusion layer 11 is formed on the silicon oxide film 2 adjacent to the P type silicon layer 3. A P plus diffusion layer 12 is formed on the silicon oxide film 2 adjacent to the N plus diffusion layer 11. On the other side of the P plus diffusion layer 12, an N plus diffusion layer 11 is formed on the silicon oxide film 2.

Here, in the cross section in FIG. 4, the thyristor operation is performed on the P-type silicon layer 3 below the gate electrode.
That potential is set.

Here, a drain avalanche is generated between the drain diffusion layer 7 and the P-type silicon layer 3, holes are injected into the P-type silicon layer 3, and the hole accumulation state (the potential is higher than that in the thermal equilibrium state). The state) is, for example, data 1.

The state in which the PN junction between the drain diffusion layer 7 and the P-type silicon layer 3 is forward biased and the holes of the P-type silicon layer 3 are emitted to the drain diffusion layer 7 side is set as data 0. .

Data 0 and 1 are differences in potential of the bulk region 3 and are stored as differences in threshold voltage of the MOS transistors.

The threshold voltage Vth1 in the data 1 state in which the potential of the bulk region 3 is high due to hole accumulation is lower than the threshold voltage Vth0 in the data 0 state.

In order to maintain the state of data 1 in which holes, which are majority carriers, are accumulated in the bulk region 3, it is necessary to apply a negative bias voltage to the word line.

The data holding state does not change even if the read operation is performed unless the reverse data write operation (erase) is performed. Thus, unlike a 1-transistor / 1-capacitor DRAM that utilizes charge storage of a capacitor, non-destructive read is possible.

In the data reading, a read potential in the middle of the threshold voltages Vth0 and Vth1 of the data 0 and 1 is applied to the word line so that no current flows in the memory cell of 0 data and the current flows in the memory cell of 1 data. Is used.

For example, the bit line is precharged to a predetermined potential, and then the word line is driven. This allows
In the case of 0 data, there is no change in the bit line precharge potential, and in the case of 1 data, the precharge potential decreases.

Next, in order to selectively write 0 data, that is, to release holes only from the bulk region of the memory cell selected by the potentials of the selected word line and bit line in the memory cell array, the word There is essentially capacitive coupling between the line and the bulk region.

In the state where holes are accumulated in the bulk region in the data 1, the word line is biased sufficiently in the negative direction,
It is necessary to hold the memory cell in a state where the gate-substrate capacitance becomes a gate oxide film capacitance, that is, in a state where a depletion layer is not formed on the surface.

In the read / write operation of 1 data and 0 data, when the word line is set to a high potential after reading and 0 data is written to the same selected cell, a negative potential is simultaneously applied to the bit line to write 1 data. In that case, a positive potential is applied to the bit line. Thus, in the cell to which 0 data is applied, the drain junction becomes forward biased, and holes in the bulk region are emitted. In the cell to which 1 data is given, avalanche breakdown occurs at the drain junction and holes are injected into the bulk region 3.

In the read / refresh operation of 1 data or 0 data, the word line held at the negative potential is raised to the positive potential, and the word line potential is set to the threshold value Vt of data 0, 1.
High potential from both h0 and Vth1 or Vth
The potential is set between 1 and Vth0.

Next, a potential is supplied to the bit line to set data 1
In the case of 1, the memory cell is deeply turned on and the potential of the bit line does not rise so much. When the data is 0, the current of the memory cell is small and the potential of the bit line rises rapidly. Thereby, the data 0 and 1 are distinguished.

At the next timing, when the read data is 1, a positive potential is applied to the bit line, and when the read data is 0, a negative potential is applied to the bit line.

Thus, when the selected memory cell is in the data 1 state, avalanche breakdown occurs at the drain junction,
Holes are injected into the bulk region 3 and the data 1 is written again. When the selected memory cell is in the state of data 0,
The drain junction becomes forward biased, holes in the bulk region 3 are released, and 0 is written again. After that, the word line is biased in the negative direction to complete the read / refresh operation.

When one data is held, the NPNP thyristor between the source and the second common power supply is on. 1 data writing is according to the following sequence.

In the SOI transistor of FIG. 2, the bit line and the word line are set to a high potential to generate hot carriers, and the potential of the floating body 3 is increased.

By moving the hot holes from the N plus layer to the P type silicon layer 3 which is a floating body,
1 is written.

When the potential exceeds a certain level, the thyristor of the source (N) 6-floating body (P) 3-N layer 11-second common power supply line (P) 12 is turned on. This makes S
The floating body 3 of the OI transistor settles to a potential between the potential of the first common power supply line (here, 0 V) and the potential of the second common power supply line (here, 2 V). This is due to the IR drop setting the potential between the potentials applied to the anode and cathode of the thyristor.

One data is set by flowing a current defined by the body potential through the bit line. MOS
The threshold of the FET changes depending on the well potential given from the outside. Even if SOI is used, the threshold value is defined by the potential of the floating gate body, and a predetermined current flows.

For 0 data, the word line is turned on, and the floating body is lifted by capacitive coupling at that time to bring the bit line to a negative potential, so that a forward bias current flows selectively between the floating body and the bit line only in a certain cell. To do so. As a result, even if 1 data is stored before this 0 data writing cycle, the thyristor is turned off and the potential of the body is set low. This is writing 0 data.

When writing data 0, the bit line potential is made negative and holes are extracted. Here, -0.6V rises to 0V over time due to the PN junction leak.

When writing data 1, the P layer, which is a floating body, is set to a high potential of about 1 V by the thyristor operation. Therefore, even if the potential of 0 data rises to 0 V, there is a potential difference of 1 V from 1 data of 1 V, and the data retention characteristic can be maintained without the influence of leak current.

Data 1 and 0 are determined by hot holes entering and flowing out from the N plus layer adjacent to the P layer which is a floating body.

For example, in the state of data 1, the N plus layer is about 1 V, and in the state of data 0, the N plus layer is -V.
It is about 0.5V.

Here, the potential of the P layer in the state of data 1 is set to 1
By setting the potential to about V and a high potential, the data retention characteristic is improved.

The MOS transistor has a first data state having a first threshold voltage in which majority carriers are injected into the semiconductor layer and a second data state having a second threshold voltage in which majority carriers in the semiconductor layer are released to the drain diffusion layer. And the data state of

In the first data state, a predetermined potential is applied by capacitive coupling from the gate electrode, avalanche breakdown occurs between the semiconductor layer and the drain diffusion layer, and majority carriers are injected into the semiconductor layer. Written by

In the second data state, a forward bias is applied between the drain diffusion layer and the semiconductor layer to which a predetermined potential is applied by capacitive coupling from the gate electrode, so that majority carriers in the semiconductor layer are transferred to the drain diffusion layer. It is written by pulling it out.

At the time of writing data, the fixed potential line is used as the reference potential, and the selected word line has a first potential higher than the reference potential.
Is applied to the unselected word line, a second potential lower than the reference potential is applied to the non-selected word line, and a third potential and a reference potential higher than the reference potential are applied to the bit line according to the first and second data states. A lower fourth potential.

At the time of reading data, a fixed potential line is used as a reference potential, and a selected word line is selected by applying a fifth potential higher than the reference potential between the first threshold voltage and the second threshold voltage. Conduction or non-conduction of the memory cell is detected.

As another data reading method,
A fifth potential higher than the first and second threshold voltages and higher than the reference potential is applied to the selected word line with the fixed potential line as the reference potential, and the conductivity of the selected memory cell is detected.

FIG. 5 shows an equivalent circuit of this embodiment. M
The back gate of the OS transistor 20 has a first PNP
The base of the bipolar transistor 21 is connected via the wiring resistor 22. The emitter of the first PNP bipolar transistor 21 is connected to the source of the MOS transistor, and the collector is connected to the base of the second PNP transistor 23. The collector of the second PNP transistor 23 is connected to the base of the first PNP transistor 21. Further, the second PNP transistor 23
The emitter of is connected to the second common power supply line 13.

A third common power supply line (not shown) is independently provided at the base of the second PNP bipolar transistor 23.
May be connected.

Here, N-type source / drain regions 6 and 7 are formed.
Has a higher potential than the P-type silicon substrate 3 in all memory states.

In this embodiment, since the data 1 is held by the latch current of the thyristor, there is no deterioration of the data holding characteristic due to the junction leak.

According to the present embodiment, it is possible to provide a semiconductor memory device which realizes a stable memory operation which does not require a refresh operation and has an infinite data retention characteristic at a high density, like the SRAM. Further, it is possible to provide a semiconductor memory device having a smaller leak current than a DRAM.

It is also possible to implement the SOI in the present embodiment as a bulk silicon layer.

In the present embodiment, the second common power supply line between adjacent MOS transistors is shared and formed by one line, so that the area of the power supply line is reduced and the semiconductor memory device High integration can be achieved.

(First Modification of First Embodiment) In this modification, as shown in FIG. 6, two second common power supply lines are provided separately for each adjacent gate electrode 5. ing. By forming in this way, it is possible to obtain the same effect as that of the first embodiment, and to independently supply power to each adjacent gate electrode, reduce the influence of mutual potential change, and reduce power supply. The potential can be stabilized.

(Second Modification of First Embodiment) In this modification, a structure as shown in FIG. 7 is used instead of FIG. 1 which is a sectional view taken along the line CD in FIG. It is adopted. Here, the second common power supply line 30 is connected to the silicon oxide film 2
It is arranged in the lower semiconductor substrate 1 as an N-type diffusion layer, and one N-type diffusion layer is provided so as to be shared by adjacent elements, thereby shortening the length in the left-right direction in FIG. 7 and further increasing integration. Can be planned.

An N-type conductive layer 31 is provided in the silicon oxide film 2 and the P-type silicon substrate 3 so as to be connected to the N-type diffusion layer 30. Here, the N-type conductive layer 31 can be formed of polysilicon or the like. The N-type conductive layer 31 penetrates the silicon oxide film 2 and is formed in the P-type semiconductor substrate 1.
It is electrically connected to the mold diffusion layer 30.

It can be realized by replacing the SOI with a bulk silicon layer.

[0084]

According to the present invention, it is possible to provide a highly integrated semiconductor memory device having improved data retention characteristics.

[Brief description of drawings]

FIG. 1 is a cross-sectional view taken along line C-D in FIG. 3 showing a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line AB in FIG. 3 showing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a top view showing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a sectional view taken along the line EF in FIG. 3 showing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 6 is a top view showing a semiconductor memory device according to a first modification of the first embodiment of the present invention.

FIG. 7 is a cross-sectional view taken along line C-D in FIG. 3 showing a semiconductor memory device according to a second modification of the first embodiment of the present invention.

FIG. 8 is an equivalent circuit diagram of a conventional DRAM cell.

FIG. 9 is a sectional view of a conventional trench type DRAN cell.

[Explanation of symbols]

1 semiconductor substrate 2 silicon oxide film 3 P type silicon layer (bulk region, floating body) 4 gate insulating film 5 gate electrode 6 N plus source diffusion layer 7 N plus drain diffusion layer 8 polysilicon plug 9 first common power supply line 10 Bit line 11 N plus diffusion layer 12 P plus diffusion layer 13 Second common power supply line 20 MOS transistor 21 First PNP bipolar transistor 22 Wiring resistor 23 Second PNP bipolar transistor 30 N type diffusion layer 31 N type conductive layer

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takashi Osawa             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside F term (reference) 5B015 HH04 JJ31 JJ44 KA13 QQ04                 5F005 AE09 AF00 AH04 CA02                 5F083 AD02 AD70 HA02 JA35 JA39                       LA11 LA12 LA16 LA21 MA06                       MA19 MA20

Claims (9)

[Claims] 1. A semiconductor substrate, an insulating layer formed on the semiconductor substrate, a semiconductor layer formed on the insulating layer and in a floating potential state, and a drain formed in the semiconductor layer and separated from each other. And a source diffusion layer, a gate insulating film formed on the semiconductor layer between the drain and source diffusion layers, and a gate electrode formed on the gate insulating film,
The gate electrode is connected to a word line, the drain diffusion layer is connected to a bit line, the source diffusion layer is connected to a fixed potential line, respectively, and the semiconductor layer has a first threshold voltage in which majority carriers are injected. MO storing one data state and a second data state having a second threshold voltage at which majority carriers of the semiconductor layer are released to the drain diffusion layer.
An S transistor, a first diffusion layer formed in the semiconductor layer, in contact with the semiconductor layer below the gate electrode, and having a conductivity type opposite to that of the source diffusion layer; and a first diffusion layer formed in the semiconductor layer. And a second diffusion layer having a conductivity type opposite to that of the first diffusion layer. 2. A semiconductor substrate, an insulating layer formed on the semiconductor substrate, a semiconductor layer formed on the insulating layer, and a first diffusion layer of the first conductivity type formed in the semiconductor layer. And a gate electrode formed in a comb shape on the first diffusion layer to which a word line potential is applied, and the semiconductor layer provided on one side between the comb-teeth shaped portions of the gate electrode, A second conductivity type drain diffusion layer provided, and a second conductivity type source diffusion layer provided on the semiconductor layer on the other side between the comb-shaped portions of the gate electrode and supplied with a first common power source; A second diffusion type first diffusion layer connected to the first diffusion layer and formed on the semiconductor layer; and a second conduction type first diffusion layer formed on the semiconductor layer, Having a second diffusion layer of the first conductivity type to which a second common power source is applied The semiconductor memory device according to claim. 3. The first diffusion layer of the second conductivity type and the second diffusion layer of the first conductivity type are linearly provided in parallel to a comb axis of the gate electrode. 2. The semiconductor storage device according to 2. 4. The semiconductor memory device according to claim 3, wherein the second diffusion layer of the first conductivity type has a folded planar shape with a central axis of line symmetry. 5. A semiconductor substrate, an insulating layer formed on the semiconductor substrate, a semiconductor layer formed on the insulating layer, and a first diffusion layer of the first conductivity type formed in the semiconductor layer. And a gate electrode formed in a comb shape on the first diffusion layer to which a word line potential is applied, and the semiconductor layer provided on one side between the comb-teeth shaped portions of the gate electrode, A second conductivity type drain diffusion layer provided, and a second conductivity type source diffusion layer provided on the semiconductor layer on the other side between the comb-shaped portions of the gate electrode and supplied with a first common power source; A second conductive type first conductive layer connected to the first diffusion layer and penetrating through the semiconductor layer from above the semiconductor substrate; and a semiconductor connected to the second conductive type first conductive layer, A second conductivity type formed in the substrate and supplied with a second common power source The semiconductor memory device characterized by having a first diffusion layer. 6. A semiconductor substrate, an insulating layer formed on the semiconductor substrate, a semiconductor layer formed on the insulating layer, and a first diffusion layer of the first conductivity type formed in the semiconductor layer. And a first gate electrode formed in a comb shape on the first diffusion layer of the first conductivity type and to which a word line potential is applied, and the semiconductor layer on one side between comb-shaped portions of the first gate electrode. A first drain diffusion layer of a second conductivity type, which is provided above and to which a bit line potential is applied; and a semiconductor layer on the other side between the comb-shaped portions of the first gate electrode, the first common power source A first source diffusion layer of a second conductivity type that is provided with a second conductivity type that is linearly formed on the semiconductor layer, is connected to the first diffusion layer, and is parallel to the comb axis of the gate electrode. And a first diffusion layer connected to the first diffusion layer of the second conductivity type, A second diffusion layer of a first conductivity type which is formed in parallel linearly on the semiconductor layer and is supplied with a second common power source; and a second diffusion layer of the first conductivity type which is connected to the second diffusion layer of the first conductivity type. A second diffusion layer of the second conductivity type linearly formed on the semiconductor layer in parallel with the second diffusion layer of the second diffusion layer, and a third diffusion layer of the first conductivity type formed in the semiconductor layer. A second gate electrode formed in a comb shape on the third diffusion layer of the first conductivity type and to which a word line potential is applied, and on the semiconductor layer on one side between comb-shaped portions of the second gate electrode And a second drain diffusion layer of the second conductivity type to which a bit line potential is applied, and the semiconductor layer on the other side between the comb-shaped portions of the second gate electrode. And a second source diffusion layer of the second conductivity type provided. 7. A semiconductor substrate, an insulating layer formed on the semiconductor substrate, a second region of the second conductivity type formed on the insulating layer and supplied with a first common power source, and a second region of the second region. A second region of the second conductivity type, which is formed apart from the first region of the conductivity type and is supplied with a potential as a bit line; a first region of the second conductivity type; and a second region of the second conductivity type. A first conductivity type first layer formed on the insulating layer between the two regions.
Region, a gate insulating film formed on the first region of the first conductivity type, a gate electrode formed on the gate insulating film and given a potential as a word line, and a gate electrode of the first conductivity type. A third region of the second conductivity type that is in contact with the first region and is supplied with the second common power source, and a second region of the first conductivity type that is in contact with the third region of the second conductivity type.
And a semiconductor memory device. 8. A second region of the second conductivity type and the first region.
A first region of conductivity type and a third region of the second conductivity type,
8. The semiconductor memory device according to claim 7, wherein the second region of the first conductivity type functions as a thyristor, and the potential fluctuation of the first region of the first conductivity type functions as a trigger. 9. The first region of the second conductivity type and the second region
The second region of conductivity type, the gate insulating film, and the gate electrode form a MOS transistor, and the potential variation of the first region of the first conductivity type is caused by the generation of channel hot carriers in the MOS transistor. The semiconductor memory device according to claim 7, wherein the semiconductor memory device occurs.