JP2002369542A - Semiconductor power module and power converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce voltage applied to respective IPMs(intelligent power module), a semiconductor power module with a protection function which cuts off when some failure is detected, under abnormal conditions for application of a semiconductor having low withstand voltage to the IPMs, in a three-level inverter formed out of the IPMs. SOLUTION: IPM 31 has two selectable operation modes; a first mode which cuts off, when failure is detected according to a protection mode setting signal ST from the outside, and a second mode which does not cut off but will output only an error signal OF. The three-level inverter 50 has four IPM 31s (X1, X2, X3, X4). X1 and X4 are set in the first mode, X2 (X3) is set in the second mode only when X1 (X4) is under ON state, and when X2 (X3) detects a failure, X1 (X4) is, first, turned off, then X2 (X3) is placed into the first mode, thereby making X2 (X3) turned off.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor power module in which a switching semiconductor element and a control circuit for controlling the same are housed in the same package, and a three-level inverter device provided with the semiconductor power module.

[0002]

2. Description of the Related Art A semiconductor power module contains a switching semiconductor element and a control circuit for controlling the switching semiconductor element in the same package, and is mainly used for a power converter such as an inverter or an uninterruptible power supply. FIG. 5 is a configuration diagram showing a conventional semiconductor power module (intelligent power module = hereinafter, referred to as IPM) described in, for example, Electronics Technology 1993-8, p. In FIG. 5, 1 is IPM and 2 is IPM.
The main circuit portion of M1 is an IGBT 3 that constitutes a main circuit, 4 is a flywheel diode that constitutes a main circuit, and 5 is an IP.
M1 is a collector terminal, 6 is an IPM1 emitter terminal, 7
Is connected to a sense emitter provided for detecting a current flowing from the collector terminal 5 to the emitter terminal 6 of the IGBT 3, and a resistor for converting a current flowing through the sense emitter into a voltage. A drive circuit 9 for turning on or off is a protection circuit for protecting the IGBT 3.
An overcurrent protection circuit 10 that detects an overcurrent of the BT3 and turns off the IGBT3, and detects a short-circuit current of the IGBT3 and detects the IGBT3.
A short-circuit current protection circuit 11 that turns off the power supply, a control power supply voltage drop protection circuit 12 that turns off the IGBT 3 when the power supply voltage of the drive circuit 8 falls below a predetermined voltage, and an overheat of the IGBT 3 and the flywheel diode 4 is detected and the IGTB 3 is turned off. There is an overheat protection circuit 13. Reference numeral 14 denotes an error output circuit that outputs an error signal FO to the outside of the IPM 1 when those protection functions operate.

The operation of the conventional IPM 1 configured as described above will be described below. When an ON signal is input as the gate signal CI, the gate of the IGBT 3 is turned on by the drive circuit 8 and the IGBT 3 is turned on. For example, when the current flowing from the collector terminal 5 to the emitter terminal 6 via the IGBT 3 in this ON state exceeds a predetermined current value set in the overcurrent protection circuit 10, the overcurrent protection circuit 10
Detects an overcurrent and outputs a protection signal OC. The protection signal OC is input to the driving circuit 8 and the driving circuit 8
Is turned off, and the IGBT 3 is turned off. Similarly,
When each of the short-circuit protection circuit 11, the control power supply voltage drop protection circuit 12, and the overheat protection circuit 13 detects an abnormality that exceeds a preset reference, the respective protection signals SC, U
V and OT are input to the drive circuit 8, and the IGBT 3 is turned off.

FIG. 6 shows an example in which the IPM 1 is applied to a three-level inverter 18 and shows a circuit configuration for one phase. As shown in FIG. 6, four stages of IPMs (U1, U1) are connected in series between the high-potential-side power supply terminal P and the low-potential-side power supply terminal N.
2, U3, U4) are connected. Also, 19, 20
Are capacitors connected in series between the high-potential-side power supply terminal P and the low-potential-side power supply terminal N, have the same capacitance, and are charged with the DC voltage E, respectively. Reference numerals 21 and 22 denote clamp diodes. Between the connection between the IPMs (U1, U2) and the intermediate potential point C, and between the two IPMs (U1, U2).
3, U4) and the intermediate potential point C, respectively. 23 is a three-level inverter 18
Output terminal.

In normal operation, three-level inverter 1
8 repeats three operation modes in order. First, two I
PM (U1, U2) turns on and other IPMs (U3, U2)
4) turns off. Next, two IPMs (U2, U3)
Turns on, and the other IPMs (U1, U4) turn off. Subsequently, two IPMs (U3, U4) are turned on, and the other IPMs (U1, U2) are turned off. Each IPM (U1-U
As a result of the above operation 4), the voltage with reference to the intermediate potential point C of the output terminal 23 changes in the order of E, 0, and -E, and the three-level inverter 18 outputs a three-level voltage. In any mode, the two IPMs 1 are turned off, and the collector voltages applied to the respective IPMs (U1 to U4) become E. Thus, in the three-level inverter 18, each IPM (U1 to U4)
May be 1/2 of the voltage between the high-potential-side DC bus and the low-potential-side DC bus (hereinafter, referred to as the DC bus voltage), and the voltage between the terminals is generally higher than the withstand voltage of the IPM used. Can handle voltage.

[0006]

Next, the operation of the conventional three-level inverter 18 configured as described above when an abnormality occurs will be described with reference to FIG. As shown in FIG. 7, the inductive load L is connected, for example, between the output terminal 23 and the low potential side DC bus. As shown in FIG. 7A, two IPMs (U1, U2) are turned on and the other IPMs are turned on.
When (U3, U4) is turned off, a load current flows from the P terminal of the capacitor 19 to the N terminal of the capacitor 20 via the IGBT 3 of the IPM (U1, U2) and the load L. For example, when the load current increases due to an abnormality in the load circuit, the IPM (U2) detects an overcurrent by the overcurrent protection circuit 9 before the IPM (U1), and the IPM (U2) is turned off. As shown in (b), the current of the load L is I
It circulates through the flywheel diode 4 of PM (U3, U4). At this time, since the IPM (U1) is still on, the entire voltage (DC bus voltage = 2E) from the P terminal of the capacitor 19 to the N terminal of the capacitor 20 is applied to the IPM (U2). .

Since the conventional semiconductor power module is configured as described above, the withstand voltage of each of the IPMs 1 constituting the three-level inverter 18 needs to be equal to or higher than the DC bus voltage in case the protection operation is activated. was there. For this reason, there is a problem that a semiconductor device having a low withstand voltage, which is an advantage of the original three-level inverter, cannot be used, so that the cost is increased. was there.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. In a three-level inverter having a protection function of shutting off when each semiconductor power module detects an abnormality, a three-level inverter having a withstand voltage is provided. It is an object of the present invention to make a low-power semiconductor power module applicable, and to provide a structure of such a semiconductor power module and a three-level inverter.

[0009]

Means for Solving the Problems Claim 1 according to the present invention.
The semiconductor power module described above conducts or cuts off a pair of main electrodes in response to a drive control signal input to a control electrode, and a switching semiconductor element to which a flywheel diode is connected in anti-parallel, An apparatus configuration comprising: a control circuit that outputs the drive control signal in response to an input control signal that is input; and abnormality detection means that detects an abnormality in the switching semiconductor element or the control circuit. In the first mode, when the abnormality is detected by the abnormality detecting means, an abnormality detection signal is output to the outside, and the drive control signal is output regardless of the input control signal. When the switching semiconductor element is cut off as "L", and no abnormality is detected (hereinafter, referred to as normal), the drive according to the input control signal is turned off. The switching semiconductor element is turned on / off by a control signal, and in the second mode, the switching semiconductor element is turned on / off by the drive control signal in accordance with the input control signal, and the abnormality is detected by the abnormality detecting means. Sometimes, it outputs an abnormality detection signal to the outside.

According to a second aspect of the present invention, in the semiconductor power module according to the first aspect, the abnormality detecting means includes an overcurrent detecting means for detecting an overcurrent flowing between the main electrodes of the switching semiconductor element; Overheat detection means for detecting overtemperature of the semiconductor element, short-circuit current detection means for detecting short-circuit current of the switching semiconductor element, or control power supply voltage for detecting that the power supply voltage supplied to the control circuit has dropped below a predetermined value It is constituted by any one of the decrease detecting means or a combination thereof.

According to a third aspect of the present invention, there is provided a semiconductor power module according to the first or second aspect, wherein the first or the second is set by an input setting signal input from the outside.
The mode is set.

According to a fourth aspect of the present invention, there is provided a power conversion apparatus comprising: a first to a fourth four units connected in series between a high-potential-side DC bus and a low-potential-side DC bus; 3. A three-level inverter device comprising the semiconductor power module described in 3 above, further comprising control means for outputting an input control signal and an input setting signal to each of the first to fourth semiconductor power modules. .

According to a fifth aspect of the present invention, there is provided a power conversion device according to the fourth aspect, wherein the control means controls the first to fourth power supply units.
, The first and fourth semiconductor power modules are always in the first mode, and the second semiconductor power module is in the first semiconductor power module. When the module is turned off, the first mode is set. When the module is turned on, the mode is set to the second mode. For the third semiconductor power module, the first mode is set when the fourth semiconductor power module is turned off.
The second mode is set to the second mode when conducting, and the first mode is always set when the second semiconductor power module is shut off.
And the fourth semiconductor power module is always shut off when the third semiconductor power module is shut off.

According to a sixth aspect of the present invention, there is provided a power converter according to the fifth aspect, wherein a first input control signal input to the first semiconductor power module and an output signal from the first semiconductor power module are output. First transmitting means for receiving a first abnormality detection signal, and transmitting a second input setting signal to the second semiconductor power module in accordance with these signals, and an output from the second semiconductor power module. Second transmission means for receiving the second abnormality detection signal to be transmitted and transmitting a first input control signal to the first semiconductor power module, and a fourth input to be inputted to the fourth semiconductor power module A control signal and a fourth abnormality detection signal output from the fourth semiconductor power module are received, and a third input setting signal to the third semiconductor power module is received according to these signals. And third transmitting means for transmitting, the fourth to the third third of the abnormality detection signal by receiving the fourth semiconductor power module which is output from the semiconductor power module
And a fourth transmitting means for transmitting the input control signal of the above.

According to a seventh aspect of the present invention, in the power conversion apparatus according to the sixth aspect, when the first semiconductor power module is in a normal state and the first input control signal is on, the first The transmitting means may be a second mode for setting a second mode.
Is transmitted to the second semiconductor power module, and when the second semiconductor power module set to the second mode outputs the second abnormality detection signal, the second transmitting means performs the above-described operation. A first procedure for turning off the first input control signal to be transmitted to the first semiconductor power module, and the first transmitting means having received the first input control signal sets a first mode The second procedure of transmitting the second input setting signal to the second semiconductor power module to the second semiconductor power module causes the second semiconductor power module in which abnormality is detected to operate after the first semiconductor power module is shut off. , When the fourth semiconductor power module is operating normally and the fourth input control signal is on, the third transmitting means sets the second mode. Third Transmits the force setting signal to the third semiconductor power module, the third set in a second mode
A third procedure in which when the semiconductor power module outputs a third abnormality detection signal, the fourth transmitting means turns off the fourth input control signal transmitted to the fourth semiconductor power module; The fourth procedure of receiving the fourth input control signal and transmitting the third input setting signal for setting the first mode to the third semiconductor power module is performed by the third transmitting means. The detected third semiconductor power module is set to the first mode and then shut off after the fourth semiconductor power module is shut off.

According to a seventh aspect of the present invention, there is provided the power conversion apparatus according to the seventh aspect, wherein the first transmitting means and the third transmitting means are provided with a delay circuit.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram showing a semiconductor power module according to Embodiment 1 of the present invention. In FIG. 1, 31 is an IPM as a semiconductor power module, 32 is a main circuit part of the IPM 31, 33 is an IGBT as a switching semiconductor element constituting the main circuit, 34 is a main circuit, and IGBT 33
Flywheel diode connected in anti-parallel to
Is a collector terminal of the IPM31, 36 is an emitter terminal of the IPM31, 37 is connected to a sense emitter provided for detecting a current flowing from the collector terminal 35 of the IGBT 33 to the emitter terminal 36, and converts a current flowing through the sense emitter into a voltage. It is the resistance to do. Also, 38
Is a drive circuit as a control circuit for receiving a gate signal CI as an input control signal from the outside and outputting a gate drive signal GP39 as a drive control signal for turning on or off the IGBT 33; Is a gate signal selection circuit.

Further, 41 is an overcurrent detection circuit for outputting an OC signal when an overcurrent exceeding a predetermined current flows in the IGBT 33, and 42 is a short-circuit current for outputting an SC signal when a short-circuit current flows in the IGBT33. A detection circuit 43 is a control power supply voltage drop protection circuit that outputs a UV signal when the power supply voltage of the drive circuit 38 becomes lower than a predetermined voltage, and 44 is an IGB
An overheat detection circuit that detects overheat of the T33 and the flywheel diode 34 and outputs an OT signal, 45 is an OC signal,
An error signal output circuit that outputs an error signal FO as an abnormality detection signal to the outside of the IPM 31 when any one of the SC signal, the UV signal, and the OT signal is received. A protection mode selection circuit that receives the protection mode setting signal ST and the error signal FO and sends a signal for selecting the gate signal CI to the gate signal selection circuit 40. The abnormality detection circuit 47 as an abnormality detection means is formed by these 41 to 46. Be composed.

The operation of the IPM 31 thus configured will be described below. In a normal state in which no abnormality is detected by each of the abnormality detection circuits 41 to 46, the error output circuit 45 outputs "L", whereby the protection mode selection circuit 46 outputs "H", and the gate signal selection is performed. The gate drive signal GP output from the circuit 40 becomes “L” when the gate signal CI is “L”, and becomes “H” when the gate signal CI is “H”, and the IGBT 33 is turned on / off according to the signal. For example, when the protection mode setting signal ST input from the outside is “H” and any abnormality is detected, the error signal output circuit 45 outputs “H” and outputs the error signal FO to the outside. Output. Thus, the protection mode selection circuit 46 outputs "L", the gate drive signal GP output from the gate signal selection circuit 40 becomes "L" regardless of the state of the gate signal CI, and the IGBT 33 is turned off. For example, when the protection mode setting signal ST input from the outside is “L” and any abnormality is detected, the error signal output circuit 45 outputs “H” and outputs the error signal FO to the outside. Output, the protection mode selection circuit 46 outputs “H”, and the gate signal selection circuit 40
A gate drive signal GP output from the gate signal CI
Is "L" if "L", and "H" if "H", so that the IGBT 33 can be turned on / off according to the gate signal CI even while detecting an abnormality.

That is, two kinds of operation modes are set in the IPM 31 by the protection mode setting signal ST input from the outside, and in the first mode in which the protection mode setting signal ST is "H", any abnormality is detected. When an abnormality is detected by the circuits 41 to 44, an error signal FO is output to the outside,
The gate drive signal GP is set to “L” regardless of the gate signal CI.
IGBT 33 is forcibly turned off. In the second mode in which the protection mode setting signal ST is “L”, when any of the abnormality detection circuits 41 to 44 detects an abnormality,
An error signal FO is output to the outside, but the IGBT 33 is turned on / off by a gate drive signal GP corresponding to the gate signal CI.
Control off. In normal operation when no abnormality is detected,
In both the first and second modes, the IGBT 33 is turned off / off by the gate drive signal GP corresponding to the gate signal CI.

Next, a power conversion apparatus in which the IPM 31 configured as described above is applied to a three-level inverter will be described below. FIG. 2 shows the four IPMs 31 shown in FIG.
FIG. 3 is a diagram showing a circuit configuration for one phase in an example in which is applied to a three-level inverter 50. As shown in FIG. 2, first to first power supply terminals are connected in series between a high-potential-side power terminal P and a low-potential-side power terminal N.
Fourth four-stage IPMs (X1, X2, X3, X4) are connected. Further, 51 and 52 are connected in series between the high-potential-side power supply terminal P and the low-potential-side power supply terminal N, have the same capacitance, and are charged with the DC voltage E, respectively. Diodes connected between the connection between the two IPMs (X1, X2) and the intermediate potential point C, and between the connection between the two IPMs (X3, X4) and the intermediate potential point C, respectively Have been. 55
Is an output terminal of the three-level inverter 50.

Reference numeral 60 denotes each IPM (X1, X2, X
3, X4) to output gate signals CI1 to CI4 and protection mode setting signals ST1 to ST4. Control circuits 61a and 61b for controlling IPM (X1, X4), and IPM (X2 , X3). In each of the control circuits 61a, 62a, 62b, and 61b, each gate signal CIX1 to CIX4 is input from the outside, and an error signal FO is supplied to each IPM (X1 to X4).
1 to FO4, and outputs gate signals CI1 to CI4 and protection mode setting signals ST1 to ST4. Note that I
Protection mode setting signal S input to PM (X1, X4)
T1 and ST4 are always set to “H” in advance.

The control circuit 61a (63b)
1b) and the gate signal CIX1 (CIX4)
AND circuit 64a that receives as input the step signal S1 (S3) and outputs the IPM gate signal CI1 (CI4)
(64b) is provided in the control circuit 61a (61b), and includes the error signal FO1 (FO4) and the IPM gate signal C.
A step signal S2 (S3) which becomes an inverted signal of I1 (CI4) and a protection mode setting signal ST2 (ST3) as an input.
OR as first (third) transmitting means for outputting 4)
Circuit. As a result, the step signal S2 (S4) output from the OR circuit 64a (64b) becomes the IPM (X
2) Protection mode setting signal ST2 (ST3) to (X3)
Sent as Further, the protection mode setting signal ST2 (ST3) input to the IPM (X2) (X3)
"L" when M (X1) (X4) is on, "H" when it is off
Becomes

Further, 65a (65b) is a control circuit 62
a (62b) and a gate signal CIX2 (CI
X3) and the error signal FO2 (FO3) as inputs.
An OR circuit that outputs a PM gate signal CI2 (CI3),
An AND circuit 66a (66b) is provided in the control circuit 62a (62b) and receives the gate signal CIX2 (CIX3) and the inverted signal of the error signal FO2 (FO3) and outputs a step signal S1 (S3). is there. This A
The ND circuit 66a (66b) and the AND circuit 63a (63
b) constitutes a second (fourth) transmission means,
Upon receiving the error signal FO2 (FO3) of M (X2) (X3), the step signal S1 (S3) is transmitted and the IPM
(X1) IPM gate signal CI1 to (X4) (CI
4) is sent out. Further, 67a (67b) is provided in the control circuit 62a (62b), and the step signal S2
This is a delay circuit provided in the transmission path of (S4).

The operation of the three-level inverter 50 configured as described above will be described with reference to FIGS. As shown in FIG. 3, an inductive load L is connected, for example, between an output terminal and a low-potential-side DC bus. In FIG. 4,
The timing chart of each signal is shown. First, FIG.
The two IPMs (X1, X2) turn on as shown in
The normal state (ta section) in which the other IPMs (X3, X4) are turned off will be described below. Normally, IPM
The error signal FO2 of (X2) = "L". At this time, when the gate signal CIX2 of the control circuit 62a becomes "H", the gate signal CI2 of the IPM (X2) becomes "H" and the IPM (X2) turns on. Since the gate signal CIX2 = “H” and the error signal FO2 = “L” of the control circuit 62a, the signal S1 becomes “H” by the AND circuit 66a.
When the gate signal CIX1 of the control circuit 61a becomes “H”, since the signal S1 is “H” from the above, IPM (X
The gate signal CI1 of 1) becomes "H" and the IPM (X1)
Turns on. Gate signal CI1 of IPM (X1) =
Since the error signal FO1 = "L" at "H", the signal S2
Becomes "L", and the protection mode setting signal ST2 of the IPM (X2) becomes "L". With the above operation, the IPM (X1,
X2) is on, the load current I is
Terminal → IPM (X1) → IPM (X2) → Flow to the capacitor N terminal via the load L.

Next, the load current I
Will be described below with reference to FIG. 3B and FIG. 4 (tb section) when IPM (X2) detects an overcurrent before IPM (X1). IP
If IPM (X2) detects an overcurrent before M (X1), error signal FO2 is output, but IPM (X2) is output.
Since the protection mode setting signal ST2 of 2) is “L”,
PM (X2) does not turn off immediately. In addition, IPM (X
Since the error signal FO2 of 2) becomes "H", the OR circuit 6
The output of 5a becomes "H", and the gate signal CI2 of the IPM (X2) becomes "H" and is kept on. IPM (X
When the error signal FO2 of 2) becomes "H", the control circuit 62
The output signal S1 of the AND circuit 66a of “a” becomes “L”.
By the signal S1 as the first step signal, the first
As a procedure, the output of the AND circuit 63a of the control circuit 61a is set to "L" to turn off the IPM (X1). By the above operation, the IPM (X2) is kept on,
(X1) is turned off, and the load current I is applied to the load L via the capacitor C terminal → the clamp diode 53 → IPM (X2).
Flows to Therefore, half of the DC bus voltage (= 2E) is stored in IPM (X1), and IPM (X3) and IPM (X
The remaining half is applied to 4). IPM (X
Even after 1) is turned off, the load current I increases due to the voltage between the capacitors CN.

Next, the operation of the IPM (X2) leading to the interruption will be described with reference to FIGS. 3C and 4C (section tc). First, I which is the output of the AND circuit 63a
Since the gate signal CI1 of PM (X1) is at "L", the signal S2 is at "H" by the OR circuit 64a.
By the signal S2 as the second step signal, the second
Of the protection mode setting signal S of the IPM (X2)
T2 is changed from "L" to "H". In this case, since the delay circuit 67a is provided, the protection mode setting signal ST2 of the IPM (X2) becomes "after a predetermined delay time T has elapsed by the delay circuit 67a after the signal S2 becomes" H ". From "L" to "H". When the protection mode setting signal ST2 becomes “H”, the overcurrent detection of the IPM (X2) causes
Since the GBT 33 is turned off, the IPM (X
2) turns off. When the IPM (X2) is turned off, the load current I flows through the flywheel diode 34 of the IPM (X3) and the flywheel diode 34 of the IPM (X4), and the DC bus voltage of 1 is supplied to the IPM (X2). / 2 is applied. Finally IPM (X1) and I
PM (X2) shares 1/2 of the DC bus voltage.

As described above, prior to IPM (X1), I
Even if PM (X2) detects an abnormality first,
Since M (X1) is turned off and then IPM (X2) is turned off, the entire voltage of the DC bus is not applied to IPM (X2). Further, since the delay circuit 67a is provided, even if the IPM (X1, X2) has a variation in the OFF operation, etc., after the IPM (X1) is surely turned off, I
PM (X2) can be turned off.

In the description of the operation with reference to FIGS.
IPM (X1, X2) has been described.
One IPM (X3, X4) turns on and the other IPM (X3, X4)
1, X2) can be similarly described. In this case, even if the IPM (X3) detects an abnormality before the IPM (X4), the IPM (X4) is turned off first by the third procedure using the third step signal S3, and then, According to the fourth procedure using the fourth step signal S4, the protection mode setting signal ST3 of the IPM (X3) is changed to "
Since the IPM (X3) is turned off by changing from “L” to “H”, the same effect can be obtained without applying the full voltage of the DC bus to the IPM (X3).

Further, the IPM 31 shown in this embodiment
Has shown the case where it was used for the three-level inverter 50,
It does not limit the use. Further, since the protection mode is set by an external signal ST, external control is facilitated. However, the protection mode can be set inside the IPM 31.

[0031]

As described above, in the semiconductor power module according to the first aspect of the present invention, the connection or disconnection between the pair of main electrodes is made in response to the drive control signal input to the control electrode. A switching semiconductor element having a wheel diode connected in anti-parallel, a control circuit for outputting the drive control signal in response to an input control signal input from the outside, and detecting an abnormality in the switching semiconductor element or the control circuit An abnormality detection unit, which has first and second operation modes. In the first mode, when an abnormality is detected by the abnormality detection unit, an abnormality detection signal is externally output. Output, and the drive control signal is set to “L” irrespective of the input control signal to shut off the switching semiconductor element. The switching semiconductor element is turned on / off by the drive control signal according to the input control signal, and in the second mode, the switching is always performed by the drive control signal according to the input control signal. Since the semiconductor element is turned on / off and an abnormality detection signal is output to the outside when an abnormality is detected by the abnormality detecting means, even if a protection function of shutting off the switching semiconductor element upon abnormality detection is provided, the semiconductor element is not temporarily shut off. It is possible to output only the abnormality detection signal, and the application range in the semiconductor power module is expanded.

According to a second aspect of the present invention, in the semiconductor power module according to the first aspect, the abnormality detecting means includes an overcurrent detecting means for detecting an overcurrent flowing between the main electrodes of the switching semiconductor element; Overheat detection means for detecting overtemperature of the semiconductor element, short-circuit current detection means for detecting short-circuit current of the switching semiconductor element, or control power supply voltage for detecting that the power supply voltage supplied to the control circuit has dropped below a predetermined value Since the semiconductor power module is constituted by any one of the drop detection means or a combination thereof, the abnormality of the semiconductor power module can be detected with high reliability.

According to a third aspect of the present invention, there is provided a semiconductor power module according to the first or second aspect, wherein the first or second input / output setting signal is inputted from the outside.
Is set, the external control becomes easy.

According to a fourth aspect of the present invention, there is provided a power conversion apparatus comprising: a first to a fourth four units connected in series between a high-potential-side DC bus and a low-potential-side DC bus; 3. A three-level inverter device comprising the semiconductor power module described in item 3 and control means for outputting an input control signal and an input setting signal to each of the first to fourth semiconductor power modules. The voltage applied to the power module at the time of abnormality can be reduced, an inexpensive semiconductor element with low withstand voltage can be used, and the loss of the device can be reduced.

According to a fifth aspect of the present invention, there is provided a power conversion apparatus according to the fourth aspect, wherein the control means controls the first to fourth power supply units.
, The first and fourth semiconductor power modules are always in the first mode, and the second semiconductor power module is in the first semiconductor power module. When the module is turned off, the first mode is set. When the module is turned on, the mode is set to the second mode. For the third semiconductor power module, the first mode is set when the fourth semiconductor power module is turned off.
The second mode is set to the second mode when conducting, and the first mode is always set when the second semiconductor power module is shut off.
When the third semiconductor power module is shut off, the fourth semiconductor power module is always shut off. Therefore, the voltage applied to the second or third semiconductor power module when an abnormality occurs. , A low-cost semiconductor element with low withstand voltage can be used, and the loss of the device can be reduced.

According to a sixth aspect of the present invention, in the power conversion apparatus according to the fifth aspect, a first input control signal input to the first semiconductor power module and an output signal from the first semiconductor power module are output. First transmitting means for receiving a first abnormality detection signal, and transmitting a second input setting signal to the second semiconductor power module in accordance with these signals, and an output from the second semiconductor power module. Second transmission means for receiving the second abnormality detection signal to be transmitted and transmitting a first input control signal to the first semiconductor power module, and a fourth input to be inputted to the fourth semiconductor power module A control signal and a fourth abnormality detection signal output from the fourth semiconductor power module are received, and a third input setting signal to the third semiconductor power module is received according to these signals. And third transmitting means for transmitting, the fourth to the third third of the abnormality detection signal by receiving the fourth semiconductor power module which is output from the semiconductor power module
And the fourth transmission means for transmitting the input control signal is provided in the control means, so that signal transmission is effective between the first and second semiconductor power modules and between the third and fourth semiconductor power modules. The voltage applied to the second or third semiconductor power module at the time of abnormality can be reduced with good controllability.

According to a seventh aspect of the present invention, in the power converter according to the sixth aspect, when the first semiconductor power module is in a normal state and the first input control signal is on, the first The transmitting means may be a second mode for setting a second mode.
Is transmitted to the second semiconductor power module, and when the second semiconductor power module set to the second mode outputs the second abnormality detection signal, the second transmitting means performs the above-described operation. A first procedure for turning off the first input control signal to be transmitted to the first semiconductor power module, and the first transmitting means having received the first input control signal sets a first mode The second procedure of transmitting the second input setting signal to the second semiconductor power module to the second semiconductor power module causes the second semiconductor power module in which abnormality is detected to operate after the first semiconductor power module is shut off. , When the fourth semiconductor power module is operating normally and the fourth input control signal is on, the third transmitting means sets the second mode. Third Transmits the force setting signal to the third semiconductor power module, the third set in a second mode
A third procedure in which when the semiconductor power module outputs a third abnormality detection signal, the fourth transmitting means turns off the fourth input control signal transmitted to the fourth semiconductor power module; The fourth procedure of receiving the fourth input control signal and transmitting the third input setting signal for setting the first mode to the third semiconductor power module is performed by the third transmitting means. The detected third semiconductor power module is set to the first mode and then shut off after the fourth semiconductor power module is shut off, so that the first and second semiconductor power modules are turned on when the first and second semiconductor power modules are turned on. When the third semiconductor power module first detects the abnormality, and when the third semiconductor power module detects the abnormality first when the third and fourth semiconductor power modules conduct. , The second voltage applied to the third semiconductor power module can be reduced with good controllability.

[0038] In the power converter according to claim 8 of the present invention, since the delay circuit is provided in the first transmitting means and the third transmitting means in claim 7, the second and third semiconductor power modules are provided. In this case, the effect of reducing the voltage applied in the event of an abnormality can be reliably and reliably obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor power module according to a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a three-level inverter according to the first embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of the three-level inverter according to the first embodiment of the present invention;

FIG. 4 is a timing chart illustrating an operation of the three-level inverter according to the first embodiment of the present invention.

FIG. 5 is a configuration diagram of a conventional semiconductor power module.

FIG. 6 is a circuit configuration diagram of a conventional three-level inverter.

FIG. 7 is a diagram illustrating the operation of a conventional three-level inverter.

[Explanation of symbols]

31 IPM as semiconductor power module, 33
IGBT as a switching semiconductor element, 34 flywheel diode, 35 collector terminal, 36 emitter terminal, 38 drive circuit as control circuit, 39
Gate drive signal GP as drive control signal, 41 overcurrent detection circuit, 42 short-circuit current detection circuit, 43 control power supply voltage drop detection circuit, 44 overheat detection circuit, 45 error signal output circuit, 46 protection mode selection circuit, 47 abnormality detection Abnormality detection circuit as means, a three-level inverter, 60 (61a, 61a, 62a, 62b) control circuit as control means, 63a, 63b AND circuit,
64a, 64b OR circuit, 65a, 65b OR circuit, 66a, 66b AND circuit, 67a, 67b delay circuit, CI Gate signal as input control signal, FO
Error signal as abnormality detection signal, S1 to S4 first
To a fourth step signal, a protection mode setting signal as an ST input setting signal, and X1 to X4 first to fourth IPMs as first to fourth semiconductor power modules.

Claims (8)

[Claims] 1. A switching semiconductor element having a flywheel diode connected in anti-parallel with a pair of main electrodes in response to a drive control signal inputted to a control electrode, and a flywheel diode being inputted from the outside. A semiconductor power module comprising: a control circuit that outputs the drive control signal in response to an input control signal; and an abnormality detection unit that detects an abnormality in the switching semiconductor element or the control circuit. It has two operation modes,
In the first mode, when an abnormality is detected by the abnormality detection means, an abnormality detection signal is output to the outside, and the drive control signal is set to “L” regardless of the input control signal to shut off the switching semiconductor element; When no abnormality is detected (hereinafter referred to as a normal state), the switching semiconductor element is turned on / off by the drive control signal according to the input control signal, and in the second mode, the switching semiconductor element is always switched to the input control signal. A semiconductor power module, wherein the switching semiconductor element is turned on / off by a corresponding drive control signal, and an abnormality detection signal is output to the outside when an abnormality is detected by the abnormality detecting means. 2. The abnormality detecting means includes an overcurrent detecting means for detecting an overcurrent flowing between main electrodes of the switching semiconductor element, an overheating detecting means for detecting an overtemperature of the switching semiconductor element, and a short circuit of the switching semiconductor element. It is characterized by comprising either short-circuit current detecting means for detecting current, or control power supply voltage drop detecting means for detecting that the power supply voltage supplied to the control circuit has dropped below a predetermined value, or a combination thereof. The semiconductor power module according to claim 1, wherein 3. The semiconductor power module according to claim 1, wherein the first or second mode is set by an input setting signal input from outside. 4. The first to fourth four units connected in series between the high-potential-side DC bus and the low-potential-side DC bus.
A three-level inverter device comprising the semiconductor power module described above, and control means for outputting an input control signal and an input setting signal to each of the first to fourth semiconductor power modules. Power converter. 5. The first and fourth semiconductor power modules are always set to a first mode by an input setting signal output from the control means to each of the first to fourth semiconductor power modules. The first semiconductor power module is in the first mode when the first semiconductor power module is shut off, and is in the second mode when the first semiconductor power module is conductive, and the fourth semiconductor power module is The first mode is set to the first mode at the time of cutoff, and the second mode is set to the second mode at the time of conduction. When the second semiconductor power module is cut off, the first semiconductor power module is also always cut off. 5. The power converter according to claim 4, wherein when the power module is shut off, the fourth semiconductor power module is always shut off. 6. Receiving a first input control signal input to the first semiconductor power module and a first abnormality detection signal output from the first semiconductor power module,
A first transmitting means for transmitting a second input setting signal to the second semiconductor power module in response to these signals; and a second abnormality detecting signal output from the second semiconductor power module for receiving A second transmitting means for transmitting a first input control signal to the first semiconductor power module;
Receiving the fourth input control signal input to the third semiconductor power module and the fourth abnormality detection signal output from the fourth semiconductor power module, and transmitting the fourth abnormality control signal to the third semiconductor power module in accordance with these signals. A third transmitting means for transmitting the third input setting signal, and a fourth input control to the fourth semiconductor power module by receiving a third abnormality detection signal output from the third semiconductor power module. The power converter according to claim 5, wherein the control unit includes a fourth transmission unit that transmits a signal. 7. When the first semiconductor power module is in a normal state and the first input control signal is on (signal state for conducting the semiconductor power module), the first transmitting means outputs A second input setting signal for setting the second mode is transmitted to the second semiconductor power module, and the second semiconductor power module set to the second mode transmits the second input signal to the second semiconductor power module.
The second transmission means turns off the first input control signal to be transmitted to the first semiconductor power module (signal state for shutting off the semiconductor power module) when the abnormality detection signal is output. And a second step of transmitting the second input setting signal for setting the first mode to the second semiconductor power module by the first transmitting means having received the first input control signal. According to the above procedure, the second semiconductor power module in which an abnormality is detected is set to the first mode and then shut off after the first semiconductor power module is shut off, and the fourth semiconductor power module is operated normally. And the fourth
When the input control signal is ON, the third transmitting means
Transmitting a third input setting signal for setting the third mode to the third semiconductor power module, and outputting the third abnormality detection signal when the third semiconductor power module set to the second mode outputs the third abnormality detection signal. A third procedure for turning off the fourth input control signal transmitted to the fourth semiconductor power module by the fourth transmitting means; and a third transmitting means for receiving the fourth input control signal. And a fourth step of transmitting a third input setting signal for setting the first mode to the third semiconductor power module. 7. The power converter according to claim 6, wherein after the power module is shut down, the power module is set to the first mode and shut down. 8. The power converter according to claim 7, wherein a delay circuit is provided in each of the first transmitting means and the third transmitting means.