JP2002359544A - Jitter-suppressing circuit, clock regenerating module, and switchboard - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a jitter-suppressing circuit, which has suppression effects even to jitter having components of a frequency both in the high region and in the region and has little phase ripples with respect to the change of ambient temperature, a clock regenerating module, and a switchboard. SOLUTION: In the jitter suppressing circuit which suppresses jitters of an input signal, using a BPF circuit which passes input signal frequency, a circuit where a plurality of BPFs different center frequencies are combined to flatten the phase properties in the vicinity of the input signal frequency is used for a BPF circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a jitter suppressing circuit for suppressing a jitter of an input signal, and more particularly to a jitter suppressing circuit for obtaining a stable internal clock signal in, for example, an exchange including various transmission devices, and using the same. Clock recovery module.

[0002]

2. Description of the Related Art An exchange or the like has a complex bipolar synchronization signal (for example, 64 KHz + 8 KHz-40) sent from a clock supply module (hereinafter referred to as "CSM").
(0 Hz) and operates in synchronization within the device. Each device converts a synchronization signal transmitted from the CSM into a unipolar signal in the device, raises the frequency by using a PLL (phase locked loop) or the like, and uses the frequency as a clock in the device. However, when the cable between the CSM and the device becomes longer and the load capacity increases, the waveform of the synchronization signal from the CSM deteriorates, and jitter occurs at the time of conversion into a unipolar signal. If the jitter is large, the reliability of data transmission is greatly reduced, and in the worst case, transmission becomes impossible. Therefore, it is necessary to suppress the jitter.

Conventionally, as a circuit for suppressing the jitter of such a clock signal, there have been a circuit using a PLL and a circuit using a band-pass filter (hereinafter, referred to as “BPF”).
FIG. 8 is a block diagram of a conventional jitter suppression circuit using a PLL. In the figure, reference numeral 1 denotes a PLL-based jitter suppression circuit, which includes a phase comparator 2, a low-pass filter (hereinafter, referred to as "LPF") 3, a voltage-controlled oscillator or a voltage-controlled crystal oscillator (hereinafter, referred to as "VCO"). 4 and a frequency divider 5. Input clock signal c
Is input to the phase comparator 2 and compared with a signal obtained by dividing the output of the VCO 4 by the frequency divider 5. The output of phase comparison 2 is
The high-frequency component is suppressed by the LPF 3, and the signal
CO4 is controlled. As a result, the output of the VCO 4 is synchronized with the input clock signal c, becomes a signal of a frequency multiplied by the frequency division ratio specified by the frequency divider 5, and this is a reference clock f.
Is output as Here, when the input clock signal c includes jitter having a high frequency component,
The reference clock f, which is attenuated by the LPF 3 and in which jitter is suppressed, is obtained. As described above, the PLL circuit itself has an operation of suppressing a high-frequency jitter component.

FIG. 9 is a block diagram of a conventional jitter suppression circuit using a BPF. In the figure, reference numeral 6 denotes a jitter suppression circuit using a BPF.
And a PLL circuit 9 connected in series.
In the BPF 7, the center frequency f ₀ of the pass band is tuned to an input clock signal frequency of 64 KHz. PL
As the L circuit 9, a circuit equivalent to the above-described PLL circuit 1 is used. The input clock signal c is applied to the BPF 7,
Even if the input signal contains jitter of high or low frequency components, the sine wave signal d with the jitter component attenuated by the BPF 7 is obtained. The sine wave signal d is converted into a rectangular wave signal e by the inverter circuit 8, and the rectangular wave signal e is input to the PLL circuit 9 to obtain a jitter-suppressed reference clock f.

[0005]

However, such a conventional jitter suppression circuit has the following problems. That is, in a circuit using a PLL, jitter having high frequency components can be suppressed by the LPF in the PLL circuit, but jitter having low frequency components cannot be suppressed. In addition, in a circuit using a BPF, it is possible to suppress jitter including a frequency component in either the high band or the low band. However, since the capacitor and the resistor constituting the BPF have temperature characteristics, the BPF is changed due to a change in ambient temperature. And the phase of the output clock signal fluctuates. Generally, the gain characteristics and phase characteristics of a BPF have frequency characteristics as shown in FIG. 10, but when the ambient temperature changes, the center frequency f ₀ moves to the left and right. In particular, since the phase characteristic shows a sharp change near the center frequency f ₀ , the phase of the output clock signal changes greatly when the ambient temperature changes.

SUMMARY OF THE INVENTION Therefore, a main object of the present invention is to provide a jitter suppressing circuit which has a suppressing effect on jitter having both high and low frequency components and has a small phase fluctuation with respect to a change in ambient temperature. , A clock recovery module and a switch.

[0007]

SUMMARY OF THE INVENTION A jitter suppressing circuit according to the present invention is a jitter suppressing circuit for suppressing jitter of an input signal using a BPF circuit passing an input signal frequency.
A PF circuit combines a plurality of BPFs having different center frequencies,
This is a flattened phase characteristic near the input signal frequency.

Further, the jitter suppression circuit of the present invention has a BP
An F circuit is obtained by connecting a plurality of BPFs having different center frequencies in series.

A clock recovery module according to the present invention comprises a B / U converter for converting a bipolar signal input into a unipolar signal, a BPF circuit connected to an output of the B / U converter and passing an input clock signal frequency, and a BPF. And a PLL circuit for generating a clock signal of a predetermined frequency based on a signal passed through the circuit. Is flattened.

In the clock recovery module according to the present invention, the BPF circuit includes a plurality of BPFs having different center frequencies connected in series.

An exchange according to the present invention includes the clock recovery module according to the present invention to suppress jitter.

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments of the present invention with reference to the accompanying drawings.

[0013]

FIG. 1 is a block diagram showing a jitter suppression circuit according to an embodiment of the present invention. FIG. 2 shows a detailed view of the BPF circuit portion. In the figure, reference numeral 10 denotes a jitter suppression circuit according to the present embodiment, which is configured by a circuit in which a BPF circuit 12, an inverter circuit 14, and a PLL circuit 16 are connected in series.

Hereinafter, the input clock signal frequency is 64 KH
The operation will be described taking z as an example. The input clock signal c has an input clock signal frequency of 64 KH
The sine wave signal d is input to the BPF circuit 12 passing near z, where the jitter component having high and low frequency components is attenuated. This sine wave signal d is converted by the inverter circuit 14 into a rectangular wave signal e. The rectangular wave signal e is input to the PLL circuit 16 to obtain a reference clock f in which jitter is suppressed. The inverter circuit 14 and the PLL circuit 16 can be equivalent to the conventional inverter circuit 8 and the conventional PLL circuit 9, respectively.

The BPF circuit 12 is an active filter using an operational amplifier as shown in FIG. 2, and has a center frequency of a pass band of 62 KHz and a Q of 100.
And the center frequency of the passband is 66 kHz and Q is 100 B
A PF2 connected in series and provided with a gain adjustment circuit for adjusting the output to a desired signal level is used.

FIG. 3 shows frequency characteristics of the BPF circuit 12 of the jitter suppression circuit according to the present embodiment. As shown in the figure, the BPF circuit 12 has a BPF 1 having a different center frequency.
And BPF2 are connected in series to obtain the desired 64
This is a signal that passes a KHz signal and has a flat phase characteristic around 64 KHz. In the present invention, since the BPF circuit having such characteristics is used, even if the center frequency of each BPF fluctuates due to a change in the ambient temperature, the phase change of the output signal d of the BPF circuit is suppressed to a small value. A reference clock signal f with little fluctuation is obtained.

The results of comparing the phase fluctuation due to the ambient temperature change between the jitter suppression circuit using the conventional BPF of FIG. 9 and the jitter suppression circuit according to the present embodiment are shown below. When the temperature characteristics of both the capacitor and the resistor are 50 ppm, in the temperature range of 0 ° C to 70 ° C,
While the conventional circuit fluctuates by a maximum of ± 300 μS, the circuit of the present embodiment improves the fluctuation to a maximum of ± 15 nS.

The results of comparing the jitter suppressing performance of the conventional PLL circuit shown in FIG. 8 with the jitter suppressing circuit of the present embodiment are shown below. FIG. 4 is a comparison table showing actual measured values of the output signal jitter when the input signal jitter is changed, and FIG. 5 is a plot of the output signal jitter versus the input signal jitter as a characteristic diagram. As shown in the figure, when the input jitter was 200 nS, the output jitter was about 70 nS in the conventional circuit, but was about 15 nS in the circuit of the present embodiment, and a performance improvement of about 5 times was achieved. I have.

In the above-described embodiment, a case has been described in which two BPFs having different center frequencies are connected in series as the BPF circuit. However, the present invention is not limited to this. Even if two or more BPFs are combined, the same effect can be obtained as long as the signal passes the frequency of the input clock signal and the phase characteristic becomes flat near the frequency.

In the above embodiment, the case where the input clock signal is 64 KHz has been described. However, the present invention is not limited to this case. The same effect can be achieved.

FIG. 6 is a block diagram of a clock recovery module according to an embodiment of the present invention. In the figure, reference numeral 20 denotes a clock recovery module according to the present embodiment, which includes an input pulse transformer 22, a B / U converter 24, a 64 kHz clock extraction circuit 26, a BPF circuit 32, a PLL circuit 34, A delay circuit 36,
Frequency dividing circuit 38, tuning circuit 40, U / B converter 42
And the output pulse transformer 44 as main components.

The input signal of the clock recovery module 20 is a composite bipolar signal of 64 KHz + 8 KHz-400 Hz from the CSM. The input signal is converted to a unipolar signal by a B / U converter 24 via a pulse transformer 22 and a 64 KHz clock extraction circuit 26, 8 KHz
It is input to the violation detection circuit 28 and the 400 Hz detection circuit 30. 64 KHz clock extraction circuit 26
Is extracted by the BPF circuit 32 for jitter suppression.
Is input to Here, since each signal is synchronized with reference to the signal of 64 KHz, the BPF circuit 12 used in the above-described jitter suppression circuit 10 is used as the BPF circuit 32.

The signal whose jitter has been suppressed is supplied to the PLL circuit 3.
4, a high-frequency clock signal is generated, and a leading / lagging circuit 3
6 and synchronized with the input signal by the frequency dividing circuit 38.
The frequency is divided into a 4 KHz clock signal. This frequency dividing circuit 38
8 KHz synchronized with the 64 KHz signal by the tuning circuit 40 from the output signal of
A signal and a 400 Hz signal are generated. Then, based on these signals, the 64K synchronized with the U / B converter 42 is used.
A composite bipolar signal of (Hz + 8 KHz−400 Hz) is synthesized and output via the output pulse transformer 44.

In addition, a 64 kHz clock extraction circuit 26
A 64 KHz disconnection detection circuit 45 which detects a disconnection of a 64 KHz signal based on a signal from the microcomputer and outputs an alarm signal, and an 8 KHz signal and 400 H based on a signal from the tuning circuit 40.
An 8 KHz disconnection detection circuit 46 for detecting each disconnection of the z signal and outputting an alarm signal, and a 400 Hz disconnection detection circuit 47
Is provided.

As described above, after the extraction of the clock signal of 64 KHz, the BPF circuit 1 of the above-described jitter suppression circuit 10
The use of No. 2 has a suppression effect even if the clock from the CSM contains a jitter having any of the high frequency component and the low frequency component, and has a stable phase with little phase change with respect to a change in the ambient temperature. The clock signal can be reproduced.

In the above embodiment, 64 KHz + 8 KH
The description has been given of the clock recovery module for the z-400 Hz composite bipolar signal. However, the present invention is not limited to this. Needless to say, the same effect is achieved.

FIG. 7 is a diagram showing a system configuration in an office including an exchange according to an embodiment of the present invention. In the figure, a station company 50 includes a backbone transmission device 52 and a CSM 54.
And a plurality of exchanges 56.

The exchange 56 has a clock recovery unit 60,
A PLL circuit section 62 and an internal clock distribution section 64 are provided. The clock reproducing unit 60 receives a signal from the clock supply module 54 or a clock signal reproduced by a higher-level switch, and reproduces a clock signal synchronized with the signal. The PLL circuit unit 62 receives a signal from the clock reproducing unit 60 and generates a signal of a required frequency in synchronization with the signal. The in-device clock distribution unit 64 receives a signal from the PLL circuit 62 and distributes a necessary clock in the device.
The clock reproducing unit 60 includes a plurality of Bs having different center frequencies.
BP with phase characteristics flattened in the pass band by combining PF
A clock recovery module having an F circuit is used.

With this arrangement, even if the clock signal from the CSM contains jitter having any of the high-frequency component and the low-frequency component due to the long-distance wiring routing in the office, the signal has the effect of suppressing the noise. Since a stable clock signal having a small phase change with respect to a change in temperature is reproduced, highly reliable transmission is enabled.

In the above embodiment, a plurality of exchanges are connected to the CS
Although the case where the switch is connected in series to M is shown, the present invention is not limited to this, and the switch may be connected in parallel to the CSM.

In the above embodiment, the case where the exchange provided with the clock recovery module of the present invention is used as the exchange in the system in the office is explained.
The present invention is not limited to this, and the same effect can be obtained by providing the clock recovery module of the present invention in any exchange including a transmission device used in the information transmission process.

[0032]

As described above, the jitter suppression circuit of the present invention combines a plurality of BPFs having different center frequencies and flattens the phase characteristics near the input signal frequency. It has an effect of suppressing a jitter having a component, and has a small phase fluctuation with respect to a change in an ambient temperature.

The clock recovery module according to the present invention uses a BPF circuit in which a plurality of BPFs having different center frequencies are combined and a phase characteristic near the input signal frequency is flattened. Even if jitter having any frequency component in the low frequency range is included, there is an effect that it has a suppression effect and can reproduce a stable clock signal with little phase change with respect to a change in ambient temperature.

Further, in the exchange according to the present invention, a plurality of BPFs having different center frequencies are combined with the BPF circuit of the clock recovery unit to flatten the phase characteristics near the input signal frequency. Has a suppression effect even if jitter having any frequency component is included,
In addition, there is an effect that a stable clock signal having a small phase change with respect to a change in the ambient temperature is reproduced, thereby enabling highly reliable transmission.

[Brief description of the drawings]

FIG. 1 is a block diagram of a jitter suppression circuit according to an embodiment of the present invention.

FIG. 2 is a detailed diagram of a BPF circuit portion of the jitter suppression circuit according to one embodiment of the present invention.

FIG. 3 is a frequency characteristic of a BPF circuit portion of the jitter suppression circuit according to one embodiment of the present invention.

FIG. 4 is a comparison table of actual measurement values of output signal jitter with respect to input signal jitter.

FIG. 5 is a graph showing output signal jitter characteristics with respect to input signal jitter.

FIG. 6 is a block diagram of a clock recovery module according to an embodiment of the present invention.

FIG. 7 is a system configuration diagram in a bureau including an exchange according to an embodiment of the present invention;

FIG. 8 is a block diagram of a conventional jitter suppression circuit using a PLL.

FIG. 9 is a block diagram of a conventional jitter suppression circuit using a BPF.

FIG. 10 shows gain characteristics and phase characteristics of a general BPF.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Jitter suppression circuit 12 BPF circuit 14 Inverter circuit 16 PLL circuit 20 Clock regeneration module 24 B / U converter 26 64 kHz clock extraction circuit 32 BPF circuit 34 PLL circuit 50 Station company 52 Backbone transmission device 54 Clock supply module 56 Switch 60 Clock regeneration Unit 62 PLL circuit unit 64 Clock distribution unit in the device

Claims (5)

[Claims] 1. A jitter suppression circuit that suppresses jitter of an input signal using a bandpass filter circuit that passes an input signal frequency, wherein the bandpass filter circuit combines a plurality of bandpass filters having different center frequencies. A jitter suppression circuit characterized in that a phase characteristic near a frequency is flattened. 2. The jitter suppression circuit according to claim 1, wherein said band-pass filter circuit comprises a plurality of band-pass filters having different center frequencies connected in series. 3. A B / U converter for converting a bipolar signal input into a unipolar signal, a bandpass filter circuit connected to an output of the B / U converter and passing an input clock signal frequency, and the bandpass filter. A PLL circuit for generating a clock signal of a predetermined frequency based on a signal passed through the circuit, wherein the band-pass filter circuit combines a plurality of band-pass filters having different center frequencies, and outputs a signal near the input signal frequency. A clock recovery module characterized by flattening the phase characteristics of the clock recovery module. 4. The clock recovery module according to claim 3, wherein said band-pass filter circuit comprises a plurality of band-pass filters having different center frequencies connected in series. 5. An exchange comprising the clock recovery module according to claim 3.