JP2002354828A - Pwm control unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that an element capable of operation in a frequency region of several times a carrier frequency is selected, as a switching element to be used in a PWM control unit wherein a voltage command value is updated asynchronously to a carrier frequency, however when a load is large, it is uneconomical to select an element of large capacity, and the upper limit of the capacity of the element exerts large influence on the upper limit of the load of a PWM control unit. SOLUTION: PWM control circuits 71, 72 and 73 are installed which control compared results from comparators 61, 62 and 63 by using a start clock 3 and a mountain and valley signal 42 of a carrier generating circuit 2. When the mountain and valley signal 42 is inputted, comparator outputs are monitored. Only when the outputs are different from the PWM control circuit outputs, the outputs are made equal to the comparator outputs synchronously to the start clock of the carrier generating circuit. When the PWM control circuit outputs are once updated, the outputs are not updated until the next mountain and valley signal is inputted, even if comparator outputs change again.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage-type PWM inverter for changing the speed of an AC motor or the like, and more particularly to a PWM control device used for an inverter using a high-speed switching element such as an IGBT.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a configuration of a conventional PWM control device. In FIG. 3, 1 is an arithmetic circuit, 2
Is a carrier generation circuit, 3 is a start clock of the carrier generation circuit, 41 is a carrier signal output from the carrier generation circuit, 51, 52 and 53 are U-phase voltage commands and V-phase voltage commands output from the arithmetic circuit. And W-phase voltage command,
61, 62 and 63 are phase-by-phase comparators for comparing the voltage signals 51, 52 and 53 for each phase output from the arithmetic circuit with the carrier signal, and 81a and 81b are the comparators 6 and 7.
IGBT not shown with U-phase PWM signal output by 1
U-phase positive signals PU and U
A phase negative signal NU is output. Reference numerals 82a and 82b are V-phase PWM signals output from the comparator 62 and are connected to a base driver (not shown) of an IGBT to output a V-phase positive signal PV and a V-phase negative signal NV. 83a and 83
b denotes a W-phase PWM signal output from the comparison circuit 63, which is connected to a base driver of an IGBT (not shown) to output a W-phase positive signal PW and a W-phase negative signal NW. The operation of the conventional PWM control device will be described. PW
In order to generate the M waveform, first, the count operation is performed with the start clock 3 of the carrier generation circuit 2. Then, the U-phase voltage command value 51 and the V-phase voltage command value 5
2. The W-phase voltage command value 53 is output. The carrier output is compared with the voltage command value of each phase. When the voltage command value exceeds the carrier output 41, each comparator becomes “H” and falls below “H”. In this case, it becomes "L". For example, the output of the U-phase comparator is divided into a positive signal and a negative signal, and is connected to a base driver of an IGBT (not shown).
Generate GBT drive signals U and / U. Note that V
Since the same applies to the phase and the W phase, the description of the operation is omitted.

[0003]

However, in the above-mentioned conventional PWM control device, the arithmetic circuit may output a voltage command value near the carrier output value. FIG. 4 shows the comparator output when the voltage command value is updated immediately after the carrier output and the voltage command value cross. After the voltage command value once drops while the carrier is rising, if a voltage command value larger than the carrier output is input, the comparator output outputs a pulse signal immediately after the voltage command value is updated. Also,
If a voltage command value smaller than the carrier output is input after the voltage command value once exceeds while the carrier is descending, a pulse signal is output immediately after the voltage command value is updated.
As described above, as the switching element used in the PWM control apparatus in which the voltage command value is updated asynchronously with the carrier cycle, an element that can operate in a frequency region several times the carrier frequency has been selected. However, when the load is increased, it is uneconomical to select an element having a large capacity, and the upper limit of the element capacity greatly affects the upper limit of the load of the PWM control device. In addition, when an element having a large capacity is not used, the carrier frequency becomes lower, and there is a problem of noise. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems, and to provide a PWM control device capable of responding to a larger capacity and corresponding to a wide range of inverter applications while keeping the switching element capacity of the PWM control device unchanged. .

[0004]

To achieve this object, the present invention provides an arithmetic circuit for calculating a voltage command value at a certain cycle, a carrier generating circuit for generating a carrier signal at the certain cycle, U, V, and W phase comparators for comparing the U, V, and W phase voltage command values output from the arithmetic circuit with the carrier signal, and outputs of these phase comparators. In the PWM control apparatus for an inverter, wherein the positive and negative polarity signals obtained for each of the U, V, and W phases are used as drive signals for the switching elements of the U, V, and W phases. A PWM control circuit for controlling an output from each of the phase comparators according to a start clock and a peak-and-valley signal generated at the top and bottom points of the carrier signal, wherein the PWM control circuit comprises:
When the peak and valley signal is input, the output of each phase comparator is monitored. Only when the output of each phase comparator is different from the output of the PWM control circuit, the PWM is synchronized with the start clock.
M control circuit output to the same value as the output of each phase comparator,
Once the output of the PWM control circuit is updated, even if the output of each phase comparator changes again, the output of the PWM control circuit is not updated until the next peak / valley signal is input.

[0005]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a PWM control device according to an embodiment of the present invention. In FIG. 1, 1 is an arithmetic circuit, 2 is a carrier generation circuit, 3 is a start clock of the carrier generation circuit, 41 is a carrier output of the carrier generation circuit, and 42 is a case where the carrier output becomes zero or an upper limit value. Peak and valley signals 51, 52 and 53 output in synchronization with the start-up clock 3 are U-phase, V-phase and W-phase voltage command values periodically calculated by the arithmetic circuit. "H" is output when the carrier output value exceeds the voltage command value, and "L" is output when the carrier output value is lower than the voltage command value, or "L" is output and lower when the carrier output value exceeds the voltage command value. U-phase, V-phase, and W-phase comparators that output "H"; 71 and 73 are PWM control circuits to which the valley signal 42, the comparator output, and the start-up clock are input;
A base circuit 81a and 81b are connected to a base driver of an IGBT (not shown) to output signals of the U-phase PWM control circuit and output U-phase and / U-phase signals.
2a and 82b are base circuits for connecting the signal output from the U-phase PWM control circuit to an IGBT base driver (not shown) to output V-phase and / V-phase signals;
Each of a and 83b is characterized in that a base circuit for connecting a signal output from the W-phase PWM control circuit to an IGBT base driver (not shown) and outputting W-phase and / W-phase signals is provided. FIG. 2 is a diagram showing one embodiment of the PWM control circuit and signal waveforms of various parts. In the PWM control circuit, 201 is an EXOR circuit, 202 is an AND circuit,
203 is an OR circuit, and 204 and 205 are flip-flop circuits. Reference numeral 206 denotes a NOT circuit. The input / output signals of the flip-flop circuits 204 and 205 are as shown in FIG. The operation of the thus configured PWM control device will be described. First, the carrier generation circuit 2 is operated by the start clock 3. Each time the arithmetic unit 1 calculates the voltage command value of each phase, the comparator compares the carrier output value with the voltage command value. The comparison operation outputs “H” when the carrier output value exceeds the voltage command value and outputs “L” when the carrier output value falls below the voltage command value, or outputs “L” when the carrier output value exceeds the voltage command value. If it is lower than the output, "H" is output from the comparator. Next, the PWM control circuit fetches the comparator output for each one of the edges of the start clock.
The captured data retains its output when it is the same as the output of the PWM control circuit, and only when it is different, the comparison output at the first occurrence after the input of the valley signal is used as the output of the PWM control circuit. . Subsequently, even if the fetched data and the PWM control circuit output are different, the PWM control circuit output is held until the next valley signal is input. Further, the output of the PWM control circuit is divided into a positive polarity signal and a negative polarity signal for each phase, and connected to a base driver of an IGBT (not shown), U phase, / U phase, V phase, / V phase, W phase.
Phase, / W phase drive signal. As described above, the signal output from the comparator is once captured by the starting clock, and the output of the PWM control circuit performs one switching based on the section divided by the valley signal, so that the number of times of switching becomes larger than the carrier frequency. However, a switching element having switching characteristics equivalent to the carrier frequency can be used. In addition, the conventional PW
If only the PWM control unit is replaced with the PWM control device of the present invention using the same switching element as that selected in the design guideline of the M control circuit, more than twice the margin for switching loss can be obtained in the circuit design, and a wide range can be obtained. A PWM waveform that can be used for an inverter can be generated.

[0006]

As described above, the PWM control apparatus of the present invention updates the PWM control circuit output to the same value as the comparator output when the PWM control circuit output and the comparator output are different data, and temporarily executes the PWM control. When the circuit output is updated, the comparator output becomes PW only after the next peak / valley signal is input.
Even if the output is different from the M control circuit output, it is not updated to the PWM control output, so that the switching period does not exceed the carrier period. Therefore, the conventional carrier asynchronous PWM
It is possible to select a switching element having a smaller allowable switching loss value than the control device. In addition, since switching is performed reliably in a frequency range lower than the carrier cycle, the life of the switching element can be expected to be extended. Further, even if the circuit is replaced with a conventional circuit, the switching loss is designed to have a margin of twice or more and can be applied to the conventional PWM control apparatus. Therefore, it is possible to provide a PWM control apparatus applicable to a wide range of inverter applications.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a PWM control device according to the present invention.

FIG. 2 is a diagram showing one embodiment of a PWM control circuit and signal waveforms of various parts.

FIG. 3 is a block diagram illustrating a configuration of a PWM control device.

FIG. 4 is a diagram showing an operation of the PWM control device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 arithmetic circuit 2 carrier generation circuit 3 start-up clock 41 carrier generation circuit output 42 valley signal 51 U-phase voltage command value 52 V-phase voltage command value 53 W-phase voltage command value 61 U-phase comparator 61 a U-phase comparator output 62 V-phase Comparator 62a U-phase comparator output 63 W-phase comparator 63a U-phase comparator output 71 U-phase control circuit 72 V-phase control circuit 73 W-phase control circuit 80a U-phase PWM control circuit output 80b V-phase PWM control circuit output 80c W Phase PWM control circuit output 81a U-phase positive signal driver 81b U-phase negative signal driver 82a V-phase positive signal driver 82b V-phase negative signal driver 83a W-phase positive signal driver 83b W-phase negative signal driver 201 EXOR circuit 202 AND circuit 203 OR circuit 204 Flip flop 205 Flip flow 206 NOT circuit

Claims (2)

[Claims] 1. An arithmetic circuit for calculating a voltage command value at a certain cycle, a carrier generating circuit for generating a carrier signal at the certain cycle, and each of U, V, and W phases output from the arithmetic circuit U, V, and W phase comparators for comparing a voltage command value and the carrier signal, respectively, and positive electrodes for each of the U, V, and W phases obtained based on the outputs of these phase comparators And a PWM signal for an inverter using the negative polarity signal as a drive signal for the switching element of each of the U, V, and W phases, a start clock of the carrier generation circuit and a valley signal generated at the top and bottom points of the carrier signal. And a PWM control circuit for controlling an output from each of the phase comparators. 2. The PWM control circuit monitors the output of each of the phase comparators when the peak and valley signals are input, and only when the output of each of the phase comparators is different from the output of the PWM control circuit, the start-up is performed. The output of the PWM control circuit is set to the same value as the output of each phase comparator in synchronization with a clock, and once the output of the PWM control circuit is updated, even if the output of each phase comparator changes again, PWM until the signal is input
2. The PWM control device according to claim 1, wherein the control circuit output is not updated.