JP2002350505A - Semiconductor integrated circuit device and inspection method therefor - Google Patents

Abstract

(57) [Problem] In a conventional test circuit of a scan path system, since a multiplexer is provided in a stage preceding a flip-flop circuit, a signal transmission time in a normal operation becomes longer, and a multiplexer is used for a NAND circuit. Since it is configured by a logic gate circuit such as a gate or a NOR gate, there is a problem that the amount of hardware is increased, resulting in an increase in chip size and cost. A switching element is provided between a plurality of combinational logic circuits and serially connects a plurality of flip-flop circuits capable of latching a signal output from the combinational logic circuit to constitute a diagnostic shift register. At the time of normal operation of the flip-flop circuit, the combinational logic circuit which is the preceding circuit is provided with output high impedance means for making its output high impedance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diagnostic technique for a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a logic integrated circuit having a built-in scan path type test circuit.

[0002]

2. Description of the Related Art As a test method of a semiconductor integrated circuit device such as a logic integrated circuit (hereinafter referred to as a logic LSI),
There is a method in which test pattern data is generated by a device called a tester, input to a logic LSI, and a data signal output from the logic LSI is compared with an expected value to make a determination.
However, in a logic LSI, as the scale of the logic increases, the number of steps in the test pattern increases, and the time required to create the test pattern and to perform a test using the test pattern increases.

Therefore, as a method of facilitating a test by a tester, a flip-flop circuit constituting an original function of a logic LSI is connected in series to design a shift register so as to be configurable. A test pattern is serially input (scanned-in) to the shift register to be fetched, the test data fetched into the shift register is input to a desired combinational logic circuit to perform a logical operation, and then an output data signal of the combinational logic circuit is outputted. A so-called scan path design technique for facilitating test has been developed and put into practical use so that the data can be taken into a flip-flop circuit constituting a shift register and shifted through a scan path to be taken out (scan out).

In a test circuit of the scan path system, a flip-flop circuit having an original function is connected in series to make a shift register possible. A multiplexer is generally used which inputs a signal from a combinational logic circuit at a preceding stage to a flip-flop circuit during normal operation.

[0005]

However, if a multiplexer is provided in the preceding stage of the flip-flop circuit as described above, an original signal during normal operation is input to the flip-flop circuit after passing through the multiplexer. Therefore, there is a problem that the signal transmission time becomes long. Conventionally, since a scan-path type multiplexer is configured by a logic gate circuit such as a NAND gate or a NOR gate, an increase in hardware accompanying the incorporation of a scan-path type test function into a logic LSI is limited. There is a problem that it reaches nearly 30%, resulting in an increase in chip size and cost.

Therefore, the inventors of the present invention used an analog switch composed of a MOSFET or the like instead of a multiplexer to connect each flip-flop circuit in series in order to form a scan path by connecting flip-flop circuits in series. Thought to connect to. However, if you use analog switches instead of multiplexers,
At the time of testing, it is necessary to consider that the signal from the combinational logic circuit at the preceding stage does not affect the test signal transmitted through the scan path.

As a means for solving such a problem, it is effective to adopt a configuration in which the output stage of the combinational logic circuit can take output high impedance. However, there is no problem as long as the combinational logic circuit can originally take the output high impedance, but if an output stage of the combinational logic circuit that does not have such a configuration is provided with a tri-state buffer or the like so as to take the output high impedance, it would be troublesome. Even if the multiplexer is omitted to reduce the circuit scale and prevent signal transmission delay, the hardware is increased to enable the output of the combinational logic circuit to have high impedance, and the signal delay also occurs, and the original purpose is increased. It became clear that we could not achieve.

Japanese Patent Application Laid-Open No. Hei 10-246755 discloses, for example, Japanese Patent Application Laid-Open No. Hei 10-246755, which discloses that the output of a circuit block that provides the original function of a logic LSI during a test is set to a high impedance state. However, this prior invention does not use a flip-flop circuit originally provided in a logic LSI to form a scan path, but instead uses a bidirectional input / output terminal of a first circuit block and a second circuit block. A scan flip-flop circuit is connected to a signal line connecting the bidirectional input / output terminal, so that test data can be directly input. In that case, in order to prevent the input of the test data from being disturbed by the signal from the bidirectional input / output terminal of another circuit block, the bidirectional input / output terminal of the circuit block to which the test data is not input is set high. This is to bring the impedance state, not to omit the multiplexer. Actually, in the prior invention, a multiplexer is used on one side while the bidirectional input / output terminal of the circuit block is set to a high impedance state.

An object of the present invention is to provide a diagnostic technique for a logic integrated circuit that enables a scan path test while suppressing an increase in signal transmission time and an increase in hardware.

Another object of the present invention is to provide a diagnostic technique capable of diagnosing a logic integrated circuit using a simple tester and thereby reducing the cost required for testing.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

The outline of a typical invention among the inventions disclosed in the present application is as follows. That is, the combination circuit includes a combinational logic circuit and a first circuit that enables a serial scan test for the combinational logic circuit. The first circuit includes a plurality of circuits each capable of transmitting a signal from an input to an output. Flip-flop circuit, a plurality of switch elements, a combinational logic circuit coupled to the plurality of flip-flop circuits, and a high-impedance means for causing a plurality of input nodes to which inputs of the flip-flop circuit are coupled to have a high impedance Wherein the signals of the plurality of input nodes are set in parallel by the plurality of flip-flop circuits.
An operating state and a second operating state in which the plurality of flip-flop circuits are connected in series by the switch element to constitute a diagnostic shift register, and wherein the high-impedance generating means is provided in the second operating state. This causes the plurality of input nodes to have high impedance.

According to the above-described means, it is possible to prevent a signal from the preceding combinational logic circuit from being input to the flip-flop circuit during the scan test, so that the switch element is provided on the scan path including the diagnostic shift register. It is not necessary to provide a multiplexer for switching between the signal path at the time of normal operation and the signal path at the time of the scan test. Therefore, the number of elements and the signal transmission time during the normal operation can be increased. It is possible to configure a test circuit of a scan path type without any.

Here, the output high impedance means includes a tristate buffer provided at an output portion of the combinational logic circuit serving as the preceding circuit, an output terminal of the combinational logic circuit serving as the preceding circuit, and the output terminal. A switch element or the like connected between the input terminal of the flip-flop circuit that receives the above signal and the like is conceivable. Although a diode or a bipolar transistor can be used as the switch element, it is preferable to use a MOS transistor. By using a MOS transistor as a switch element, a resistor is not required, and a scan path type test circuit can be incorporated into a semiconductor integrated circuit with a relatively small number of elements.

Further, the combinational logic circuit is composed of a plurality of circuits, the first circuit is provided between the combinational logic circuits, and the output high-impedance generating means is provided at a stage prior to supplying a signal to the plurality of input nodes. The output impedance of the combinational logic circuit, which is a circuit, can be made high in the second operation state.

A wiring for feeding back an output signal of one of the flip-flop circuits forming the diagnostic shift register to an input terminal of a flip-flop circuit which is a circuit preceding the shift register when the shift register is formed; An exclusive OR of a switch element provided in the middle of a wiring and a signal fed back by the wiring and an output signal of one of the flip-flop circuits in the middle stage constituting the diagnostic shift register is used for another flip-flop. A logic gate circuit that can be applied to an input terminal of the loop circuit. As a result, a test pattern generation circuit capable of automatically generating a test pattern can be configured by using a flip-flop circuit originally provided in a semiconductor integrated circuit, and a test can be executed by a simple tester. Become like

Further, a test input terminal for supplying a test signal from the outside to the diagnostic shift register constituted by the flip-flop circuit, and a data signal shifted by the diagnostic shift register to the outside. And a test output terminal for outputting.

According to another aspect of the present invention, there is provided a semiconductor having a plurality of combinational logic circuits and a plurality of flip-flop circuits provided between the combinational logic circuits and capable of latching signals output from the combinational logic circuits. In the integrated circuit device, a switch element that forms a diagnostic shift register by connecting the flip-flop circuits in series is provided, and a combinational logic that becomes a pre-stage circuit during normal operation of the flip-flop circuit that forms the diagnostic shift register is provided. The circuit is configured to be in an inactive state when the flip-flop circuit is activated to operate as a diagnostic shift register.

In this case, a signal from the preceding combinational logic circuit can be prevented from being input to the flip-flop circuit during the scan test. Therefore, a switch element is provided on the scan path including the diagnostic shift register. It is not necessary to provide a multiplexer for switching between the signal path during the normal operation and the signal path during the scan test, so that the number of elements and the signal transmission time during the normal operation do not increase. A scan circuit test circuit can be configured.

In the above case, when the flip-flop circuit is activated to operate as a diagnostic shift register, the combinational logic circuit serving as the preceding-stage circuit is inactivated. An external power supply voltage terminal for providing an operation power supply for the flip-flop circuit and an external power supply voltage terminal for providing an operation power supply for at least the combinational logic circuit serving as the preceding circuit are separately provided, and the flip-flop circuit operates as a diagnostic shift register. Therefore, it is desirable to shut off the power to the external power supply voltage terminal that supplies the operating power of the combinational logic circuit that is the pre-stage circuit when activated.
Thereby, without providing any elements in the internal circuit,
The combinational logic circuit can be deactivated when the flip-flop circuit is activated to operate as a diagnostic shift register, and a switch element is provided on a scan path including the diagnostic shift register. It is not necessary to provide a multiplexer for switching between the signal path during the normal operation and the signal path during the scan test.

Also in this case, a diode or a bipolar transistor can be used as the switch element, but it is preferable to use a MOS transistor. By using a MOS transistor as a switch element, a resistor is not required, and a scan path type test circuit can be incorporated into a semiconductor integrated circuit with a relatively small number of elements.

Further, another invention of the present application relates to a plurality of combinational logic circuits, a plurality of flip-flop circuits provided between these combinational logic circuits and capable of latching a signal output from the combinational logic circuit, A switching element that connects a flip-flop circuit in series to form a diagnostic shift register, and supplies an external power supply voltage terminal that supplies an operation power supply of the flip-flop circuit and an operation power supply of at least the combinational logic circuit that is the preceding circuit. In a test method of a semiconductor integrated circuit device provided with an external power supply voltage terminal separately, a diagnostic shift register is constructed by conducting the switch element in a state where the power supply voltage to the combinational logic circuit is cut off. A first operation of inputting data, and supplying a power supply voltage to the combinational logic circuit after inputting test data. The scan test of repeating a second operation to incorporate the output of the combinational logic circuit in the shift register, in which to perform also as a screening. As a result, it is not necessary to perform screening separately from the logic test by the scan test, and the test process and the time required for the test can be greatly reduced.

It is also possible to carry out the scan test at a temperature higher than room temperature. Thus, it is not necessary to perform a burn-in test or an aging test separately from a logic test by a scan test, and the test process and the time required for the test can be further reduced.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a logic L to which a first embodiment of a scan path type test circuit according to the present invention is applied.
1 shows a schematic configuration of an SI. In FIG. 1, LG1, LG
2 and LG3 are combinational logic circuits such as random logic which does not include a flip-flop circuit therein, and FF11 and F3.
FF1n are flip-flop circuits provided between the first combinational logic circuit LG1 and the second combinational logic circuit LG2, and FF21, FF22 ... FF2m are the second combinational logic circuit LG1 and the third combinational logic circuit LG3. Combinational logic circuit L
A flip-flop circuit provided between G2 and G2.
These flip-flop circuits are required to realize the function of the logic LSI. The TMC is a mode control circuit that determines that the test mode has been set based on signals supplied to the mode setting terminals P1 and P2 from outside the chip, and generates and outputs an internal control signal for a test operation. is there.

In the first embodiment, as shown in FIG. 1, flip-flop circuits FF11-FF
Switch elements SW11 and SW12 for chain-connecting the data output terminals and the data input terminals of F13 and FF21 to FF23 to form a shift register;
, And SW21, SW22, ... are provided.
Then, the flip-flop circuit FF11 corresponding to the first stage,
The data input terminal of the FF 21 is connected to the scan-in data input terminals SDi1 and SDi2. On the other hand, flip-flop circuits FF1n and FF2m to be the final stages
Is a scan-out data output terminal S.
Do1 and Do2. Switch element SW
As 11 to SW2m, for example, p-channel MOSFE
It is desirable to use a T or n-channel MOSFET or a transmission gate formed by connecting these in parallel.

Each of the flip-flop circuits FF11-FF11
The FFs 13 and FF21 to FF23 are configured to be operable by a scan clock signal SCK supplied to the test clock terminal Tck from outside the chip during a scan test. On the other hand, the switch element SW11,
, And SW21, SW22,... Are turned on during a scan test based on a control signal TS from the mode control circuit TMC. Then, the flip-flop circuits FF11 to FF13 and FF21 to FF23
Is configured to sequentially fetch test data input to the scan-in data input terminals SDi1 and SDi2 in synchronization with the scan clock signal SCK and shift the test data to the next flip-flop circuit.

Furthermore, in this embodiment, each combinational logic circuit LG1, LG2, LG3 and the power supply voltage terminal Vc
c and the power supply switches PSW11, PSW12; PSW21, PSW2
2: PSW31 and PSW32 are provided, and these power switches PSW11 to PSW32 are turned off during a scan test based on a control signal PF from the mode control circuit TMC. Thus, each of the combinational logic circuits LG1, LG2, and LG3 is configured to be in the output high impedance state while the flip-flop circuits FF11 to FF13 and FF21 to FF23 form a scan path and shift the test. ing.

The power switches PSW11-PSW
The SW 32 can be set to only one of the power supply voltage Vcc side and the ground potential side. Further, in FIG. 1, a power switch is provided for each combinational logic circuit. However, it is also possible to provide a common power supply switch for a plurality of combinational logic circuits. Further, FIG. 1 shows a case in which there are two scan paths. The output terminal of the last flip-flop circuit FF1n in the first column and the first flip-flop circuit FF21 in the second column are shown in FIG.
And a transmission switch may be provided in the middle of the wiring to connect between the input terminals to form one scan path, or three or more scan paths may be provided. is there.

FIG. 3 shows the timing of each signal at the time of a scan test using the scan path.
At the time of the scan test, a test mode is set from the mode setting terminals P1 and P2. As a result, the high-level test control signal TS is output from the mode control circuit MDC, and the switch elements SW11 to SW2m on the scan path are output.
Is turned on, and a low-level power control signal PF is output from the mode control circuit MDC, and the power switches PSW11 to PSW32 are turned off.

Thereafter, serial test data is input to the scan-in data input terminals SDi1 and SDi2 from outside the chip by a tester or the like, and a scan clock signal SCK is supplied. Then, inside the chip, the test data input to the scan-in data input terminals SDi1 and SDi2 are shifted one after another through the scan path, and the flip-flop circuits FF11 to FF
Predetermined test data is set in F13 and FF21 to FF23. At this time, the data output from the combinational logic circuits LG1 and LG2 and latched by the flip-flop circuit in the previous test operation is sequentially output from the scan-out data output terminals SDo1 and SDo2.

Next, the test control signal TS from the mode control circuit MDC changes to the low level, the switch elements SW11 to SW2m on the scan path are turned off, and the power supply control signal PF changes to the high level instead. The power switches PSW11 to PSW32 are turned on, the power supply voltage (Vcc) and the ground potential (GND) are supplied to each of the combinational logic circuits LG1, LG2, and LG3, and a logic operation is performed based on the data set in the flip-flop circuit. .

The output data of each of the combinational logic circuits LG1, LG2, LG3 formed by the logic operation is latched by the flip-flop circuits FF11 to FF2m. At this time, since the output signal from the combinational logic circuit LG3 at the final stage is output from the normal output terminal OUT, it can be observed by a tester. Thereafter, the switch elements SW11 to SW2m on the scan path are turned on again, and the power switches PSW11 to PSW3
2 is turned off, and the scanning clock signal SCK is turned off.
Is supplied, the latch data is sequentially shifted in synchronization with the clock signal, and the scan-out data output terminal SD
Output from o1 and SDp2 to the outside of the chip. At this time, the next test data can be input to the scan path from the scan-in data input terminals SDi1 and SDi2.

As described above, in this embodiment, the signal can be transmitted by turning on the switch on the scan path, and the delay time is reduced as compared with the case where the signal is transmitted via a multiplexer or a logic gate. can do. Further, since a scan path type test circuit can be configured only by providing one switch element at a stage preceding each flip-flop circuit on the scan path, hardware accompanying the incorporation of the scan test circuit into a chip is required. The increase in the amount and the increase in the chip size can be reduced.

The design data (gate-level connection information) that forms a scan path by chain-connecting flip-flop circuits using the switch elements described in the above-described embodiment is converted into a hardware IP (Intellectual PID).
A roperty) core may be registered in a database or the like, and used in the development of the next product or provided to the user for a fee. As a result, once completed design data can be reused as design resources, the development period of a new product can be shortened, and new business opportunities can be created.

FIG. 2 shows a schematic configuration of a logic LSI to which a second embodiment of the scan path type test circuit according to the present invention is applied. In the second embodiment, as in the first embodiment shown in FIG.
Considering the case where there is a circuit that does not enter the output high impedance state due to the charge of the floating internal node only by shutting off the power supply of G1, LG2, LG3, the output high impedance circuit HIP is provided for such a circuit. Is provided.

As shown in FIG. 4A, the output high impedance circuit HIP includes switch elements SW31, SW32,... Connected between the combinational logic circuit LG and the next flip-flop circuit. .., SWn, or a circuit provided with a tri-state buffer TBF as shown in FIG. These switch elements SW31 to SWn and the tristate buffer TBF can be controlled by a control signal PF generated at the same timing as the power supply control signal PF in the first embodiment. As described above, when the output high impedance circuit HIP is provided in each of the combinational logic circuits LG1, LG2, and LG3, the power switches PSW11 to PSW11 shown in FIG.
W32 is unnecessary.

Further, if a new tri-state buffer as shown in FIG. 4B is provided in the combinational logic circuit, the signal transmission is slowed down during normal operation. It is desirable to use switch elements SW31, SW32,... SWn as shown in A). However, some combinational logic circuits LG1 originally have a tri-state buffer at the output. Therefore, in such a part, a tri-state buffer that originally exists may be used to control the buffer during the scan test so that the output high impedance state is achieved.

Further, the combinational logic circuit to which the second embodiment is applied and the combinational logic circuit to which the first embodiment is applied may be mixed on one semiconductor chip.
Further, a switch element for output high impedance as shown in FIG. 4A and a tri-state buffer as shown in FIG. 4B are mixed on the output side of one combinational logic circuit. Can also be provided.

FIG. 5 shows a modification of the first embodiment shown in FIG. In the embodiment of FIG. 1, the combinational logic circuits include power switches PSW11 to PSW11 to PSW11.
The output of the combinational logic circuit is set to a high impedance state by providing a W32 and turning off a power switch during data shift by a scan path. On the other hand, in the modification of FIG. 5, the combinational logic circuits LG1, LG2,
The external power supply terminal and ground terminal for LG3 ... and the external power supply terminal and ground terminal for flip-flop circuit FF are connected to Vcc1, Vcc2 and GND1, GN.
D2 is provided separately, and power supply switches PSW1 and PSW2 are provided outside the chip at the power supply terminals Vcc1 and GND1 for the combinational logic circuit.
By turning off SW2, the combinational logic circuits LG1, LG
2, LG3... Can be brought into a high impedance state. Here, the power switches PSW1 and PSW2 are connected to the power supply voltage Vc.
It is also possible to use only one of the c1 side and the ground potential GND1 side.

FIG. 6 shows a switch element SW11 on the scan path used in the first and second embodiments.
An example in which a diode is used instead of the MOSFET as .about.SW2m will be described. Specifically, a diode Dj is connected between the data output terminal of the flip-flop circuit FFj and the data input terminal of the next-stage flip-flop circuit FFj + 1 so as to be in the forward direction from FFj to FFj + 1. Have been.

When a diode is used as a switch element for signal transmission as described above, when a ground-side MOSFET (not shown) at the last stage of the combinational logic circuit LGi is turned on during normal operation, the diodes Dj, Dj + 1,. , Through which the current flows from the output terminals of the flip-flop circuits FFj, FFj + 1,... To the final-stage ground-side MOSFET of the preceding combinational logic circuit LGi. Therefore, in order to prevent this current, resistors Rj, Rj + 1... Are connected in series with diodes Dj, Dj + 1.
Is connected.

When a diode is used as a switch element for signal transmission, the input level to the subsequent circuit cannot be sufficiently reduced when the output signal of the preceding circuit (flip-flop circuit FFj) is at a low level. Therefore, the combinational logic circuit LGi and the flip-flop circuit FF
j, FFj + 1... and signal transmission lines STLj, S
A pull-down resistor R is connected between TLj + 1 and the ground point GND.
dj are provided. Note that this pull-down resistor Rdj is particularly effective when the flip-flop circuit is formed of a bipolar transistor, and is desirably omitted when the flip-flop circuit is formed of a MOSFET.

As described above, in the above-described embodiment, the MOSFE is not used to switch the input to the flip-flop circuit without using a multiplexer as in the related art.
Since a T, a diode, and a resistor are used, an increase in the area of the circuit, that is, an increase in the chip size can be reduced when a scan path type test facilitating circuit is incorporated in a logic LSI.

More specifically, a flip-flop circuit provided with a multiplexer MUX on the input side includes two clocked inverters INV for switching between normal input data D and scan-in data Si as shown in FIG.
1, INV2 and an inverter INV3 for generating a reverse-phase signal of the switching control signal SEL.
However, when the above embodiment is applied, instead of the multiplexer MUX shown in FIG. 7, only one MOSFET or one diode and two resistors are added. Will be done.

FIG. 7 shows, as an example, the positive-phase output D including a master latch MLT and a slave latch SLT.
Although a type flip-flop circuit is shown, a flip-flop circuit S-FF with a set terminal or a flip-flop circuit R-FF with a reset terminal, and two outputs of normal phase (Q) and reverse phase (/ Q) are possible. The same applies to the case where another type of flip-flop circuit such as a flip-flop circuit is used.

FIG. 8 shows a third embodiment of the present invention.
In this embodiment, a test pattern generation function is added to the scan path type test circuit of the first embodiment. 8, the same circuits as those in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.

In the third embodiment, in addition to the switch elements SW11 to SW1n for chain coupling between flip-flop circuits FF11 to FF1n provided between the combinational logic circuits LG1 and LG2, A line Lfd for feeding back the output signal of the flip-flop circuit FF1n to the data input terminal of the first flip-flop circuit FF11 is provided, and a switch element SW4 is provided in the middle of the feedback line Lfd.
1 and SW42 are provided. Although not particularly limited, a switch element SW20 that connects the first scan path and the second scan path to form one scan path is also provided.

In this embodiment, EO is set between predetermined flip-flop circuits (FF11 and FF2 in FIG. 8) among the flip-flop circuits FF11 to FF1n.
An R (exclusive or) gate G10 is provided,
One input terminal of the E-OR gate G10 receives the output signal of the preceding flip-flop circuit (FF11) and the E-OR gate G10.
The last flip-flop circuit FF1 is connected to the other input terminal of the OR gate G10 via the feedback line Lfd.
n output signals can be input. Furthermore, E
A switch element SW43 for fixing the input potential is provided at the other input terminal of the OR gate G10. Note that the connection position of the E-OR gate G10 is not limited to the position between the first and second flip-flop circuits, but may be between other flip-flop circuits such as the second and third stages. .

Table 1 shows that each of the switch elements SW11 to SW11
The relationship between the on / off state of SW2m, SW20; SW41, SW42; SW43 and the operation mode of the LSI is shown.

[0050]

[Table 1]

Hereinafter, the operation of the test circuit according to this embodiment will be described with reference to Table 1. As shown in Table 1, during normal operation, the switch elements SW11 to SW2
m, SW20; SW41, SW42 are turned off. The switch element SW43 may be on or off. As a result, the signal output from the preceding combination logic circuit LG1 is supplied to the next combination logic circuit LG2 via the flip-flop circuits FF11 to FF1n, and the signal output from the combination logic circuit LG2 is output from the flip-flop circuits FF21 to FF21. The signal is supplied to a combinational logic circuit (not shown) at the next stage via the FF 2m.

At this time, since the switch elements SW11 to SW2m on the scan path are off, the outputs of the flip-flop circuits FF11 to FF1n are not input to the next-stage flip-flop circuit and the feedback wiring Lfd Upper switch elements SW41, SW
42 is also off, so that the output signal of the last flip-flop circuit FF1n is
There is no feedback to the data input terminal of F11. Further, even if the output of the E-OR gate G10 is undefined due to the on / off state of the switch element SW43, the effect on the flip-flop circuit FF12 is cut off because the switch element SW11 is off. . As a result, the logic LSI performs the original logic operation. The E-OR during normal operation
In order to prevent useless operation of the gate G10, the power switches PSW11 to PSW11 according to the first embodiment are connected to the gate G10.
A power switch similar to the SW 32 may be provided to shut off the power of the E-OR gate G10 during normal operation.

Next, at the time of the scan test, as shown in Table 1, the switch elements SW11 to SW2m and SW20 are turned on, and the switch elements SW41 and SW4 are turned on.
2 is turned off, and the switch element SW43 is turned on. Here, when the switch element SW43 is turned on, E−
The OR gate G10 operates to output a signal of the same logic level as the other input signal when one input is fixed to a low level. That is, the output of the flip-flop circuit FF11 is directly transmitted to the flip-flop circuit FF12. Thus, a scan path similar to that described in the first embodiment is formed, and a scan test can be performed.

Further, at the time of the self-test using the test pattern generation function, as shown in Table 1, switch elements SW11 to SW1n and switch elements SW4
1, SW42 is turned on, and switch elements SW20 and SW43 are turned off. Switch elements SW21-
SW2m may be on or off. As a result, in the portion of the flip-flop circuit between the combinational logic circuits LG1 and LG2, the output signal of the last flip-flop circuit FF1n is applied to the data input of the first flip-flop circuit FF11 and the intermediate flip-flop circuit (FF12 in the figure). A ring-shaped shift register to be fed back to the terminal is formed. A circuit having such a configuration is widely known in the field of testing as a linear feedback shift register (LFSR) that generates a pseudo random pattern.

The pseudo-random pattern generated by the linear feedback shift register (LFSR) is supplied to the combinational logic circuit LG2, and an output signal obtained by performing a logical operation using the pseudo-random pattern as an input signal is taken into the flip-flop circuits FF21 to FF2m. When the switch elements SW21 to SW2m are turned off, they are further supplied to the combination logic circuit at the subsequent stage. Therefore, the logic of the logic LSI can be evaluated by observing the signal of the output terminal in the normal operation with the tester and comparing the signal with the expected value. When the switch elements SW21 to SW2m are turned on, the scan clock signal SC is supplied to the flip-flop circuits FF21 to FF2m.
Supply K, output the latched data to the outside from the scan-out terminal SDo, observe with a tester,
By comparing with the expected value, the logic of the combinational logic circuit LG1 can be evaluated.

The linear feedback shift register (LFSR) generates a pseudo-random pattern. If the initial value set in the linear feedback shift register (LFSR) is known in advance, the generated pattern is predicted. Therefore, the expected value need not be generated inside the chip. The initial value can be set by applying the scan-in data from the input terminal SDi through the scan path in the same manner as the scan test data.

In FIG. 8, a wiring Lfd for feeding back the output signal of the last flip-flop circuit FF1n to the data input terminal of the first flip-flop circuit FF11 only for the first column flip-flop circuits FF11 to FF1n. Is provided, and the switch elements SW41 and SW4 are provided in the middle of the feedback wiring Lfd.
2 and the SW 43 and the E-OR gate G10, the linear feedback shift register can be configured. However, the flip-flop circuits FF21 to FF2m in the second column
May be provided with a similar feedback wiring and switch to configure a linear feedback shift register that generates a pseudo random pattern.

FIG. 9 shows an example of a logic LSI to which the third embodiment is applied. In FIG. 9, reference numeral 100 indicates a third
The logic LSI 200 to which the embodiment of
This is a tester for testing the SI100. In the logic LSI 100 of this embodiment, a memory 1
20 are built-in. The logic unit 110 has a configuration as shown in FIG. 8, where 130 is a pattern generation circuit composed of the flip-flop circuits FF11 to FF1n, and TMC is a mode control circuit.

In the logic LSI of this embodiment, the scan test can be executed by setting the logic LSI to the scan test mode by the tester 200 and applying the scan clock signal SCK. Also, if an initial value is set in the pattern generation circuit 130 by the tester 200 and then the scan clock signal SCK is applied, a test pattern is automatically generated inside the chip and the logic unit 110 operates. By monitoring the output signal, the chip can be evaluated.

Further, in the scan test mode,
Scan clock signal SCK provided from tester 200
By performing the test by adjusting the timing of the test, the test data is input from the preceding flip-flop circuit to the logic circuit of interest at a certain timing, and the data output from the logic circuit is appropriately delayed by a predetermined delay time. A timing test for diagnosing a timing margin can be performed by latching at a later stage flip-flop circuit at an appropriate timing and checking whether data is taken in.

Further, in this embodiment, the internal memory 12
For B, a BIST (built-in self test) circuit 140 for testing the memory is provided. Therefore, as a tester for testing the logic LSI of this embodiment, there is no need to use an expensive tester having a high function, and the cost required for the test can be greatly reduced. When the LSI incorporates an analog circuit, an analog BIST circuit for testing the analog circuit may be further provided in the chip, or a BOST method for testing the analog circuit from outside the chip may be applied.

As one of the LSI test facilitation techniques, there is known a technique of pattern-compressing output data output from a logic circuit or a memory operating according to a test pattern and outputting the compressed data to the outside of a chip. Also in the embodiment, a compression circuit may be provided after the logic unit to compress the output data and output the data. In that case, a pattern compression circuit called MISR is
Like the FSR, it can be configured using a flip-flop circuit that configures a logic unit. Therefore, such a mechanism (wiring for connecting appropriate flip-flop circuits, a switch, a logic gate, and the like) is provided in advance. You may do so.

Next, an LSI inspection method to which the above-described embodiment is applied and its advantages will be described by using a conventional logic LSI having a built-in memory.
The description will be made in comparison with the SI inspection method.

Inspection of a conventional semiconductor memory has been performed according to a procedure as shown in FIG. That is, when the pre-process of forming a memory and a logic circuit on a wafer is completed, a DC voltage is applied to pads on the wafer by a probe to check whether the memory circuit has a desired DC voltage characteristic. A functional test for checking whether or not there is a defective bit in the memory array, a rescue process for replacing the detected defective bit with a spare memory cell, and applying a DC voltage to a pad on the wafer so that the memory circuit has a desired DC voltage characteristic. DC of the logic part that checks whether or not
Test, function test to check whether the logic circuit performs normal logic operation using scan path, timing test to check how much operation margin the logic circuit has, application of power supply voltage to LSI higher than during normal operation Screening to detect chips with latent defects, assembly process into package, DC test in package state, scan test in code ○ 10 package state, timing test in code ○ 11 package state, code ○ 12 package state 13 Burn-in (synonymous with aging) test to check the reliability of operating the circuit for several to several tens of hours by applying a high voltage at high temperature, code 14 DC test at low temperature, code ○ 15 Scan test at low temperature, code ○ 16 Timing test at low temperature, code ○ 17 Script at low temperature , Sign ○
14 'DC test at high temperature, symbol ○ 15' scan test at high temperature, symbol ○ 16 'timing test at high temperature,
It was finished as a finished product through screening at high temperature 17 '.

On the other hand, when the embodiment of FIG. 5 which is a modification of the first embodiment of the present invention is applied, the power supply voltage supplied to the power supply terminal for the combinational logic circuit is switched, that is, applied intermittently. Become so. This makes it possible to perform a scan test for operating the combinational logic circuit while applying stress. In addition, the power supply voltage used at this time is changed to the power supply voltage during normal operation (for example, 3.3.
If the voltage is set higher than V), for example, 5 to 10 V, a larger stress can be applied to the logic circuit. Therefore, it is possible to omit the screening performed by the above-described symbols 1212, ○ 17, and 1717 ′.

FIG. 11 shows a test procedure in a logic LSI with built-in memory to which the embodiment of FIG. 5 is applied.
By replacing the scan test performed in the processes of reference numerals 1010, ○ 15, and 1515 'in FIG. 10 with the scan test of the embodiment of FIG. 5, as shown in FIG. Symbols ○ 12, ○ 17, ○ in FIG.
The screening performed in the step 17 ′ can be omitted. Further, in the process of reference numeral 15 ', the scan test is performed while applying stress due to the switching of the power supply voltage at a high temperature, so that the burn-in test of reference numeral 13 can be omitted. As a result, the test process and the required test time can be significantly reduced.

Further, if a technique of forming an LFSR by a scan path and performing a self test according to the third embodiment of the present invention is applied, a test can be performed with a simple tester. At the time of the burn-in that has been performed, it is possible to cause the LSI to perform a self-test by using a simple test function of the burn-in device. As a result, as shown in FIG.
It is possible to omit the scan test performed in the process of 10, reference numeral 15, and reference numeral 15 '. Also in this case, the test process and the required test time can be significantly reduced as compared with the conventional method.

Further, design data (gate-level connection information) for forming a scan path by chain-connecting flip-flop circuits using the switch elements as described in the above-described embodiment is transferred to a hardware IP (Intellectual PID).
A roperty) core may be registered in a database or the like, and used in the development of the next product or provided to the user for a fee. As a result, once completed design data can be reused as design resources, the development period of a new product can be shortened, and new business opportunities can be created.

Next, a specific method of using design data (gate-level connection information) constituting the scan path of the above-described embodiment in the form of a hardware IP will be described with reference to FIG.

When developing a logic LSI, first, a logic function of a semiconductor integrated circuit to be developed is designed (step S101). This logic function design is generally HD
This is performed using L (Hardware Description Language). Note that, since the EDA vendor provides a support tool (program) for automatically creating an HDL description from a state transition diagram and a flowchart, the HDL description can be efficiently performed. Also, the design data described in HDL is
A virtual test for verifying proper operation is performed by a verification program that generates a test pattern called a vector. If a defect is found by the virtual test, the HDL description is corrected.

Next, a circuit is designed at the logic gate level based on the data designed in step S101 (step S102). Specifically, cells such as a logic gate and a flip-flop circuit which constitute a circuit having a desired function are designed. And, based on this design data,
Logic synthesis is performed to create design data in which connection information between each logic gate and cell is described in the form of a netlist (step S103). In this case as well, a program called a logic synthesis tool for converting design data described in HDL into design data at the logic gate level and synthesizing the design data is provided by the EDA vendor, so that the program can be used by using the program. . The generated logic gate level design data is verified again by a test vector (virtual tester). If a defect is found by the virtual tester, the design data at the logic gate level is corrected.

Next, a scan path for a scan test is designed (step S104). At this time, I
The connection information of the scan path converted into P is used. Thereafter, logic synthesis is performed using the above-described design data and scan path IP data using a logic synthesis tool to convert the data into gate level design data including the scan path (step S105). In this way, the design of the scan path can be completed relatively easily.

Then, based on the logic gate level design data including the chip's original functional circuits and scan paths described in the netlist format obtained by the logic synthesis, the element-level layout data is generated by the automatic layout tool. Is generated (step S106). Such automatic layout tools are also provided by multiple EDA vendors. Then, a simulation considering the actual load is performed based on the layout data to check whether the circuit satisfies the requirements (step S10).
7).

Next, the layout of the chips on the wafer is determined (step S108). Thereafter, mask pattern data is generated by artwork based on the determined layout data, and a mask is created based on the data (step S109). At this time, the wiring pattern mask includes a pattern of the wiring for connection between chips formed in the scribe area.

Thereafter, a semiconductor integrated circuit is formed by performing processing such as diffusion processing and wiring pattern formation on the semiconductor wafer in the previous step (step S110). Then, the probe at the tip of the cable extended from the test apparatus is brought into contact with the electrode pad of each chip on the wafer, and the memory test and the logic section test including the scan path test are performed according to the procedure of FIG. (Step S111). After the probe test, dicing for dividing the wafer into chips is performed (step S112).

The divided chips are sealed in a package with a sealing material such as a resin (step S113). At this time, the chips determined to be defective in the probe test in step S111 are removed in advance. Then, a test is performed again in the package state according to the procedure of FIG. 11 (step S114). Those determined as defective in this test are marked on the package surface and removed in the sorting step, and only products having desired characteristics are shipped as finished products (step S115).

In the above-described embodiment, the case where the design data constituting the scan path is converted into hardware IP as gate-level connection information has been described.
The IP may be used as the description information of the function level so that it can be used in the function design performed in step S1.
The IP may be used as the connection information at the element level so that it can be used in the layout design performed in 108.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist of the invention. Needless to say. For example, in the above-described embodiment, an LSI that assumes a MOSFET as an element forming a circuit has been described. However, the present invention can be applied to an LSI including a bipolar transistor. In that case, a bipolar transistor can be used as a switch element provided between flip-flop circuits in order to make a scan path configurable. In such a case, it is desirable to provide a resistor Rj on the scan path and a pull-down resistor Rdj at the input terminal of each flip-flop circuit according to FIG. 6 showing an embodiment using a diode as a switch element.

The present invention can be applied not only to the case where all the combinational logic circuits are random logic but also to the case where some of the combinational logic circuits are memory circuits or PLAs (programmable logic arrays). .

In the above description, the invention made mainly by the present inventor is described by using the logic L
Although the description has been given of the case where the present invention is applied to the SI, the present invention is not limited to this. The present invention can also be applied to an analog LSI or an LSI in which a digital circuit and an analog circuit are mixed.

[0081]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, according to the present invention, when designing a semiconductor integrated circuit device with a diagnostic function, a diagnostic circuit that enables a scan path test while suppressing an increase in signal transmission time and hardware can be incorporated. In addition, a test pattern generation circuit can be configured using a flip-flop circuit originally provided in a semiconductor integrated circuit. This makes it possible to diagnose a logic circuit using a simple tester, which is necessary for testing. Cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a logic LSI to which a first embodiment of a scan path type test circuit according to the present invention is applied;

FIG. 2 is a block diagram showing a schematic configuration of a logic LSI to which a second embodiment of the scan path type test circuit according to the present invention is applied; FIG. 2 is a circuit configuration diagram showing one embodiment of a flip-flop circuit suitable for a diagnostic circuit of the present invention.

FIG. 3 is a timing chart showing timings of various signals at the time of a scan test in a logic LSI having a diagnostic function according to the present invention.

FIG. 4 is a circuit configuration diagram showing a specific example of an output high-impedance unit provided in the combinational logic circuit.

FIG. 5 is a block diagram showing a schematic configuration of a logic LSI to which a third embodiment of the scan path type test circuit according to the present invention is applied;

FIG. 6 is a circuit configuration diagram showing another specific example of a connection switch element between flip-flop circuits constituting a scan path type test circuit according to the present invention.

FIG. 7 is a logical configuration diagram illustrating an example of a conventional flip-flop circuit having a multiplexer in an input unit.

FIG. 8 is a block diagram showing a modification of the scan path test circuit according to the present invention.

FIG. 9 is a block diagram showing a configuration example of a logic LSI to which a scan path test circuit according to the present invention is applied.

FIG. 10 is a flowchart showing a procedure of a conventional method for testing a logic LSI having a built-in memory.

FIG. 11 is a flowchart illustrating an example of a procedure of a method of inspecting a logic LSI having a scan path according to the present invention.

FIG. 12 is a flowchart illustrating another example of the procedure of the method of inspecting a logic LSI having a scan path according to the present invention.

FIG. 13 is a flowchart showing a manufacturing process of a logic LSI to which the scan path type test circuit according to the present invention is applied.

[Explanation of symbols]

 FF11-FF2m Flip-flop circuit LG1, LG2 Combinational logic circuit SW11-SW2m Switch element for scan path configuration PSW1-PSW32 Power switch SDi Scan-in data input terminal SDo Scan data output terminal SCK Scan clock signal HIP Output high-impedance generator TBF Tri State buffer MUX Multiplexer MLT Master latch circuit SLT Slave latch circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G132 AA01 AB03 AB04 AC14 AG01 AK07 AK14 AK24 5F038 DF17 DT02 DT04 DT06 DT15 EZ20

Claims (11)

[Claims] 1. A combinational logic circuit, comprising: a first circuit that enables a serial scan test on the combinational logic circuit, wherein each of the first circuits transmits a signal from an input to an output. A plurality of possible flip-flop circuits, a plurality of switch elements, a combinational logic circuit coupled to the plurality of flip-flop circuits, and a high level for causing a plurality of input nodes to which inputs of the flip-flop circuits are coupled to have a high impedance. A first operating state including impedance setting means for setting signals of the plurality of input nodes in parallel to the plurality of flip-flop circuits, and a diagnosis by connecting the plurality of flip-flop circuits in series by the switch element And a second operation state for configuring the shift register for A semiconductor integrated circuit device wherein the plurality of input nodes are set to high impedance by the high impedance means in a working state. 2. The combinational logic circuit comprises a plurality of logic circuits, wherein the first circuit is provided between the combinational logic circuits, and wherein the output high-impedance means comprises a pre-stage for supplying a signal to the plurality of input nodes. 2. The semiconductor integrated circuit device according to claim 1, wherein the output impedance of the combinational logic circuit is a high impedance in the second operation state. 3. The high impedance output means,
3. The semiconductor integrated circuit device according to claim 2, wherein the semiconductor integrated circuit device is a tri-state buffer provided at an output unit of the combinational logic circuit serving as the preceding-stage circuit. 4. The high impedance output means,
9. A switch element connected between an output terminal of the combinational logic circuit serving as the preceding circuit and an input terminal of the flip-flop circuit in the first circuit for receiving a signal from the output terminal. 3. The semiconductor integrated circuit device according to 2. 5. The semiconductor integrated circuit device according to claim 2, wherein said switch element is a MOS transistor. 6. A wiring for feeding back an output signal of any one of the flip-flop circuits constituting the diagnostic shift register to an input terminal of a flip-flop circuit which is a circuit preceding the shift register when the shift register is constructed. An exclusive OR of a switch element provided in the middle of a wiring and a signal fed back by the wiring and an output signal of one of the flip-flop circuits in the middle stage constituting the diagnostic shift register is used for another flip-flop. 6. The semiconductor integrated circuit device according to claim 2, further comprising a logic gate circuit that can be applied to an input terminal of the loop circuit. 7. A test input terminal for supplying a test signal from the outside to the diagnostic shift register constituted by the flip-flop circuit, and a data signal shifted by the diagnostic shift register to the outside. 3. The semiconductor integrated circuit device according to claim 2, further comprising a test output terminal for outputting. 8. A semiconductor integrated circuit device comprising: a plurality of combinational logic circuits; and a plurality of flip-flop circuits provided between the combinational logic circuits and capable of latching a signal output from the combinational logic circuit, The flip-flop circuit is connected in series to provide a switch element that constitutes a diagnostic shift register, and the combinational logic circuit that becomes a preceding stage circuit during normal operation of the flip-flop circuit that constitutes the diagnostic shift register includes the flip-flop circuit. A semiconductor integrated circuit device which is configured to be in an inactive state when the pump circuit is activated to operate as a diagnostic shift register. 9. An external power supply voltage terminal for supplying an operation power supply of the flip-flop circuit and an external power supply voltage terminal for supplying an operation power supply of at least the combinational logic circuit serving as the preceding circuit are provided separately. When the combinational logic circuit is activated to operate as a diagnostic shift register, the power supply to the external power supply voltage terminal that supplies the operating power supply of the combinational logic circuit serving as the preceding-stage circuit is cut off, so that the combinational logic circuit is disabled 9. The semiconductor integrated circuit device according to claim 8, wherein the device is configured to be in an activated state. 10. A combination of a plurality of combinational logic circuits, a plurality of flip-flop circuits provided between these combinational logic circuits and capable of latching a signal output from the combinational logic circuit, and the flip-flop circuits connected in series. A switch element constituting a diagnostic shift register, wherein an external power supply voltage terminal for supplying an operation power supply for the flip-flop circuit and an external power supply voltage terminal for supplying an operation power supply for at least the combinational logic circuit serving as the preceding circuit are separately provided. A method for testing a semiconductor integrated circuit device, comprising: turning on the switch element in a state where a power supply voltage to the combinational logic circuit is cut off to form a diagnostic shift register and input test data. Operation, and after supplying test data, supply the power supply voltage to the combinational logic circuit and raise the output of the combinational logic circuit. A test method for a semiconductor integrated circuit device, wherein a scan test for repeating the second operation to be taken into the shift register is also performed as screening. 11. The method according to claim 10, wherein the scan test is performed at a temperature higher than room temperature.