JP2002343095A - Semiconductor memory and its test method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable confirming easily a normal/defective condition of cut off of a fuse for replacing a defective memory cell by a redundant memory cell when a function test of each pellet on a semiconductor wafer is performed. SOLUTION: A test circuit 10 including a fuse for cut off test (parity fuse) 11 is provided in a redundant memory cell selection decoder 20. An output signal obtained by inputting the prescribed test signal STEST to the test circuit 10 is varied in accordance with cut off or non-cut-off of the fuse 11 for cut off test. Thereby, a normal/defective condition of cut off of fuses 7 for switching provided in a plurality of fuse cut off discriminating section is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device provided with a redundant memory cell and a test method thereof, and more particularly, a desired fuse is blown in order to use a redundant memory cell instead of a defective memory cell. In some cases, the present invention relates to a semiconductor memory device that can easily determine whether the fuse has been cut or not by a test and a method of testing the semiconductor memory device.

[0002]

2. Description of the Related Art In general, a semiconductor memory device of this type, in which the quality of a fuse blown can be determined by a test, generally includes a normal memory cell section including a plurality of normal memory cells arranged at predetermined addresses and a normal memory cell portion. A redundant memory cell unit including a plurality of redundant memory cells to be used in place of the memory cells; and a fuse cut determination unit that determines whether a fuse has been cut corresponding to the address of the defective normal memory cell. ing.

[0003] Generally, this "fuse disconnection determination unit"
It has n latch circuits and n two-input Ex-OR circuits corresponding to the n address signals A1 to An (where n is a natural number of 2 or more).

Each of the n latch circuits is, for example,
When the corresponding fuse is blown, a signal of a logic high (H) level (hereinafter, simply referred to as “H level”) is output,
If the fuse is not blown, a signal of a logic low (L) level (hereinafter simply referred to as “L level”) is output to the corresponding two-input Ex-OR circuit. An output signal of the corresponding latch circuit and a corresponding address signal are input to each of the Ex-OR circuits. If the values of the two signals match, for example, an H-level signal is output.
Output level signal.

In a latch circuit corresponding to an address of a defective normal memory cell, a fuse is cut to use a redundant memory cell. Therefore, the output signal of the latch circuit becomes, for example, H level. In this state, the corresponding E
When an H-level address signal is input to the x-OR circuit, the output signal of the Ex-OR circuit goes high.
Thus, the redundant memory cell corresponding to the address is selected and used in place of the defective normal memory cell at the address corresponding to the input address signal.

On the other hand, in other cases, the Ex-OR
The output of the circuit becomes L level, and the redundant memory switching signal also becomes L level.
Therefore, the normal memory cell at the address corresponding to the input address signal is selected and used. That is, the redundant memory at the address corresponding to the input address signal is not used.

FIG. 5 is a circuit diagram showing a schematic configuration of a main part of a conventional redundant memory cell selection decoder of this type of semiconductor memory device.

Referring to FIG. 5, a conventional redundant memory cell selection decoder 120 includes two p-channel MOS transistors 101 and 102, one inverter 103, and n
N-channel MOS transistors 104, n two-input Ex-OR circuits 105, and n latch circuits 10
6 is provided. Each of the latch circuits 106 has a fuse 107. Although the fuse 107 is drawn outside the latch circuit 106 in FIG. 5 for easy understanding, it is actually provided inside the latch circuit 106.

The source and drain of p-channel MOS transistor 101 are connected to a power supply line to which power supply voltage V _DD is applied and node 108, respectively. The gate of the MOS transistor 101 is connected to the input terminal T101 of the redundant memory cell selection decoder 120, and a decoder selection signal S _SEL for determining whether the decoder 120 is selected or not is applied.

The source and the drain of the p-channel MOS transistor 102 are connected to the power supply line to which the power supply voltage V _DD is applied and the node 108, similarly to the MOS transistor 101. The gate of the MOS transistor 102 is connected to the output terminal T102 of the redundant memory cell selection decoder 120, and a redundant memory cell switching signal S _REP which is an output signal of the decoder 120 is applied. The input terminal and the output terminal of the inverter 103 are connected to the node 1
08 and an output terminal T102. M
The OS transistor 102 and the inverter 103 are connected to the node 1
It functions as a “latch circuit” for holding the voltage level of 08.

[0011] The n MOS transistors 104 corresponding to each of the address signals A1 to An, the n Ex-OR circuits 105 and the n latch circuits 106 corresponding to the MOS transistors 104 include a "fuse blow determination circuit". Is constituted. That is, n “fuse disconnection determination circuits” are provided corresponding to each of the n address signals A1 to An input to the redundant memory cell selection decoder 120.

The source of the transistor 104 corresponding to the address signal A1 is grounded, in other words, connected to a ground (GND) line. The transistor 10
4 has its drain connected to the node 108 and its gate connected to the output terminal of the corresponding Ex-OR circuit 105. One of the two input terminals of the Ex-OR circuit 105 is connected to the input terminal of the address signal A1, and the other is connected to the output terminal of the corresponding latch circuit 106.

The transistor 104, the Ex-OR circuit 105, and the latch circuit 106 corresponding to each of the address signals A2 to An have the same configuration as those corresponding to the address signal A1. One of the two input terminals of the Ex-OR circuit 105 is connected to the input terminals of the address signals A2 to An, and the other is connected to the corresponding latch circuit 10.
6 output terminals.

Next, the operation of the conventional redundant memory cell selection decoder 120 having the above configuration will be described.

In general, when a function test of this type of semiconductor memory device is performed and it is determined that a normal memory cell at a certain address is defective and should be replaced (switched) with a redundant memory cell, The fuse 107 of the latch circuit 106 corresponding to the address is blown. The cutting of the fuse 107 is performed, for example, by irradiating a laser beam to blow the fuse 107. Here, the output signal of each latch circuit 106 is determined by the fuse 10
It is assumed that 7 is at the L level when disconnected and is at the H level when not disconnected.

[0016] In this case, the voltage level of the decoder selection signal S _SEL applied to the input terminal T101 is the decoder 120 when it is L level is selected, and is, at the time of selection of the decoder 120, p-channel MOS transistor 101 Is applied with the L-level decoder selection signal _SSEL, so that the p-channel MOS transistor 101
N. As a result, the voltage level of the node 108 becomes H level (voltage value = V _DD ).

In this state, the address signal Ak (1 ≦ k ≦) corresponding to the address to be replaced with the redundant memory cell is set.
When n) is at the L level, the fuse 107 of the latch circuit 106 corresponding to the address signal Ak is blown. As a result, the output of the latch circuit 106 becomes L level.
At this time, the Ex-OR circuit 1 corresponding to the address signal Ak
The output of the transistor 05 goes high, and the n-channel MOS transistor 104 corresponding to the address signal Ak is turned on. Therefore, the node 108 is at the H level (voltage value =
V _DD ) to the L level (voltage value = GND). As a result, the redundant memory cell switching signal S _REP output from the output terminal T102 goes to the H level.

On the other hand, the memory cells to be replaced with redundant memory cells
Address signal Ak corresponding to the dress is at H level
And the Ex-OR circuit 105 corresponding to the address signal Ak
Is at the L level and corresponds to the address signal Ak.
The n-channel MOS transistor 104 turns off.
Therefore, the node 108 is at the H level (voltage value = V_DD)
As a result, the redundancy output from the output terminal T102 is maintained.
Long memory cell switching signal S _REPBecomes H level. Like this
Defective normal memory cell switches to redundant memory cell
Can be

That is, when the address signal Ak corresponding to the address to be replaced with the redundant memory cell is at the H level, the voltage level of the node 108 becomes the H level, and as a result, the redundant memory output to the output terminal T2 The cell switching signal S _REP goes low. On the other hand, an address signal A corresponding to an address that does not need to be replaced with a redundant memory cell
When 1 to A (k-1) or A (k + 1) to An are at the H level, the voltage level of the node 108 becomes the L level (voltage value = GND), and as a result, the redundancy output to the output terminal T2 The memory cell switching signal S _REP goes low. In this case, the normal memory cell cannot be switched to the corresponding redundant memory cell. That is, the normal memory cell of the corresponding address is used.

[0020]

The above-described conventional redundant memory cell selection decoder 120 of a semiconductor memory device has the following problems.

In recent years, the pellet size of semiconductor memory devices has become smaller and smaller, so that the fuse 10
The layout interval of No. 7 is also getting narrower. As a result, when a fuse 107 of a desired latch circuit 106 is selectively cut to replace a normal memory cell with a redundant memory cell, a disconnection failure often occurs. For example, an adjacent fuse 107 is erroneously blown, or a small piece of the blown (melted) fuse adheres to an adjacent fuse 107 to cause a short circuit between the fuses 107.

The quality of the cut of the fuse 107 is checked after performing a functional test on each pellet of the semiconductor memory device on the semiconductor wafer. Therefore, whether the defect of the pellet is caused by the defective cut of the fuse 107, etc. (Eg, poor diffusion of impurities). As a result, it takes a long time (for example, about one week) to analyze the defect of the pellet.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of easily confirming whether or not a fuse for replacing a redundant memory cell has been blown, when performing a functional test on each pellet on a semiconductor wafer, and a semiconductor memory device therefor. A test method for a semiconductor memory device is provided.

Another object of the present invention is to provide a semiconductor memory device capable of executing a failure analysis in a short time (for example, about one hour) and a test method of the semiconductor memory device.

Further objects of the present invention will become clear from the following description.

[0026]

(1) A semiconductor memory device according to the present invention is used in place of a normal memory cell section including a plurality of normal memory cells and a defective memory cell existing in the normal memory cell. A redundant memory cell portion including a plurality of redundant memory cells, and a necessary redundant memory cell can be selected and used from the redundant memory cell portion corresponding to a defective memory cell present in the normal memory cell. A redundant memory cell selection decoder, wherein the redundant memory cell selection decoder has a plurality of fuse disconnection determination units, and each of the fuse disconnection determination units replaces the defective memory cell with the redundant memory cell. In the semiconductor memory device having a switching fuse for indicating that the fuse should be used, the redundant memory cell selection decoder includes a test including a disconnection test fuse. A test circuit is provided, and the test circuit is configured such that an output signal obtained by inputting a predetermined test signal to the test circuit is different depending on whether or not the cut test fuse is cut, Thereby, it is possible to know whether or not the switching fuse has been cut.

(2) In the semiconductor memory device of the present invention, the redundant memory cell selection decoder has a plurality of fuse cut determination units, and each of the fuse cut determination units is
There is a switching fuse indicating that a redundant memory cell should be used instead of a defective memory cell. The redundant memory cell selection decoder is provided with a test circuit including a disconnection test fuse, and the test circuit outputs an output signal obtained by inputting a predetermined test signal to the test circuit. Is different depending on whether or not the switching fuse is cut, so that it is possible to know whether the switching fuse has been cut or not.

Therefore, it is possible to easily confirm whether or not the switching fuse for replacing with the redundant memory cell is cut, when performing a functional test on each pellet on the semiconductor wafer. As a result, the failure analysis can be performed in a short time (for example, about 1 hour).

(3) In a preferred example of the semiconductor memory device of the present invention, the output terminals of the plurality of fuse cut determination units of the redundant memory cell selection decoder are connected to a common node, and the output signal of the test circuit is output. Is input to the node.

In another preferred embodiment of the semiconductor memory device according to the present invention, the disconnection test fuse of the test circuit is connected to one input / output terminal of a transistor, and the test signal is supplied to a control terminal of the transistor. Applied.

(4) The method for testing a semiconductor memory device according to the present invention is the method for testing a semiconductor memory device according to the above (1), wherein the step of counting the number of cuts of the switching fuse; Using the output signal, determining whether the disconnection test fuse is disconnected, the number of disconnection of the switching fuse, and the determination result of whether the disconnection test fuse is disconnected based on the determination result. Determining whether the fuse has been cut or not.

(5) In the method for testing a semiconductor memory device according to the present invention, the step of counting the number of cuts of the switching fuse and the presence or absence of cutting of the cut test fuse are performed by using the output signal of the test circuit. Determining, the number of cuts of the switching fuse, based on the determination result of the presence or absence of cutting of the cutting test fuse,
A step of determining whether the switching fuse has been cut or not, so that the quality of the fuse to be replaced with the redundant memory cell can be easily determined when performing a functional test on each pellet on the semiconductor wafer. You can check. Further, the failure analysis can be executed in a short time (for example, about 1 hour).

(6) In a preferred example of the method for testing a semiconductor memory device according to the present invention, the output terminals of the plurality of fuse cut determination units of the redundant memory cell selection decoder are connected to a common node, and the test circuit Is input to the node.

In another preferred example of the method for testing a semiconductor memory device according to the present invention, the disconnection test fuse of the test circuit is connected to one input / output terminal of a transistor, and the control terminal of the transistor is connected to the control terminal of the transistor. A test signal is applied.

(7) It should be noted that other semiconductor memory devices capable of judging whether or not the switching fuse has been cut are disclosed in JP-A-10-125742 and JP-A-11-66893.
No. 6,086,045. However, these are clearly different in configuration from the semiconductor device of the present invention.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be specifically described below with reference to the accompanying drawings.

(First Embodiment) FIG. 1 is a circuit diagram showing a schematic main configuration of a redundant memory cell selection decoder of a semiconductor memory device according to a first embodiment of the present invention.

Referring to FIG. 1, redundant memory cell selection decoder 20 of the semiconductor memory device according to the first embodiment of the present invention has two p-channels, similarly to the conventional redundancy memory cell selection decoder 120 shown in FIG. MOS transistors 1, 2
, One inverter 3 and n n-channel MOSs
The circuit includes a transistor 4, n Ex-OR circuits 5, and n latch circuits 6. Each of the latch circuits 6
It has a fuse 7. To facilitate understanding, Figure 1
Although the fuse 7 is illustrated outside the latch circuit 6, the fuse 7 is actually provided inside the latch circuit.

The source and the drain of the p-channel MOS transistor 1 are connected to the power supply line to which the power supply voltage V _DD is applied and the node 8, respectively. MOS transistor 1
Is connected to the input terminal T1 of the redundant memory cell selection decoder 20, and a decoder selection signal _SSEL for determining whether the decoder 20 is selected or not is applied.

The source and the drain of the p-channel MOS transistor 2 are connected to the power supply line to which the power supply voltage V _DD is applied and the node 8 similarly to the MOS transistor 1. The gate of the MOS transistor 2 is connected to the output terminal T2 of the redundant memory cell selection decoder 20, and a redundant memory switching signal S _REP which is an output signal of the decoder 20 is applied. The input terminal and the output terminal of the inverter 3 are connected to the node 8 and the output terminal T2, respectively. MOS transistor 2 and inverter 3 function as a “latch circuit” for holding the voltage level at node 8.

The MOS transistor 4 corresponding to each of the address signals A1 to An, and the Ex-OR circuit 5 and the latch circuit 6 corresponding to the MOS transistor 4 constitute a "fuse disconnection determination circuit". That is, n “fuse disconnection determination circuits” are provided corresponding to each of the n address signals A1 to An input to the redundant memory cell selection decoder 20.

The source of the transistor 4 corresponding to the address signal A1 is grounded, in other words, grounded (G
ND) line. The drain of the transistor 4 is connected to the node 8 and its gate is connected to the corresponding Ex-
It is connected to the output terminal of the OR circuit 5. This Ex-O
One of the two input terminals of the R circuit 5 is connected to the input terminal of the address signal A1, and the other is connected to the output terminal of the corresponding latch circuit 6.

The transistor 4, the Ex-OR circuit 5, and the latch circuit 6 corresponding to each of the address signals A2 to An
It has the same configuration as those corresponding to the address signal A1. Of the two input terminals of the Ex-OR circuit 5,
One is connected to the input terminals of the address signals A2 to An, respectively, and the other is connected to the output terminal of the corresponding latch circuit 6, respectively.

The above configuration is the same as that of the conventional redundant memory cell selection decoder 120 shown in FIG.

The redundant memory cell selection decoder 20 of the first embodiment further includes a test circuit 10. The test circuit 10 includes a test parity fuse (a disconnection test fuse) 11, an n-channel MOS transistor 12, a NAND circuit 13, an inverter 14,
and an n-channel MOS transistor 15.

The two terminals of the parity fuse 11 are
The power supply line (voltage value = V _DD ) and the drain of the MOS transistor 12 are connected to each other. The source of the MOS transistor 12 is grounded, in other words, ground (G
ND) line. The gate of the MOS transistor 12 is connected to a predetermined external pin (not shown) of the semiconductor memory device or a pad (electrode) electrically connected to the external pin, and a predetermined test signal S
_TEST is applied.

One of two input terminals of the NAND circuit 13 is connected to a predetermined external pin or a pad (electrode) electrically connected to the external pin, and a predetermined test signal _STEST is applied. Is done. The other is fuse 1
1 and a connection point 16 between the MOS transistor 12. The output terminal of the NAND circuit 13 is connected to the inverter 14
Is connected to the input terminal of

The output terminal of the inverter 4 is connected to the gate of the MOS transistor 15. The source of the MOS transistor 15 is connected to a ground (GND) line, and the drain is connected to the node 8.

Next, the operation of the redundant memory cell selection decoder 20 of the first embodiment having the above configuration will be described.

As described above, when it is determined from the function test of the semiconductor memory device that the normal memory cell at a certain address is defective and should be replaced (switched) with a redundant memory cell, the address of that address is determined. , The fuse 7 of the latch circuit 6 is cut. The cutting of the fuse 7 is performed, for example, by irradiating a laser beam to blow the fuse 7. Here, it is assumed that the output signal of each latch circuit 6 is at the L level when the fuse 7 of the latch circuit 6 is cut, and is at the H level when the fuse 7 is not cut.

In this case, assuming that the decoder 20 is selected when the voltage level of the decoder selection signal _SSEL applied to the input terminal T1 is at the L level, the p-channel MOS transistor is selected when the decoder 20 is selected. 1 turns ON, and as a result, the voltage level of the node 8 becomes H level (voltage value = V _DD ).

In this state, the address signal Ak (1 ≦ k ≦) corresponding to the address to be replaced with the redundant memory cell is set.
When n) is at the L level, the fuse 7 of the latch circuit 6 corresponding to the address signal Ak is cut, and the output of the latch circuit 6 is at the L level. At this time, the address signal Ak
, The output of the Ex-OR circuit 5 becomes H level,
The MOS transistor 4 corresponding to the address signal Ak
N. Therefore, the node 8 is at the H level (voltage value = V
_DD ) to the L level (voltage value = GND), and as a result, the redundant memory cell switching signal S _REP output from the output terminal T2 goes to the H level.

On the other hand, when the address signal Ak corresponding to the address to be replaced with the redundant memory cell is at the H level, the output of the Ex-OR circuit 5 corresponding to the address signal Ak is at the L level, and the output of the Ex-OR circuit 5 corresponds to the address signal Ak. MO to do
The S transistor 4 is turned off. Therefore, node 8
Is maintained at the H level (voltage value = V _DD ). As a result, the redundant memory cell switching signal S _REP output from the output terminal T2 is output.
Becomes H level. Thus, the defective normal memory cell is switched to the redundant memory cell.

That is, when an address signal Ak corresponding to an address to be replaced with a redundant memory cell is input, the voltage level of node 8 attains an H level.
Redundant memory cell switching signal S output to output terminal T2
_REP goes to L level. On the other hand, address signals A1 to A corresponding to addresses which do not need to be replaced with redundant memory cells.
When (k-1) and A (k + 1) to An are input,
The voltage level of the node 8 becomes L level (voltage value = GND), and as a result, the redundant memory cell switching signal S _REP output to the output terminal T2 becomes H level. In this case, the normal memory cell cannot be switched to the corresponding redundant memory cell.

Next, the operation of the test circuit 10 will be described with reference to the timing chart of FIG.

The test circuit 10 tests whether or not necessary ones of the n fuses 6 are correctly blown in accordance with the address to be replaced with the redundant memory cell (that is, the address signal Ak). belongs to.

Parity fuse 11 of test circuit 10
Is not disconnected, the power supply voltage V _DD is applied to the connection point 16 at time t10 as shown in FIG. 2B. That is, one input terminal of the NAND circuit 13
An input signal of H level (voltage value = V _DD ) is applied. The gate voltage is H level of the n-channel MOS transistor 15, the signal at the node 8 is at the L level (voltage value = 0), the redundant memory switching signal S _{RE P} is at H level.

At time t11, in order to access a desired memory cell, n pieces of "fuse-cut determination circuits"
Are changed from L level to H level or from H level to L level. Thereafter, at time t12, the decoder selection signal _SSEL applied to the input terminal T1 is changed from H level to L level. Thereby, the p-channel MO
Since the S transistor 1 is turned on, the node 8 becomes H level.

The parity fuse 11 is not blown.
Therefore, the power supply voltage V _DDIs applied
Therefore, one input terminal of the NAND circuit 13
The applied input signal is at the H level.

Subsequently, at time t13, the gate of the n-channel MOS transistor 12 of the test circuit 10 and N
The test signal _STEST applied to the other input terminal of the AND circuit 13 is changed from L level to H level. At this time, the test signal S of H level is applied to the gate.
_The transistor 12 to which _TEST is applied turns ON. As a result, both of the two input signals of the NAND circuit 13 become H level, and the output signal of the NAND circuit 13 becomes L level.
Level. Since the output signal of NAND circuit 13 is inverted by inverter 14 and applied to the gate of n-channel MOS transistor 15, the signal applied to the gate of MOS transistor 15 is held at the H level. As a result, the MOS transistor 15 is turned on, and the voltage at the node 8 is maintained at the L level. Since the voltage at the node 8 is inverted by the inverter 3 and then output to the output terminal T2 as the redundant memory switching signal S _REP , the redundant memory switching signal S _REP is held at the H level.

As described above, even when address signals A1 to An of addresses to be replaced with the redundant memory cells are input, redundant memory cell switching signal S _REP output to output terminal T2 is held at the H level. However, replacement with a redundant memory is not performed. That is, the value of the defective normal memory cell is read. At this time, the output signal of the external pin is in a high impedance state.

On the other hand, when the parity fuse 11 of the test circuit 10 is cut, the power supply voltage V _DD is not applied to the connection point 16 at time t0, as shown in FIG. Since the floating state occurs, no input signal is applied to one input terminal of the NAND circuit 13. Also, n
The gate voltage of the channel MOS transistor 15 is at the L level, the signal at the node 8 is at the H level (voltage value = V _DD ), and the redundant memory switching signal S _REP is at the H level.

At time t1, in order to access a desired memory cell, the address signals A1 to An applied to the n "fuse cut determination circuits" are changed from L level to H level or from H level to L level. Changes to Thereafter, at time t2, the decoder selection signal _SSEL applied to the input terminal T1 is changed from H level to L level. As a result, the p-channel MOS transistor 1 is turned on, so that the node 8 is kept at the H level.

Since the parity fuse 11 has been blown, no signal is applied to the connection point 16 and, therefore, N
No input signal is applied to one input terminal of the AND circuit 13.

Subsequently, at time t3, the test circuit 1
0 n-channel MOS transistor 12 with gate and NA
The test signal _STEST applied to the other input terminal of the ND circuit 13 is changed from L level to H level. At this time, the transistor 12 to which the power supply voltage V _DD is not applied to the drain remains OFF. Therefore, the output signal of the NAND circuit 13 goes high. N
Since the output signal of AND circuit 13 is inverted by inverter 14 and applied to the gate of n-channel MOS transistor 15, the signal applied to the gate of MOS transistor 15 is held at L level. As a result, the MOS transistor 15 is turned off, and the voltage at the node 8 is maintained at the H level. The voltage at node 8 is at time t
4, the output terminal T
2 is output as a redundant memory switching signal S _REP ,
Redundant memory switching signal S _REP changes from H level to L level.

As described above, the parity of the test circuit 10
When the fuse 11 is blown, the address signals A1 to An of the address to be replaced with the redundant memory cell are input at time t1, and the data selection signal S at time t2.
_SEL changes from H level to L level, and at time t3, the test signal _STEST changes from L level to H level. As a result, since the redundant memory cell switching signal S _REP output to the output terminal T2 changes from the H level to the L level, the defective normal memory is replaced with the corresponding redundant memory. That is, the value of the normal redundant memory cell is read instead of the defective normal memory. At this time, the output signal of the external pin becomes L level or H level according to the value of the redundant memory cell.
Become a level.

As described above, in this test using the test circuit 10, when reading the value of the defective normal memory cell, the output signal of the external pin is set to a high impedance state,
When the value of the redundant memory cell is read, the value of the redundant memory cell is read. However, since a specific example of this method has been conventionally performed in a similar test and is known, Detailed description is omitted.

As described above, the parity fuse 1
Since the output signal of the external pin differs depending on whether 1 is cut or not, it is possible to distinguish whether the number of cuts of the fuse 7 corresponding to the address to be replaced with the redundant memory cell is even or odd. .

In the above-described fuse cut confirmation test, whether the fuse 7 has been cut correctly is checked in accordance with the steps shown in FIG.

That is, in step S1, information on the level (H or L) of the address signal at the time of switching the redundant memory cell can be stored in the tester for performing the functional test by the read test of the value of the redundant memory cell. The number of cuts of the switching fuse 7 is counted based on the information.

In step S2, the above-described test for checking whether the parity fuse 11 has been cut is performed to check whether or not the parity fuse 11 has been cut for each of the plurality of redundant memory cell selection decoders 20. And
It is determined whether the number of cuts of the parity fuse 11 is even or odd.

In step S3, the information on the number of cuts of the switching fuse 7 obtained in step S1 is compared with the information on whether the number of cuts of the parity fuse 11 obtained in step S2 is even or odd. Check whether or not. If there is a contradiction, it is determined that there is a disconnection failure of the switching fuse 7. If there is no inconsistency, it is determined that there is no disconnection failure of the switching fuse 7.

Considering the role of the parity fuse 11, its operation requires high reliability. Therefore, it is preferable to set the width and the interval to be larger than those of the switching fuses 7 and to make them with a marginal design.

As described above, in the semiconductor memory device according to the first embodiment of the present invention, in the test for confirming whether or not the switching fuse 7 has been cut, whether or not the cut has been correctly performed is determined by the semiconductor memory device on the semiconductor wafer. Since it is known when performing a functional test on the pellet, the time required for failure analysis can be greatly reduced. For example, what took about one week is reduced to about one hour or less.

(Second Embodiment) FIG. 3 is a circuit diagram showing a main configuration of a redundant memory cell selection decoder 20A of a semiconductor memory device according to a second embodiment of the present invention.

In the redundant memory cell selection decoder 20A of the second embodiment, the test circuit 10A has the same configuration as the test circuit 10 of the redundant memory cell selection decoder 20 of the first embodiment.
Only the configuration is different from that of the other, and the other configuration is the same.

The test circuit 10A includes (a) the test circuit 1
A NOR circuit 13A is provided in place of the NAND circuit 13 of 0, (b) the logic level of the test signal S _TEST ′ is opposite to the test signal S _TEST of the test circuit 10, and (c)
It has the same configuration as the test circuit 10 of the first embodiment except that the test signal S _TEST ′ is applied to the gate of the transistor 12 via the inverter 17. Therefore, corresponding elements are denoted by the same reference numerals and description thereof will be omitted.

It is apparent that the semiconductor memory device according to the second embodiment of the present invention can obtain the same operation as that of the first embodiment and can obtain the same effect.

The above first and second embodiments show specific examples of the present invention, and the present invention relates to the first and second embodiments.
It is not limited to the configuration of the embodiment. It goes without saying that various modifications are possible without departing from the spirit of the present invention.

[0080]

As described above, according to the semiconductor memory device of the present invention and the method of testing the semiconductor memory device,
Whether or not the fuse for replacing the redundant memory cell has been cut can be easily checked when a functional test is performed on each pellet on the semiconductor wafer. Further, the failure analysis can be performed in a short time (for example, about 1 hour).

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a schematic main configuration of a redundant memory cell selection decoder of a semiconductor memory device according to a first embodiment of the present invention;

FIG. 2 is a timing chart showing an operation of a test circuit of a redundant memory cell selection decoder of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a flowchart illustrating an operation of a test circuit of a redundant memory cell selection decoder of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating a schematic configuration of a main part of a redundant memory cell selection decoder of a semiconductor memory device according to a second embodiment of the present invention;

FIG. 5 is a circuit diagram showing a schematic configuration of a main part of a redundant memory cell selection decoder of a conventional semiconductor memory device.

[Explanation of symbols]

Reference Signs List 1 p-channel MOS transistor 2 p-channel MOS transistor 3 inverter 4 n-channel MOS transistor 5 Ex-OR circuit 6 latch circuit 7 fuse 8 node 10, 10A test circuit 11 parity fuse 12 n-channel MOS transistor 13 NAND circuit 13A NOR circuit 14 Inverter 15 n-channel MOS transistor 16 connection point 17 inverter 20 and 20A redundant memory selection decoder T1 input terminal T2 output terminal A1 to An, Ak address signal S _SEL decoder selection signal S _TEST , S _TEST 'test signal S _REP redundant memory switching signal

Continued on front page F-term (reference) 2G132 AA08 AB00 AD06 AH04 AK07 AL09 5B003 AA06 AC01 AD08 AE04 5L106 AA08 BB02 CC04 CC08 CC12 CC21 CC32 DD12 DD25 GG07

Claims (6)

[Claims] A normal memory cell section including a plurality of normal memory cells; a redundant memory cell section including a plurality of redundant memory cells used in place of defective memory cells existing in the normal memory cells; A redundant memory cell selection decoder for selecting and using the required redundant memory cell from the redundant memory cell portion corresponding to a defective memory cell present in the memory cell; The decoder has a plurality of fuse cut determination units, and each of the fuse cut determination units has a switching fuse indicating that the redundant memory cell should be used instead of the defective memory cell. In the semiconductor memory device, a test circuit including a fuse for a disconnection test is provided in the redundant memory cell selection decoder, and the test circuit includes a test circuit. An output signal obtained by inputting a predetermined test signal to the reset circuit is configured to be different depending on whether or not the disconnection test fuse has been cut, whereby it is possible to know whether or not the switching fuse has been cut. A semiconductor memory device characterized by being able to perform. 2. The output terminal of a plurality of fuse cut determination units of the redundant memory cell selection decoder is connected to a common node, and an output signal of the test circuit is input to the node. 13. The semiconductor device according to claim 1. 3. The test circuit according to claim 1, wherein the disconnection test fuse of the test circuit is connected to one input / output terminal of a transistor, and the test signal is applied to a control terminal of the transistor. Semiconductor device. 4. The method for testing a semiconductor memory device according to claim 1, wherein the step of counting the number of cuts of the switching fuse is performed, and the cut test fuse is used by using the output signal of the test circuit. Determining whether or not the switching fuse has been cut, and determining whether or not the switching fuse has been cut based on the number of cuts of the switching fuse and the determination result of whether or not the cutting test fuse has been cut. A method for testing a semiconductor memory device, comprising: 5. The redundant memory cell selection decoder according to claim 4, wherein output terminals of the plurality of fuse cut determination units are connected to a common node, and an output signal of the test circuit is input to the node. Semiconductor device testing method. 6. The test circuit according to claim 4, wherein the disconnection test fuse of the test circuit is connected to one input / output terminal of a transistor, and the test signal is applied to a control terminal of the transistor. Test method for semiconductor device.