JP2002341825A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently conduct current value detection and to improve numerical aperture of an active matrix organic EL display in which luminance correction is conducted by measuring the load current of organic EL elements with a current measuring circuit and correcting display data using the measurement result. SOLUTION: One frame interval Tf is constituted of a current measuring interval Tm and a display interval Ta and scanning is conducted with a cycle of several tens of [Hz], for example. In the interval Tm, a prescribed voltage is beforehand given to the organic EL elements of each element circuit, scanning signal lines G1 to G15 which are one unit in terms of fifteen lines, for example, are successively selected and current characteristics are measured. The succeeding display interval Ta is constituted of a light emitting interval Td and an erasing interval Tsa. Thus, the current which flows in the power supply lines becomes only for the load current of the selected element circuits and current measurement is conducted at the signal controller side outside a display region, even in an active matrix panel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic EL (Electr
o Luminescence element and FED (Field Emission Device)
The present invention relates to a display device configured by arranging electro-optical elements such as elements in a matrix.

[0002]

2. Description of the Related Art In recent years, thin display devices using self-luminous devices such as the organic EL elements and FED elements have been actively developed. In these self-luminous devices, it is known that the light emission luminance of the element is proportional to the current density flowing through the element. In addition, it is known that element characteristics, particularly applied voltage-current characteristics, vary, and it is considered that a drive circuit using a constant current source is preferable in these devices. However, since it is difficult to actually configure a constant current source,
A constant current drive circuit is configured using a constant voltage source. In this case, a method has been proposed in which means for detecting the current flowing through the element is provided, and the current detected by the detecting means is controlled to be constant.

FIG. 32 is a diagram showing an example of an organic EL display 101 in which luminance correction is performed using such a current detecting means.
It was shown in the official gazette. This display 101
Is a passively driven display, and the organic EL panel 102 has a plurality of cathodes c0 to c0 orthogonal to each other.
cn and the anodes s0 to sm, the display area is divided into a matrix, and the organic EL element 1
03 are arranged.

A cathode drive circuit 104 for driving the cathodes c0 to cn, or an anode drive circuit pg0 to pgm for individually driving the anodes s0 to sm, is provided outside or integrally with the organic EL panel 102. And current detection circuits is0 to ism for detecting the respective output currents from the anode drive circuits pg0 to pgm. The current value detected by the current detection circuits is0 to ism (collectively indicated by reference numeral is) is used as a control device 105
The lighting time or the lighting current corresponding to the display information of each display area is adjusted in accordance with the detected current value.

The current detection circuit is, for example, shown in FIG.
As shown in the figure, the resistance r1 is connected to the line to each anode s0 to sm.
Are connected in series, and the voltage between the terminals of the resistor r1 is detected by the A / D conversion circuit 106 and output.

FIG. 34 shows another example of an organic EL device in which luminance correction is performed using the above-described current detecting means.
FIG. 10 is a diagram showing a display 111, which is disclosed in
4410. The display 111 is an active drive display, and all the organic EL elements of the display panel 112 are controlled by the controller 11.
3 drives at a constant voltage via the scanning circuit 114 and the power supply circuit 115, and stores a current value measured at that time in a current value memory 116 as described later, and stores the stored data and A / A The display data input from the outside through the D conversion circuit 117 is processed by the arithmetic circuit 118, and the obtained display data is given to each pixel via the frame memory 119 and the writing circuit 120. Has adjusted the sum.

In the case of this active drive, the display panel 1
Each of the twelve pixels 121 has a configuration as shown in FIG. That is, a TFT 122 for capturing display data, a capacitor 123 for storing the captured display data,
An organic EL element 124 and a TFT 125 for driving the organic EL element 124 in accordance with the output voltage of the capacitor 123
And a current detector 126 for measuring a current flowing through the organic EL element 124.

By selecting a scanning signal line, the TFT 1
22 is turned on, and the voltage of the data signal line is stored in the capacitor 123. Even when the TFT 122 is in a non-conductive state, the voltage of the capacitor
5 is controlled to adjust the amount of current flowing through the organic EL element 124. Therefore, the current detector 126 is connected to the TFT 12
5 and the organic EL element 124, the output of the current detector 126 is converted into digital data by an A / D conversion circuit 127 and stored in the current value memory 116, and the sum of the current values as described above is calculated. Adjustments are being made.

[0009]

In the prior art described above, in a passive drive display device such as the display 101 of JP-A-2000-187467, the cathodes c0 to cn are sequentially selected. s0-sm
If the current flowing through is measured, the selected cathodes c0 to c
The current of the organic EL element 103 at the intersection with n can be measured. However, Japanese Patent Application Laid-Open No. 10-25441
In a display device of an active drive like the organic EL display 111 of No. 0, as described above, even if the scanning signal line is in a non-selected state, the voltage of the capacitor 123 causes the TFT 1 to operate.
25, and a current is flowing through the organic EL element 124. For this reason, the current can be measured only for each organic EL element 124, and the current cannot be efficiently measured collectively for each signal line outside the display area as in the case of the passive drive. There is a problem. There is also a problem that the area of each organic EL element 124, that is, the aperture ratio cannot be improved.

An object of the present invention is to provide a display device capable of efficiently detecting the current value of each electro-optical element and improving the aperture ratio even in active driving. .

[0011]

A display device according to the present invention includes an electro-optical element in each area defined by a plurality of first and second signal lines that intersect each other.
In a display device driven by a corresponding first active element to perform a display corresponding to a signal level output to a second signal line while being selected by the first signal line, A current measuring unit arranged along the second signal line and configured to measure a current of a first power supply line for supplying a load current to the electro-optical element; and holding data measured by the current measuring unit. A storage unit that corrects display data input from the outside using data read from the storage unit and creates a signal level to be output to the second signal line; In addition to the selection by the first signal line, the selection by the first signal line and the unit display period in which the signal level corresponding to the display data is output to the second signal line. Signal Previously defining outputs a signal level, and wherein the inclusion of time Yuku performing measured by the current measuring means.

According to the above configuration, an electro-optical element such as an organic EL element is provided in each of a plurality of first and second signal lines intersecting each other and arranged in a matrix. A display in which an electro-optical element performs a display corresponding to a signal level output to a second signal line by being sequentially selected by the first signal line by a corresponding first active element such as a TFT. In the device,
A current measuring means for measuring a current of a first power supply line disposed along the second signal line; and correcting display data based on the measurement result, for each unit display period, or The current is periodically measured for each of the plurality of unit display periods.

Therefore, in dynamically correcting display data for obtaining a desired gradation in response to a change in ambient temperature or the like, even in the case of an active matrix panel, the current measuring means must be provided in each region (electrical area). It is not necessary to provide for each of the optical elements, but it is sufficient to provide for each first power supply line (= second signal line) or a plurality of first power supply lines. Thus, the current value of each electro-optical element can be efficiently detected, and the area of the electro-optical element in each region, that is, the aperture ratio can be improved.

Further, the display device of the present invention has a memory element for holding a signal level taken in by the first active element, in connection with the electro-optical element, wherein the memory element holds the signal level. A scan controller for deriving a selected output and a signal controller for outputting a signal level to the second signal line perform initialization of the memory element and scanning for setting the electro-optical element to a non-light emitting state immediately before a measurement period. It is characterized by.

According to the above configuration, the scanning controller and the signal controller perform scanning for setting the display state by loading the signal level into a memory element realized by a capacitor or the like, and perform one or more display periods. On the other hand, when the measurement period is periodically inserted as described above, immediately before the measurement period, a scan for setting the electro-optical element to the non-light emitting state by initializing the memory element is performed.

Therefore, by setting the non-light emitting state immediately before the measurement period in the above scanning, the influence of other electro-optical elements can be eliminated, and a desired load current of the electro-optical element can be accurately measured.

Still further, the display device of the present invention, in response to the memory element, responds to a selection output from a third signal line from which a selection output is derived alternatively from the first signal line. And a second active element for giving a signal level different from the second signal line to the memory element, wherein a display signal level is set by the first active element and erased by the second active element. The signal level is set.

According to the above arrangement, after the display is started by the scanning of the first signal line, before the scanning is completed for all the first signal lines, the scanning of the second signal line is performed. The display can be deleted. That is, the unit display time can be shorter than the scanning period.

Therefore, in performing the digital gradation control, it is possible to accurately display the data of the lower bits in a short time corresponding to the weight of the bits.
Fine gradation control with a large number of bits can be performed.

The display device according to the present invention may further comprise, in relation to the memory element, one or a plurality of pixel memories for holding a signal level taken in by the first active element, and individual pixel memories for the pixel memories. And a third active element selectively driven by a bit selection line, wherein a display signal level is set to the memory element via the first active element when the first signal line is selected. And the third active element is selectively driven to set the display signal level in the pixel memory, and the third active element is selectively driven in the non-selected state of the first signal line. The display signal level is switched to the display signal level from the pixel memory.

According to the above configuration, display is performed by scanning the first signal line, and the display signal level is written into the pixel memory corresponding to the bit selection line by selecting the bit selection line. I can put it. And
By selecting the bit selection line while the first signal line is not selected, the display signal level can be read from the pixel memory.

Therefore, within one scanning period in which the first signal line is sequentially scanned, the remaining time of displaying the lower bit data can be used for displaying the upper bit data. Even if a scanning period at equal intervals is set for each bit, a new time-division gray scale display in which a non-scanning period or a non-light emitting period in a display period can be reduced can be realized.

Still further, in the display device according to the present invention, power is supplied to the memory element from a second power supply line provided separately from the first power supply line for supplying a load current to the electro-optical element. It is characterized by the following.

According to the above configuration, while the first active element is selected, the display is performed by setting the potential of the first power supply line to a potential at which the load current does not flow, for example, the GND potential. Without writing, only writing of a signal level to a memory element can be performed. Further, the display period of the electro-optical element based on the data stored in the memory element or the pixel memory can be controlled independently of the scanning period of the first active element, and time-division gray scale display can be realized in the display period. Can also.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a diagram showing an overall configuration of an organic EL display 1 according to a first embodiment of the present invention. The organic EL display 1 generally includes an organic EL panel 2
, A scanning controller 3, a signal controller 4, and a latch circuit 5. The organic EL panel 2 includes a plurality of scanning signal lines G1, G2,
.., Gm (when collectively referred to as G below)
, And data signal lines D1, D2,..., Dn (hereinafter collectively referred to as D), and element circuits A11, A12,
.., A1n; A21,.
(Referred to below as A). Each of the element circuits A captures the signal level output from the signal controller 4 to the corresponding data signal line D while the scanning controller 3 selects the corresponding scanning signal line G,
The display corresponding to the signal level is performed.

A synchronization signal and a data signal are externally input to the organic EL display 1. The scanning controller 3 outputs a selection signal to each of the scanning signal lines G in response to the synchronization signal. The latch circuit 5 includes:
In response to the synchronization signal, the data signals are sequentially latched, serially input data signals are accumulated for one line, and the data signals are paralleled by the number of the data signal lines D1 to Dn. Output to the signal controller 4. In the signal controller 4, the data signals are supplied to D / A conversion circuits F1 to F1 corresponding to the data signal lines D1 to Dn.
Fn (collectively referred to as F hereinafter) is converted into an analog signal, and the data signal lines D1 to Dn
Respectively.

The organic EL panel 2 has power lines E1 to En supplied with power from a power line E0 in parallel with the data signal lines D1 to Dn so as to penetrate the element circuits A (hereinafter, collectively referred to as "power lines E1 to En"). (Indicated by reference numeral E). At the ends of the power supply lines E1 to En on the signal controller 4 side, current measuring circuits K1 to Kn (hereinafter collectively indicated by a reference numeral K) are provided, respectively.
At a predetermined measurement timing, a current flowing through each of the element circuits A11 to Amn via the power supply lines E1 to En is measured line by line as described later. The measurement result becomes a correction value (or voltage data for giving a necessary current value) of each element circuit A, and is stored in each of the memories M1 to Mn. The data signal lines D1 to D1
In writing a data signal via n, arithmetic circuits B1 to Bn (hereinafter collectively referred to as B)
Are the data signals from the latch circuit 5 in the memories M1 to M
n, and then, as described above, D / A
The signals are output to the conversion circuits F1 to Fn. Thus, the luminance correction of each element circuit A is performed.

FIG. 2 is an electric circuit diagram of the element circuit A.
The element circuit A is an active element, and has a gate connected to the scanning signal line G, a source (drain) connected to the data signal line D, and a gate connected to the scanning signal line G. An n-type TFT Q1 for receiving the data signal from the data signal line D, a capacitor C1 connected to a drain (source) of the TFT Q1 for holding the captured data signal, an organic EL element P, and the capacitor A p-type TFT Q for controlling a current flowing from the power supply line E to the organic EL element P in accordance with the charging voltage of C1.
2 is provided.

FIG. 3 shows a gate voltage of the TFT Q2 and a device current characteristic of the organic EL device P in the electro-optical device composed of the TFT Q2 and the organic EL device P. This characteristic is obtained when the voltage of the power supply line E in FIG. 1 is + 6V. The potential stored in the capacitor C1 is corrected by the arithmetic circuit B using the correction value stored in the memory M as described above, so that the element current of the organic EL element P can be corrected. Brightness correction can be performed so that a constant brightness can always be obtained with respect to the time-dependent change of P and temperature characteristics.

In FIG. 1 and FIG. 2, the element circuit A is described as one pixel, but this is for the sake of simplicity. Actually, the R of the element circuit A in FIG.
One of each of the GBs may be a set of pixels, or each of the RGB components may be composed of a plurality of element circuits A.

FIG. 4 shows an organic EL device constructed as described above.
FIG. 4 is a diagram illustrating an example of a method for driving the display 1. The organic EL display 1 has a D / A conversion circuit F as described above.
, The data signal is converted into a corresponding analog voltage level, and the TFT Q2
An analog gradation control for controlling a current flowing through the element P is performed. In FIG. 4, the scanning signal line is one of G1 to G15.
It is assumed that one unit is composed of five scanning signal lines G1 to G1.
The selection state of G15 is shown in FIGS.

In this scanning example, one frame period Tf is composed of a current measurement period Tm and a display period Ta.
For example, scanning is performed at a period of several tens [Hz]. In the current measurement period Tm, the scanning signal lines G1 to G15 are sequentially selected. At this time, the arithmetic circuit B applies a predetermined voltage to the organic EL element P of each element circuit A.
The current characteristics of the L elements P are measured in order. The following display period T
“a” includes a light emitting period Td and an erasing period Tsa. In the scanning period Ts within the light emitting period Td, similarly to the current measuring period Tm, the scanning signal lines G1 to G15 are sequentially selected, the data signal is taken into the capacitor C1, and the remaining period of the light emitting period Td is , A display corresponding to the data signal is performed. Thereafter, in the present invention, before the current measurement is performed, the scanning signal lines G1 to G
15 are sequentially selected, and the data of the capacitor C1 is erased and initialized.

As described above, the capacitor C as a memory element
1, the current flowing through the power supply line E is limited to the element circuit A selected by the scanning signal line G by performing current measurement after initializing all the element circuits A. Since the load current is used, the current can be commonly measured for each power supply line E (= data signal line D) under the control of the signal controller 4 outside the display area. Thus, when dynamically correcting display data for obtaining a desired gradation in response to a change in ambient temperature or the like, the current value of each organic EL element P can be set even in the active matrix organic EL panel 2. Detection can be performed efficiently, and the area of the organic EL element P in each element circuit A, that is, the aperture ratio can be improved.

In the example of FIG. 4, the current is measured every display period Ta (frame period Tf).
When the measurement is performed for each of a plurality of frames, the erasing period Tsa may be provided in a frame immediately before the frame in which the current measurement is performed, and the current measuring period Tm may be provided following the erasing period Tsa.

FIG. 5 shows a second embodiment of the present invention.
7 will be described below.

FIG. 5 is a diagram showing the overall configuration of an organic EL display 11 according to a second embodiment of the present invention. The organic EL display 11 is similar to the above-described organic EL display 1, and corresponding portions are denoted by the same reference numerals, and description thereof will be omitted. It should be noted that the organic EL display 1 has digital gradation control while the organic EL display 1 has analog gradation control. For this reason, memories Ma1 to Man (hereinafter collectively indicated by a reference numeral Ma) are inserted in the places where the arithmetic circuits B1 to Bn in FIG. Then, the memory Ma converts the input pixel-unit data into bit-unit data. In the present embodiment, the organic EL panel 2a includes the element circuits A in parallel with the scanning signal lines G1 to Gm.
a11 to Aamn (hereinafter collectively referred to as Aa
), And the other scanning signal lines S1 to Sm
(When collectively referred to as S hereinafter), the scanning controller 3a selectively controls these scanning signal lines G and S.

Here, when the organic EL element is driven by the active element, the method of realizing gray scale display can be roughly classified into analog gray scale control and digital gray scale control. This is a method of controlling the value of the current flowing through the organic EL element as described above. On the other hand, digital gradation control can be divided into pixel division gradation and time division gradation. In the pixel division gradation, one pixel is composed of a plurality of organic EL elements, and each organic EL element is selectively used. Is a method of performing gray scale display by on / off driving, and the time division gray scale is a method of controlling the time of the current flowing through the organic EL element.
The pixel division gray scale is not suitable for high definition use since one pixel is composed of a plurality of organic EL elements as described above, and the present invention is directed to time division gray scale.

As is clear from FIG. 4, while a certain scanning signal line Gi is selected, the remaining scanning signal lines G1
~ Gi-1, Gi + 1 ~ Gm cannot be selected,
Therefore, when performing the time division gray scale control, when a certain bit of data is output to a certain scanning signal line Gi, the next bit of data is output because the remaining scanning signal line Gi + 1 After outputting data to all of Gm, G1 to Gi-1, the unit display time by the lower bit data becomes longer, and the one-frame period Tf becomes longer. For this reason, the scanning signal line S is provided, and the display started by the scanning signal line G is switched to blank display by scanning by the scanning signal line S, so that the unit display time is shorter than the scanning period Ts. It is possible to shorten it.

When the data signal output from the memory Ma is "1", the voltage corresponding to the data signal becomes D /
The element circuit Aa from the A conversion circuit F via the data signal line D
When the output data signal is “0”, the voltage for hiding the organic EL element P is
The data is supplied from the D / A conversion circuit F to the element circuit A via the data signal line D.

FIG. 6 is an electric circuit diagram of the element circuit Aa. This element circuit Aa is different from the aforementioned element circuit A in that
While another scanning signal line G is selected, the element circuit Aa
In order to switch the display to a blank display, another active element, a gate is connected to the scanning signal line S, a source (drain) is connected to the capacitor C1, and a drain (source) is initialized (organic EL) The potential for rendering the element P non-display) (the potential of the power supply line E in the example of FIG. 6).
And an n-type TFT Q3. This T
When the FTQ3 conducts, the data stored in the capacitor C1 is erased, and the organic EL element P performs the blank display. The configuration of the element circuit Aa shown in FIG.
SID '00 DIGES by Inukai et al.
T, pages 924 to 927.

FIG. 7 is a diagram showing an example of a method of driving the organic EL display 11 by time division gray scale.
In the example of FIG. 7, the scanning signal lines of the organic EL panel 2a are assumed to be one unit with 15 lines G1 to G15.
The selection states of the scanning signal lines G1 to G15 are shown in FIGS.
This is indicated by (17). FIG. 7B shows the weight of the bit. FIG. 7 (1) shows a unit time display within a period of each section, and FIG. 7 (18) shows a total time display (the number of unit times). One frame period Tf is composed of 60 unit times. I have.

In this scanning example, as in the scanning example of FIG. 4, the one-frame period Tf is composed of a current measuring period Tm and a display period Ta.
z]. In the current measurement period Tm, the scanning signal lines G1 to G15 are sequentially selected, and at this time, the memory Ma applies a predetermined voltage to the organic EL element P of each element circuit Aa. It is measured in order.

The subsequent display period Ta also includes a light emitting period Td and an erasing period Tsa. Within the light emission period Td, four scanning periods Ts1 to Ts corresponding to each bit
4 is set. In this scanning example, the weight of one bit is 2
It corresponds to a unit time. In the first scanning period Ts1,
The scanning signal lines G1 to G15 are sequentially selected, the data signal of bit1 is taken into the capacitor C1, and the display is performed, and after two unit time, the scanning signal lines S1 to S15 are sequentially selected and Blank scanning is performed. . Next scanning period Ts
2, the scanning signal lines G1 to G15 are sequentially selected, the data signal of bit2 is taken into the capacitor C1, and the display is performed. After four unit time, the scanning signal lines S1 to S15 are sequentially selected and the blank scanning is performed. Is performed.

Subsequently, in the scanning period Ts3, the scanning signal lines G1 to G15 are sequentially selected, and the capacitor C1 is set to bi.
The data signal at t3 is taken in and the display is performed. This b
With the weight of it3, display is performed over 8 unit times,
The scanning period Ts4 continues without performing the blank scanning.
Then, the data signal of bit 4 is taken in, and the display is performed for 16 unit times. Thus, the ratio of the display period of each bit is 1: 2: 4: 8. When the display of bit 4 is completed, the erasing period T consisting of 7 unit times is set.
sa, and Blan in preparation for the next current measurement period Tm.
k scans are performed.

As described above, the scanning signal line S and the TFT Q3
Is provided, the display started by the scanning signal line G is switched to the blank display by scanning with the scanning signal line S, and the unit display time is made shorter than the scanning period Ts to perform digital gradation control. Bit data can be accurately displayed in a short time corresponding to the weight of the bit, and fine gradation control with a large number of bits can be performed.

In the driving method shown in FIG. 7, the scanning during the light emission period Td is performed by the SID '00 DIGEST.
Pp. 924 to 927, and the example of FIG.
Further, by setting the erasing period Tsa and the current measuring period Tm, the current measurement is realized while performing the time division gray scale.

In the light emission period Td, the light emission potential stored in the capacitor C1 of each element circuit A is set for each element circuit A based on the current value of each element circuit A measured in the current measurement period Tm. Is done. That is, a predetermined voltage is stored in the capacitor C1 of each element circuit A in the current measurement period Tm, and at this time, a current value flowing through the organic EL element P of each element circuit A is measured using the current measurement circuit K, Based on the result, a correction value for each element circuit A is created and stored in the memory M. When the data is at the light emission potential in the light emission period Td, the D / A conversion circuit F generates a voltage based on the correction value for each element circuit A, and stores the light emission potential in the capacitor C1 of each element circuit A.

FIG. 8 shows a third embodiment of the present invention.
15 will be described below.

FIG. 8 shows an organic E according to a third embodiment of the present invention.
FIG. 9 is a diagram showing the entire configuration of the L display 21. FIG. 9 is an electric circuit diagram of an element circuit Ab in the organic EL panel 2b of the organic EL display 21. This organic EL
The display 11 is the organic EL display 1 described above.
Similar to FIG. 11, corresponding portions are denoted by the same reference numerals and description thereof is omitted.

The organic EL display 21 employs a special scanning method as described later. Before describing the structure, the scanning method of FIG. 7 will be described in detail. In the scanning method of FIG. 7, the scanning time required for 4-bit time division gray scale display is one scanning time of 7 × 5 (= 4b
(it minutes + Blank minutes) = 35 unit times, whereas the necessary display period Ta is the scanning time of the first bit 7+
Second-bit scanning time 7 + 3-bit light-emitting period 8 + 4
Light emission period of the 16th bit + Blank scanning time 7 = 45
Unit time. In the display period Ta, the time actually used for light emission is 2 + 4 + 8 + 16 = 30 unit time.

As described above, in the driving method shown in FIG. 7, since there are many periods during which scanning is not performed in the display period Ta and periods that are not used for light emission, the time per scan is shortened accordingly and high speed is achieved. Since it is necessary to scan, the controller 3
It is necessary to increase the speed of the drive circuits and active elements such as a and 4. In addition, the fact that there is a time during which no light is used during the display period Ta means that the light emission intensity per unit time must be increased accordingly, and the current flowing through the organic EL element P increases by that much, and the time-dependent change occurs. The problem is that it wakes up quickly.

Therefore, as a driving method of the time division gradation which can eliminate the non-scanning period and the non-light emitting period in the display period Ta, it is conceivable to use the driving method of Japanese Patent Application Laid-Open No. 63-226178. . FIG. 10 is a diagram showing a driving method according to the prior art. In the example of FIG.
The scanning signal lines of the matrix type display are G1 to G15.
Are assumed to be one unit, and the selection states of the scanning signal lines G1 to G15 are shown in FIGS. 10 (3) to (17), respectively. Then, each pixel has 16 gradations (4b
It) realizes the gradation display of each bit, and the weight of each bit 1:
Each pixel performs a corresponding binary display for a time proportional to 2: 4: 8. FIG. 10A shows a unit time, and one frame period Tf is composed of 15 unit times. FIG. 10B shows the weight of the bit.

Each pixel has a memory element.
In (3) to (17), the diagonal lines indicate that they are selected by the scanning signal line, and the state is held until the next diagonal line. Thus, the ratio of the display period of each bit is 1: 2: 4: 8.

However, it is impossible to simultaneously write different data to a plurality of pixels respectively corresponding to different scanning signal lines using a common data signal line. As shown as a partial time in 11 (2), each unit time in FIG. 10 (1) is further divided by the number 4 of bits, and the first bit is written in the first partial time of each unit time. In the second partial time, the second bit is written, in the third partial time, the third bit is written, and in the fourth partial time, the fourth bit is written.
By performing the writing of the bit, the time division gradation control as shown in FIG. 10 is enabled. Note that FIG.
The unit time of (1) is shown in FIG. 10 (1), the bit weight of FIG. 11 (3) is shown in FIG. 10 (2), and FIGS. 11 (4) to (18).
Corresponds to FIGS. 10 (3) to (17), respectively. FIG. 11 (19) shows the total of the partial time.

When the erasing period Tsa and the current measuring period Tm are introduced into this prior art, FIGS.
It becomes as shown by. FIG. 12 (1) to FIG. 12 (17)
10 (1) to 10 (17) respectively, and FIG. 12 (18) shows the total time. FIG.
FIG. 13 shows the details of FIG. 11 and FIG. 12 together, and FIG. 13 (1) to FIG.
1 (1) to FIG. 11 (18), and FIG.
9) is a display of the total time.

Therefore, for example, as shown in FIG. 12, the element circuits Ab11 to Ab1n corresponding to the scanning signal line G1 have the current measurement period Tm ended and the display period Ta
Display the data of bit1 from the first unit time during
Bit 2 data is displayed from the second unit time, bit 3 data is displayed from the fourth unit time, bit 4 data is displayed from the eighth unit time, and Blank data is displayed from the 16th unit time.

The same unit time is composed of four partial times as shown in FIG. 13, and writing corresponding to different bits is performed in each partial time. In the first partial time of each unit time, bit 1 is written, in the second partial time, bit 2 is written, and in the third partial time, bit 3 is written.
Is written, and bit4 is written in the fourth partial time.

That is, for example, as shown in FIG. 13D, bit 1 data is written and displayed in the element circuits Ab11 to Ab1n corresponding to the scanning signal line G1 in the first partial time of the first unit time. , Blank data is written and displayed at the first partial time of the second unit time. Bit 2 data is written and displayed at the second partial time of the second unit time, and Blank data is written and displayed at the second partial time of the fourth unit time. Bit 3 data is written and displayed in the third partial time of the fourth unit time, and Blank data is written and displayed in the third partial time of the eighth unit time. The data of bit 4 is written and displayed at the fourth partial time of the eighth unit time, and B is written at the fourth partial time of the 16th unit time.
Write the rank data and display it. Then, as shown in FIG. 13 (5), writing is performed on the element circuits Ab21 to Ab2n corresponding to the next scanning signal line G2 with a delay of one unit time from the timing of the scanning signal line G1. Thereafter, writing is sequentially performed with a delay of one unit time for each scanning signal line.

However, in such a driving method, the first
Although the scanning signal line G1 must return to the display of bit1 in seven unit times, the current measurement period Tm and the display period Ta
If they continue alternately, they cannot do so. For this reason,
As shown in FIG. 13, the time used for light emission is 4 + 8 +
In order to secure 16 + 32 = 60 partial times, 60 partial times of the erasing period Tsa in which the scanning signal lines G1 to G15 are sequentially scanned and erased during the 60 partial times of the light emitting period Td are required. Time is required as the display period Ta. Also, during this display period Ta,
The time actually used for scanning is only 60 partial hours. When time-division gray scale display is performed by a display device having the current measurement period Tm as in the present invention, such a display period T
In order to shorten the non-scanning period and the time not used for light emission in a, a scanning method different from the conventional method is required.

Therefore, it should be noted that in the organic EL display 21, as shown in FIG.
Has a plurality of (two in the example of FIG. 9) pixel memories R1 and R2.
2 and a scanning controller 3b as shown in FIG.
Means that the stored contents are read out by the corresponding bit select lines Sa and Sb and set in the capacitor C1. The bit selection lines Sa and Sb are organic E
On the L panel 2b, it is arranged in parallel with the scanning signal line G so as to penetrate the element circuit Ab. The pixel memory R
1 and R2 are the same as those of the circuit element A of FIG. 2, and an n-type TFT Q1 that takes in a data signal from the corresponding data signal line D while being selected by the scanning signal line G.
A capacitor C1 for holding a data signal captured by the TFT Q1, an organic EL element P, and a p for controlling a current flowing from the power supply line E to the organic EL element P in accordance with the charging voltage of the capacitor C1. TFT Q2.

Each of the pixel memories R1 and R2 is configured to be equal to each other, and is a single stage composed of an n-type TFT Q10 as an active element for controlling writing / reading of the data signal, a p-type TFT Q11 and an n-type TFT Q12. Eye CMOS inverter INV1 and p-type TFT Q13
And a second-stage CMOS inverter INV2 comprising an n-type TFT Q14. The power supply voltage of the CMOS inverters INV1 and INV2 is equal to the power supply line E
And a voltage between the ground potential and the CMOS inverter I
The output of NV1 is applied to the input of CMOS inverter INV2, and the output of CMOS inverter INV2 is
The signal is fed back to the input of the inverter INV1, and self-holding, that is, memory operation is performed. The bit selection lines Sa and Sb are connected to the gates of the pixel memories R1 and R2, respectively.

Therefore, when the bit line selection line Sa, Sb is selected and the TFT Q10 is turned on while the scanning signal line G is selected, that is, the TFT Q1 is turned on, the data signal line is sent to the pixel memories R1, R2. A data signal is written from D and the scanning signal line G is not selected, that is, while the TFT Q1 is cut off, the bit selection line S
When a and Sb are selected and the TFT Q10 is turned on, the data signal is read from the pixel memories R1 and R2 and set in the capacitor C1. Further, the bit selection lines Sa,
When the scanning signal line G is selected while Sb is not selected, that is, when the TFT Q10 is turned off, that is, when the TFT Q1 is turned on, the data signal is not written in the pixel memories R1 and R2, but is set only on the capacitor C1. Is done.

In order to set the data signal read from the pixel memories R1 and R2 to the capacitor C1, the charge stored in the capacitor C1 causes the stored contents of the pixel memories R1 and R2 to be rewritten. So that the capacitance of the capacitor C1 can be controlled within a range in which the TFT Q2 can be controlled for the longest time to be controlled.
It is desirable to set the value as small as possible.

Referring to FIG. 8, in organic EL display 21, D / A in organic EL display 1 in FIG.
The conversion circuits F1 to Fn are replaced with the memories Mb1 to Mb.
bn (to be collectively referred to as Mb hereinafter) is inserted. The input display data is measured for each element circuit A, corrected in the arithmetic circuit B based on the correction value stored in the memory M, and the data to be displayed for each element circuit A thus obtained. Is the memory Mb
Is stored in

On the other hand, although not particularly related to the above-described scanning method, the signal controller 4b includes the power supply lines E1 to E1.
A current measuring circuit K0 is provided in common for En, and the current measuring circuit K0 performs a multiplex operation on each of the power supply lines E1 to En to sequentially measure the load current, and stores the corresponding memories M1 to M1. Output to Mn. By using the common current measurement circuit K0 in this manner, measurement variations can be eliminated.

However, as described above, each power line E1
To En, the current measuring circuits K1 to Kn are individually provided, all the element circuits Ab within one current measuring period Tm.
Measurements for 11 to Abmn can be made. Therefore, in the multiplex operation, in response to the selection output to the scanning signal line G, all the element circuits Ab of one line are set within one scanning period in which each scanning signal line G is selected.
Measurement is performed for i1 to Abin (i represents an arbitrary line), that is, as in the examples of FIGS.
All the element circuits Ab11 to Ab within the current measurement period Tm
bmn may be measured, or one or more, for example, three RGB element circuits may be measured per line during the one scanning period. The number of measurement elements may be set according to a desired measurement cycle. However, since the current measurement period Tm becomes longer, it is more preferable to perform the measurement for each of the three RGB element circuits than to perform the measurement for all the element circuits Ab11 to Abmn within one current measurement period Tm.

The organic EL display 21 having the following scanning method may be provided with the current measuring circuits K 1 to Kn. It goes without saying that the circuit K0 may be used.

FIG. 14 shows the structure of the organic E formed as described above.
FIG. 9 is a diagram illustrating an example of a driving method using time division gray scale by the L display 21. In FIG. 14, the current measurement period T
The display period Ta after the completion of m is described. Also in this example, the scanning signal lines of the organic EL panel 2b are G1 to G15.
14 are assumed to be one unit, and the selection states of the scanning signal lines G1 to G15 are shown in FIGS. 14 (7) to (21). FIG. 14A shows a unit time display, and FIG.
4 (22) is a total time display (unit time number). FIG. 14C shows the total display time of bit 4 data,
FIG. 14 (5) shows the total display time of bit 3 data. FIG. 14 (6) shows bit weights.

It should be noted that the bit selection line Sa1 shown in FIG. 14 (2) (Sa1 to Sa15 should be described in correspondence with the scanning signal lines G1 to G15, but only Sa1 for simplification of the drawing) The same applies to the following bit selection line Sb.) And the scanning of FIG.
Is a selection scan of the bit selection line Sb1 shown in FIG. The bit selection lines Sa and Sb are in a non-selected state unless otherwise specified. In FIGS. 14 (2) and (4), a high level H indicates a selected state. B is stored in the pixel memories R1 and R2.
It is assumed that it4 data and bit3 data are respectively stored. Each scanning period Ts1 to Ts4 is 15
Consists of unit time.

In the first scanning period Ts1 of the display period Ta, the scanning signal lines G1 to G15 are sequentially selected and bit
While displaying the data of No. 4, the bit selection line Sa is selected, and the data of the bit 4 is written into the pixel memory R1. The data of the bit 4 is displayed until the selection of the scanning signal lines G1 to G15 is completed, that is, for 15 unit times.

When the scanning period Ts1 ends, the next scanning period Ts2 is successively entered. While switching the display from the data corresponding to bit4 to the data of bit3, the bit selection line Sb is selected and the data of bit3 is stored in the pixel memory. R
It is written to 2. Then, after the data of the bit 3 is displayed for 9 unit times in the scanning period Ts2, the bit selection line Sa is selected so as to follow the selection while the scanning signal lines G1 to G15 are not selected. The data of bit 4 is read from the pixel memory R1 and is displayed over the remaining six unit times. This gives b
The total display time of the data of it4 is 21 unit times.

When the scanning period Ts2 ends in this manner, in the scanning period Ts3, the display is switched from the data corresponding to bit4 to the data of bit2, and after the display is performed for eight unit times, the scanning signal lines G1 to G15 are not selected. In the state, the bit selection line Sb
Is selected, the data of bit 3 is read from the pixel memory R2, and is displayed over the remaining six unit times. As a result, the total display time of the data of bit 3 is 16 unit times.

In the scanning period Ts4, the display is switched from the data corresponding to bit3 to the data of bit1, and after displaying for 4 unit times, the bit selection line Sa is selected and the data of bit4 is read out again from the pixel memory R1. ,
It is displayed for the remaining 11 unit times. As a result, the total display time of the data of bit 4 is 32 unit times, and the ratio of the display period of each bit is 1: 2: 4:
It becomes 8.

When the scanning period Ts4 ends, the next erasing period Tsa continues, and the display is switched from the data in the pixel memory R1 corresponding to bit4 to the data corresponding to the non-light emitting state, and held in the capacitor C1. As it goes, a blank display is performed. By temporarily erasing the load current flowing through all the circuit elements Ab by the selection in the erasing period Tsa, measurement in the next current measuring period Tm becomes possible. In the erasing period Tsa, the data in the pixel memories R1 and R2 may be erased together with the erasing of the data in the capacitor C1, as shown in FIG.

By performing such scanning, the display period Ta required for 4-bit time division gray scale display is one scanning period 15 × (4 bits + Blank) = 75 unit times. , The time actually used for light emission
4 + 8 + 16 + 32 = 60 unit time.

As described above, using the pixel memories R1 and R2,
By selecting the bit selection lines Sa and Sb when not selected by the scanning signal line G, the data of the upper bits can be read and displayed at an arbitrary timing.
As a result, when the display of the lower bit data is completed, the remaining time of the lower bit in the scanning period Ts can be used for displaying the upper bit data. Even when the scanning period is set, a new time-division gray scale display can be realized in which the period during which scanning is not performed in the display period Ta and the time during which light is not used can be reduced.

When most of the display period Ta is used for light emission as described above, it is possible to compensate for this by shortening the non-light-emission time in response to the darkening of the display with time. Since it disappears, so that the color of RGB is aligned,
It is preferable to adjust the current values of the organic EL elements of the remaining colors in accordance with the change over time in the current characteristics of the organic EL element.

The above-described driving method is effective in shortening a period during which scanning is not performed in the display period Ta and a period of time not being used for light emission even in a configuration in which the above-described current measurement is not performed. It is possible. Therefore, a driving method in a configuration having no current measurement period Tm is shown in FIG. FIG.
(1) to (22) correspond to FIGS. 14 (1) to (22), respectively. It should be noted that the erasing period Tsa is eliminated, and the light emitting period Td becomes the display period Ta and the frame period Tf as they are.

In such a case, the above-mentioned Japanese Patent Application Laid-Open No.
Compared with the time division gray scale display method of No. 226178, by shortening the non-scanning period and the non-light-emitting time in the display period Ta, it is possible to obtain the same or higher scanning and light-emitting efficiency. , The control can be easily performed.

In the present driving method, the number of scanning signal lines G is set to 15 such that the time used for light emission = the scanning time required for time-division gray scale display (1). Table 1 shows the results obtained by examining the conditions satisfying Expression 1 for 4-bit gradation display.

[0082]

[Table 1]

In Table 1, (a) is the number of bits, (b)
Is the number of scanning signal lines, (c) is the number of scanning signal lines × bit number = scanning time required for time-division gray scale display, (d) is a display period per gray scale, and (e) is used for light emission. This is a gradation display period. (F) is a judgment, and “▲” means that the number of scanning signal lines × the number of bits> time-division gray scale display and gray scale display is not possible with this configuration, and “△” means If the scanning is discontinuous, 4-bit gradation display is possible, and “○” is the case where the expression 1 is satisfied and gradation display is possible.

Further, although “△” is shown in (f), gradation display is possible, but when the number of display gradations is limited unless the scanning is discontinuous, it is possible to display by making the scanning continuous. The number of gradations is shown in (g). Further, (h) indicates the number of required pixel memory elements, and indicates that the number of memory elements required is the number of “○”. In addition, what is shown in Table 1 is
Only when the required number of memories is 2 or less.

On the other hand, Table 2 similarly shows the results of determining the feasibility in the case of 2-bit gradation display.
The contents of (h) correspond to Table 1, respectively.

[0086]

[Table 2]

It is understood from Table 2 that when the number of scanning signal lines is a multiple of three, the above-mentioned expression 1 is satisfied. Note that Table 1 shows only the case where the required number of memories is one.

Table 3 also shows the feasibility determination results in the case of 3-bit gradation display.
The contents of (h) correspond to Tables 1 and 2, respectively.

[0089]

[Table 3]

It is understood from Table 3 that when the number of scanning signal lines is a multiple of seven, the above-mentioned expression 1 is satisfied. Table 3 shows only the case where the number of required memories is one.

FIG. 1 shows a fourth embodiment of the present invention.
The following is a description based on FIGS.

FIG. 16 is an electric circuit diagram of the element circuit Ac in the organic EL display according to the fourth embodiment of the present invention. The element circuit Ac is similar to the element circuit Aa shown in FIG. 6 and the element circuit Ab shown in FIG. 9, and corresponding parts are denoted by the same reference numerals and description thereof is omitted. It should be noted that this element circuit Ac includes a pixel memory R1 and a TFT Q3 for erasing stored data by connecting the capacitor C1 (and the pixel memory R1) to an initialization potential. It is.

A driving method using such an element circuit Ac is as shown in FIG. FIG. 17A shows a partial time obtained by dividing the scanning period Ts into eight equal parts, and FIG.
The total display time of the data at t4 is shown, FIG. 17 (5) shows the bit weight, and (22) shows the total time display.
FIG. 14 (2) shows the selective scanning of the bit selection line Sa1, and FIG. 14 (4) shows the selective scanning of the scanning signal line S1.
On the other hand, in this example, 16 scanning signal lines G1 to G16 are assumed to be one unit, and FIG. 17 (6) to (21)
Indicates each selection state. The current measurement period Tm
Will be omitted, and only the subsequent display period Ta will be described.

During the first scanning period Ts1 of the display period Ta, b
While displaying the data of it4, the data is stored in the pixel memory R1 via the TFT Q10. When the selection of the scanning signal lines G1 to G16 is completed, the next scanning period Ts2 is successively entered, and the display is switched from the data corresponding to bit4 to the data of bit3. At this time, the scanning period Ts is set longer than the data display period corresponding to bit3, and when the display period of the data corresponding to bit3 ends as described above, the data to be displayed so as to follow the scan corresponds to bit4. Although the scan for switching to the changed data may be performed, in the example of FIG. 17, such a scan is not inserted since the data display period corresponds to the scan period Ts = bit3.

When the scanning for displaying the data corresponding to bit 3 is completed for the scanning signal lines G1 to G16, the next scanning period Ts3 is continuously entered, and the display is switched to the data corresponding to bit 2. In order to follow this scanning, the selection scanning of the bit selection line Sa is started after four partial times, and T
Data is read from the pixel memory R1 via the FTQ10, and data corresponding to bit4 is displayed again.
When the scanning for holding the data corresponding to bit2 in the capacitor C1 is completed for the scanning signal lines G1 to G16, the next scanning period Ts4 is successively entered, and the display is switched to the data corresponding to bit1. As you follow this scan,
After two partial hours, the data is read from the pixel memory R1, and the data corresponding to bit 4 is displayed again. Until the display corresponding to the data of the last bit4, 8 + 4
Since the display is performed only for 12 partial times, the scanning signal line S is selectively scanned after 4 partial times so as to follow this scan, the data of the capacitor C1 is erased, and a blank display is performed in the next current measurement period Tm. I do. At this time,
As shown in FIG. 17, the bit selection line Sa may also perform selective scanning to erase data in the pixel memory R1.

As described above, in the last scanning period Ts4, if the display of data corresponding to bit 4 (= display of all data) is completed and an extra time is left,
At that time, the scanning signal lines G1 to G16 and the bit selection line S
By performing the erase scan by the selective scan of the scan signal line S capable of performing the scan independent of a, the time used for light emission for n bits = nb in each of the above-described embodiments.
If it is not the time necessary for scanning for it, there are problems such as extra scanning time is required and the number of display gradations is reduced. In the present embodiment, such a problem is solved. Can be eliminated.

Although the number of scanning signal lines is set to 16 in FIG. 17, the number of scanning signal lines is equal to or more than the display period of bit 3 (2) Time used for light emission ≧ number of scanning signal lines × (number of bits) 4-1) Display period of + bit1 (3) Scanning time required for time-division gray scale display ≧ time used for light emission (4) The number of scanning signal lines is selected from the number of scanning signal lines. Table 4 shows the results of examining the conditions satisfying these expressions 2 to 4 for 4-bit gray scale display.

[0098]

[Table 4]

In Table 4, (a) is the number of bits, and (b)
Is the number of scanning signal lines, (c) is the number of scanning signal lines × bit number = scanning time required for time-division gray scale display, (d) is a display period per gray scale, (e) is a display period of bit 3, (F) is the display period of the number of scanning signal lines × (bit number 4-1) + bit1, and (g) is the gradation display period used for light emission.
(H) is a determination. “▲” indicates that the display can be performed at the 4-bit gray scale but the light emission period is discontinuous, and “△” indicates that the display can be performed at the 4-bit gray scale. In addition, the light emission period is continuous, and “○” is the case where the above Expressions 2 to 4 are satisfied.

From Table 4, it can be seen that the number of scanning signal lines is 4, 8, 9, 1
In the case of 2,13,14,16 lines (below but omitted)
It is understood that the above equations 2 to 4 are satisfied. FIG.
Then, 16 scanning signal lines G1 to G16 and 4 bit
This is a gradation display, and the display scanning is continuously performed as shown by the solid line, which matches the results in Table 4.

On the other hand, Table 5 similarly shows the feasibility determination results in the case of 2-bit gradation display.
The contents of (h) correspond to Table 4 respectively.

[0102]

[Table 5]

From Table 5, it can be seen that the number of scanning signal lines is 2, 3,
In the case of 4, 5, 6 (the following is omitted), the above formulas 2 to 4
It is understood that the above is satisfied.

Table 6 also shows the determination results of the feasibility in the case of 3-bit gradation display.
The contents of (h) correspond to Tables 4 and 5, respectively.

[0105]

[Table 6]

It is understood from Table 6 that the number of scanning signal lines is 3, 5,
It is understood that in the cases of 6, 7, 8, 9, and 10 (hereinafter, omitted but omitted), the above Expressions 2 to 4 are satisfied.

The scanning method shown in FIG. 17 can be applied to a configuration in which no current is measured, similarly to the scanning method shown in FIG. 14, and an example of a driving method in that case is shown in FIG. Show. FIGS. 18 (1) to (22) correspond to FIG.
7 (1) to 7 (22). With this configuration, even when the current is not measured, the time used for light emission for n bitsｂnbit
Scanning in the time required for minute scanning can be realized.

FIG. 19 shows an example of a driving method when the light emission in Table 4 is discontinuous. This FIG.
Is an example of 4-bit “で” in Table 4 (h).
A case where ten scanning signal lines G1 to G10 are shown, which is an example of a determination in which light emission periods are discontinuous although display is possible in gradations, is shown. FIGS. 19 (1) to 19 (5) and (16) show FIG.
(1) to (5) and (22), respectively, and the selection states of the scanning signal lines G1 to G10 are respectively shown in FIG.
(6) to (15). In FIG. 19A, the scanning period Ts is divided into ten equal parts.

During the first scanning period Ts1 of the display period Ta, b
While displaying the data of it4, the data is stored in the pixel memory R1 via the TFT Q10. In order to immediately follow the scanning, the scanning signal line S is selectively scanned after one partial time, and the data of the capacitor C1 is scanned. Is erased, and a blank display is performed. When the selection of the scanning signal lines G1 to G10 is completed by this scanning, the next scanning period Ts2 is successively entered, and the display is switched from the data corresponding to bit4 to the data corresponding to bit1. In order to follow this scanning, the bit selection line Sa is selectively scanned after two partial times, data is read from the pixel memory R1 via the TFT Q10, and data corresponding to bit4 is displayed.

When the scanning for displaying the data corresponding to bit 1 is completed for the scanning signal lines G1 to G10, the next scanning period Ts3 is continuously entered, and the display is switched to the data corresponding to bit 3. In order to follow this scanning, the selection scanning of the bit selection line Sa is started after 8 partial time, and T
Data is read from the pixel memory R1 via the FTQ10, and data corresponding to bit4 is displayed again.
When the scanning for holding the data corresponding to bit 3 in the capacitor C1 is completed for the scanning signal lines G1 to G10, the next scanning period Ts4 is continuously entered to switch the display to the data corresponding to bit 2. As you follow this scan,
After four partial hours, the data is read from the pixel memory R1, and the data corresponding to bit 4 is displayed again. 1 + 8 before the display corresponding to the data of the last bit 4
Since + 2 = 11 partial time periods are displayed, the scanning signal line S is selectively scanned after 5 partial time periods so as to follow this scan, the data of the capacitor C1 is erased, and blanking is performed in the next current measurement period Tm. Display.

As described above, if the existence of the display period Td discrete in one frame period Tf is allowed,
As in the case of the scan in FIG. 17, it is possible to realize the scan for the time required for the scan for n bits, which is the time used for light emission for n bits.

The driving method shown in FIG. 19 also corresponds to the driving method shown in FIG.
Similar to the driving method shown in FIGS. 4 and 17, a configuration in which current measurement is not performed can also be applied. An example of the driving method in that case is shown in FIG. 20. FIGS. 20 (1) to (1)
6) respectively correspond to FIGS. 19 (1) to 19 (16).

FIG. 2 shows a fifth embodiment of the present invention.
The following is a description based on FIGS. 1 to 23.

FIG. 21 is an electric circuit diagram of the element circuit Ad in the organic EL display according to the fifth embodiment of the present invention. This element circuit Ad is similar to the element circuit Ac shown in FIG. 16 described above, and corresponding portions are denoted by the same reference numerals and description thereof is omitted. It should be noted that the element circuit Ad includes another power line Ea for logic independent of the power line E, and the capacitor C1 and the pixel memory R1 are connected to the power line Ea. is there.

By providing this new logic power supply line Ea, the scanning shown in FIG. 19 can be changed as shown in FIG. FIGS. 22 (1) to (3), (5) to
(17) corresponds to FIGS. 19 (1) to (3) and (4) to (16).
Respectively. FIG. 22D shows the voltage of the power supply line E. In this example, the voltage can be changed between the VDD potential and the GND potential.

First, a current measurement period Tm is provided at the beginning of one frame period Tf, during which period the current of each element circuit Ad is measured with the power supply line E set to the VDD potential. Next, in the scanning period Ts1, the power supply line E is set to the GND potential and
4 is stored in the pixel memory R1. To follow this scan, blank display is performed after one unit time, and a potential corresponding to the non-light emitting state is held in the capacitor C1. In this scanning period Ts1, the power supply line E
Is the GND potential as described above, so that the organic EL
The element P does not emit light.

When such bit 4 data is sequentially written to the pixel memory R1 with respect to the scanning signal lines G1 to G10, after the power supply line E is set to the VDD potential, the next scanning period Ts2 is entered. The data corresponding to bit1 is displayed. Then, the data in the pixel memory R1 is read out after two unit time to follow this scan,
The display corresponding to the data at t4 is performed for the first time.

In the scanning period Ts3, data corresponding to bit 3 is displayed.
After a unit time, the data in the pixel memory R1 is read out,
The display corresponding to the data of bit 4 is performed again. Also in the scanning period Ts4, after the data corresponding to bit2 is displayed, the data in the pixel memory R1 is read out four unit times later, and the display corresponding to the data in bit4 is performed again. Thus, the data corresponding to bit 4 is 8 + 2 +
6 = 16 unit times are displayed. Thereafter, the erasing period Tsa
Then, once the current flowing through all the circuit elements Ad is cleared, the current can be measured in the next current measurement period Tm.

As described above, by writing data to the pixel memory R1 while controlling the power supply line E of the organic EL element P, the number of scanning signal lines indicated by “▲” in the judgment (h) of Table 4 is obtained. (Display of the same one frame) can be continuously displayed, and the limitation on the number of scanning signal lines can be eliminated.

The driving method shown in FIG. 22 is also the same as that shown in FIG.
Similar to the driving method shown in FIGS. 4 and 17, a configuration in which current measurement is not performed can also be applied, and an example of the driving method in that case is shown in FIG. FIGS. 23 (1) to 23 (1)
7) corresponds to FIGS. 22 (1) to (17), respectively.

FIG. 2 shows a sixth embodiment of the present invention.
The following is a description based on FIGS. 4 to 26.

FIG. 24 is an electric circuit diagram of the element circuit Ae in the organic EL display according to the sixth embodiment of the present invention. The element circuit Ae is similar to the element circuit Ad shown in FIG. 21 described above, and corresponding portions are denoted by the same reference numerals and description thereof is omitted. It should be noted that in the element circuit Ae, the selection signal line S and the TFT Q3 corresponding thereto are not provided. That is, when the power supply line E of the organic EL element P and the power supply line Ea of the pixel memory R1 are individually controlled as in the element circuit Ad described above, the TF for initialization is controlled as in the element circuit Ae.
Even in a configuration without TQ3, equivalent display can be performed.

FIG. 25 is a diagram showing an example of a method of driving the element circuit Ae. 25 (1) to (4), (5),
(14) corresponds to FIGS. 22 (1) to (4), (6) and (17).
Respectively. In this example, the scanning signal line is G
1 to G8, and the selected state is shown in FIG.
(6) to (13) are shown. In FIG. 25A, the scanning period Ts is equally divided into eight.

First, a current measurement period Tm is provided at the beginning of one frame period Tf, and in that period, the current of each element circuit Ae is measured with the power supply line E set to the VDD potential. Next, in the scanning period Ts1, the power supply line E is set to the GND potential and
4 is stored in the pixel memory R1. In order to follow this scanning, in the above-described element circuit Ad, blank display data is set in the capacitor C1 after one unit time, whereas in this element circuit Ae, blank scanning is not performed. Is the GND potential as described above, the organic EL element P does not emit light.

When such bit 4 data is written to the pixel memory R1 in order on the scanning signal lines G1 to G8, the power supply line E is set to the VDD potential, and then the next scanning period Ts2 is entered. The data corresponding to bit1 is displayed. Then, after two unit times, the data in the pixel memory R1 is read out and the bit
The display corresponding to the data No. 4 is performed for the first time.

In the scanning period Ts3, data corresponding to bit 3 is displayed over the entire length of the scanning unit Ts3 for 8 unit times, and when the display of the data in bit 3 is completed, the next scanning period Ts4 is entered and bit 2 is entered. Four units of time after the corresponding data is displayed, the data in the pixel memory R1 is read, and the display corresponding to the data in bit4 is performed again. When the reading of the data of bit 4 is completed for all the scanning signal lines G1 to G8, the data corresponding to bit 4 is displayed for 6 + 8 = 14 unit times, so that the data is erased after another 2 unit times. Period Tsa
And the potential of the power supply line E is set to the GND potential.
By clearing the current flowing through all circuit elements Ae,
Current measurement can be performed in the next current measurement period Tm.

Here, the conditions under which the above-described scanning is possible are as follows: time used for light emission ≧ (number of scanning signal lines × (number of bits 4-1) + display period of bit 1) (5). Therefore, even if the determination (f) in Table 1 indicates “▲” and the display cannot be performed, the above Expression 5 is satisfied. Therefore, the scanning becomes discontinuous as shown in FIG. The display in the key is possible. As described above, by employing this driving method, the above-described problem of the limitation on the number of scanning signal lines can be eased.

FIG. 26 shows a driving method shown in FIG.
FIG. 4 is a diagram illustrating an example of a driving method when current measurement is not performed. FIGS. 26 (1) to (14) show FIGS. 25 (1) to (1).
4) respectively.

FIG. 2 shows a seventh embodiment of the present invention.
7 and FIG. 28 are as follows.

FIG. 27 is an electric circuit diagram of the element circuit Af in the organic EL display according to the seventh embodiment of the present invention. The element circuit Af is similar to the element circuit Ad shown in FIG. 21 described above, and corresponding portions are denoted by the same reference numerals and description thereof is omitted. It should be noted that this element circuit Af includes two pixel memories R21 and R22, which are constituted by capacitors C21 and C22 and n-type TFTs Q21 and Q22 inserted in series with the capacitors C21 and C22. It is. On the other hand, the capacitor C1 is connected to a power supply line E via an n-type TFT Q20, and the TFT Q20 is controlled by a selection line Sc.

Therefore, the above-mentioned pixel memories R1, R2
Has stored digital data in a static memory configuration including CMOS inverters INV1 and INV2, whereas the pixel memories R21 and R22 can store analog data in a dynamic memory configuration including capacitors C21 and C22. Thus, the above-described digital gradation control and the analog gradation control based on the voltage value can be used together. When the storage time required for the pixel memories R21 and R22 is within one frame period Tf of several Hz or more as described above, even if the pixel memories R21 and R22 have a dynamic memory configuration as described above,
There is not much trouble. Further, even if the capacitors C21 and C22 are not newly formed, the potential can be held by using the floating element attached to the active element such as the TFT Q20 or the organic EL element P.

The TFT Q is controlled by the bit selection lines Sa and Sb.
When none of the transistors 21 and Q22 is conducting, the TFT Q20 is conducted by the selection line Sc and the capacitor C
Data writing / erasing / reading to 1 is performed. With this configuration, the luminance correction of the organic EL element P can be performed by using both the digital gradation control and the analog gradation control as described above.

The element circuit Ag of FIG. 28 is similar to the above-described element circuit Af, and controls the non-emission state of the organic EL element P and the write / erase / read state of data to / from the capacitor C1. Are realized individually.

An eighth embodiment of the present invention will be described with reference to FIG.
The following is a description based on FIGS. 9 to 31.

FIG. 29 is an electric circuit diagram of the element circuit Ah in the organic EL display according to the eighth embodiment of the present invention. This element circuit Ah is similar to the element circuit Ab shown in FIG. 9 described above, and corresponding portions are denoted by the same reference numerals and description thereof is omitted. In the element circuit Ah, the pixel memory R2 in the element circuit Ab is not provided, and only the pixel memory R1 is provided. This element circuit Ah, even in the case of one pixel memory R1, makes the scanning discontinuous as in the element circuit Ae, as described in detail below.
It is possible to perform it gray scale display.

FIG. 30 is a diagram showing an example of a driving method of the element circuit Ah. In FIG. 30, the current measurement period T
The display period Ta after the completion of m is described. In this example, 14 scanning signal lines G1 to G14 are assumed to be one unit, and the selection states of the scanning signal lines G1 to G14 are shown in FIGS. 30 (5) to (18). FIG.
(1) is a unit time display, and FIG. 30 (19) is a total time display (unit time number). FIG. 30 (3) shows the bit
4 shows the total display time of the data No. 4, and FIG. 30 (4) shows the bit weight. FIG. 30 (2) shows the bit selection line Sa
1 shows a selective scan.

In the first scanning period Ts1 of the display period Ta, the scanning signal lines G1 to G14 are sequentially selected and bit
While displaying the data of No. 4, the bit selection line Sa is selected, and the data of the bit 4 is written into the pixel memory R1. The data of the bit 4 is displayed until the selection of the scanning signal lines G1 to G14 is completed, that is, for 14 unit times.

When the scanning period Ts1 ends, the next scanning period Ts2 is successively entered, and the display is switched from the data corresponding to bit4 to the data of bit3 while the display of bit3 is changed.
Is displayed over the 16 unit time. Here, since the scanning period Ts2 is 14 unit times, after the scanning signal line G14 is selectively scanned, two unit times become a pause period.

When the pause period ends, the scanning period Ts
In 3, the display is changed from the data corresponding to bit3 to bit2.
After the display is switched over to 8 units of time and displayed for 8 unit times, the bit selection line Sa is selected and the data of bit 4 is stored in the pixel memory R1 so as to follow the selection while the scanning signal lines G1 to G14 are not selected. And displayed over the remaining six unit times. This gives b
The total display time of the data of it4 is 20 unit times.

In the scanning period Ts4, the display is switched from the data corresponding to bit 4 to the data of bit 1, and after displaying for 4 unit times, the bit selection line Sa is selected and the data of bit 4 is read out again from the pixel memory R1. ,
It is displayed for the remaining 10 unit times. The pause period of two unit times after the scanning period Ts4 is also the same as the bit period.
4 continues to be displayed. By this, the bit
The total display time of the data of No. 4 is 32 unit times, and each b
The ratio of the display period of it is 1: 2: 4: 8.

When the pause period ends, the next erase period Tsa starts, and the display is performed in the pixel memory R corresponding to bit 4.
The data is switched from the data of No. 1 to the data corresponding to the non-light emitting state, and the data is stored in the capacitor C1 and blank display is performed.

By performing the discontinuous scanning with the pause period inserted, even if one pixel memory R1 has four pixels,
Bit gradation display can be performed. However, the time actually used for scanning is longer than in the configuration including the erasing TFT Q3 as in the element circuit Ac of FIG. Table 7 shows the ratio.

[0143]

[Table 7]

In Table 7, (a) shows the number of bits (FIG. 30).
4), (b) is the number of scanning signal lines (14 in FIG. 30),
(C) is the time required for scanning (in FIG. 30, 4 × 14 =
56d), (d) is a display period per gradation,
(E) is the display period of the second bit (16 unit time in FIG. 30), (f) is the time actually used in this drive method (60 unit time in FIG. 30), and (h) is the actual use Time / ratio of time originally required for scanning.

Table 7 includes the conditions shown in FIG.
Some cases where the number of bits is 4, 5, and 6 are illustrated. From Table 7, although the ratio of the scanning time to the display period is reduced by about 20%, by performing the discontinuous scanning, the TFT Q3 for erasing and the TFT and the scanning signal line S by adding the scanning signal line S are added. An increase in the number of wirings can be avoided.

FIG. 31 shows a driving method shown in FIG.
FIG. 4 is a diagram illustrating an example of a driving method when current measurement is not performed. FIGS. 31 (1) to (19) show FIGS. 30 (1) to (1).
9) respectively. By the way, when such a current measurement is not performed, the element circuit A shown in FIG.
In c, there is a non-light emitting period as shown in FIG. 18, whereas in the element circuit Ah shown in FIG. 29, there is no non-light emitting period as shown in FIG. 31. That is, if there is no non-emission period,
Accordingly, the luminance per unit time for obtaining the required luminance as the average luminance in one frame period Tf can be reduced. The organic EL element tends to have a longer life as the instantaneous light emission luminance is lower even at the same light emission luminance. Therefore, it can be said that the driving method in FIG. 31 is more advantageous than the driving method in FIG.

The structure of the organic EL element P is realized by, for example, forming a transparent anode such as ITO on a glass substrate and forming an organic multilayer film and a cathode such as Al on the transparent anode. be able to. Although the organic multilayer film has several structures, for example, CuPc is used as a hole injecting layer (or an anode buffer layer), TPD is used as a hole transport layer, and DPVBi, Zn is used as a light emitting layer.
(Oxz) 2, Alq or the like using DCM as a dopant,
As the electron transport layer, a configuration in which Alq or the like is laminated is preferable.

On the other hand, as a TFT for driving the organic EL element P as described above, it is necessary to use a TFT manufactured by a polycrystalline silicon process having a large charge mobility, for example, Japanese Patent Application Laid-Open No. 10-301536. Can be realized. In the above steps, the maximum temperature of the process can be suppressed to about 600 ° C. at the time of forming the gate insulating film, and high heat-resistant glass can be used.

[0149]

As described above, according to the display device of the present invention, the load current is measured in the display device in which the electro-optical elements arranged in a matrix are driven by the first active elements. In correcting the display data based on the current, the current is periodically measured for each unit display period or for a plurality of unit display periods.

Therefore, in dynamically correcting display data for obtaining a desired gradation in response to a change in ambient temperature or the like, even if the panel is of an active matrix, the current measuring means must be connected to each electro-optical element. This eliminates the necessity of providing each time, the current value can be detected efficiently, and the aperture ratio can be improved.

In the display device of the present invention, as described above, in a configuration having a memory element, even when scanning is not performed, the display device emits light when display data is present, so that a load given a predetermined signal level is applied. When the current is measured, scanning is performed in advance to set the non-light-emitting state while the effect of the load current of the other electro-optical element is caused.

Therefore, the influence of the other electro-optical element can be eliminated, and the desired load current of the electro-optical element can be accurately measured.

Further, as described above, the display device of the present invention further includes a second active element in association with the memory element, and sets a display signal level by the first active element. The erase signal level is set by the two active elements.

Therefore, after the display is started by the selective scanning of the first active element and before the selective scanning is completed for all the first active elements, the selective scanning of the second active element is performed by the selective scanning. The display can be erased, and the unit display time can be shorter than the scanning period. Accordingly, in performing digital gradation control, it is possible to accurately perform short-time display corresponding to the weight of the lower-order bit data, and perform fine gradation control with a large number of bits. be able to.

In addition, as described above, the display device of the present invention is provided with one or a plurality of pixel memories in association with the memory elements, and the one or more pixel memories are provided for the first active element.
Are driven by a bit selection line different from the signal line of (1).

Therefore, in one scanning period, the remaining time of displaying lower-order bit data can be used for displaying higher-order bit data. , It is possible to realize a new time-division gray scale display in which the non-scanning period and the non-light emitting period in the display period can be shortened.

Further, as described above, in the display device of the present invention, the second power supply line provided separately from the first power supply line for supplying a load current to the electro-optical element is provided in the memory element. Power supply from.

Therefore, by setting the potential of the first power supply line to a potential at which the load current does not flow, for example, a GND potential while the first active element is selected, the memory can be displayed without performing display. Only the writing of the signal level to the element can be performed. In addition, the display period of the electro-optical element based on the data stored in the memory element or the pixel memory,
Control can be performed independently of the scanning period of the first active element, and time division gray scale display can be realized in the display period.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an overall configuration of an organic EL display according to a first embodiment of the present invention.

FIG. 2 is an electric circuit diagram of an element circuit in the organic EL display shown in FIG.

FIG. 3 is a graph showing current characteristics of the electro-optical element.

FIG. 4 is a diagram showing an example of a driving method of the organic EL display shown in FIG.

FIG. 5 is a diagram illustrating an overall configuration of an organic EL display according to a second embodiment of the present invention.

6 is an electric circuit diagram of an element circuit in the organic EL display shown in FIG.

FIG. 7 is a diagram showing an example of a driving method of the organic EL display shown in FIG.

FIG. 8 is a diagram illustrating an overall configuration of an organic EL display according to a third embodiment of the present invention.

9 is an electric circuit diagram of an element circuit in the organic EL display shown in FIG.

FIG. 10 is a diagram illustrating a method of driving a display according to the prior art.

11 is a diagram showing a part of the driving method shown in FIG. 10 in detail.

FIG. 12 is a diagram in a case where an erasing period and a current measuring period as in the present invention are introduced into the driving method of FIG. 10;

FIG. 13 is a diagram in a case where an erasing period and a current measuring period as in the present invention are introduced into the driving method of FIG. 11;

FIG. 14 is a diagram showing an example of a driving method of the organic EL display shown in FIG.

15 is a diagram illustrating a case where the driving method illustrated in FIG. 14 is used in a configuration in which an erasing period and a current measuring period are not set.

FIG. 16 is an electric circuit diagram of an element circuit in an organic EL display according to a fourth embodiment of the present invention.

17 is a diagram illustrating an example of a method of driving an organic EL display using the element circuit illustrated in FIG.

18 is a diagram illustrating a case where the driving method illustrated in FIG. 17 is used in a configuration in which an erasing period and a current measuring period are not set.

FIG. 19 is a diagram showing an example of a driving method in a case where light emission is discontinuous in an organic EL display using the element circuit shown in FIG.

20 is a diagram illustrating a case where the driving method illustrated in FIG. 19 is used in a configuration in which an erasing period and a current measuring period are not set.

FIG. 21 is an electric circuit diagram of an element circuit in an organic EL display according to a fifth embodiment of the present invention.

FIG. 22 is a diagram illustrating an example of a driving method of an organic EL display using the element circuit illustrated in FIG. 21.

FIG. 23 is a diagram showing a case where the driving method shown in FIG. 22 is used for a configuration in which an erasing period and a current measuring period are not set.

FIG. 24 is an electric circuit diagram of an element circuit in an organic EL display according to a sixth embodiment of the present invention.

25 is a diagram illustrating an example of a method for driving an organic EL display using the element circuit illustrated in FIG.

26 is a diagram when the driving method shown in FIG. 25 is used in a configuration in which an erasing period and a current measuring period are not set.

FIG. 27 is an electric circuit diagram of an element circuit in an organic EL display according to a seventh embodiment of the present invention.

FIG. 28 is an electric circuit diagram showing a similar configuration of the element circuit shown in FIG. 27.

FIG. 29 is an electric circuit diagram of an element circuit in an organic EL display according to an eighth embodiment of the present invention.

30 is a diagram illustrating an example of a method for driving an organic EL display using the element circuit illustrated in FIG. 29.

31 is a diagram in the case where the driving method shown in FIG. 30 is used in a configuration in which an erasing period and a current measuring period are not set.

FIG. 32 is a diagram showing an example of a conventional organic EL display in which luminance correction is performed using current detection means.

FIG. 33 is a block diagram of a current detection circuit used in the organic EL display shown in FIG.

FIG. 34 is a diagram showing another example of a conventional organic EL display in which luminance correction is performed using current detection means.

35 is a block diagram of a pixel used in the organic EL display shown in FIG.

[Explanation of symbols]

1,11,21 Organic EL display 2,2a, 2b Organic EL panel 3,3a, 3b Scan controller 4,4a, 4b Signal controller 5 Latch circuit A11-Amn; Aa11-Aamn Element circuit Ab; Ac; Ad; Ae; Af; Ag; Ah Element circuit B1 to Bn Arithmetic circuit (correction means) C1 capacitor (memory element) C21, C22 capacitor D1 to Dn Data signal line (second signal line) E0 power supply line E1 to En power supply line (first Ea power line (second power line) F1 to Fn D / A conversion circuit G1 to Gm scanning signal line (first signal line) INV1, INV2 CMOS inverter K0; K1 to Kn current measuring circuit M1 Mn memory (storage means) Ma1 to Man memory Mb1 to Mbn memory P Organic EL element (electro-optical element) Q TFT (first active element) Q2, Q10, Q11~Q14, Q20~Q22 T
FT Q3 TFT (second active element) S1 to Sm Scan signal line (third signal line) Sa, Sb Bit select line Sc Select line R1, R2; R21, R22 Pixel memory

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/22 G09G 3/22 E H05B 33/14 H05B 33/14 A

Claims (5)

[Claims] An electro-optical element is provided in each area defined by a plurality of first and second signal lines intersecting each other, and the electro-optical element is controlled by a corresponding first active element. A display device driven to perform a display corresponding to a signal level output to a second signal line while being selected by one signal line, wherein the display device is arranged along the second signal line. Current measuring means for measuring a current of a first power supply line for supplying a load current to the electro-optical element, a storage means for holding data measured by the current measuring means, and display data inputted from outside. Correction means for making corrections using data read from the storage means to create a signal level to be output to the second signal line, wherein the second signal is selected together with the selection by the first signal line. Display data on line For a unit display period in which a signal level corresponding to the current level is output, a predetermined signal level is periodically output to the second signal line together with the selection by the first signal line, A display device including a period in which the measurement is performed in the display device. 2. A scanning controller, having a memory element for holding a signal level captured by the first active element, associated with the electro-optical element, and outputting a selected output to the first signal line. And a signal controller that outputs a signal level to the second signal line, performs a scan immediately before a measurement period to initialize the memory element and make the electro-optical element emit no light. The display device according to the above. 3. A second signal line in response to a selection output from a third signal line from which a selection output is derived as an alternative to the first signal line in connection with the memory element. A second active element for providing a signal level different from that of the memory element to the memory element, wherein a display signal level is set by the first active element, and an erase signal level is set by the second active element. 3. The display device according to claim 2, wherein: 4. In connection with said memory element, one or a plurality of pixel memories holding a signal level taken by said first active element, and a bit selection line individually corresponding to said pixel memory. And a third active element selectively driven by the third signal line. When the first signal line is in a selected state, a display signal level is set to the memory element via the first active element, and Is selectively driven to set a display signal level in the pixel memory, and in a state where the first signal line is not selected, the third active element is selectively driven to display a display signal from the pixel memory. The display device according to claim 2, wherein the display device is switched to a level. 5. A memory device comprising: a second power supply line provided separately from a first power supply line for supplying a load current to the electro-optical element;
3. A power supply is performed from the power supply line of claim 2.
The display device according to any one of claims 1 to 4.