JP2002319294A - Semiconductor memory device - Google Patents

Abstract

(57) [Problem] To provide a semiconductor circuit capable of performing high-speed reading without increasing the transistor size of a bit line charger. SOLUTION: Bit line chargers 200 to 203 connected to bit lines 910 to 913 of memory cell arrays 11a and 11b to charge the bit lines, and latch circuits 250 and 2 for storing an address at which reading has been performed.
51 and a control circuit 10a, 1 for selecting the bit line charger based on the information of the latch circuits 250, 251.
0b, and the size of the bit line charger is reduced by configuring the control circuits 10a and 10b to selectively charge the read bit line after the read operation by the bit line charger. .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read circuit of a semiconductor memory.

[0002]

2. Description of the Related Art Semiconductor non-volatile memories are capable of retaining stored information even when the power is turned off, and thus have been widely applied to information systems and communication systems. Above all, the flash memory is realized at a low cost by reducing the memory cell size by erasing the entire chip or in blocks, and the demand is rapidly expanding.

As a new flash memory system, a system using a P-channel transistor in an N-type substrate is known. The reading, writing, and erasing operations of a P-type flash memory using P-channel transistors will be described with reference to FIGS.

FIG. 8A is a schematic sectional view of a memory cell of a conventional P-type flash memory. The memory cell includes a drain 71 and a source 72 formed of a counter-conductivity-type high-concentration impurity region formed on the surface of the first conductivity-type semiconductor substrate 70, and a channel formed between the drain 71 and the source 72. A floating gate 75 is formed on the region 73 via a gate insulating film 74, and a control gate 77 is formed on the floating gate 75 via an interlayer insulating film. FIG. 8B shows this symbol display.

In the nonvolatile memory cell having such a structure, the threshold voltage of the memory cell changes according to the charge stored in the floating gate 75. The injection and extraction of electrons into and from the floating gate 75 are performed as follows.

The operation of injecting electrons into the floating gate 75 is called "writing", and
The injection of electrons into 5 lowers the threshold voltage of the memory cell. The operation of extracting electrons from the floating gate 75 is called "erasing", and the extraction of electrons from the floating gate 75 increases the threshold voltage of the memory cell.

In the write operation, the source 72 is released, and a high voltage of about -5 volts is applied to the drain 71 and about 8 volts is applied to the control gate 77. Under this voltage condition, a high electric field is generated near the drain 71, and a band-to-band tunnel current is generated between the drain 71 and the substrate 70. At this time, electrons flowing from the drain 71 to the substrate 70 are excited and become hot electrons. The hot electrons are supplied to the control gate 77
Is accelerated by the high electric field generated by the high voltage applied to the floating gate 75, jumps over the potential barrier by the gate insulating film 74, is injected into the floating gate 75, and the writing is completed.

In the erase operation, the drain 71 is released, a voltage of about 8 volts is applied to the source 72 and the substrate 70, and a voltage of about -8 volts is applied to the control gate 77. Under this voltage condition, a high electric field is applied to the gate insulating film 74 between the floating gate 75 and the source 72, a Fowler-Nordheim tunnel current flows, and the electrons accumulated in the floating gate 75 are drawn to the substrate 70. It is removed and erasing is completed.

FIG. 9 illustrates the principle of reading from the P-channel type flash memory shown in FIG. 80
Is a current characteristic of a data determination reference, 81 is a memory cell current characteristic in a written state, and 82 is a memory cell current characteristic in an erased state. The ground potential VSS is applied to the control gate 77 of the selected memory cell as a selection potential,
The substrate 70 and the source 72 are set to the power supply voltage VDD,
A potential of about 1 volt is applied to the drain 71 as a drain voltage at the time of reading.

When the selected memory cell is in the "written state", the source 72 and the drain 71 of the memory cell become conductive. On the other hand, when the memory cell selected as described above is in the “erased state”, the source 72 and the drain 71 of the memory cell become non-conductive.

At a certain power supply voltage VACT, a current larger than the current characteristic 80 flows through the memory cell in the "written state" as shown by a characteristic 81. On the other hand,
A current smaller than the current characteristic 80 flows through the memory cell in the “erased state” as shown by a characteristic 82. Here, the current flowing between the source 72 and the drain 71 of the selected memory cell is detected and compared with the current characteristic 80 to obtain “L”.
Alternatively, the operation of converting the logic voltage level to “H” is referred to as a “read operation”.

In this specification, the reference current characteristic 80 is the memory cell current characteristic 8 in the "written state".
It has a characteristic of (1/2) of 1. It is also assumed that the memory cell current characteristic 82 in the erased state is 0.

The flash memory cell array 4 in which the basic unit memory cells shown in FIG.
It is configured as shown in FIG. 900,901,
902, 903 are first to fourth word lines, 910, 91
1, 912, 913 are first to fourth bit lines,
M33 is the aforementioned memory cell having a double gate structure.

In the flash memory array 4, first to fourth word lines 900 to 903 in which the memory cells M00 to M33 are electrically connected to the control gate 77, and a first word line in which the drain 71 is electrically connected. To the fourth bit line 910
913 are arranged at the respective intersections.

The control gates 77 of the memory cells in the same row are connected in common, and the corresponding first to fourth word lines 900 to 900 are connected.
903. Further, the drains 71 of the memory cells in the same column are commonly connected to each other, and
It is connected to fourth bit lines 910-913. The sources 72 of all the memory cells M00 to M33 are also commonly connected to each other to form a line SL. The substrate 70 of all the memory cells M00 to M33 is common and forms a line NW.

In the flash memory array 4 thus configured, in the read operation, the substrate 70 and the source 72 are set to the power supply voltage VDD, and the word lines 900 to
One of the bits 903 is selected as the ground potential VSS and one of the bit lines 910 to 913 is selected as 1 volt which is the drain voltage at the time of reading, so that any one bit can be selectively selected. Can be read out.

A conventional column selection method at the time of reading will be described with reference to FIGS. FIG. 14 shows the relationship between FIG. 10, FIG. 11, and FIG. FIG.
Reference numeral 1 denotes a conventional read column selection circuit 5.

/ PRC is a bit line charger control signal,
YG0 and YG1 are first and second column gate selection signals of the first stage, WG0 and WG1 are first and second column gate selection signals of the second stage, and 100 to 103 are common bit line charger control signals / PRC. First to fourth controlled by
Bit line chargers 110 and 112 are first and second column gates in the first stage, and are controlled by a first column gate selection signal YG0 in the first stage. 111, 113
Are the first and third column gates in the first stage, and the second and third column gates in the first stage
Is controlled by the column gate selection signal YG1.

Reference numeral 120 denotes a second-stage first column gate controlled by a second-stage first column gate selection signal WG0, and 121 denotes a second-stage second column gate selection signal W.
A second column gate of the second stage controlled by G1;
130 is a data output node.

The first to fourth bit lines 910 to 913 are
First to fourth bit line chargers 100 to 10 respectively
3, and the first bit line 910 is connected to the node 90 via the first column gate 110 of the first stage. The second bit line 911 is connected to the node 90 via the first-stage third column gate 111. The third bit line 912 is connected to the second stage of the first stage.
Is connected to the node 91 via the column gate 112 of FIG. The fourth bit line 913 is connected to the node 91 via the first-stage fourth column gate 113. The node 90 is connected to the data output node 130 via the first column gate 120 of the second stage. The node 91 is connected to the data output node 130 via the second column gate 121 of the second stage.

The control signal generating circuit 6 for outputting various signals in FIG. 11 is configured as shown in FIG.
PR is a control signal for controlling the bit line charger control signal / PRC, A0 [1: 0] is a first address bus for selecting the first-stage column gate selection signals YG0 and YG1, and A1 [1: 0] is This is a second address bus for selecting the second-stage column gate selection signals WG0 and WG1.

The column selection of the flash memory is performed by selecting one bit from the first address bus A0 [1: 0], and thereby selecting a first-stage column gate selection signal YG0 or YG0.
1 and also in the second address bus A
When one bit is selected from 1 [1: 0], one of the second-stage column gate selection signals WG0 and WG1 is selected. Accordingly, data output node 130 is electrically connected to any one of bit lines 910 to 913.

A conventional read operation will be described with reference to FIGS. Here, FIG. 13 shows a flash memory having the configuration of FIG. 13, reference numeral 4 denotes a flash memory cell array having the configuration shown in FIG. 10, 5 denotes a read column selection circuit shown in FIG. 11, 6 denotes a control signal generation circuit shown in FIG. 12, 160 denotes a sense amplifier, and 175
Is a read reference circuit, 135 is a reference data output node, DOUT is the sense amplifier 160
, A detection result output node 700, a row decoder 700,
Is a control logic and address decoder circuit.

The conventional flash memory circuit includes a flash memory cell array 4 having the configuration shown in FIG.
Flash memory cell array 4 and bit lines 910-91
3, a column selection circuit 5 connected to the column selection circuit 5, a signal line / PRC and YG0, YG1, W
A control signal generation circuit 6 of a column selection circuit connected via G0 and WG1, a row decoder 700 connected to the flash memory cell array 4 via word lines 900 to 903, and a control signal generation circuit 6 of a column selection circuit And a control logic and address decoder circuit 701 connected to the row decoder 700 via a control signal, a control circuit 702 for generating SL and NW control signals of the flash memory cell array 4, and a read reference circuit 1
75, the read reference circuit 175 and the reference data output node 135, and the read column selection circuit 5 and the data output node 130,
Further, the sense amplifier 160 is connected to a control logic and address decoder circuit 701 via a control signal and connected to DOUT.

FIG. 15 is a schematic diagram of a read circuit of a flash memory having the configuration shown in FIG. In FIG. 15, DIS is a discharger control signal, Y
GR is the first-stage column gate selection signal, WGR is the second-stage column gate selection signal, and 170 is the characteristic 8 in FIG.
0, a reference signal / REF is a control signal of the reference cell 170, 105 is a charger having the same electrical characteristics as the first to fourth bit line chargers, and 115 is a first to first bit of the first stage. A first-stage reference cell column gate 125 having the same electrical characteristics as the fourth column gate. Reference numeral 125 denotes a second-stage reference cell having the same electrical characteristics as the first and second second-stage column gates. Cell column gates, 140 is a first discharger, 145 is a second discharger, 150 is the parasitic capacitance of the first to fourth bit lines 910 to 913, and 155 is the first to fourth bit lines. Bit lines 910 to 91
3 is a capacitor having the same value as the parasitic capacitance of the node 3, 160 is the node 1
This is a sense amplifier that detects a potential difference between the signals 30 and 135 and converts the difference into a logical value.

In the conventional read circuit, the power supply potential VDD is connected to the bit line 910 via the memory cell M00,
The bit line 91 is provided by the column selection circuit 5 of FIG.
0 is connected to the data output node 130, the data output node 130 is connected to the ground via the first discharger 140 controlled by the control signal DIS, and the power supply potential VDD as in the data system. Is the reference cell 1 controlled by the control signal / REF
70, the drain node 915 is connected to the power supply potential VDD via the capacitor 155.
The charger 1 controlled by the control signal / PRC
05 is connected to the power supply potential VDD, and to the node 95 via the first-stage reference cell column gate 115 controlled by the control signal YGR, and the node 95 is connected to the second-stage reference controlled by the control signal WGR. The reference data output node 135 is connected to the reference data output node 135 via the cell column gate 125, and the reference data output node 135 includes a reference system connected to the ground via the second discharger 145 controlled by the control signal DIS. Is done.

FIG. 16 is a waveform chart for explaining the operation of FIG. FIG. 17 is an enlarged view of a main part of FIG. In FIG. 16, MODE is a mode signal input from outside the flash memory circuit and determines a mode of the flash memory circuit, AIN is an address signal input from outside the flash memory circuit and determines a memory cell to be read, and / TRG is A trigger signal which is input from outside the flash memory circuit and determines execution timing of a mode of the flash memory circuit. Note that the above-described control signal of the readout circuit and necessary nodes are denoted by the same reference numerals.

In the conventional read operation, the mode signal MOD
E is set to the read state, the address to be read is input to the address signal AIN, and / TRC is first selected by deactivating / TRG,
Bit lines 910-913 and reference cell 17
A drain node 915 power supply potential of 0 is electrically connected to VDD. At this time, equivalent charges are accumulated in the parasitic capacitance 150 in the bit lines 910 to 913 and in the capacitance 155 in the drain node 915 of the reference cell 170, respectively. Thereafter, by activating / TRG, the selection of / PRC is released, and the first first-stage column gate selection signal YG0 and the first second-stage column gate selection signal WG0 enter a selected state. , Bit line 910 and data output node 130 are electrically connected,
The first-stage reference cell column gate selection signal YGR and the second-stage reference cell column gate selection signal WGR are selected, and the drain node 915 of the reference cell 170 and the reference data output node 135 are electrically connected. . Thereafter, when the discharger control signal DIS is selected at an appropriate time, the bit line 910 is connected to the ground potential via the first first-stage column gate 110 and the first second-stage column gate 120. Connected. Here, the memory cell M0
0 is a write state, the current characteristic 81 between the source 72 set to the power supply potential VDD and the grounded battery.
On current I ^MEM is generated as shown in the on-resistance × data output node 130 first discharger 140
The potential becomes 1300, which is the ON current ^IMEM . When the memory cell M00 is in the erased state, the source 72
Since no current flows between data output node and ground potential, data output node 130 is at ground state 1301. On the other hand, since the reference cell 170 has a half characteristic of the current characteristic 81, the potential of the reference data output node 135 is the ON resistance of the second discharger 145 × ON current I
It becomes the potential 1302 of ^MEM ÷ 2. Here, the sense amplifier 160 compares the potential of the data output node 130 with the potential of the reference data output node 135. If the potential of the data output node 130 is higher than the potential of the reference data output node 135, the logic data "L" is output.
If the potential of the data output node 130 is lower than the potential of the reference data output node 135, the logic data “H” is output to the detection result output node DOUT.

[0029]

However, the conventional configuration has the following problems. 1. To perform high-speed reading, the bit lines 910 to
It is necessary to charge 913 at a high speed, and accordingly, it is necessary to increase the transistor size of the bit line chargers 100 to 103.

2. Since the control signal / PRC is activated each time / TRG becomes inactive, the current consumption in the control signal generating circuit 6 of the column selecting circuit increases, and the operation becomes unstable.

3. Since the bit lines 910 to 913 are separately charged, erroneous reading due to a difference due to a charge difference between the respective bit lines is likely to occur when electric noise occurs.

4. A charger 105 having the same electrical characteristics as the first to fourth bit line chargers for the reference circuit, and a first stage having the same electrical characteristics as the first to fourth column gates of the first stage. The column gate 115 for the reference cell, the first and second
And a second-stage reference cell column gate 125 having the same electrical characteristics as the column gate, a capacitor 155 having the same value as the parasitic capacitance of the first to fourth bit lines 910 to 913, and the like. Must be provided.

5. In order to read with high accuracy, the capacity 15
5 needs to have the same characteristics as the bit lines 910 to 913, but has a large variation due to a diffusion state or the like due to a different configuration.

An object of the present invention is to provide a semiconductor memory device that can solve the above problems.

[0035]

The present invention has the following configuration. 1. 1. Charge means for selecting the charger of the bit line from which the reading has been performed. 2. A control signal generation circuit for a read column selection circuit with a read address information storage function 3. Equalizer for electrically connecting adjacent bit lines during a charging operation. 4. Reference cell arranged on the bit line of the memory cell This is reading means for activating the reference cell during a charging operation.

[0036]

FIG. 1 is a block diagram showing an embodiment of the present invention.
And FIG. 2 to FIG. The same reference numerals in the drawings denote the same elements as those described above, and the description will be given.

FIG. 1 shows a read column selecting circuit 1 according to the present invention. First to fourth bit lines 910 to 913 are connected to a data output node 130 in the same manner as in the conventional example shown in FIG. ing.

200 and 201 are common control signals / PRC
The first and second bit line chargers 202 and 203 controlled by 0 are the third and fourth bit line chargers 210 controlled by a common control signal / PRC1.
Is a first equalizer controlled by the control signal / PRC0, and 211 is a second equalizer controlled by the control signal / PRC1.

The first bit line 910 is connected to the power supply potential VDD via the first bit line charger 200, and the second bit line 911 is connected to the second bit line charger 201.
To the power supply potential VDD via the third bit line 9
12 is connected to the power supply potential VDD via the third bit line charger 202, and the fourth bit line 913 is connected to the power supply potential VDD via the fourth bit line charger 203.

The first bit line 910 is connected to the second bit line 911 via the first equalizer 210,
The bit line 912 is connected to the fourth bit line 913 via the second equalizer 211.

FIG. 2 shows a control signal generation circuit of a read column selection circuit according to the present invention. In FIG. 2, / P
RC0 is the first and second bit line chargers 200, 20
1 is a control signal common to the third and fourth bit line chargers 202 and 203, and / PRC1 is a control signal common to the third and fourth bit line chargers 202 and 203.
0 and 251 are latch circuits for storing the selected address, / RST is a reset signal for setting the contents of the latch circuit to an initial value, and LAT is a control signal for storing an address in the latch circuit. is there.

One of the control signals / PRC0 and / PRC1 is selected based on the information stored in the latch circuits 250 and 251. Thereafter, the first column is controlled in the same manner as in the conventional example shown in FIG. Gate selection signal YG
0, YG1 and one of the second-stage column gate selection signals WG0, WG1 are selected.

FIG. 3 shows a memory cell array according to the present invention. The first memory cell array 11a and the second memory cell array 11b have exactly the same structure. "Or" B ".

R00T to R03T, R00B to R03B
Are the first to fourth reference cells, / REFT is a control signal for controlling the reference cells R00T to R03T,
REFB is a control signal for controlling the reference cells R00B to R03B, M00T to M13T, and M00B to M13.
B is a memory cell.

More specifically, the memory cell array according to the present invention has the same configuration as that of the conventional memory cell array shown in FIG.
And the memory cells M00B to M13B are configured by reference cells R00 to R03 sharing a bit line 910 and sharing a gate selection line / REF, respectively.

FIG. 4 is a schematic diagram of a flash memory circuit according to the present invention. In FIG. 4, 1a and 1b correspond to FIG.
In the read column selecting circuit according to the present invention shown in FIG.
These are referred to as first and second read column selection circuits.

Reference numerals 10a and 10b denote control signal generating circuits according to the present invention shown in FIG. 2, which are referred to as first and second control signal generating circuits. 11a is the first memory cell array of the present invention shown in FIG. 3 (a), 11b is the second memory cell array of the present invention shown in FIG. 3 (b), 80a and 80
b denotes first and second row decoders as reference cell control means, 81 denotes a control logic and address decoder circuit, and 130T and 130B denote data output nodes.

More specifically, the flash memory circuit according to the present invention comprises a first flash memory cell array 11a.
A first read column selecting circuit 1a connected to the first flash memory cell array 11a and bit lines 910T to 913T, a first reading column selecting circuit 1a, and signal lines / PRC0, / A first control signal generating circuit 10a connected via PRC1 and YG0T, YG1T, WG0T, WG1T, a first flash memory cell array 11a, a word line 900T,
901T and a first row decoder 80a connected via a control signal / REFT, a first control circuit 70a for generating SL and NW control signals of the first flash memory cell array 11a, and a second flash memory cell array 11b, a second read column selection circuit 1b connected to the second flash memory cell array 11b via bit lines 910B to 913B,
Read column select circuit 1b and signal line / PRC0
B, / PRC1B and YG0B, YG1B, WG0
B, WG1B, and a second control signal generating circuit 10b, and a second flash memory cell array 11b
And word lines 900B, 901B and control signal / RE
A second row decoder 80b connected via the FB,
A control logic and address decoder circuit for connecting the first and second control signal generation circuits 10a and 10b and the first and second row decoders 80a and 80b to a sense amplifier 160 as a read circuit via a control signal. 81
And a control logic and address decoder via a first read column select circuit 1a and a data output node 130T, a second read column select circuit 1b and a data output node 130B, and further via a control signal. The circuit 81 includes a sense amplifier 160 connected to DOUT and connected to DOUT.

FIG. 5 shows a connection state between the first read column selection circuit 1a, the first control signal generation circuit 10a and the first flash memory cell array 11a, and the second read column selection circuit 1b. The same applies to the connection state between the second control signal generation circuit 10b and the second flash memory cell array 11b.

FIG. 6 is a schematic diagram of a read circuit of a flash memory. FIG. 6 shows an element for reading data from the memory cell M00T.

R00B is a reference cell, which has the characteristic 80 of FIG. 9 described above and has the configuration shown in FIG. 3B.
/ REFB is a control signal for the reference cell R00B, and 150 is the first to fourth bit lines 910 to 91 described above.
A parasitic capacitance 3 and a sense amplifier 160 detect a potential difference between the nodes 130 and 135 and convert it into a logical value.

In the read circuit of the present invention, the power supply potential VDD is applied to the bit line 910T via the memory cell M00T.
And the bit line 910T and the data output node 130T are connected by the column selection circuit of FIG.
A data system 170T whose data output node 130T is connected to a ground state via a first discharger 140T controlled by a control signal DIS, and a power supply potential VDD is connected to a bit line via a reference cell R00B similarly to the data system. 910B, the bit line 910B and the data output node 130B are connected by the column selection circuit of FIG. 1, and the data output node 130B is grounded via the second discharger 140B controlled by the control signal DIS. It is composed of a connected reference system 170B.

The read operation of the flash memory configured as described above will be described with reference to FIGS. FIG.
FIG. 4 is a waveform diagram for explaining a read operation of the flash memory according to the present invention.

The read operation in the present invention is performed in advance by using / PRC0T, / PRC1T, / PRC0B, / PR
Bit lines 910T to 913T and 910B to 913B are connected to charger 200T, charger 200B, and reference cells R00T to R03T and R00B to R0 when C1B, / REFT, and / REFB are selected.
3B, it is electrically connected to the power supply potential VDD.

At this time, the bit lines 910T to 913T have a parasitic capacitance of 150T and the bit lines 910B to 913B have a parasitic capacitance of 150T.
, Equivalent charges are respectively accumulated in the parasitic capacitance 150B. Subsequently, by setting the mode signal MODE to the read state, / PRC0T, / PRC1T,
The selection of / PRC0B and / PRC1B is released. Here, the address to be read is input to the address signal AIN, and after that, by activating / TRG,
The selection of / REFT and / REFB is temporarily canceled and bit lines 910T to 913T and 910B to 913B
Is in an electrically disconnected state. Thereafter, the word line 900 of the memory cell M00T to be read out at an appropriate time is used.
T, word line / REFB of reference cell R00B,
When the first first-stage column gate selection signal YG0 and the first second-stage column gate selection signal WG0 are in the selected state, bit line 910T and data output node 130T are connected to bit line 910B and data output node 1
30B are electrically connected to each other. At this time, the read address is stored in the latch circuit 250 or 251. Thereafter, by selecting the discharger control signal DIS at an appropriate time, the bit line 9 is selected.
10T is connected to the ground potential via the first first-stage column gate 110T and the first second-stage column gate 120T. Similarly, the bit line 910B is connected to the ground potential via the first first-stage column gate 110B and the first second-stage column gate 120B.

Here, as in the conventional case, memory cell M00T
Is in the write state, the data output node 13
0T is the potential 1 when the erase state is at the potential 1300.
It becomes 301. On the other hand, the data output node 130B has the potential 1305. Here, by activating the sense amplifier 160 by the control signal SAA, the sense amplifier 160 is activated.
Compares the potential of the first data output node 130T with the potential of the second data output node 130B, and the potential of the first data output node 130T
If the potential is higher than 0B, logical data '0' is output to the detection result output node DOUT, and if the potential of the first data output node 130T is lower than the potential of the second data output node 130B, logical data '1' is output to the detection result output node DOUT. . DO
After output to the UT, / TRG is deactivated so that the discharger control signal DIS, the first-stage column gate selection signal YG0, the first second-stage column gate selection signal WG0, and the control signal SAA are output. Each becomes inactive. Here, charger control signals / PRC0T and / PRC0B are selected and activated based on the information stored in latch circuit 250 or 251. Thus, the read bit lines 910T and 910B are electrically connected to the power supply potential VDD via the chargers 200T and 200B.

Here, as shown in FIG.
0 is controlled by the same control signal / PRC0 as that of the charger 200, so that the adjacent bit lines 910 and 911
Are electrically connected. Charger 201 on bit line 911 also has control signal / PR similar to that of charger 200.
Since control is performed by C0, the read bit line 900 is connected to the equalizer 210 and the charger 20.
1 is also electrically connected to the power supply potential VDD. Also, reference control signals / REFT, / REF
By activating B, each bit line is electrically connected to the power supply potential VDD via the reference cells R00T to R03T and R00B to R03B.

With this configuration, the bit line 910
Since the charging to 913 is performed after the reading is performed, the time by the charging does not limit the reading speed. Thus, the size of the bit line charger can be reduced.

The control signal / PRC is supplied to the latch circuit 25
Based on the information stored in 0 or 251, the current consumption in the control signal generation circuits 10 a and 10 b of the column selection circuit can be limited.

Since the bit lines 910 to 913 are simultaneously charged by the equalizer 210, the same charge state can be set between physically adjacent bit lines.
Therefore, even when electric noise occurs, there is no charge difference between the respective bit lines, so that erroneous reading hardly occurs and the reliability is high.

The memory cell array and the sense amplifier 1
Since the reference cells are arranged in the memory cell array in exactly the same way via 60, there is no need to separately provide circuit elements such as column gates and capacitors for the reference circuit.

Further, since the reference cell is arranged on the bit line of the memory cell, the electrical characteristics such as the parasitic capacitance and the transistor size are the same, so that the variation caused by the diffusion state is small. As a result, accurate reading can be performed.

Since the bit line is charged via the reference cell arranged on the bit line of the memory cell, the size of the bit line charger can be reduced.

[0064]

As described above, the semiconductor memory device of the present invention comprises a bit line charger connected to a bit line of a memory cell array for charging the bit line, a latch circuit for storing an address from which reading has been performed, and Since a control circuit for selecting the bit line charger based on the information of the latch circuit is provided, the control circuit selectively charges the read bit line after the read operation by the bit line charger. With such a configuration, the size of the bit line charger can be reduced.

Since control signal / PRC is based on information stored in the latch circuit, current consumption in the control signal generation circuit of the column selection circuit can be limited. Since the bit lines are simultaneously charged by the equalizer, the same charge state can be set between physically adjacent bit lines. Therefore, even when electric noise occurs, there is no charge difference between the respective bit lines, so that the reliability is improved.

Further, since the reference cells are arranged in the memory cell array in exactly the same manner via the memory cell array and the sense amplifier, it is not necessary to separately provide a circuit element such as a column gate and a capacitor for the reference circuit.

Further, since the reference cell is arranged on the bit line of the memory cell, the electrical characteristics such as the parasitic capacitance and the transistor size are the same, so that the variation due to the diffusion state is small. As a result, accurate reading can be performed.

In addition, since the bit line is charged via the reference cell arranged on the bit line of the memory cell, the size of the bit line charger can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a read column selection circuit according to the present invention.

FIG. 2 is a circuit diagram of a control signal generation circuit in the read column selection circuit of the present invention.

FIG. 3 is a configuration diagram of a memory cell array of the present invention.

FIG. 4 is a schematic diagram of a circuit configuration of the present invention.

FIG. 5 is a connection diagram of main parts in FIG. 4;

FIG. 6 is a schematic diagram of a read circuit of the present invention.

FIG. 7 is a waveform chart for explaining a read operation of the present invention.

FIG. 8 is a schematic sectional view of a memory cell of a P-type flash memory.

FIG. 9 is an explanatory diagram of a reading principle of a P-channel type flash memory.

FIG. 10 is a configuration diagram of a flash memory cell array.

FIG. 11 shows a conventional read column selection circuit.

FIG. 12 is a control signal generation circuit of a conventional read column selection circuit.

FIG. 13 is a schematic circuit diagram of a conventional flash memory.

FIG. 14 is a connection diagram of main parts in FIG. 13;

FIG. 15 is a schematic diagram of a conventional read circuit.

FIG. 16 is a waveform chart illustrating a conventional operation.

FIG. 17 is an enlarged view of a main part of FIG. 16;

[Explanation of symbols]

1a, 1b First and second column selecting circuits for reading 10a, 10b First and second control signal generating circuits 11a First memory cell array 11b Second memory cell array 110-113 First-stage column gate 115 First-stage Reference cell column gates 120, 121 Second-stage column gate 125 Second-stage reference cell column gate 130 Data output node 130T, 130B Data output node 135 Reference data output node 140 First discharger 145 Second Discharger 150 Parasitic capacitance of bit lines 910 to 913 155 Capacity 160 Sense amplifier 170 Reference cell 175 showing characteristic 80 175 Reading reference circuit 200 to 203 Bit line charger 210, 211 Bit line equalizer The 250, 251 address latch circuit 700 row decoder 701 control logic and address decoder circuit 800 row decoder 801 control logic and address decoder circuit 900 to 903 word line 910 to 913 bit line A0 [1: 0] address bus A1 [1: 0] Address bus AIN Address signal DOUT Detection result output node DIS Discharger control signal LAT Control signal for latch circuit M00 to M33 Memory cell MODE Mode signal Control signal for controlling PR / PRC R00 to R03 Reference cell R00B Reference cell WG0, WG1 Second-stage column gate selection signal WGR Second-stage column gate selection signal YG0, YG1 First-stage column gate selection signal YGR First-stage column gate selection signal / PRC DOO line charger control signal / PRC0, the trigger signal for determining the reset signal / TRG execution timing of the control signal / RST latch circuit of the control signal / REFB reference cell R00B control signal / REF reference cell 170 of / PRCl bit line charger

Claims (7)

[Claims] 1. A bit line charger connected to a bit line of a memory cell array to charge the bit line, a latch circuit for storing an address from which reading has been performed, and a bit line charger based on information of the latch circuit. And a control circuit for selecting. 2. The semiconductor memory device according to claim 1, wherein said control circuit is configured to selectively charge a bit line from which reading has been performed after said reading, by said bit line charger. 3. A bit line charger connected to a bit line of a memory cell array to charge the bit line, a bit line equalizer for equalizing between bit lines selected by different addresses among the bit lines, and the bit line A control circuit for simultaneously controlling the charger and the bit line equalizer. 4. A latch circuit for storing a read address, wherein the read bit line is selectively read after the read operation by the bit line charger and the bit line equalizer based on the information of the latch circuit. 4. The semiconductor memory device according to claim 3, wherein said semiconductor memory device is configured to be charged. 5. A first memory cell array in which a reference cell is disposed, a first selection circuit of the memory cell array, and the same configuration as the first memory cell array and the first selection circuit. A semiconductor comprising: a second memory cell array and a second selection circuit; and a read circuit for reading from a memory cell of the first memory cell array using a reference cell in the second memory cell array. Memory device. 6. The semiconductor device according to claim 1, wherein the reference cells in the first and second memory cell arrays are connected to a common bit line with the memory cells in the first and second memory cell arrays. 6. The semiconductor memory device according to 5. 7. The semiconductor memory device according to claim 6, further comprising reference cell control means for controlling the reference cell to be activated during a bit line charging operation.