JP2002318638A - Information processing system and semiconductor integrated circuit device - Google Patents

Abstract

[PROBLEMS] To provide an information processing system capable of high-speed signal processing and a flexible system configuration, and a semiconductor integrated circuit device suitable for the information processing system. SOLUTION: A first circuit block for performing signal processing in response to a clock signal and a second circuit block for transmitting and receiving data between the first circuit block in response to a supplied clock signal. An information processing system including a feedback type phase compensator provided in the first circuit block so as to have a delay time in a signal transmission path from the first circuit block to the second circuit block. A clock signal for the second circuit block is generated by synchronizing the feedback signal and the clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system and a semiconductor integrated circuit device, and more particularly to an information processing system requiring high-speed signal processing and a flexible system configuration and a semiconductor integrated circuit device suitable for the information processing system. It is about technology.

[0002]

2. Description of the Related Art When a digital signal processing system is composed of a combination of a plurality of digital integrated circuits, for example,
When a microcomputer system includes a plurality of digital integrated circuits, it is necessary to supply a clock signal used in a master device such as a microprocessor to a slave device such as a memory circuit. At this time, the master device uses a PLL or DL
Clock phase adjustment is performed by a feedback type phase compensator (or feedback type phase comparator) such as L. Examples of using a feedback phase compensator for such clock distribution are disclosed in JP-A-6-350440 and JP-A-10-19045.
No. 4, JP-A-10-200515 and the like.

[0003]

SUMMARY OF THE INVENTION Japanese Patent Application Laid-Open No. Hei 6-35044
However, even if the clock phase is adjusted by a feedback phase compensator as disclosed in Japanese Patent Application Laid-Open No. H10-190454 and Japanese Patent Laid-Open No. Is generated. Therefore, the delay time t
After the access time tAC at the slave device such as a memory with a delay of prop1, the slave device outputs the output signal OU.
Form T. The signal OUT is transmitted as the input signal IN of the delay time tprop2 in the signal path from the slave device to the master device. Therefore, the input signal I
The setup time tsu for taking in N becomes short.

Japanese Patent Laid-Open No. Hei 10-200515 discloses a technique for avoiding a phase difference due to a delay in a signal line between the master and the slave. According to the technique disclosed in the above publication, a PLL circuit, a switch circuit, and a control circuit are provided in both the master and the slave, and the master side P
After the LL is completely synchronized, the output of the slave-side PLL is transmitted to the master side by the switch, the phase with the master-side clock is detected by the master-side phase comparator, and the slave-side PLL is controlled. Synchronize two PLLs. However, according to the technology disclosed in this publication, not only a PLL circuit and a switch control circuit are required for each of the master device and the slave device, but also a phase comparator that forms a part of the slave-side PLL circuit is provided on the master side. Therefore, the circuit scale becomes complicated, and a dedicated device for such a system is designed and manufactured, and the system lacks flexibility.

An object of the present invention is to provide an information processing system capable of high-speed signal processing and a flexible system configuration, and a semiconductor integrated circuit device suitable for the information processing system. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. Information processing including a first circuit block for performing signal processing in response to a clock signal, and a second circuit block for transmitting and receiving data between the first circuit block in response to a supplied clock signal A feedback signal, wherein a feedback phase compensator is provided in the first circuit block so as to have a delay time in a signal transmission path from the first circuit block to the second circuit block. And the clock signal are synchronized to generate a clock signal for the second circuit block.

[0007] The outline of another typical invention disclosed in the present application will be briefly described as follows. An internal clock signal, a feedback signal, and a feedback-type phase compensator are supplied to each other, and the feedback-type phase compensator generates a clock signal whose phase or timing is corrected based on the clock signal and the feedback signal. The correction clock signal is supplied to the first output circuit through the first output circuit.
And a clock signal of the second external terminal is supplied to an input circuit to form a feedback signal of the feedback phase compensator.

[0008]

FIG. 1 is a schematic block diagram showing one embodiment of an information processing system according to the present invention. FIG. 1 mainly shows a clock system of the information processing system. The information processing system of this embodiment includes a master device such as a one-chip microcomputer and a slave device such as a synchronous DRAM (Dynamic Random Access Memory).

The master device has a clock signal CLK having a bus frequency for transmitting and receiving signals to and from the slave devices. The feedback phase compensator receives two signals, the clock signal CLK and the feedback signal CKI,
A clock signal CKO whose phase or timing is appropriately corrected is generated and transmitted to the slave device. The master device of this embodiment has the external terminal (CKO) for clock output and the external terminal (CKI) for input of a feedback signal. In the following description, to avoid complication of a sentence, signal names and corresponding terminal names are denoted by the same reference numerals.

As described above, the output-only external terminal (CK)
O) and an external terminal exclusively for input (CKI) are provided, and in relation to the external terminal for clock input of the slave device (CKIn), the external terminal (CKO) is connected to (CKO).
I) and the external terminal (CKO) to (CK)
The wiring leading to In) is made to have the same length. In other words, the signal transmission path is configured such that the signal propagation delay time on the wiring from CKO to CKI and the signal propagation delay time on the wiring from the external terminal (CKO) to (CKIn) are substantially equal. I do.

The feedback phase compensator in the master device operates so as to synchronize the clock signal CLK with the feedback signal CKI having a signal propagation delay time on the wiring from the external terminal (CKO) to (CKI). I do. That is,
In the feedback phase compensator, a clock CKO whose phase is advanced with respect to the clock signal CLK by the signal propagation delay time is generated. As a result, the phase or timing of the clock signal CLK of the master device and the clock signal CKIn supplied to the slave device can be appropriately adjusted.

That is, a feedback type phase compensation circuit is provided in a master device formed by one semiconductor integrated circuit device, and the phase of the internal clock signal CLK and the feedback signal CKI are corrected or adjusted to be directed to the slave device. Generated clock CKO. Utilizing such a phase compensation operation, a mechanism for equalizing the wiring length from CK to CKI of the master device and the wiring length from CKO to the clock input CKIn of the slave device is used to achieve CL.
Timing skew between K and CKI and CKn can be prevented from occurring.

FIG. 2 is a schematic block diagram showing another embodiment of the information processing system according to the present invention. FIG. 1 mainly shows a clock signal distribution configuration in the information processing system. 2. Description of the Related Art Advances in semiconductor technology have led to a trend toward technology in which a plurality of semiconductor chips, such as a microcomputer chip, a DRAM chip, and a flash memory chip, for configuring an electronic system are configured as a semiconductor integrated circuit device in one package. It creates sex.

That is, instead of a plurality of semiconductor chips,
QFP (Quad Flat Packa)
ge) or CSP (Chip Size Package or Chip Scale Packa)
ge) and BGA (Ball Grid Array), when using a plurality of semiconductor devices packaged by a packaging technology and mounting the plurality of semiconductor devices on a mounting substrate such as a printed circuit board, the distance between the semiconductor chips and the It is difficult to reduce the wiring distance, the signal delay due to the wiring is large, and restrictions are imposed on speeding up and miniaturizing the device or system.

On the other hand, in the multi-chip module (Multi Chip Module) technology, a bare chip or a plurality of extremely small semiconductor chips having a small size substantially equivalent to a bare chip is integrated. Since the semiconductor integrated circuit device is in the form of one package, the wiring distance between the chips can be reduced, the capacitance of the wiring can be reduced, and the characteristics of the semiconductor device can be improved. In addition, by forming a plurality of chips into one package, the semiconductor device can be downsized, and the mounting area can be reduced, so that the semiconductor device can be downsized.

In the information processing system of this embodiment, a master device including a microcomputer chip configured as a multi-chip module as described above and a slave device such as a DRAM coupled to the microcomputer chip are included in one package. Mounted on Also in such a multi-chip module, in order to reduce clock skew between the master device and the slave device, CKO and CKI are provided in the master device as in the embodiment of FIG.
In this case, equal-length wiring is performed between the wiring and KIn.

Thus, in the master device and the slave device provided in the multi-chip module, the wiring length from CKO to CKI of the master device and the clock input CKI from the CKO to the slave device
By a mechanism for equalizing the wiring lengths up to n, the timing skew between CLK (see FIG. 1) and CKI and CKn without the master device can be sufficiently reduced. Thus, the characteristics of the semiconductor device can be further improved, and the semiconductor device can be reduced in size and its mounting area can be reduced by forming a plurality of chips into one package.

FIG. 3 is a schematic block diagram of an embodiment of the information processing system according to the present invention. FIG. 1 also shows a clock signal distribution configuration in the information processing system and an internal circuit operated thereby. In this embodiment, the chip A constitutes the master device, and the chip B constitutes the slave device.

A chip A as a master device has a clock signal CLK for transmitting and receiving signals to and from a slave device as a chip B for signal processing. The feedback phase compensator receives the clock signal CLK and the feedback signal CKI, and synchronizes the clock signal C
Generate KO and send it out to chip B. The chip A of this embodiment has an external terminal (CKO) for the clock output and an external terminal (C
KI).

As described above, in the chip A, the output-only external terminal (CKO) and the input-only external terminal (CKI)
Are provided, and an external terminal (CK) for clock input of the chip B is provided.
With respect to (In), the wiring from the external terminal (CKO) to (CKI) and the wiring from the external terminal (CKO) to (CKIn) have the same length. Thereby, as shown in the timing chart of FIG. 4, the timing of the clock CLK indicating a clock signal for a bus line (not shown) in the chip A and the timing of the clock signal CKIn supplied to the chip B are favorably adjusted. Can be.

The chip A operates the flip-flop circuit FF1 and the like by the clock signal CLK of the bus frequency to transmit data to the chip B. For example,
If the chip B is a memory circuit as described above, an address signal;
If it is a read / write control signal and a write operation, it outputs write data. In the chip B, the flip-flop circuit FF2 and the like are controlled by the clock signal CKIn substantially synchronized in timing with the clock signal CLK on the chip A side, and the signal is sent from the chip A to capture the signal.

For example, the chip B is a synchronous DRAM
When the read operation is instructed, the selection of the memory cell of the synchronous DRAM and the read data are performed according to the clock signal C in accordance with the CAS latency.
Flip-flop circuit FF3 after a plurality of cycles of LKn
Is output from the synchronous DRAM such that That is, in the timing chart of FIG. 4, in the chip B, the time tAC from the rise of the clock CKIn to the setting of the output data in the flip-flop circuit FF3 becomes the access time, and the signal propagation delay time tprop2 from the chip B to the signal transmission path. , And reaches the chip A. The time tsu from the data input by the chip A to the rise of the next cycle of the synchronization clock CLK of the bus frequency is the setup time of the input signal in the chip A.

The physical distance between the chips A and B is
This results in a signal propagation delay time. In a system having a propagation delay time (tprop1) in the synchronous data transfer timing from the chip A to the chip B as shown in FIG. 14, when a high bus frequency exceeding, for example, 133 MHz is reached, the propagation allowed off-chip Delay time (tpro
p) must be extremely short. Accordingly, the signal transmission line is required to have a short length of, for example, about 3 cm or less, which makes it difficult to configure an information processing system including a plurality of chips on a mounting board.

In other words, when the system is composed of only two chips A and B, even if only the clock supply path can be made 3 cm or less, even if the clock supply path can be made 3 cm or less, a plurality of bits transmitted in synchronism therewith are required. It is difficult to make all of them including the address signal, control signal, and data signal less than the above 3 cm. In addition, since there are often a plurality of slave devices for one master device, As described above, it is not realistic to mount the slave device within the range of 3 cm.

In this embodiment, a feedback type phase compensator (or a feedback type phase comparator) such as a PLL (or DLL) circuit is used.
Is used, the phase compensation in the PLL circuit is compensated by the internal clock (bus clock CLK) and the CKI. By making the distance between CKO and CKI and the distance between CKO and CKIn equal length wiring in FIG. 3, the timing skew between the chips of the bus synchronization clock between the chips A and B becomes sufficiently small. As shown in FIG. 4, the time corresponding to the propagation delay time tprop1 of the clock signal from chip A to chip B as shown in FIG.
Not needed during cyc. Therefore, a margin can be given to the off-chip design, and a further increase in the speed can be easily realized. That is, the propagation delay time tprop1 is allocated to the setup time tsu to secure an operation margin,
Alternatively, the clock cycle tcyc can be shortened by that amount and can be directed to higher speed.

FIG. 5 is a schematic block diagram showing another embodiment of the information processing system according to the present invention. In this figure, the clock system of the information processing system is mainly shown in the same manner as FIG. The information processing system of this embodiment includes a master device such as a one-chip microcomputer and a synchronous DRAM (Dynamic Landem.
(Access memory) and the like.

In this embodiment, a delay circuit is provided in the master device. That is, a circuit that delays the signal input to the terminal CKI and inputs the delayed signal to the feedback phase compensator is added. This configuration ensures synchronization even if the wiring from the clock output CKO of the master device to the feedback input CKI and the wiring from the clock output CKO of the master device to the clock input CKIn of the slave device are not equal-length wiring or cannot be performed. In order to compensate, a mechanism for adjusting the delay amount corresponding to the inside of the semiconductor chip constituting the master device is provided.

That is, the distance from the clock output CKO of the master device to the feedback input CKI, and the clock input CKI of the slave device from the clock output CKO.
The distance to the middle part of the wiring toward n is equal length,
From such an intermediate part, the clock input CK of the slave device
The wiring delay up to In is set to a delay amount equal to the delay amount provided in the master device. Thus, the clock CLK of the master device and the clock input CKIn of the slave device can be synchronized.

The delay circuit provided in the master device has a variable delay circuit that can cope with the amount of wiring delay from the intermediate section to the clock input CKIn of the slave device depending on the system configuration and mounting form. You. Although not particularly limited, the delay amount of this variable delay circuit can be adjusted by a digital signal.
The digital signal is held in a storage circuit such as a register. In other words, the master device can be made versatile by setting the digital signal by software.

FIG. 6 is a schematic block diagram showing another embodiment of the information processing system according to the present invention. In this figure, the clock system of the information processing system is mainly shown as in FIG. The information processing system of this embodiment includes one master device such as a one-chip microcomputer and a synchronous DRA.
It comprises three slave devices 1 to 3 such as M (dynamic random access memory).

The master device of this embodiment has a feedback phase compensator and a variable delay circuit therein similarly to the master device of the embodiment of FIG. The distance from the external terminal corresponding to the clock output CKO of the master device to the first intermediate point a is common to each wiring path from the clock output CKO to the feedback input or the clock input CKIn of the slave device. Therefore, the wiring length from the first intermediate point a to the external terminal corresponding to the feedback input CKI and the second intermediate point a to the second
The wiring L1 up to the intermediate point b is made equal in length.

Of the wiring paths leading to the clock inputs CKIn of the three slave devices, the third intermediate point c from the second intermediate point b toward the slave device 1 and the third intermediate point b from the second intermediate point b to the slave device 2 The wiring length of the fourth intermediate point d toward No. 3 is equalized as L2. And
The wiring length from the third intermediate point c to the external terminal corresponding to the clock input CKIn of the slave device 1 and the wiring length from the fourth intermediate point d to the external terminal corresponding to the clock input CKIn of the slave devices 2 and 3 Are equalized as in L3. That is, the wiring lengths from the second intermediate point b to the external terminals corresponding to the clock inputs CKIn of the slave devices 1, 2, and 3 are equal to each other. In other words, the propagation delay time from the second intermediate point b to the clock input CKIn of each of the slave devices 1, 2, and 3 is made equal.

Therefore, by setting a delay amount corresponding to the propagation delay time from the intermediate point b to the clock input CKIn of each of the slave devices 1, 2, and 3 in a variable delay circuit (not shown) provided in the master device. , The master device clock CLK and the respective clock inputs CKIn of the slave devices 1, 2 and 3 can be satisfactorily synchronized with each other. Thus, by providing the master device with the variable delay circuit that delays the feedback input CKI, the master device can be used in an information processing system having various slave devices having different numbers and mounting forms.

FIG. 7 is a block diagram showing a main part of an embodiment of a semiconductor integrated circuit device suitable for the information processing system according to the present invention. The semiconductor integrated circuit device of this embodiment is directed to the master device, and a clock supply circuit directed to a slave device is illustratively shown.

The clock supply circuit includes an oscillation circuit and a control unit. The oscillation circuit includes the feedback phase compensator and a delay circuit for the feedback signal CKI, that is, a variable delay circuit for setting a delay amount. The clock output CKO formed by the feedback phase compensator is output from an external terminal. Further, the feedback clock CKI is input from an external terminal through the external wiring as described above. This feedback signal CK
I is input to the feedback phase compensator through the delay amount circuit, and is phase-synchronized with the internal clock CLK.

The control section has a bus interface and a delay amount control register. The bus interface is connected to the internal bus, and the feedback signal CKI is supplied to the delay amount control register through the internal bus and the bus interface.
Is set. For example, a digital signal corresponding to the above-described delay amount is stored in a memory circuit such as a ROM, and the RO signal is output when the system power is turned on or when the system is reset.
M reads the digital signal to the internal bus,
The data is written to the illustrated register through the bus interface. Thus, as shown in the timing chart of FIG. 8, the timing of the clock CLK of the master device and the timing of the input clock CKIn of the slave device can be matched.

As shown in FIG. 8, the feedback type phase compensator
The clock CLK supplied to the input and the feedback signal CKI
Synchronize with the timing. Here, CKI is not a feedback signal of the external terminal but a signal delayed by a delay amount circuit for convenience. The total delay amount (tprop) of the wiring path from the clock output CKO to the clock input CKI and the delay amount circuit as in the above-described embodiment is the signal path from the clock output CKO to the clock input CKIn of the slave device. By making the delay amount (tprop) equal, the timing of the feedback signal CKI at the feedback input terminal of the feedback phase comparator, that is, the clock CLK and the clock input CKIn of the slave device can be matched. That is, the feedback phase compensator operates to advance the phase of the clock output CKO to compensate for the delay amount (tprop), and the propagation delay time (tprop) is compensated between the master device and the slave device. Is done.

FIG. 9 is a block diagram showing a main part of another embodiment of the semiconductor integrated circuit device suitable for the information processing system according to the present invention. The semiconductor integrated circuit device of this embodiment is directed to the master device, and a clock supply circuit capable of coping with various types of connection of slave devices is shown as an example.

In this embodiment, a first output circuit OB1 for clock output and a switch SW for selectively transmitting a clock formed by the feedback phase compensator are provided at the output of the feedback phase compensator. And a second output circuit OB2. The output signal of the first output circuit OB1 is supplied to an external terminal CK.
O, and the output signal of the second output circuit OB2 is output from the external terminal CKIO / CKI. That is, the external terminal CKIO / CKI is connected to the switch S
In the first operation mode in which W is turned off, the switch SW is used as the feedback input CKI in the same manner as described above. It is used properly. The output section of the input circuit IB that receives the feedback signal is provided with a delay amount circuit whose delay amount is set by the register described with reference to FIG.

FIG. 10 is a schematic block diagram showing another embodiment of the information processing system according to the present invention.
In the figure, the semiconductor integrated circuit device of the embodiment of FIG. 9 is used as a master device. In the information processing system of this embodiment, one master device provides a relatively large number of slave devices. When a relatively large number of slave devices are provided, only one output circuit OB1 does not have a sufficient ability to supply a clock to all of these slave devices. Need to be provided.

As described above, in a system in which the number of slave devices is large and it is difficult to output a clock to all the slave devices using only the output circuit OB1, the master device is operated in the second operation mode. . Although not particularly limited, the operation control terminal C is set to one level, the switch SW is turned on,
Further, the second output circuit OB2 is brought into an operating state.

In the second operation mode, a clock can be output from the terminals CKIO / CKI via the second output circuit OB2. Therefore, the slave devices are divided into a first set and a second set, and the first output circuit OB1 supplies a clock to a plurality of slave devices constituting the first set, and the second output circuit OB1 supplies the clock to the second set. The output circuit OB2 supplies a clock to a plurality of slave devices forming the second set. By dividing the slave devices into two groups and distributing the clocks to the first output circuit OB1 and the second output circuit OB2, the clock buffer as described above is necessary. Absent.

In the information processing system of this embodiment, the delay amount of the delay circuit provided in the master device is set to a delay time close to the propagation delay time of the clock from the master device to the slave device. The phase difference between CLK and the clock input CKIn of the slave device can be made sufficiently small. Strictly speaking, since it is difficult to make the signal paths to the slave devices divided into the two groups equal, it is set to a propagation delay time that does not cause a malfunction in data transfer.

In a system in which a clock can be supplied by the output circuit OB1 of the master device, the master device is operated in the first operation mode. Although not particularly limited, the operation control terminal C is set to the other level, and the switch SW is turned off so that the second output circuit O
B2 is in a non-operating state, that is, external terminals CKIO / CKI
The output is set to a high impedance state so as not to hinder the input of the feedback signal from the input terminal.

In the circuit of the embodiment shown in FIGS. 1 to 3 and the embodiment of FIG. 9 as well, in the second operation mode, the capture of the feedback signal for clock synchronization is all performed on the receiving end side of the signal line. Therefore, by performing impedance matching, it is not necessary to consider the influence of the waveform shape due to reflection. That is,
There is no erroneous operation in which the PLL or DLL is unlocked due to reflection noise or the like.

However, when operating in the second operation mode as in the embodiment of FIG. 11, the chip (Chi) constituting the master device is operated as shown in FIG.
In p) A, the feedback phase compensator generates a clock signal (O1) synchronized with the clock CLK, and outputs it to the output circuit OB.
2 through the input / output terminal CKIO and the transmission line connected to the input / output terminal CKIO to the receiving device of the chip B as a slave device. The output signal of the input / output terminal CKIO is fed back to the feedback phase compensator through the input circuit IB. At this time, the output impedance of the output circuit OB2 is matched with the characteristic impedance of the transmission line. For this reason, the signal at the input / output terminal CKIO rises to a level that is half the signal amplitude as shown in the waveform (S1), which is transmitted to the input of the receiving device through the transmission line, and the input at the receiving device is input. Negative noise generated by the capacitance is returned by reflection.

In a high-speed system, the transmission line is also formed short, and the rise and fall of the clock signal are made fast, so that the impedance matching causes the voltage of the input / output terminal CKIO to be close to half the signal amplitude. The reflected noise is superimposed at a certain timing. The input circuit IB has a threshold voltage of
Since the signal amplitude is set to about 1/2 of the signal amplitude, the negative feedback noise portion of the waveform (S1) generated at the input / output terminal CKIO is formed as a low level waveform (S2) to form a feedback type phase compensation. In this case, a malfunction may occur, in which the phase lock in the feedback phase compensator is released.

FIG. 12 is a block diagram showing a main part of another embodiment of the semiconductor integrated circuit device suitable for the information processing system according to the present invention. The semiconductor integrated circuit device of this embodiment is directed to the master device of FIG. 9 and exemplarily shows a clock supply circuit directed to a slave device.

In this embodiment, the second output circuit O is used in order to prevent a malfunction such that the phase lock in the feedback phase compensator is lost when used in the second operation mode.
B2 is composed of a main buffer and a sub-buffer. Output signals of the feedback phase compensator are supplied to the inputs of the main buffer and the sub-buffer via the switch SW, and the respective output terminals are connected to the external terminal CKIO / C.
Connected to KI. The sub-buffer is driven by sub-buffer control. The sub-buffer control is based on the control signal set by the control register.
The sub-buffer is activated with a delay time set by the control register with respect to the main buffer.

FIG. 13 shows the output circuit OB2 of FIG.
The circuit diagram of one embodiment is shown. The main buffer includes a P-channel MOSFET Q1 and an N-channel MOSFET Q2. P-channel type MO
The input signal P1 for driving is supplied to the gate of the SFET Q1, and the input signal N1 for driving is supplied to the gate of the N-channel MOSFET Q2.

To output a high level from the output terminal CKIO, both the input signals P1 and N1 are set to a low level. That is, the P-channel MOSFET Q1 is turned on by the low level of the input signal P1, and the N-channel MOSFET Q1 is turned on by the low level of the input signal N1.
Since Q2 is turned off, MO is output from the output terminal CKI.
A high level corresponding to the power supply voltage VDD is output according to the ON state of the SFET Q1.

To output a low level from the output terminal CKIO, both the input signals P1 and N1 are set to a high level. That is, the P-channel MOSFET Q1 is turned off by the high level of the input signal P1, and the N-channel MOSFET Q1 is turned off by the high level of the input signal N1.
Since Q2 is turned on, MO is output from the output terminal CKI.
A low level corresponding to the ground potential VSS is output according to the ON state of the SFET Q2.

The sub-buffer is a P-channel type MOSF
ETQ3 and N-channel MOSFET Q4. The gate of the P-channel MOSFET Q3
The drive input signal P3 formed by the sub-buffer control is supplied, and the drive input signal N3 formed by the sub-buffer control is supplied to the gate of the N-channel MOSFET Q2.

The sub-buffer control is performed by a variable delay circuit D1 according to a first control signal set in a control register.
Is determined. The variable delay circuit D1 forms delay signals P2 and N2 obtained by respectively delaying the input signals P1 and N1 for driving the main buffer. The delay signal P2 is inverted by an inverter circuit N1 and supplied to one input of a NAND (NAND) gate circuit. The delay signal N2 is inverted by an inverter circuit N2 and supplied to one input of a NOR (NOR) gate circuit G2.

The delay time of the variable delay circuit D2 is determined by the second control signal set by the control register. The variable delay circuit D2 is connected to the delay signals P2 and N2.
Are respectively delayed and supplied to the other inputs of the NAND gate circuit G1 and the NOR gate circuit G2. That is, the NAND gate circuit G1 forms a logical signal P3 of an inverted signal of the delay signal P2 and a signal obtained by delaying the inverted signal by the variable delay circuit D2, and drives the P-channel MOSFET Q3 of the sub-buffer.
The NOR gate circuit G2 forms a logical signal N3 of an inverted signal of the delayed signal N2 and a signal obtained by delaying the inverted signal by the variable delay circuit D2, and drives the N-channel MOSFET Q4 of the sub-buffer.

The variable delay circuits D1 and D2 can be adjusted in delay amount by a control register comprising a plurality of programmable bits. The variable delay circuit D1 is an adjustment amount for the time length of the wiring connected to the output unit, and the variable delay circuit D2 is an adjustment amount for the time length of the influence of the reflection. In the figure, the adjustment of the delay amount is set by a control register. However, instead of this configuration, it is also possible to adopt an embodiment such as setting by a metal option or setting by an external mode pin in the layout.

FIG. 15 is a waveform chart for explaining an example of the operation of the output circuit OB2. The figure shows a waveform when the output signal is changed from L (low level) to H (high level). Input signals P1 and N
When 1 changes from the high level to the low level, the delay signals P2 and N2 are delayed by the delay time D1. The inverted signal (H) of the delay signal P2 and a signal obtained by delaying the delay signal P2 by the delay time D2 are supplied to the NAND gate circuit G1, and the output signal P3 is output from the delay time D1.
Changes to a low level after the elapse of the delay time, and becomes a high level signal after the elapse of the delay time D2. Since the P-channel MOSFET Q3 of the sub-buffer is turned on in response to the signal P3, the output level of the external terminal CKIO becomes
The intermediate potential is pulled up by the ON state of the MOSFET Q3.

That is, in FIG.
The output impedance in the ON state of TQ1 and the MOSF
Since the output impedance in the ON state of the ETQ3 is made parallel to pull up the intermediate potential due to the impedance matching, even if reflection noise as shown by a dotted line in FIG. Power supply voltage V
It is changed toward DD. Thus, in the input circuit that receives the signal of the external terminal CKIO, it is possible to prevent the occurrence of the glitch as described above.

FIG. 16 is a waveform chart for explaining another example of the operation of the output circuit OB2. In the figure, the output signal is changed from H (high level) to L (low level).
The waveform when changing to is shown. Input signal P1
And N1 are changed from the low level to the high level, the delay signals P2 and N2 are delayed by the delay time D1. The inverted signal (L) of the delay signal N2 and the delay signal N
2 is delayed by the delay time D2.
2, the output signal N3 changes to a high level after the elapse of the delay time D1, and furthermore, the output signal N3
After the lapse of 2, the signal becomes low level.

The N of the sub-buffer corresponds to the signal N3.
When the channel type MOSFET Q4 is turned on, M
By the ON state of OSFET Q4, the MOSFET Q2
Of the external terminal CKIO by pulling down the intermediate potential of the external terminal CKIO due to the impedance matching between the output impedance due to the ON state of the transmission line and the characteristic impedance of the transmission line. To the ground potential VSS of the circuit from the intermediate potential.
It is changed to go to. Thereby, the external terminal C
In the input circuit receiving the KIO signal, it is possible to prevent the occurrence of the glitch as described above.

In FIG. 12, when the master device is set to the second operation mode for the clock phase adjustment, the clock CKO1 formed by the feedback phase compensator is supplied to the external terminal CKI through the output circuit OB2.
Output from O / CKI to slave device.
The signal output from the external terminal CKIO / CKI is
The signal is fed back to the input side of the feedback type phase compensator by the input circuit IB. At this time, as described above, the external terminal CKIO /
In the CKI, a glitch elimination circuit is provided so that even if glitches due to reflection noise occur, the phase lock in the feedback phase compensator is not lost.

The glitch removing circuit is divided into a rising glitch removing circuit and a falling glitch removing circuit.
To remove glitches generated at the time of falling, an AND gate circuit G3 whose gate is controlled by the output signal of the feedback phase compensator, that is, the input signal O1 of the output buffer OB1 is used. An output signal I1 of the input buffer IB is transmitted through the AND gate circuit G3. An OR gate circuit G4 receiving the output signal I2 of the AND gate circuit is used to remove the glitch generated at the rising edge. The OR gate circuit G4 receives the signal I2 and the signal I3 obtained by delaying the signal I2 by the delay circuit Delay and feeds the signal I2 back to the feedback phase compensator.
4 is formed. The delay time of the delay circuit Delay can be adjusted by a control register. This delay time is set to a delay amount corresponding to the width of the rising glitch.

FIG. 14 is a waveform chart for explaining the operation of the glitch removing circuit. When the signal O1 falls from the high level to the low level, the signal O1 changes from the high level to the low level,
The gate of the AND gate circuit G3 is closed. As a result, the transmission of the glitch generated in the signal I1 in response to the reflected noise by the input buffer IB at the time of the fall is inhibited. As a result, no glitch occurs in the output signal I2 of the gate circuit G3 when it falls.

When the signal O1 rises from the low level to the high level, the signal O1 changes from the low level to the high level, and the gate of the AND gate circuit G3 is opened. As a result, at the time of the rise, the input buffer IB responds to the reflection noise and the signal I1
Is passed through the gate circuit G3 as it is, a glitch occurs at the rising edge of the signal I2. The glitch at the rise of the signal I2 is caused by the signal I2
(OR) gate circuit G receiving the delay signal I3
4, and the glitch-free feedback signal I4 is input to the feedback phase compensator. That is, the low level portion of the signal I2 due to the glitch is the delayed signal I2.
The signal overlaps with the high level portion due to the delay of 3 and is removed by the OR gate G4.

As described above, in the master device according to the present invention, the clock phase is adjusted by the feedback type phase compensator such as PLL or DLL, and the external terminal C is adjusted.
It has an operation mode for supplying from a KIO / CKI to a slave device such as a memory (not shown). In a master device having such an operation mode, a glitch is prevented from being generated as an output circuit OB2 by a combination of the main buffer, a sub-buffer, and a sub-buffer control, and a glitch removing circuit is added as an input buffer. In this embodiment, on the output circuit side, the generation of glitch is prevented or the amount of generation is reduced,
On the input circuit side, the amount of delay adjustment to be adjusted by the delay circuit Delay in response to the decrease in the amount of glitch generation can be reduced.

FIG. 17 is a flowchart for explaining a procedure for performing the clock synchronization (prevention, reduction, and elimination of glitches) in the semiconductor integrated circuit device according to the present invention. The wiring delay amount is calculated by determining the external load corresponding to the system configuration.
This delay amount is calculated as a portion deviated from the synchronization by the wiring equal length, that is, a wiring amount from an intermediate portion from the clock output of the master device to the slave device to an input of the slave device. In the case of prevention or reduction and removal of glitches, the reflection is calculated. The register value is determined according to the above calculation result. That is, a register value for synchronization, a register value for setting the operation timing of the sub-buffer, and a register value for setting the delay time of the delay circuit are obtained.

The register values as described above are stored in a ROM provided in the semiconductor integrated circuit device. This ROM
In addition to the most typical mask ROM, an electrically writable non-volatile memory or a fuse element to which writing is performed by cutting with a laser beam may be used. Since the register value is written in the ROM as described above, in the initial setting when the power is turned on to the semiconductor integrated circuit device, the reading of the value, that is, the reading of the ROM is performed. A register for setting a delay time of a delay circuit for synchronization,
Each value is set in the sub-buffer control and the control register for removing the rising glitch,
The operation of the semiconductor integrated circuit device starts.

The operation and effect obtained from the above embodiment are as follows. (1) A second circuit for exchanging data between a first circuit block that performs signal processing in response to a clock signal and the first circuit block in response to a supplied clock signal.
An information processing system including a feedback type phase compensator provided in the first circuit block;
Generating a clock signal directed to the second circuit block by synchronizing the clock signal with the feedback signal having a delay time in a signal transmission path from the circuit block to the second circuit block. By doing so, the clock skew between the devices is eliminated by devising the clock wiring, so that an effect that a system configuration of high-speed synchronous design can be realized with a simple configuration is obtained.

(2) In addition to the above, a signal transmission path from the output terminal of the feedback phase compensator to the input terminal of the feedback signal, and from the output terminal to the clock input terminal of the second circuit block. When the signal transmission path and the signal transmission path are configured to have the same length, an effect that a system of a high-speed synchronous design can be realized by a simple mounting form is obtained.

(3) In addition to the above, a signal transmission path from an output terminal of the feedback type phase compensator to an input terminal of the feedback signal, and a signal transmission path from the output terminal to a clock input terminal of the second circuit block. A signal transmission path from the intermediate point to the intermediate point has an equal length, and a delay circuit set to a delay time corresponding to the delay time in the signal transmission path from the intermediate point to the clock input terminal of the second circuit block is provided. By providing the feedback type phase compensator in the signal transmission path extending from the output terminal to the input terminal of the feedback signal, it is possible to obtain an effect that the mounting form of the system can have flexibility.

(4) In addition to the above, the first circuit block and the second circuit block are formed in a package that can be regarded as a single semiconductor integrated circuit device in appearance, thereby reducing the size of the system. And speeding up can be achieved.

(5) In addition to the above, by forming the first circuit block and the second circuit block in a semiconductor integrated circuit device, respectively, an effect is obtained that a system can be formed by assembling on a mounting board. Can be

(6) In addition to the above, a first external terminal for causing the first semiconductor integrated circuit device to output a clock signal formed by the feedback type phase compensator through a first output circuit; By providing a second external terminal for inputting a clock signal output from the first external terminal as a feedback signal, a flexible system can be realized, and no feedback signal glitch occurs. The effect that a stable operation of the vessel can be realized is obtained.

(7) In addition to the above, by extending the delay circuit into a variable delay circuit having a delay time set corresponding to a digital signal and incorporating the variable delay circuit in the first semiconductor integrated circuit device, it is possible to expand the system. The effect of being able to respond to changes is obtained.

(8) In addition to the above, a switch means for selectively transmitting a clock signal formed by the feedback phase compensator, and a second output for receiving the clock signal transmitted by the switch means By further providing a circuit and a signal output path for outputting an output signal of the second output circuit from the second external terminal, a clock can be supplied also from the second output circuit, thereby expanding or changing the system. The effect that it can respond also is obtained.

(9) In addition to the above, the switch means is set to transmit a signal, and the first and second external terminals each have one or more clocks of the second semiconductor integrated circuit device. By connecting the input terminals,
The effect is obtained that a system having a large number of slave devices can be constructed.

(10) In addition to the above, as the second output circuit, an output terminal is connected to the second external terminal, and the output matches the characteristic impedance of a signal transmission path connected to the output terminal. By using a main buffer having impedance, a sub-buffer having an output terminal connected to the second external terminal, and a control circuit for delaying the operation timing of the sub-buffer from the operation timing of the output buffer, the glitch of the feedback signal is reduced. Is obtained, and a stable operation of the feedback phase compensator can be realized.

(11) In addition to the above, an input circuit having an input terminal connected to the second external terminal is further provided, and an output signal of the input circuit and the second output are provided at an output section of the input circuit. A first logic gate circuit receiving an input signal of the circuit and removing a glitch when the output signal of the input circuit changes from a first level to a second level; and an output signal of the first logic gate circuit And a second logic gate circuit that receives the delay signal and removes a glitch when the output signal of the input circuit changes from the second level to the first level, thereby providing a glitch generated in the feedback signal. Is removed, and an effect that a stable operation of the feedback phase compensator can be realized is obtained.

(12) An internal clock signal, a feedback signal, and a feedback type phase compensator are supplied to generate a clock signal in which the clock signal and the feedback signal are synchronized, and the first clock signal is fed through a first output circuit. The clock signal of the second external terminal is supplied to an input circuit to generate a feedback signal of the feedback phase compensator, thereby eliminating clock skew between devices by contriving clock wiring. The effect is obtained that a semiconductor integrated circuit device suitable for a stable high-speed synchronous design system can be obtained.

(13) In addition to the above, a switch means for selectively transmitting a clock signal formed by the feedback phase compensator, and a second output receiving the clock signal transmitted by the switch means Circuit and a signal output path for outputting the output signal of the second output circuit from the second external terminal, thereby providing various systems such as a high-speed synchronous design system and a system having many slave devices. An advantage is obtained that a semiconductor integrated circuit device that can be used for a semiconductor device can be obtained.

(14) In addition to the above, in the first operation mode in which the switch means performs signal transmission, the second output circuit is set to the operating state, and the second operation mode in which the switch means does not perform signal transmission. In this case, a semiconductor integrated circuit device that can be used in various systems such as a high-speed synchronous design system and a system having many slave devices is selectively obtained by selectively using the second output circuit in an output high impedance state. Is obtained.

(15) In addition to the above, a variable delay circuit for changing a delay time is further provided between the output terminal of the input circuit and the feedback input terminal of the feedback phase compensator, thereby providing a system. The effect that the synchronization design can be performed in correspondence with the mounting form of (1) is obtained.

(16) In addition to the above, by further providing a register for setting the delay time of the variable delay circuit, there is an effect that a synchronization design corresponding to a system implementation can be performed by software. can get.

(17) In addition to the above, as the second output circuit, an output terminal is connected to the second external terminal, and the output matches the characteristic impedance of a signal transmission path connected to the output terminal. By using a main buffer having impedance, a sub-buffer having an output terminal connected to the second external terminal, and a control circuit for delaying the operation timing of the sub-buffer from the operation timing of the output buffer, the glitch of the feedback signal is reduced. Is obtained, and a stable operation of the feedback phase compensator can be realized.

(18) In addition to the above, the output section of the input circuit receives the output signal of the input circuit and the input signal of the second output circuit, and outputs the output signal of the input circuit to the first section. A first logic gate circuit for removing a glitch when the level changes from the second level to the second level; an output signal of the first logic gate circuit and a delay signal thereof; By providing the second logic gate circuit for removing glitches when the level changes from the first level to the first level, it is possible to remove glitches generated in the feedback signal and realize a stable operation of the feedback phase compensator. The effect is obtained.

The invention made by the present inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, the first
And the second circuit block may be formed on one semiconductor substrate. For example, with the development of semiconductor integrated circuit manufacturing technology, system LSI
In a large-scale integrated circuit such as that described above, a system is configured by combining a master block such as a microprocessor and a slave block such as a memory. High-speed synchronization that compensates for the propagation delay time can be realized.

In FIG. 12, the circuit for removing glitches is any circuit that generates a pulse in synchronization with the rising and falling timings at which the glitch occurs, and prohibits the transmission of the glitch using this pulse. You may. The information set in the control register is stored in a storage device such as a ROM and automatically read out and set, as well as input from an external terminal or a plurality of external terminals corresponding to digital signals. A fixed voltage of a high level and a low level may be supplied.
INDUSTRIAL APPLICABILITY The present invention can be widely used for information processing systems and semiconductor integrated circuit devices having a function of transmitting and receiving data in synchronization with a clock.

[0088]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. Information processing including a first circuit block for performing signal processing in response to a clock signal, and a second circuit block for transmitting and receiving data between the first circuit block in response to a supplied clock signal A feedback signal, wherein a feedback phase compensator is provided in the first circuit block so as to have a delay time in a signal transmission path from the first circuit block to the second circuit block. By generating a clock signal for the second circuit block by synchronizing the clock signal and the clock signal, clock skew between devices is eliminated by devising a clock wiring, so that a high-speed synchronous design can be achieved with a simple configuration. Can be realized.

The internal clock signal, the feedback signal, and the feedback type phase compensator are supplied to generate a clock signal in which the clock signal and the feedback signal are synchronized. The clock signal is supplied from a first external terminal through a first output circuit. By outputting the clock signal of the second external terminal to the input circuit and forming the feedback signal of the feedback type phase compensator, the clock skew between devices can be eliminated by contriving the clock wiring to achieve stable operation. A semiconductor integrated circuit device suitable for a high-speed synchronous design system can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing one embodiment of an information processing system according to the present invention.

FIG. 2 is a schematic block diagram showing another embodiment of the information processing system according to the present invention.

FIG. 3 is a schematic block diagram showing one embodiment of an information processing system according to the present invention.

FIG. 4 is a timing chart for explaining an example of the operation of the information processing system of FIG. 3;

FIG. 5 is a schematic block diagram showing another embodiment of the information processing system according to the present invention.

FIG. 6 is a schematic block diagram showing another embodiment of the information processing system according to the present invention.

FIG. 7 is a main block diagram showing one embodiment of a semiconductor integrated circuit device suitable for the information processing system according to the present invention.

FIG. 8 is a timing chart for explaining the operation of the feedback phase comparator provided in the semiconductor integrated circuit device according to the present invention.

FIG. 9 is a main part block diagram showing another embodiment of a semiconductor integrated circuit device suitable for the information processing system according to the present invention.

FIG. 10 is a schematic block diagram showing another embodiment of the information processing system according to the present invention.

FIG. 11 is a configuration diagram for describing a problem in a clock supply circuit using a feedback phase compensator.

FIG. 12 is a main part block diagram showing another embodiment of a semiconductor integrated circuit device suitable for the information processing system according to the present invention.

FIG. 13 is a circuit diagram showing one embodiment of the output circuit OB2 of FIG.

14 is a waveform chart for explaining the operation of the glitch removal circuit in FIG.

15 is a waveform chart for explaining an example of the operation of the output circuit OB2 of FIG.

FIG. 16 is a waveform chart for explaining another example of the operation of the output circuit OB2 of FIG.

FIG. 17 is a flowchart illustrating a procedure for performing the clock synchronization (prevention, reduction, and removal of glitches) in the semiconductor integrated circuit device according to the present invention.

FIG. 18 is a timing chart for explaining an example of the operation of the conventional information processing system.

[Explanation of symbols]

FF1 to FF4: flip-flop circuit, IB: input circuit, OB1: first output circuit, OB2: second output circuit, D1, D2, Delay: delay circuit, Q1 to Q4: MO
SFETs, G1 to G4 ... gate circuits, N1, N2 ... inverter circuits.

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (19)

[Claims] A first circuit block that performs signal processing in response to a first clock signal and supplies a clock signal corresponding to the first clock signal to a first terminal; and a clock signal of the first terminal. And a second circuit block for transmitting and receiving data to and from the first circuit block, wherein the first circuit block transmits a signal delayed with respect to a clock of the first terminal. A feedback type phase compensator that receives the feedback signal and controls the phase of the clock signal supplied to the first terminal, wherein a delay time of the feedback signal with respect to the first clock signal is equal to the first circuit block; An information processing system having a delay time for compensating for a delay time in a signal transmission path to be provided between the information processing system and the second circuit block. 2. The feedback signal according to claim 1, wherein a first signal transmission path from the first terminal to the clock input terminal of the second circuit block is extracted, and a signal is taken out of the first signal transmission path. And a second signal transmission path to be supplied to an input terminal for the information processing. 3. A signal transmission path from the first terminal to an input terminal for the feedback signal, and a signal transmission path from the first terminal to a clock input terminal of the second circuit block. The information processing system is characterized by having the same length. 4. The signal transmission path according to claim 1, wherein the signal transmission path extends from the first terminal to the input terminal for the feedback signal, and a signal transmission path extends from the first terminal to a clock input terminal of the second circuit block. The signal transmission path to the point is of equal length, and the delay circuit set to a delay time corresponding to the delay time in the signal transmission path from the intermediate point to the clock input terminal of the second circuit block is the same as the delay circuit described above. An information processing system provided on a signal transmission path leading to one terminal and an input terminal for a feedback signal. 5. The semiconductor device according to claim 2, wherein the first circuit block and the second circuit block are one
An information processing system formed in one package which is regarded as one semiconductor integrated circuit device. 6. The semiconductor device according to claim 2, wherein the first circuit block is formed in a first semiconductor integrated circuit device, and the second circuit block is formed in a second semiconductor integrated circuit device. An information processing system, comprising: 7. The first semiconductor integrated circuit device according to claim 6, wherein the first semiconductor integrated circuit device comprises: a first external terminal as the first terminal to which a clock signal formed by the feedback phase compensator is supplied; An information processing system having a second external terminal as the input terminal for a feedback signal. 8. The information according to claim 7, wherein the delay circuit is a variable delay circuit built in the first semiconductor integrated circuit device and having a delay time set by a digital signal. Processing system. 9. The feedback type phase compensator according to claim 7, wherein the first semiconductor integrated circuit device is provided between an output of the feedback type phase compensator and the first external terminal. And a second output circuit provided between the output of the feedback phase compensator and the second external terminal. A first switch state enabling transmission of the output of the feedback phase compensator to the second external terminal via the second output circuit; and Second
An information processing system, further comprising a switch having a second switch state for disabling transmission to the second external terminal via the output circuit of (1). 10. The clock of one or more second semiconductor integrated circuit devices according to claim 9, wherein said switch means is set so as to transmit a signal, and said first and second external terminals each have a clock of one or more second semiconductor integrated circuit devices. An information processing system to which an input terminal is connected. 11. The output impedance according to claim 10, wherein an output terminal is connected to the second external terminal, and the second output circuit matches a characteristic impedance of a signal transmission path to be connected to the output terminal. A first output buffer circuit having an output terminal connected to the second external terminal, and an operation timing of the second output buffer circuit being shorter than an operation timing of the first output buffer circuit. An information processing system, comprising: a control circuit for delaying. 12. The input circuit according to claim 10, further comprising: an input circuit having an input terminal connected to the second external terminal, wherein an output section of the input circuit includes an output signal of the input circuit and the second output terminal. A first logic circuit receiving the input signal of the output circuit, and removing a glitch when the output signal of the input circuit changes from the first level to the second level; and an output signal of the first logic circuit. And a second logic circuit for receiving the delay signal and removing a glitch when the output signal of the input circuit changes from the second level to the first level. 13. A feedback phase compensator for receiving an internal clock signal and a feedback signal to generate a clock signal in which the clock signal and the feedback signal are synchronized, and formed by the feedback phase compensator. A first output circuit for receiving a clock signal, a first external terminal connected to an output terminal of the first output circuit, and a clock signal for receiving a clock signal from a second external terminal; A semiconductor integrated circuit device comprising: an input circuit for forming the feedback signal. 14. The feedback type phase compensator according to claim 13, wherein a second output circuit provided between an output of the feedback type phase compensator and the second external terminal; A first operation mode enabling transmission to the second external terminal via the second output circuit, and a second operation mode for outputting the output of the feedback phase compensator.
And a switch having a second operation mode for disabling transmission to the second external terminal via the output circuit. 15. The second output circuit according to claim 14, wherein the second output circuit is activated when the switch is in the first operation mode in which the switch transmits signals. A semiconductor integrated circuit device, wherein the second output circuit is in an output high impedance state in an operation mode. 16. A variable delay circuit capable of controlling a delay time between an output terminal of the input circuit and a feedback input terminal of the feedback phase compensator according to any one of claims 13 to 15. A semiconductor integrated circuit device comprising: 17. The semiconductor integrated circuit device according to claim 16, further comprising a register for setting a delay time of said variable delay circuit. 18. The second output circuit according to claim 14, wherein an output terminal is connected to the second external terminal, and a characteristic impedance of a signal transmission path to be connected to the output terminal. A first output buffer circuit having an output impedance matching the first output buffer circuit, an output terminal connected to the second external terminal, and an operation timing of the second output buffer circuit. And a control circuit that delays the operation timing of the semiconductor integrated circuit. 19. The output circuit according to claim 18, wherein the output section of the input circuit receives an output signal of the input circuit and an input signal of the second output circuit, and outputs an output signal of the input circuit to a first level. A first logic circuit for removing a glitch when the signal changes from the second level to the second level, and an output signal of the input circuit receiving the output signal of the first logic circuit and its delay signal from the second level. A second logic circuit that removes a glitch when the level changes to one level.