JP2002313943A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which P- and N-channel transistors having low threshold voltages and different kinds of metal gate electrodes can be formed by a simple manufacturing method. SOLUTION: In this semiconductor device having the P-channel transistor 1 and N-channel transistor 2, the gate electrode 21 of the transistor 1 is composed of rhenium and the gate electrode 31 of the transistor 2 is composed of a rhenium-titanium alloy.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a gate electrode using rhenium and a rhenium alloy and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional MOSFET (Metal Oxide Semi
The gate electrode of a conductor field effect transistor) was generally formed using polycrystalline silicon.
Recently, demands to reduce power consumption have led to NMO
It is common to use a so-called dual gate structure in which N-type polycrystalline silicon is used for the gate electrode of the S transistor and P-type polycrystalline silicon is used for the gate electrode of the PMOS transistor.

In the above-mentioned dual gate structure, there is a problem of so-called boron penetration, in which boron contained in P-type polycrystalline silicon diffuses into a silicon substrate through a gate insulating film. Further, since a depletion layer always occurs at the interface with the gate insulating film in polycrystalline silicon, the capacitance-converted thickness of the gate insulating film is larger than the actual thickness. Therefore, in order to reduce the thickness of the gate insulating film for miniaturization of the device, 0.5 nm to 1.0 nm
It is necessary to make it extra thin. By reducing the thickness of the gate insulating film in this manner, a problem that a tunnel leak current increases has arisen.

As a method for solving such a problem of polycrystalline silicon, use of a refractory metal as a gate electrode material has been considered. The metal gate electrode does not have the problem of the penetration of boron and the problem of the generation of a depletion layer. On the other hand, the metal gate electrode has a new problem that the threshold voltage is higher than that of the polycrystalline silicon gate electrode.

[0005] For example, when titanium nitride is used as a gate electrode material, the threshold electrode cannot be lowered to 0.4 V or less even if the impurity distribution on the surface of the silicon substrate is adjusted, Nishinohara et al. ., Extended Abstracts of the
2000 International Conference on Solid State Devi
ces and Materials, B-1-4 (2000) p.46-47. The reason is that the work function of titanium nitride is 4.5 e
V, and is located near the mid-gap of the silicon forbidden band.
The work function difference is about 0 for both transistors.
This is because it becomes about 5 eV.

Therefore, the idea of forming the gate electrode of the PMOS transistor and the gate electrode of the NMOS transistor using different kinds of metals has been proposed in, for example, The In.
ternational Technology Roadmap for Semiconductors,
(1999) p.128. That is, rhenium or iridium having a work function of about 5.0 eV and located near the upper end of the valence band of the silicon substrate is used for the gate electrode of the PMOS transistor, and silicon having a work function of about 4.0 eV is used for the gate electrode of the NMO transistor. The idea is to use niobium or zirconium located near the bottom of the conduction band of the substrate.

[0007]

SUMMARY OF THE INVENTION However, PMO
In order to use different kinds of metals for the gate electrode of the S transistor and the gate electrode of the NMOS transistor, the respective gate electrodes must be formed in different steps. For example, a PMO is formed over the entire surface of a gate insulating film of an NMOS transistor while the gate insulating film is hidden by a dummy film such as polycrystalline silicon.
After depositing, for example, iridium as a gate electrode material of the S transistor, the iridium other than the region where the PMOS transistor is formed is removed. Next, after removing the dummy film in the formation region of the NMOS transistor, an NMO
For example, zirconium is deposited as a gate electrode material of the S transistor. After that, zirconium other than the region where the NMOS transistor is formed is removed. As described above, two film forming steps, two lithography (eg, mask) steps, and two removal (eg, etching) steps are required, so that the number of steps is greatly increased and the steps become very long. The formation method is also complicated and difficult. Therefore, different types of metal gate electrodes that can be formed by a simple manufacturing method have been demanded.

[0008]

SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device and a method of manufacturing the same to solve the above-mentioned problems.

A semiconductor device according to the present invention is a semiconductor device having a P-channel transistor and an N-channel transistor, wherein the gate electrode of the P-channel transistor is made of rhenium, and the gate electrode of the N-channel transistor is made of a rhenium titanium alloy. It becomes.

In the above semiconductor device, the gate electrode of the P-channel transistor is made of rhenium, and its work function is 4.75 eV. The work function at the upper end of the valence band of silicon is 5.17 eV. Since the work functions have close values, the threshold voltage of the PMOS transistor can be easily reduced to about 0.3 V or less. The gate electrode of the N-channel transistor is made of a rhenium-titanium alloy, and its work function is 4.18 eV when titanium is 17 atomic%, for example. The work function value of a rhenium titanium alloy is described in, for example,
Edition Chemistry Handbook Basic Edition II ”(Heisei 5-9-30) Maruzen II-4
90. The work function at the bottom of the conduction band of silicon is 4.05 eV. Since the work functions have close values, the threshold voltage of the NMOS transistor can be easily reduced to about 0.3 V or less.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which a P-channel transistor and an N-channel transistor are formed on a semiconductor substrate.
Forming a gate electrode of a channel transistor and a gate electrode of the N-channel transistor with rhenium;
Selectively introducing titanium into the gate electrode of the N-channel transistor to form a rhenium-titanium alloy.

In the method of manufacturing a semiconductor device, the step of forming the gate electrode of the P-channel transistor and the gate electrode of the N-channel transistor with rhenium;
Since a step of selectively introducing titanium into the gate electrode of the channel transistor and forming a rhenium-titanium alloy is provided, the gate electrode of the P-channel transistor and the gate electrode of the N-channel transistor are formed by a single film forming step of rhenium. If a mask is used for the introduction of titanium, two lithography steps are performed together with a resist mask forming step used when patterning the deposited rhenium on the gate electrode, and one lithography step is performed to pattern the deposited rhenium on the gate electrode. Since only a removal (for example, etching) process is required, the number of processes is small and the process is simple.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the semiconductor device according to the present invention will be described with reference to the schematic sectional view of FIG.

As shown in FIG. 1, a silicon substrate 11 has an element isolation region 12 for separating a region for forming a P-channel transistor and a region for forming an N-channel transistor.
Are formed, for example, by STI (Shallow Trench Isolation) technology. This element isolation region 12 is LOC
It may be formed by OS (Local Oxidation of Silicon) technology. A P-well 13 is formed in the formation region of the N-channel transistor, and an N-well 14 is formed in the formation region of the P-channel transistor. Further, an impurity for adjusting a threshold voltage is introduced into the upper layer of the P well 13 and the N well 14.

On the silicon substrate 11, a gate insulating film 15 is formed of, for example, a silicon oxide film having a thickness of 2.5 nm. Further, a gate electrode 21 is formed on the silicon substrate 11 in the formation region of the P-channel transistor via the gate insulating film 15, for example,
It is formed of a rhenium film having a thickness of 0 nm. Also, N
A gate electrode 31 is formed on the silicon substrate 11 in the formation region of the channel transistor via the gate insulating film 15. The gate electrode 31 is formed, for example, by introducing titanium into a rhenium film of the same layer as the gate electrode 21 so that the titanium content is 12 atomic% or more and 22 atomic% or less. The method of introducing titanium is, for example, by an ion implantation method.

When the titanium concentration is lower than 12 atomic% and higher than 22 atomic%, the work function of the rhenium titanium alloy deviates from the work function (4.05 eV) at the lower end of the conduction band of silicon. Not preferred. Therefore, as described above, it is preferable that the titanium concentration in the rhenium film be 12 atomic% or more and 22 atomic% or less.

The N on both sides of the gate electrode 21
Above the well region 14, lightly doped diffusion layers 22 and 23 of a P-channel transistor are formed. A side wall 24 is formed on the side wall of the gate electrode 21 by, for example, a silicon nitride film. Further, the above gate electrode 2
Source / drain diffusion layers 25 and 26 of a P-channel transistor are formed on the N-well region 14 on both sides of the transistor 1 via the low-concentration diffusion layers 22 and 23.

On the other hand, lightly doped diffusion layers 32 and 33 of an N-channel transistor are formed on the P well region 13 on both sides of the gate electrode 31. A sidewall 34 is formed on each side wall of the gate electrode 31 by, for example, a silicon nitride film. Further, source / drain diffusion layers 35 and 36 of the P-channel transistor are formed on the P well region 13 on both sides of the gate electrode 31 via the low concentration diffusion layers 32 and 33.

As described above, the P-channel transistor 1 and the N-channel transistor 2 are formed.

In the above-described semiconductor device, the gate electrode 21 of the P-channel transistor 1 is made of rhenium and has a work function of 4.75 eV. The work function at the upper end of the valence band of silicon is 5.17 eV. Since the work functions have close values, the threshold voltage of the P-channel transistor 1 can be easily reduced to about 0.3 V or less. The gate electrode 31 of the N-channel transistor 2 is made of a rhenium-titanium alloy, and its work function is 4.18 eV when titanium is 17 atomic%, for example. For example, the work function value of a rhenium-titanium alloy is described in “Revised 4th Edition, Basic Handbook of Chemistry II” (edited by The Chemical Society of Japan)
0) It is described in Maruzen II-490. The work function at the bottom of the conduction band of silicon is 4.05 eV.
Since the work functions have close values, the threshold voltage of the N-channel transistor 2 can be easily reduced to about 0.3 V or less.

Next, a second embodiment according to the semiconductor device of the present invention will be described with reference to the schematic sectional view of FIG.
2, the same components as those described with reference to FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 2, on a silicon substrate 11, an element isolation region 12 for separating a P-channel transistor formation region and an N-channel transistor formation region is provided.
Are formed, for example, by STI (Shallow Trench Isolation) technology. This element isolation region 12 is LOC
It may be formed by OS (Local Oxidation of Silicon) technology. A P-well 13 is formed in the formation region of the N-channel transistor, and an N-well 14 is formed in the formation region of the P-channel transistor. Further, an impurity for adjusting a threshold voltage is introduced into the upper layer of the P well 13 and the N well 14.

On the silicon substrate 11, an interlayer insulating film 4 is formed.
5 is formed of, for example, a silicon oxide film. Gate grooves 46 and 47 are formed in the interlayer insulating film 45 in the formation region of the P-channel transistor and the formation region of the N-channel transistor. Each gate groove 46, 4
The sidewall of 7 is formed by sidewalls 24 and 34. On the inner surface of each of the gate grooves 46 and 47, a gate insulating film 48 is formed of, for example, an aluminum oxide film having a thickness of 7 nm. Further, a gate electrode 21 made of a rhenium film 49 is formed in the gate groove 46 in the formation region of the P-channel transistor with the gate insulating film 48 interposed therebetween.
Further, the gate groove 4 in the region where the N-channel transistor is formed is formed.
7 has a gate electrode 31 with the gate insulating film 48 interposed therebetween.
Are formed. The gate electrode 31 is formed, for example, by introducing titanium into a rhenium film 49 of the same layer as the gate electrode 21 so that the titanium content is 12 atomic% or more and 22 atomic% or less. The method of introducing titanium is, for example, by an ion implantation method.

When the titanium concentration is lower than 12 atomic% and higher than 22 atomic%, the work function of the rhenium titanium alloy deviates from the work function (4.05 eV) at the bottom of the conduction band of silicon. Not preferred. Therefore, as described above, it is preferable that the titanium concentration in the rhenium film be 12 atomic% or more and 22 atomic% or less.

The N on both sides of the gate electrode 21
Above the well region 14, lightly doped diffusion layers 22 and 23 of a P-channel transistor are formed. Further, source / drain diffusion layers 25 and 26 of the P-channel transistor are formed on the N well region 14 on both sides of the gate electrode 21 via the low concentration diffusion layers 22 and 23.

On the other hand, lightly doped diffusion layers 32 and 33 of an N-channel transistor are formed on the P well region 13 on both sides of the gate electrode 31. Further, the P well region 13 on both sides of the gate electrode 31 is formed.
In the upper layer, the source / drain diffusion layers 35, 36 of the P-channel transistor are interposed via the low concentration diffusion layers 32, 33.
Are formed.

As described above, the P-channel transistor 3 and the N-channel transistor 4 are formed.

In the second embodiment, the first
The same operation and effect as those of the embodiment can be obtained.

The first aspect of the method for manufacturing a semiconductor device of the present invention is as follows.
The embodiment will be described with reference to schematic sectional views of FIGS. 3 and 4, the same components as those described with reference to FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 3A, an element isolation region 12 for separating a P-channel transistor formation region and an N-channel transistor formation region is formed on a silicon substrate 11.
Is formed by, for example, STI (Shallow Trench Isolation) technology. This element isolation region 12 has a LOCOS (L
Oxidation of Silicon) technology. Next, a P well 13 is formed in the formation region of the N-channel transistor, and an N well 14 is formed in the formation region of the P-channel transistor. The P well 13 and the N well 14 can be formed by, for example, an ion implantation method using a mask provided with an opening only on each region.

Next, an impurity is introduced into P well 13 and N well 14 in order to adjust the threshold voltage. This impurity introduction can be performed, for example, by an ion implantation method using a mask having openings only on the respective regions. Next, as shown in FIG.
A gate insulating film 15 is formed on the substrate 1. The gate insulating film 15 is formed by, for example, forming a silicon oxide film having a thickness of 2.5 nm in an oxidizing atmosphere at 750 ° C. by a pyrogenic oxidation method using nitrogen dilution.

Next, as shown in FIG.
By a D (Physical Vapor Deposition) method, a rhenium film 16 is formed to a thickness of, for example, 100 nm on the silicon substrate 11 on which the above processing has been performed. Subsequently, a resist film 17 is formed on the rhenium film 16 by a coating method. Thereafter, the resist film is exposed to light by lithography so that an opening is formed in a region where the N-channel transistor is formed, and then is developed and baked to be patterned into a resist mask. Using the patterned resist film 17 as a mask, titanium is introduced into the rhenium film on the N-channel transistor formation region by an ion implantation method. In this ion implantation method, the rhenium film 16
For example, the dose is set to 6 × 10 ¹⁴ / cm ² or more so that the concentration of titanium therein becomes 12 atomic% or more and 22 atomic% or less.
Ion implantation is performed so as to be 1.1 × 10 ¹⁵ / cm ² or less.

When the titanium concentration is lower than 12 atomic% and higher than 22 atomic%, the work function of the rhenium titanium alloy deviates from the work function at the bottom of the conduction band of silicon (4.05 eV). Not preferred. Therefore, as described above, it is preferable that the titanium concentration in the rhenium film be 12 atomic% or more and 22 atomic% or less.

After removing the resist film 17, a heat treatment is performed to convert the rhenium film on the N-channel transistor formation region into a rhenium-titanium alloy, thereby forming a rhenium-titanium alloy film 18. In this heat treatment, for example, the atmosphere is nitrogen, the processing temperature is set to 800 ° C. to 1100 ° C., and the processing time is set to 0.001 minute to 10 minutes. Note that the heat treatment time is appropriately selected by an existing heat treatment method such as laser annealing, lamp annealing, and furnace annealing that can also perform spike annealing. Further, this heat treatment can also serve as a heat treatment for activating impurities to be performed later. In that case, the heat treatment for alloying need not be performed here.

Next, the rhenium film 16 is applied by a coating method.
After a resist film is formed thereon, the resist film is processed by a normal lithography technique to form a resist pattern (not shown) for forming a gate electrode. Next, etching using this resist pattern as a mask,
The rhenium film 16 and the rhenium titanium alloy film 18 are patterned by, for example, reactive ion etching (RIE) to form the gate electrode 21 of the P-channel transistor with the rhenium film 16 as shown in FIG. Then, the gate electrode 31 of the N-channel transistor is formed of the rhenium titanium alloy film 18. Thereafter, the resist pattern used as the etching mask is removed.

Next, as shown in FIG. 4 (5), a resist film (not shown) is formed which covers the formation region of the N-channel transistor and has an opening in the formation region of the P-channel transistor. Film and the gate electrode 21
Is used as a mask to introduce a P-type impurity (for example, boron or boron difluoride) into the upper layer of the N-well region 14,
The low concentration diffusion layers 22 and 23 of the P-channel transistor are formed. After that, the resist film is removed.

Next, a resist film (not shown) is formed to cover the formation region of the P-channel transistor and to have an opening in the formation region of the N-channel transistor. A type impurity (for example, phosphorus or arsenic) is introduced into the upper layer of the P well region 13 to form the low concentration diffusion layers 32 and 33 of the N channel transistor. After that, the resist film is removed.

The formation of the low concentration diffusion layers 22 and 23 and the formation of the low concentration diffusion layers 32 and 33 may be performed in any order.

Next, an insulating film is formed by depositing silicon nitride by, for example, a chemical vapor deposition method so as to cover the gate electrodes 21 and 31, and the insulating film is etched back to form the gate electrodes 21 and 31. Side walls 24 and 34 are formed on each side wall of the base 31.

Next, as shown in FIG. 4 (6), a resist film (not shown) is formed which covers the N-channel transistor formation region and has an opening in the P-channel transistor formation region. Film and the gate electrode 21
P-type impurities (for example, boron or boron difluoride) are introduced into the upper layer of the N-well region 14 using the mask and the sidewalls 24 as masks, and the source / drain diffusion layers 25 and 26 of the P-channel transistor are 21
Are formed in the N-well region 14 on both sides of the low density diffusion layers 22 and 23. After that, the resist film is removed.

Next, a resist film (not shown) is formed to cover the formation region of the P-channel transistor and provide an opening in the formation region of the N-channel transistor, and the resist film, the gate electrode 31 and the sidewalls 34 are formed. And an N-type impurity (for example, phosphorus or arsenic)
Is introduced into the upper layer of the P well region 13 to form source / drain diffusion layers 35 and 36 of the N-channel transistor in the P well region 13 on both sides of the gate electrode 31 via the low concentration diffusion layers 32 and 33. I do. afterwards,
The resist film is removed.

The source / drain diffusion layers 25,
Either of the source and drain diffusion layers 35 and 36 may be formed first.

Thereafter, a heat treatment for activating the impurities is performed.
By this heat treatment, each source / drain 25, 26,
35, 36, each low concentration diffusion layer 22, 23, 32, 33,
The impurities in the P well region 13 and the N well region 14 are activated. As the heat treatment conditions, for example, the atmosphere is set to nitrogen, the processing temperature is set to 800 ° C. to 1100 ° C., and the processing time is set to 0.001 minute to 10 minutes. Note that the heat treatment time is appropriately selected by an existing heat treatment method such as laser annealing, lamp annealing, and furnace annealing that can also perform spike annealing. If heat treatment is not performed after ion implantation of titanium into the rhenium film 16, the heat treatment for activation can diffuse titanium into the rhenium film 16 to promote alloying of rhenium-titanium. It is. Thus, P-channel transistor 1 and N-channel transistor 2 are completed.

In the manufacturing method according to the first embodiment, P
After forming the gate electrode 21 of the channel transistor 1 and the gate electrode 31 of the N-channel transistor 2 with the rhenium film 16, the gate electrode 31 of the N-channel transistor 2 is formed.
And the rhenium film 16 is formed into a rhenium-titanium alloy to form a rhenium-titanium alloy film 18. Thus, the gate electrode 21 of the p-channel transistor 1 is formed.
And the gate electrode 31 of the N-channel transistor 2 are formed by a single film forming step of the rhenium film 16 and, if a mask is used for introducing titanium, the formed rhenium film 16 is formed by the gate electrode 2.
Only two lithography steps in combination with a resist mask forming step used for patterning into 1 and 31 and one removal (eg, etching) step to pattern the formed rhenium film 16 on the gate electrodes 21 and 31 are required. Therefore, the number of steps is small and the operation becomes simple.

In the manufacturing method according to the first embodiment, since the gate electrode 21 of the P-channel transistor 1 is formed of the rhenium film 16, its work function is 4.7.
5 eV. The work function at the upper end of the valence band of silicon is 5.17 eV. Since the work functions have close values, the threshold voltage of the P-channel transistor 1 can be easily reduced to about 0.3 V or less.
Further, titanium is ion-implanted into the rhenium film 16 to form a rhenium-titanium alloy film 18 and the rhenium-titanium alloy film 18 is used for the gate electrode 31 of the N-channel transistor 2. %, It becomes 4.18 eV. The work function at the bottom of the conduction band of silicon is 4.05 eV. Since the work functions have close values, the threshold voltage of the N-channel transistor 2 can be easily reduced to about 0.3 V or less.

Next, a second embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to the schematic sectional views of FIGS. 5 and 6, the same components as those described with reference to FIG. 2 are denoted by the same reference numerals.

As shown in FIG. 5A, an element isolation region 12 for separating a P-channel transistor formation region and an N-channel transistor formation region from a silicon substrate 11 is formed.
Is formed by, for example, STI (Shallow Trench Isolation) technology. This element isolation region 12 has a LOCOS (L
Oxidation of Silicon) technology. Next, a P well 13 is formed in the formation region of the N-channel transistor, and an N well 14 is formed in the formation region of the P-channel transistor. The P well 13 and the N well 14 can be formed by, for example, an ion implantation method using a mask provided with an opening only on each region.

Next, impurities are introduced into P well 13 and N well 14 in order to adjust the threshold voltage. This impurity introduction can be performed, for example, by an ion implantation method using a mask having openings only on the respective regions. Next, as shown in FIG.
A dummy gate insulating film 41 is formed of a silicon oxide film having a thickness of, for example, 10 nm on the substrate 1. Next, the dummy gate electrode film 42 is, for example, 1
It is formed of a 00 nm polycrystalline silicon film.

Next, after a resist film is formed on the dummy gate electrode film 42 by a coating method, the resist film is processed by a usual lithography technique to form a resist pattern (not shown) for forming a dummy gate electrode. ) Is formed. Subsequently, etching using this resist pattern as a mask, for example, reactive ion etching (RIE)
Thus, the dummy gate electrode film 42 is patterned, and as shown in FIG. 5C, the dummy gate electrode film 42 is
And a dummy gate electrode 44 of an N-channel transistor are formed. Thereafter, the resist pattern used as the etching mask is removed.

Next, as shown in FIG. 5D, a resist film (not shown) is formed which covers the formation region of the N-channel transistor and has an opening in the formation region of the P-channel transistor. Using the film and the dummy gate electrode 43 as a mask, a P-type impurity (for example, boron or boron difluoride) is introduced into the upper layer of the N well region 14, and the low concentration diffusion layers 22 and 2 of the P channel transistor are formed.
Form 3 After that, the resist film is removed.

Next, a resist film (not shown) is formed to cover the P-channel transistor formation region and provide an opening in the N-channel transistor formation region, and the resist film and the dummy gate electrode 44 are used as a mask. An N-type impurity (for example, phosphorus or arsenic) is
3 to form the low-concentration diffusion layers 32 and 33 of the N-channel transistor. After that, the resist film is removed.

The formation of the low-concentration diffusion layers 22 and 23 and the low-concentration diffusion layers 32 and 33 may be performed in any order.

Next, after an insulating film is formed on the entire surface, the insulating film is etched back and the dummy gate electrode 43,
Sidewalls 24 and 34 are formed on each side wall 44.
The insulating film is formed by depositing silicon nitride by, for example, a chemical vapor deposition method.

Next, a resist film (not shown) is formed to cover the N-channel transistor formation region and provide an opening in the P-channel transistor formation region, and the resist film, the dummy gate electrode 43, and the side wall are formed. 24, a P-type impurity (for example, boron or boron difluoride) is introduced into the upper layer of the N well region 14, and the low concentration diffusion layer 22 is formed in the N well region 14 on both sides of the dummy gate electrode 43. 23, the source / drain diffusion layers 25, 2 of the P-channel transistor
6 is formed. After that, the resist film is removed.

Next, a resist film (not shown) is formed to cover the P-channel transistor formation region and provide an opening in the N-channel transistor formation region, and the resist film, the dummy gate electrode 44, and the sidewalls are formed. 34, an N-type impurity (for example, phosphorus or arsenic) is introduced into the upper layer of the P well region 13 and the P well region 13 on both sides of the dummy gate electrode 44 is interposed through the low concentration diffusion layers 32 and 33. Thus, source / drain diffusion layers 35 and 36 of the N-channel transistor are formed. After that, the resist film is removed.

The source / drain diffusion layer 25,
Either of the source and drain diffusion layers 35 and 36 may be formed first.

Next, an interlayer insulating film 45 is formed of, for example, a silicon oxide film so as to cover the dummy gate electrodes 43 and 44 by a chemical vapor deposition method. This interlayer insulating film 45
Are formed at least higher than the dummy gate electrodes 43 and 44.

Thereafter, as shown in FIG. 6 (5), the surface of the interlayer insulating film 45 is flattened by a flattening technique, and the upper portions of the dummy gate electrodes 43 and 44 (see FIG. 6 (4)) are formed. To expose. As this flattening technique, for example, chemical mechanical polishing can be used. Alternatively, an etching method may be used. Next, the dummy gate electrodes 43 and 44 [see (4) in FIG. 6] and the dummy gate insulating film 41 thereunder are removed by, for example, etching to form gate grooves 46 and 47. In the etching of the dummy gate insulating film 41, the upper layer of the interlayer insulating film 45 is also etched.

Next, as shown in (6) of FIG.
A gate insulating film 48 is formed on the inner surfaces of the gate grooves 46 and 47 by depositing, for example, aluminum oxide to a thickness of 7 nm by a (Physical Vapor Deposition) method. At this time, the gate insulating film 48 is also formed on the interlayer insulating film 45. Further, the gate grooves 46, 4
Then, a rhenium film 49 is formed so as to bury 7.

Next, as shown in FIG. 6 (7), the rhenium film 49 and the gate insulating film 48 formed on the interlayer insulating film 45 by chemical mechanical polishing.
[See (6) in FIG. 6] is removed. Thus, the rhenium film 49 is embedded in the gate grooves 46 and 47 via the gate insulating film 48.

Subsequently, the interlayer insulating film 45 is formed by a coating method.
A resist film 50 is formed thereon. After that, the resist film 50 is exposed by lithography so that the opening 51 is formed on the region where the N-channel transistor is to be formed. Then, the resist film 50 is patterned into a resist mask by performing development, baking and the like. This patterned resist film 5
Using 0 as a mask, titanium is introduced into the rhenium film 49 above the N-channel transistor formation region by an ion implantation method. In this ion implantation method, for example, the dose is set to 6 × 10 ¹⁴ / cm ² or more so that the titanium concentration in the rhenium film 16 becomes 12 atom% or more and 22 atom% or less.
Ion implantation is performed so as to be 1 × 10 ¹⁵ / cm ² or less.

When the titanium concentration is lower than 12 atomic% and higher than 22 atomic%, the work function of the rhenium titanium alloy deviates from the work function at the bottom of the conduction band of silicon (4.05 eV). Not preferred. Therefore, as described above, it is preferable that the titanium concentration in the rhenium film be 12 atomic% or more and 22 atomic% or less.

Thereafter, a heat treatment is performed as shown in FIG. As the heat treatment conditions, for example, the atmosphere is set to nitrogen, the processing temperature is set to 800 ° C. to 1100 ° C., and the processing time is set to 0.001 minute to 10 minutes. The heat treatment time is appropriately selected according to an existing heat treatment method such as laser annealing, lamp annealing, and furnace annealing that can also perform spike annealing. By this heat treatment, each source / drain 25, 26, 3
5, 36, each low concentration diffusion layer 22, 23, 32, 33, P
The impurities in well region 13 and N well region 14 are activated. Further, titanium is diffused into the rhenium film 49 to promote alloying with rhenium titanium. Thus, the rhenium film 49 is formed in the gate groove 46 via the gate insulating film 48.
Is formed, and a gate electrode 31 made of a rhenium-titanium alloy film is formed in the gate groove 47 with a gate insulating film 48 interposed therebetween, whereby the P-channel transistor 3 and the N-channel transistor 4 are completed.

In the manufacturing method of the second embodiment, P
After forming the gate electrode 21 of the channel transistor 3 and the gate electrode 31 of the N-channel transistor 4 with the rhenium film 49, the gate electrode 31 of the N-channel transistor 2 is formed.
And the rhenium film 49 is formed into a rhenium-titanium alloy film by selectively introducing titanium into the rhenium-titanium alloy film.
The gate electrode 31 of the channel transistor 4 is used for patterning the dummy gate electrodes 43 and 44 in which the formed rhenium film 49 is embedded and the formed rhenium film 49 is used if a mask is used for introducing titanium. Since only two lithography steps in combination with the resist mask forming step and two removal (eg, etching) steps for patterning and removing the dummy gate electrodes 43 and 44 are required, a P-channel transistor as in the related art is used. The number of steps is smaller than that of the manufacturing method in which the metal film forming the gate electrode and the metal film forming the gate electrode of the N-channel transistor are separately formed.

In the manufacturing method according to the second embodiment, since the gate electrode 21 of the P-channel transistor 3 is formed of the rhenium film 49, the work function is 4.7.
5 eV. The work function at the upper end of the valence band of silicon is 5.17 eV. Since the work functions have close values, the threshold voltage of the P-channel transistor 3 can be easily reduced to about 0.3 V or less.
In addition, titanium is ion-implanted into the rhenium film 49 to form a rhenium-titanium alloy film, and since this rhenium-titanium alloy film is used for the gate electrode 31 of the N-channel transistor 4, its work function is, for example, 17 atomic% of titanium. At this time, it becomes 4.18 eV. The work function at the bottom of the conduction band of silicon is 4.05 eV. Since the work functions have close values, the threshold voltage of the N-channel transistor 4 can be easily reduced to about 0.3 V or less.

The materials and thicknesses of the gate insulating films 15 and 48 and the rhenium films 16 and 4 described in each of the above embodiments.
9 is an example, and the work function value of the gate electrode of the P-channel transistor is higher than the work function value of the upper end of the valence band of silicon. If the work function value of the gate electrode of the N-channel transistor is close to the work function value at the lower end of the conduction band of silicon, it can be changed as appropriate.

[0067]

As described above, according to the semiconductor device of the present invention, the work function of the gate electrode of the P-channel transistor can be made closer to the upper end of the valence band of silicon, and the work function of the gate electrode of the N-channel transistor can be reduced. Since the work function can be close to the bottom of the conduction band of silicon,
The high threshold voltage of the metal gate electrode, which has conventionally been a problem, can be reduced to about 0.3 V or less.

According to the method of manufacturing a semiconductor device of the present invention,
When forming a metal gate electrode having a different work function between an N-channel transistor and a P-channel transistor, after forming a rhenium film on the entire surface, alloying is performed by introducing an impurity only into the rhenium film on the N-channel transistor formation region side. By doing so, the work function is changed. Therefore, the number of steps is reduced as compared with the case where different kinds of metals are formed on the N-channel transistor and the P-channel transistor. Further, the work function of the gate electrode of the P-channel transistor can be closer to the upper end of the valence band of silicon, and the work function of the gate electrode of the N-channel transistor can be closer to the lower end of the conduction band of silicon.
The high threshold voltage of the metal gate electrode, which has conventionally been a problem, can be reduced to about 0.3 V or less.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a schematic sectional view showing a second embodiment of the semiconductor device of the present invention.

FIGS. 3A to 3C are schematic cross-sectional views (1) to (3) showing a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a schematic sectional view (4) to (6) showing a first embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a schematic sectional view (1) to (4) showing a second embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 6 is a schematic sectional view (5) to (8) showing a second embodiment of the method for manufacturing a semiconductor device of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... P-channel transistor, 2 ... N-channel transistor, 21, 31 ... Gate electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/78 F term (Reference) 4M104 AA01 BB04 BB38 CC05 DD03 DD04 DD33 DD65 DD80 DD82 DD83 DD94 EE03 EE16 GG09 GG10 GG14 5F048 AA07 AA09 AC03 BB09 BB10 BB11 BC06 BE03 DA27 DA30 5F140 AA01 AA02 AA06 AA24 AA40 AB03 AC01 BA01 BC06 BD11 BE07 BE09 BF01 BF05 BF06 BF38 BG04 BG05 BG08 BG14 BG30 BG32 BG33 BG33 BG33 BG33 BG33 BG33 BG33 BG33 BG33 BG33 BG33 BG33 BG33 BG33 BG33 BG33 BG33 CE07

Claims (6)

[Claims] 1. A semiconductor device having a P-channel transistor and an N-channel transistor, wherein a gate electrode of the P-channel transistor is made of rhenium, and a gate electrode of the N-channel transistor is made of a rhenium titanium alloy. Semiconductor device. 2. The rhenium-titanium alloy contains 1: 1 rhenium.
2. The semiconductor device according to claim 1, wherein titanium is added in an amount of 2 atomic% to 22 atomic%. 3. The rhenium-titanium alloy contains 1: 1
2. The semiconductor device according to claim 1, wherein titanium is ion-implanted at 2 atomic% or more and 22 atomic% or less. 4. A method for manufacturing a semiconductor device in which a P-channel transistor and an N-channel transistor are formed on a semiconductor substrate, comprising: forming a gate electrode of the P-channel transistor and a gate electrode of the N-channel transistor with rhenium; Selectively introducing titanium into the gate electrode of the N-channel transistor to form a rhenium-titanium alloy. 5. The rhenium-titanium alloy contains 1: 1 rhenium.
5. The method for manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is formed by adding 2 atomic% to 22 atomic% of titanium. 6. The rhenium titanium alloy contains 1: 1
5. The method for manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is formed by ion-implanting titanium of 2 at% to 22 at%.