JP2002300030A - Lock detector - Google Patents

Abstract

(57) [PROBLEMS] To provide a lock detection circuit capable of determining lock / unlock without the need for a delay circuit requiring time adjustment with high accuracy. SOLUTION: A phase comparison signal P of a clock recovery circuit 36 is provided.
Differential amplifier 19 for subtracting C from the edge density signal ED
A DC detector 14 for converting a voltage amplitude of a predetermined frequency domain component of an output signal of the differential amplifier 19 into a DC voltage;
A voltage comparator for comparing an output signal of the DC detector with a predetermined voltage VR;

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lock detector for determining a synchronization state (lock / unlock) of a phase locked loop (PLL) widely used in optical communication and wireless communication, and more particularly to an input of a clock recovery circuit or the like. The present invention relates to a lock detector that accurately determines a PLL synchronization state when a signal is random data.

[0002]

2. Description of the Related Art FIG. 12 shows a clock recovery circuit (reference:
CRHogge, JR., "A Self Correcting Clock Recovery Cir
cuit ", Journal of Lightwave Tech., vol.LT-3, No.6,198
5, p1323) and a conventional lock detector added to it (Reference: RCDen Dulk, "Digital PLL Lock-Detection C
ircuit ", IEEE Electronics Letters, Vol.24, No.14,198
8, p880).

The clock recovery circuit 36 includes a phase comparison circuit 1
1, a differential amplifier 5, a loop filter 6, and a voltage controlled oscillator (hereinafter abbreviated as VCO) 7. The phase comparison circuit 11 includes a D-type flip-flop (hereinafter, referred to as a D-type flip-flop).
DFF), an EXOR gate 2, a delay circuit 3, and an EXOR gate 4. The conventional lock detector 18 includes a delay circuit 12, a DFF 13, a DC detector 14, and a voltage comparator 15.

A clock recovery circuit 36 receives an input data signal Din from a data input terminal 8 and receives the data signal Din.
The clock signal CLK is reproduced from in and output to the clock output terminal 10, and the data signal Q obtained by reproducing the data signal Din in the discriminator by the DFF 1 is output to the data output terminal 9.

Next, the operation of the clock recovery circuit 36 will be described. FIG. 13 shows waveforms representing the operations of the clock recovery circuit and the conventional lock detector. In FIG. 13, (a) is the input data signal Din, (b) is the recovered clock signal CLK, (c)
Is a reproduction data signal Q, (d) is an output signal (delay signal) Delay of the delay circuit 3, (e) is an output signal (phase comparison signal) PC of the EXOR gate 2, and (f) is an output signal (phase comparison signal) of the EXOR gate 4. (G) is the output signal CD of the delay circuit 12, (h) is the output signal LD of the DFF 13, and (i) is the output signal LDET of the lock detector 18.

The DFF 1 outputs a reproduced data signal Q, which is reproduced data of the input data signal Din, to the data output terminal 9 by punching out the input data signal Din with the reproduced clock signal CLK.

Here, the phase relationship between the input data signal Din and the reproduction clock signal CLK, which has the most margin for the DFF 1 to operate normally, is such that the rising edge of the reproduction clock signal CLK is at the middle of the edge of the input data signal Din. It is a case where it is located. The case of this phase relationship is shown in FIG.

FIG. 13 (I) shows a case where the phase of the reproduced clock signal CLK is advanced as compared with the state of (II).
FIG. 13 (III) shows a case where the phase of the reproduced clock signal CLK is delayed compared to the state of (I). On the other hand, if the delay time of the delay circuit 3 is set to シ ン ボ ル symbol of the input data, the delay circuit 3 in the phase relationship of FIG.
Output signal Delay coincides with the reproduced data signal Q.

The EXOR gate 2 calculates the exclusive OR of the input data signal Din and the reproduced data signal Q and outputs a phase comparison signal PC. The EXOR 4 outputs the exclusive OR of the input data signal Din and the delay signal Delay. And outputs an edge density signal ED. The differential amplifier 5 receives the phase comparison signal PC
The loop filter 6 limits the high-frequency component of the subtraction result and sends it to the VCO 7 as a control voltage.

In the phase relationship shown in FIG. 13 (II), the reproduced data signal Q and the delay signal Delay coincide with each other.
C and the edge density signal ED also match. Accordingly, the output of the differential amplifier 5 becomes zero and the output (VCO
7 is constant, and phase synchronization is maintained.

In the phase relationship of FIG. 13 (I) (when the CLK phase is advanced), the phase of the reproduced data signal Q advances with respect to the delay signal Delay. It becomes narrow in proportion to. As a result, the output of the differential amplifier 5 takes a negative value, and the output of the loop filter 6 (the control voltage of the VCO 7) changes in the direction of decreasing the voltage.
By performing control to delay the phase of the VCO 7, phase synchronization is maintained.

Conversely, the phase relationship (CLK
In the case where the phase is delayed, the phase of the reproduced data signal Q is delayed with respect to the delayed signal Delay.
The pulse width of C increases in proportion to the amount of phase advance. As a result, the output of the differential amplifier 5 takes a positive value, the output of the loop filter 6 (the control voltage of the VCO 7) changes in a direction to increase the voltage, and the phase of the VCO 7 is controlled to advance, thereby maintaining the phase synchronization. You.

When an ideal perfect integrator such as a charge pump is used for the loop filter 6, the VCO
13 (II) is realized irrespective of the free-running frequency of the VCO 7, but when an incomplete integrator such as a passive filter is used for the loop filter 6, depending on the free-running frequency of the VCO 7 ( There is a possibility that phase synchronization can be realized in various phase relationships including I) to (III). Hereinafter, a case where an incomplete integrator is used as the loop filter 6 will be described as an example.

Next, the operation of the conventional lock detector 18 will be described. The output signal CD of the delay circuit 12 delays the reproduced clock signal CLK by 90 degrees or 270 degrees. FIG.
(g) shows the output signal C of the delay circuit 12 in the case of a 270-degree delay.
D is described. The DFF 13 punches out the delay signal CD with the input data signal Din and outputs a signal LD (b). FIG.
3 (a) and 3 (g), three types of phase relationships ((I) to (II) shown in FIG.
In (I)), the signal LD in (h) is always low.

On the other hand, when the clock recovery circuit 36 is in the unlocked state, the phase relationship between the input data signal Din and the delay signal CD constantly changes, so that high and low alternately appear in the signal LD. . Therefore, this signal LD
Is constant or whether high and low appear alternately, it is possible to determine whether the lock or unlock state. The DC detector 14 and the voltage comparator 15 are inserted to make this determination.

FIGS. 14A to 14C show a conventional lock detector 18.
It is a figure which shows operation | movement. FIG. 14A shows the input data signal Di.
9 shows characteristics of the output signal LD of the DFF 13 with respect to a bit rate of n. The range of the bit rate in which the locked state is maintained when the bit rate is changed is called a lock range. Within the lock range, the bit rate and Din-C
The LK phase relationships correspond one-to-one. That is, when lock is realized at the center of the lock range, the phase relationship is as shown in FIG. 13 (II), and when lock is realized below the lock range, the phase relationship is as shown in FIG. VCO7 than
Of the control voltage is realized, and the CLK phase is advanced as shown in FIG. 13 (I). Conversely, when the lock is realized above the lock range, the control for raising the control voltage of the VCO 7 is realized as compared with the case of (II), and the CLK phase is advanced as shown in FIG. 13 (III). State.

As shown in FIG. 14 (a), lock can be maintained even if the CLK phase is further advanced than the state (II), and even if the CLK phase is further delayed than the state (III). Locks can be maintained.

On the other hand, the phase relations (I), (II) and (II) in FIG.
In all of the cases (I), the output signal LD of the DFF 13 becomes low, but when the CLK phase is further advanced than the state (II) or the CLK phase is further delayed than the state (III), the DFF 13 Is high. The boundary between the high and the low does not clearly separate with the change of the bit rate, but there is a boundary region where the high and the low alternately appear due to the phase fluctuation peculiar to the phase locked loop.

The DC detector 14 converts the amplitude of the signal LD into a DC level. FIG. 15A is an implementation example of the DC detector 14. In the figure, 25 is a capacitor, 26 and 27 are diodes, 28 is a capacitor, 29 is a resistor, 30 is an input terminal, 31
Is an output terminal. When a signal that alternates between high and low is input to the input terminal 30, a high voltage appears at the output terminal 31, and when a high or low constant voltage is input, the ground voltage is output.

FIG. 14B shows the characteristics of the output signal DD of the DC detector 14 with respect to the bit rate of the input data signal Din. As shown in the figure, the signal DD has a high level in a region where high and low alternately appear in the signal LD. By setting the reference voltage VR of the voltage comparator 15 to an appropriate value, the output signal LDET of the voltage comparator 15 (that is, the output signal of the lock detector 18) is low when locked, and the output signal LDET is high when unlocked. (FIG. 14
(c)), lock / unlock can be determined.

[0021]

As described above,
Although the lock detector 18 of the related art can discriminate between locked and unlocked states, as shown in FIG. 14 (c), there are two areas where a locked state is erroneously determined as unlocked. Where the erroneously detected portion appears in the bit rate is determined by the delay amount of the delay circuit 12, but considering the jitter tolerance, the erroneously detected portion is determined by the bit rate of the input data signal Din actually operated. It is necessary to design the delay amount as far as possible.

Assuming that the center of the lock range is made to match the bit rate of the input data signal Din to be operated by adjusting the VCO 7, the delay amount of the delay circuit 12 is 90
In the case of degrees or 270 degrees (FIG. 14 (c)), the erroneously detected portion appears at the position farthest from the bit rate (= the center of the lock range) of the input data signal Din actually used. As described above, the conventional lock detector 18 has a problem that the delay amount of the delay circuit 12 needs to be adjusted with high accuracy.

Further, the DC detector 14 in the conventional lock detector 18 includes a diode 26 shown in FIG.
Since the amplitude of the voltage drop of 27 is lost, the output amplitude becomes small and the accuracy of discrimination in the voltage comparator 15 cannot be increased. In addition, the voltage drop of the diodes 26 and 27 generally has high temperature dependency. Temperature compensation is required for stable lock detection. As described above, the conventional lock detector 18 has a problem in that it is necessary to use the DC detector 14, which is difficult to achieve high accuracy.

Therefore, instead of the DC detector 14, FIG.
An integrator shown in (b) can be used (in the figure, 32 is a resistor, 33 is a capacitor, 34 is an input terminal, and 35 is an output terminal), but the DC detector 14 is in a predetermined frequency range. While converting the voltage amplitude of the component to a DC voltage,
The integrator converts the entire frequency range including the DC component into DC.

For this reason, when the output signal LD of the DFF 13 is high (even if it is kept constant), a high voltage appears at the integrator output, and two erroneous signals appear in FIG. In all the areas outside the detection part, it is erroneously determined to be unlocked despite being in the locked state. That is, when the DC detector 14 is simply replaced with an integrator in the conventional lock detector 18, an area of about half of the lock range is an erroneous detection area.

Accordingly, a first object of the present invention is to provide a lock detector which can remove a circuit which needs to be adjusted with high precision, such as the delay circuit 12, and can determine lock / unlock without adjustment. To provide.

A second object of the present invention is to provide a lock detector which can remove a DC detector which is difficult to achieve high accuracy and can determine lock / unlock with a simple circuit such as an integrator. It is in.

[0028]

According to the present invention, a voltage-controlled oscillator whose oscillation frequency is controlled by a voltage and a phase difference between an output signal of the voltage-controlled oscillator and an input data signal are detected. A phase comparison circuit that detects a phase comparison signal PC including a DC voltage component proportional to the phase difference and an edge density of the input data signal and outputs an edge density signal ED including a DC voltage component proportional to the edge density; And a loop filter for extracting a component below a predetermined band from an output signal of the circuit and transmitting the component as a control voltage to the voltage controlled oscillator. Amplifier for subtracting the edge signal and the edge density signal ED, and a voltage of a predetermined frequency domain component of an output signal of the differential amplifier A DC detector for converting the width of DC voltage, and a lock detector, characterized in that it comprises a voltage comparator for comparing an output signal with a predetermined voltage of the DC detector.

According to a second aspect of the present invention, a voltage controlled oscillator whose oscillation frequency is controlled by a voltage, and a phase difference between an output signal of the voltage controlled oscillator and an input data signal are detected, and a DC voltage component proportional to the phase difference is detected. Including phase comparison signal P
C and a phase comparison circuit for detecting an edge density of the input data signal and outputting an edge density signal ED including a DC voltage component proportional to the edge density; and detecting a component of a predetermined band or less from an output signal of the phase comparison circuit. A lock detector for determining a synchronization state in a clock recovery circuit having a loop filter for sending out a control voltage to the voltage-controlled oscillator, wherein an exclusive OR of the phase comparison signal PC and the edge density signal ED is provided. And a DC detector for converting a voltage amplitude of a predetermined frequency domain component of an output signal of the EXOR gate into a DC voltage,
A lock detector comprising a voltage comparator for comparing an output signal of the DC detector with a predetermined voltage.

According to a third aspect of the present invention, there is provided a voltage controlled oscillator whose oscillation frequency is controlled by a voltage, and a phase difference between an output signal of the voltage controlled oscillator and an input data signal, and a DC voltage component proportional to the phase difference is detected. Including phase comparison signal P
C and a phase comparison circuit for detecting an edge density of the input data signal and outputting an edge density signal ED including a DC voltage component proportional to the edge density; and detecting a component of a predetermined band or less from an output signal of the phase comparison circuit. A lock detector for determining a synchronization state in a clock recovery circuit having a loop filter for sending out a control voltage to the voltage-controlled oscillator, wherein an exclusive OR of the phase comparison signal PC and the edge density signal ED is provided. A lock detector, comprising: an EXOR gate for calculating the following equation; an integrator for extracting a DC component of an output signal of the EXOR gate; and a voltage comparator for comparing the output signal of the integrator with a predetermined voltage. And

According to a fourth aspect of the present invention, there is provided a voltage controlled oscillator whose oscillation frequency is controlled by a voltage, an identifier for inputting an output of the voltage controlled oscillator as a clock to identify an input data signal, and A first EXOR gate for performing an exclusive OR operation with the output signal of the discriminator and outputting a phase comparison signal PC, a delay circuit for delaying the input data signal, and an output signal of the delay circuit and the input data signal; Of the edge density signal E
A phase comparison circuit including a second EXOR gate for outputting D, and a loop filter for extracting a component below a predetermined band from an output signal of the phase comparison circuit and transmitting the extracted component to the voltage controlled oscillator. A lock detector for judging a state, wherein a third exclusive OR operation is performed between an output signal of the discriminator and an output of the delay circuit.
EXOR gate, a DC detector for converting a voltage amplitude of a predetermined frequency domain component of the output signal of the third EXOR gate into a DC voltage, and a voltage for comparing the output signal of the DC detector with the predetermined voltage And a lock detector.

According to a fifth aspect of the present invention, there is provided a voltage controlled oscillator whose oscillation frequency is controlled by a voltage, an identifier for inputting an output of the voltage controlled oscillator as a clock to identify an input data signal, and A first EXOR gate for performing an exclusive OR operation with the output signal of the discriminator and outputting a phase comparison signal PC, a delay circuit for delaying the input data signal, and an output signal of the delay circuit and the input data signal; Of the edge density signal E
A phase comparison circuit including a second EXOR gate for outputting D, and a loop filter for extracting a component below a predetermined band from an output signal of the phase comparison circuit and transmitting the extracted component to the voltage controlled oscillator. A third EXOR gate for performing an exclusive OR operation of an output signal of the discriminator and an output signal of the delay circuit; and a lock detector for determining a state of the output signal of the third EXOR gate. A lock detector includes an integrator for extracting a DC component, and a voltage comparator for comparing an output signal of the integrator with a predetermined voltage.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIG. 1 is a circuit diagram showing a clock recovery circuit and a lock detector connected to the clock recovery circuit according to a first embodiment of the present invention. The clock recovery circuit 36 includes the phase comparison circuit 11, the differential amplifier 5, the loop filter 6, and the VCO 7,
Are DFF1, EXOR gate 2, delay circuit 3 and EXO
And an R gate 4. Further, the lock detector 20 of the present embodiment includes the differential amplifier 19 and the DC detector 14.
And a voltage comparator 15.

FIG. 2 is a timing chart showing the operation of the clock recovery circuit and the lock detector according to the first embodiment of the present invention. In the figure, (a) shows an input data signal Di.
n, (b) is a reproduced clock signal CLK, (c) is a reproduced data signal Q, (d) is an output signal (delay signal) Delay of the delay circuit 3,
(e) is the output signal (phase comparison signal) P of the EXOR gate 2
C, (f) is an EXOR gate 4 output signal (edge density signal) ED, (g) is an output signal LD of the differential amplifier 19, and (h) is an output signal of the voltage comparator 15, that is, an output signal of the lock detector 20. LDET.

As described above, the clock recovery circuit 36 receives the input data signal Din, and outputs a reproduction clock signal CLK and a reproduction data signal Q which is reproduction data of the input data signal Din.

FIG. 2 (II) shows the case of the phase relationship between the input data signal Din and the reproduced clock signal CLK which has the most margin for the DFF1 as the discriminator to operate normally. FIG. 2 (I) shows a case where the CLK phase is advanced compared to the state (II), and FIG. 2 (III) shows a case where the CLK phase is delayed compared to the state (II). Each is described.

In the phase relationship shown in FIG. 2I (when the CLK phase is advanced), the phase of the reproduced data signal Q is advanced with respect to the delay signal Delay, so that the pulse width of the phase comparison signal PC is equal to the advanced phase. It becomes narrow in proportion to. As a result, the output signal of the differential amplifier 5 takes a negative value, the output signal of the loop filter 6 (the control voltage of the VCO 7) changes in a direction of decreasing the voltage, and the phase of the VCO 7 is controlled to be delayed. Synchronization is maintained.

On the other hand, in the phase relationship shown in FIG. 2 (III) (when the CLK phase is delayed), the phase of the reproduced data signal Q is delayed with respect to the delay signal Delay. It becomes wider in proportion to the amount of progress. As a result, the output signal of the differential amplifier 5 takes a positive value, the output signal of the loop filter 6 (the control voltage of the VCO 7) changes in a direction to increase the voltage, and the phase of the VCO 7 is controlled to be advanced. Synchronization is maintained.

The clock recovery circuit 3 exemplified here
6, the description will be made on the assumption that an incomplete integrator such as a passive filter is used as the loop filter 6. in this case,
Depending on the free-running frequency of the VCO 7, phase synchronization may be realized in various phase relationships including (I) to (III).

Next, the operation of the lock detector 20 of this embodiment will be described. The differential amplifier 19 receives the phase comparison signal PC of the EXOR gate 2 and the edge density signal ED of the EXOR gate 4, performs a subtraction operation, and outputs an output signal LD.

In the case of the optimal phase relationship (FIG. 2 (II)),
Since the phase comparison signal PC matches the edge density signal ED, the output signal LD has a predetermined value (intermediate potential).

On the other hand, when the CLK phase is advanced (FIG. 2)
In (I)), since the pulse of the phase comparison signal PC is thinner than the edge density signal ED, the output signal LD includes a pulse in the low potential direction. Conversely, when the CLK phase is delayed (FIG. 2 (III)), the phase comparison signal PC
Is thicker than the edge density signal ED, the output signal LD includes a pulse in the high potential direction.

FIG. 3 is a diagram showing the operation of the lock detector 20 of this embodiment. FIG. 3A shows the characteristics of the output signal DD of the DC detector 14 with respect to the bit rate of the input data signal Din. In the case of the optimal phase relationship (FIG. 3 (II)), the output signal LD has a substantially constant voltage, so that the DC detector 14
Is a voltage close to the ground potential.

On the other hand, when the CLK phase is advanced (FIG. 3
(I)), since the output signal LD includes a pulse, the output signal DD has a higher potential than (II). Here, as the CLK phase advances, the pulse width of the output signal LD increases,
The output signal DD is observed as a higher voltage.

Similarly, even when the CLK phase is delayed (FIG. 3 (III)), the output signal LD includes a pulse, so that the output signal DD has a higher potential than that of (II). Where CL
The more the K phase is delayed, the wider the pulse width of the output signal LD becomes, and the output signal DD is observed as a higher voltage.

On the other hand, when the clock recovery circuit 36 is in the unlocked state, the phase relationship between the input data signal Din and the recovered clock signal CLK constantly changes, so that the output signal L
The pulse width of D changes periodically, and the output signal DD becomes a high potential.

FIG. 3B shows the characteristics of the output signal LDET of the lock detector 20 with respect to the bit rate of the input data signal Din. By setting the reference voltage VR of the voltage comparator 15 to an appropriate value, the output signal of the voltage comparator 15 (that is, the output signal of the lock detector 20) LDE at the time of locking is set.
When T is low and unlocked, LDET is high and lock / unlock can be determined.

The lock detector 20 of the present embodiment does not require a delay circuit that requires high-precision adjustment in the conventional lock detector 18 (FIG. 12), and thus detects lock / unlock without adjustment. It is possible. Further, as shown in FIG. 3B, the lock detector 20 of the present embodiment can eliminate an area where the lock state is erroneously detected as unlocked, which is a problem in the conventional lock detector. .

Note that if the reference voltage VR shown in FIG. 3A is set too low, a region where the lock state is erroneously detected as unlocked at both ends of the lock range, but the center of the lock range is normally set. Since the free-running frequency of the VCO 7 is adjusted so as to be synchronized in the vicinity, even if such an erroneous detection area exists, no problem occurs in operation.

[Second Embodiment] FIG. 4 is a circuit diagram showing a clock recovery circuit and a lock detector connected to the clock recovery circuit according to a second embodiment of the present invention. The lock detector 22 according to the present embodiment includes an EXOR gate 21, a DC detector 14, and a voltage comparator 15.

FIG. 5 is a timing chart showing the operation of the clock recovery circuit and the lock detector 22 according to the second embodiment of the present invention. In the figure, (a) is an input data signal Din, (b) is a reproduced clock signal CLK, (c) is a reproduced data signal Q, and (d) is an output signal (delay signal) Dela of the delay circuit 3.
y and (e) are output signals (phase comparison signals) of the EXOR gate 2
PC, (f) is an output signal (edge density signal) ED of the EXOR gate 4, and (g) is an output signal L of the EXOR gate 21.
D and (h) are output signals of the voltage comparator 15, that is, output signals LDET of the lock detector 22.

As described above, the clock recovery circuit 36 receives the input data signal Din and outputs the recovered clock signal CLK and the reproduced data signal Q. FIG. 5 (II) shows the case of the phase relationship between the input data signal Din and the reproduced clock signal CLK which has the most margin for the DFF1 as the discriminator to operate normally. FIG. 5 (I) shows a case where the CLK phase is advanced compared to the state (II), and FIG. 5 (III) shows a case where the CLK phase is delayed compared to the state (II).
Respectively.

Next, the operation of the lock detector 22 of this embodiment will be described. EXOR gate 21 is EXOR gate 2
, And the edge density signal ED of the EXOR gate 4, perform an exclusive OR operation, and output the signal L.
D is output. In the case of the optimal phase relationship (FIG. 5 (II)), the phase comparison signal PC matches the edge density signal ED, so that the output signal LD is always low.

On the other hand, when the CLK phase is advanced (FIG. 5
(I)) or when the CLK phase is delayed (see FIG.
I)) includes the pulse of the phase comparison signal PC and the edge density signal E
Since a difference occurs in the pulse width between the pulse D and the pulse D, a mismatch occurs between the phase comparison signal PC and the edge density signal ED.
The EXOR gate 21 sets its output signal LD high when detecting this mismatch.

FIG. 6 is a diagram showing the operation of the lock detector 22 of this embodiment. FIG. 6A shows characteristics of the output signal DD of the DC detector 14 with respect to the bit rate of the input data signal Din. In the case of the optimum phase relationship (FIG. 6 (II)), the output signal LD is always low, so that the output signal DD of the DC detector 14 has a voltage close to the ground potential.

On the other hand, when the CLK phase is advanced (FIG. 6)
(I)), since the output signal LD includes a pulse, the output signal DD has a higher potential than (II). Here, as the CLK phase advances, the pulse width of the output signal LD increases,
The output signal DD is observed as a higher voltage.

Similarly, when the CLK phase is delayed (FIG. 6 (III)), the output signal LD also has a pulse, so that the output signal DD has a higher potential than that of (II). Where CL
The more the K phase is delayed, the wider the pulse width of the output signal LD becomes, and the output signal DD is observed as a higher voltage.

FIG. 6B shows the characteristics of the output signal LDET of the lock detector 22 with respect to the bit rate of the input data Din. By setting the reference voltage VR of the voltage comparator 15 to an appropriate value, the output signal LDET of the voltage comparator 15 (that is, the output signal of the lock detector 22) LDET is low at the time of locking, and LDET is high at the time of unlocking. / Unlock determination.

The lock detector 22 according to the present embodiment does not require the delay circuit 12 which requires high-precision adjustment in the conventional lock detector 18, and thus can detect lock / unlock without adjustment. It is. Further, as shown in FIG. 6B, the lock detector 22 of the present embodiment can eliminate an area where the lock state is erroneously detected as unlocked, which is a problem in the conventional lock detector. .

If the reference voltage VR shown in FIG. 6A is set too low, a region where the lock state is erroneously detected as unlocked at both ends of the lock range is generated.
Normally, VCO7 is synchronized near the center of the lock range.
Since the self-running frequency is adjusted, there is no operational problem even if such an erroneous detection region exists.

[Third Embodiment] FIG. 7 is a circuit diagram showing a clock recovery circuit and a lock detector connected to the clock recovery circuit according to a third embodiment of the present invention. Lock detector 2 of the present embodiment
4 is an EXOR gate 21, an integrator 23, and a voltage comparator 1
And 5.

This embodiment has a configuration in which the DC detector 14 in the lock detector of the second embodiment is replaced with an integrator 23. Accordingly, the operation of the clock recovery circuit 36 and the output signal L of the EXOR gate 21 in the lock detector 24
The operation up to D is the operation of the second embodiment (FIGS.
The description is omitted because it is the same as (g)).

The integrator 23 of this embodiment is, for example, as shown in FIG.
This can be realized by the circuit shown in FIG. In the figure, input terminal 3
The voltage applied to 4 is integrated by a resistor 32 and a capacitor 33 and applied to an output terminal 35.

As shown in FIG. 5, the EXOR gate 21
Is always low in the optimal phase relationship (FIG. 5 (II)), and when the CLK phase is advanced (FIG. 5).
(I)) or when the CLK phase is delayed (Fig. 5 (III))
Shows a short high pulse. Here, this pulse width becomes wider as the CLK phase advances, or as the phase delays, the delay increases. That is, as the CLK phase advances, the pulse width of the output signal LD increases, and the output signal DD of the integrator 23 is observed as a higher voltage. As the CLK phase delays, the pulse width of the output signal LD increases, and the output signal LD increases. Signal DD is observed as a higher voltage.

Therefore, the bit rate dependency of the input data signal Din of the output signal DD of the integrator 23 of the present embodiment is as follows.
DC detector 14 in lock detector of second embodiment
The output signal DD has the same shape as the bit rate dependency of the input data signal Din (FIG. 6A).

The lock detector 24 according to the present embodiment is characterized in that the non-adjustment, disappearance of the erroneous detection area,
In addition to maintaining the advantages of the present invention, another object of the present invention is to realize the elimination of the DC detector in the lock detector. That is, according to the present embodiment, the erroneous detection area can be reduced without using a DC detector that is difficult to obtain high accuracy, without using a delay circuit (in the lock detector) that required high-precision adjustment. A non-existent lock detector can be realized.

[Fourth Embodiment] FIG. 8 is a circuit diagram showing a clock recovery circuit and a lock detector according to a fourth embodiment of the present invention connected to the clock recovery circuit. The lock detector 22A of the present embodiment includes an EXOR gate 21, a DC detector 14, and a voltage comparator 15.

FIG. 9 is a timing chart showing the operation of the clock recovery circuit and the lock detector 22A according to the fourth embodiment of the present invention. In the figure, (a) is an input data signal Din, (b) is a reproduced clock signal CLK, (c) is a reproduced data signal Q, and (d) is an output signal (delay signal) Del of the delay circuit 3.
ay, (e) are the output signal (phase comparison signal) PC of the EXOR gate 2, (f) is the output signal (edge density signal) ED of the EXOR gate 4, (g) is the output signal LD of the EXOR gate 21, (h) ) Is the output signal of the voltage comparator 15, that is, the output signal LDET of the lock detector 22A.

As described above, the clock recovery circuit 36 receives the input data signal Din, and outputs a recovered clock signal CLK and a reproduced data signal Q of the input data signal Din.

FIG. 9 (II) shows the case of the phase relationship between the input data signal Din and the reproduced clock signal CLK which has the most allowance for the DFF1 as the discriminator to operate normally. FIG. 9 (I) shows a case where the CLK phase is advanced compared to the state (II), and FIG. 9 (III) shows a case where the CLK phase is delayed compared to the state (II). Each is described.

Next, the operation of the lock detector 22A of this embodiment will be described. The EXOR gate 21 receives the reproduced data signal Q output from the DFF 1 and the delay signal Delay output from the delay circuit 3, performs an exclusive OR operation, and outputs an output signal LD. In the case of the optimal phase relationship (see FIG. 9 (I
In I)), since the input data signal Q matches the delay signal Delay, the output signal LD is always low.

On the other hand, when the CLK phase is advanced (FIG. 9)
(I)) or when the CLK phase is delayed (FIG. 9 (II
In (I)), since a difference occurs between the rising position and the falling position between the input data signal Q and the delay signal Delay, a mismatch occurs between the input data signal Q and the delay signal Delay. The EXOR gate 21 sets its output signal LD high when detecting this mismatch.

FIG. 10 shows the lock detector 22A of the present embodiment.
It is an explanatory view showing the operation of. FIG. 10A shows characteristics of the output signal DD of the DC detector 14 with respect to the bit rate of the input data signal Din. In the case of the optimal phase relationship (see FIG. 9 (I
In I)), since the output signal LD is always low, the output signal DD of the DC detector 14 has a voltage close to the ground potential.

On the other hand, when the CLK phase is advanced (FIG. 9)
(I)), since the output signal LD includes a pulse, the output signal DD has a higher potential than (II). Here, as the CLK phase advances, the pulse width of the output signal LD increases,
The output signal DD is observed as a higher voltage.

Similarly, even when the CLK phase is delayed (FIG. 9 (III)), the output signal LD includes a pulse, so that the potential of the output signal DD becomes higher than that of (II). Where CL
The more the K phase is delayed, the wider the pulse width of the output signal LD becomes, and the output signal DD is observed as a higher voltage.

FIG. 10B shows the characteristics of the output signal LDET of the lock detector 22 with respect to the bit rate of the input data signal Din. By setting the reference voltage VR of the voltage comparator 15 to an appropriate value, the output signal of the voltage comparator 15 (that is, the output signal of the lock detector 22) LD is locked when locked.
ET is low, LDET is high when unlocked,
Lock / unlock can be determined.

The lock detector 22A of the present embodiment does not require the delay circuit 12, which requires high-precision adjustment in the conventional lock detector 18, so that lock / unlock can be detected without adjustment. It is. Further, as shown in FIG. 10 (b), the lock detector 22A of the present embodiment can eliminate an area where the lock state is erroneously detected as unlocked, which is a problem in the conventional lock detector. . Further, the lock detector 22A of the present embodiment includes an output signal PC of the EXOR gate 2 and an output signal ED of the EXOR gate 4.
Is input to the EXOR gate 21 (Embodiment 2 and Embodiment 3).
Since the frequency component of the signal input to the XOR gate 21 can be suppressed to half, the band of the signal processing frequency can be narrowed, and operation with low power is possible. Therefore, when devices having the same performance are used, operation at a high bit rate is possible.

[Fifth Embodiment] FIG. 11 is a circuit diagram showing a clock recovery circuit and a lock detector according to a fifth embodiment of the present invention connected thereto. The lock detector 24A of the present embodiment includes an EXOR gate 21, an integrator 23, and a voltage comparator 15.

This embodiment has a configuration in which the DC detector 14 in the lock detector 22A of the fourth embodiment is replaced with an integrator 23. Therefore, the operation of the clock recovery circuit 36 and the operation up to the output signal LD of the EXOR gate 21 in the lock detector 24A are the same as the operations of the fourth embodiment (FIGS. 9A to 9G). Therefore, the description is omitted.

The integrator 23 of the present embodiment is, for example, as shown in FIG.
This can be realized by the circuit shown in FIG. In the figure, input terminal 3
The voltage applied to 4 is integrated by a resistor 32 and a capacitor 33 and applied to an output terminal 35.

As shown in FIG. 9, the EXOR gate 21
Is always low in the optimal phase relationship (FIG. 9 (II)) and the CLK phase is advanced (FIG. 9 (I)).
Alternatively, when the CLK phase is delayed (FIG. 9 (III)), a short high pulse appears.

Here, the pulse width becomes wider as the CLK phase advances, or as the CLK phase delays, the pulse width increases. That is, as the CLK phase advances, the pulse width of the output signal LD increases, and the output signal DD of the integrator 23 is observed as a higher voltage. As the CLK phase delays, the pulse width of the output signal LD increases, and the output signal LD increases. Signal DD is observed as a higher voltage. Therefore, the integrator 23 of the present embodiment
The bit rate dependency of the input data signal Din of the output signal of FIG. 10 is the bit rate dependency of the input data signal Din of the DC detector 14 in the lock detector of the fourth embodiment (FIG. 10).
It has the same shape as (a)).

The lock detector 24A of the present embodiment has a fourth
In addition to the advantages of the non-adjustment, disappearance of the erroneous detection area, narrowing of the signal processing frequency, which were the features of the embodiment, another object of the present invention is to provide a lock detector. This eliminates the need for a DC detector. That is, according to the present embodiment, without using a DC detector that is difficult to achieve high accuracy, without using a delay circuit (in the lock detector) that required high-accuracy adjustment,
A lock detector having no erroneous detection region can be realized.

[0084]

As described above, the lock detector of the present invention can determine lock / unlock without adjustment. Further, in the lock detector of the present invention including the integrator, the lock / unlock can be determined without the DC detector.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a clock recovery circuit and a lock detector connected thereto according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the circuit of FIG.

FIG. 3 is an explanatory diagram showing an operation of the lock detector 20 of FIG.

FIG. 4 is a circuit diagram of a clock recovery circuit and a lock detector connected thereto according to a second embodiment of the present invention;

FIG. 5 is a timing chart showing the operation of the circuit of FIG.

FIG. 6 is an explanatory diagram showing an operation of the lock detector 22 of FIG.

FIG. 7 is a circuit diagram of a clock recovery circuit and a lock detector connected to the clock recovery circuit according to the third embodiment of the present invention.

FIG. 8 is a circuit diagram of a clock recovery circuit and a lock detector connected to the clock recovery circuit according to a fourth embodiment of the present invention.

9 is a timing chart illustrating the operation of the circuit in FIG.

FIG. 10 is an explanatory diagram showing the operation of the lock detector 22A of FIG.

FIG. 11 is a circuit diagram of a clock recovery circuit and a lock detector connected thereto according to a fifth embodiment of the present invention.

FIG. 12 is a circuit diagram of a clock recovery circuit and a conventional lock detector connected thereto.

13 is a timing chart illustrating the operation of the circuit in FIG.

14 is a characteristic diagram showing an operation of the clock detector 18 of FIG.

15A is a specific circuit diagram of a DC detector, and FIG. 15B is a specific circuit diagram of an integrator.

[Explanation of symbols]

1: DFF, 2: EXOR gate, 3: delay circuit, 4:
EXOR gate, 5: differential amplifier, 6: loop filter, 7: voltage controlled oscillator (VCO), 8: data input terminal, 9: data output terminal, 10: clock output terminal, 1
1: phase comparison circuit, 12: delay circuit, 13: DFF, 1
4: DC detector, 15: voltage comparator, 16: reference voltage input terminal, 17: lock detection output terminal, 18: conventional lock detector, 19: differential amplifier, 20: lock detector, 2
1: EXOR gate, 22, 22A: lock detector, 2
3: Integrator, 24, 24A: Lock detector, 25, 2
8, 33: capacity, 26, 27: diode, 29, 3
2: resistance, 30, 34: input terminal, 31, 35: output terminal, 36: clock recovery circuit.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Takanori Enoki 2-3-1 Otemachi, Chiyoda-ku, Tokyo F-term in Nippon Telegraph and Telephone Corporation (reference) 5J106 AA03 BB02 CC02 CC21 CC41 CC58 DD05 DD47 DD48 EE08 HH02 JJ09 KK29 LL07 5K047 AA16 BB01 BB02 GG11 MM46 MM50 MM53 MM62

Claims (5)

[Claims] 1. A voltage controlled oscillator whose oscillation frequency is controlled by a voltage, and a phase comparison signal PC which detects a phase difference between an output signal of the voltage controlled oscillator and an input data signal and includes a DC voltage component proportional to the phase difference. A phase comparator for detecting an edge density of the input data signal and outputting an edge density signal ED including a DC voltage component proportional to the edge density; extracting a component of a predetermined band or less from an output signal of the phase comparator; A lock detector for determining a synchronization state in a clock recovery circuit including a loop filter for transmitting a control voltage to the voltage controlled oscillator, wherein a differential for subtracting the phase comparison signal PC and the edge density signal ED is provided. An amplifier; a DC detector for converting a voltage amplitude of a predetermined frequency domain component of an output signal of the differential amplifier into a DC voltage; A lock detector comprising: a voltage comparator that compares an output signal of a flow detector with a predetermined voltage. 2. A voltage controlled oscillator whose oscillation frequency is controlled by a voltage, and a phase comparison signal PC including a DC voltage component proportional to the phase difference detected by detecting a phase difference between an output signal of the voltage controlled oscillator and an input data signal. A phase comparator for detecting an edge density of the input data signal and outputting an edge density signal ED including a DC voltage component proportional to the edge density; extracting a component of a predetermined band or less from an output signal of the phase comparator; A lock detector for determining a synchronization state in a clock recovery circuit including a loop filter that sends a control voltage to the voltage-controlled oscillator, comprising: an exclusive OR of the phase comparison signal PC and the edge density signal ED. An EXOR gate for calculating, and a voltage amplitude of a predetermined frequency domain component of an output signal of the EXOR gate is converted into a DC voltage. A lock detector comprising: a DC detector; and a voltage comparator for comparing an output signal of the DC detector with a predetermined voltage. 3. A voltage-controlled oscillator whose oscillation frequency is controlled by a voltage, and a phase comparison signal PC including a DC voltage component proportional to the phase difference, detecting a phase difference between an output signal of the voltage-controlled oscillator and an input data signal. A phase comparator for detecting an edge density of the input data signal and outputting an edge density signal ED including a DC voltage component proportional to the edge density; extracting a component of a predetermined band or less from an output signal of the phase comparator; A lock detector for determining a synchronization state in a clock recovery circuit including a loop filter that sends a control voltage to the voltage-controlled oscillator, comprising: an exclusive OR of the phase comparison signal PC and the edge density signal ED. An EXOR gate for performing an operation, an integrator for extracting a DC component of an output signal of the EXOR gate, and an output signal of the integrator. A lock detector, comprising: a voltage comparator that compares the voltage with a predetermined voltage. 4. A voltage-controlled oscillator whose oscillation frequency is controlled by a voltage, a discriminator for inputting an output of the voltage-controlled oscillator as a clock to discriminate an input data signal, an input data signal and an output of the discriminator. A first EXOR for performing an exclusive OR operation with a signal and outputting a phase comparison signal PC
A phase comparison circuit including a gate, a delay circuit for delaying the input data signal, and a second EXOR gate for performing an exclusive OR operation on an output signal of the delay circuit and the input data signal and outputting an edge density signal ED; A clock recovery circuit including a loop filter that extracts a component equal to or less than a predetermined band from an output signal of the phase comparison circuit and sends the extracted component to the voltage-controlled oscillator. A third EXOR gate for performing an exclusive OR operation on an output signal and the output of the delay circuit;
A DC detector that converts a voltage amplitude of a predetermined frequency domain component of the output signal of the XOR gate into a DC voltage, and a voltage comparator that compares the output signal of the DC detector with a predetermined voltage. Lock detector. 5. A voltage controlled oscillator whose oscillation frequency is controlled by a voltage, a discriminator for discriminating an input data signal by inputting an output of the voltage controlled oscillator as a clock, an input data signal and an output of the discriminator. A first EXOR for performing an exclusive OR operation with a signal and outputting a phase comparison signal PC
A phase comparison circuit including a gate, a delay circuit for delaying the input data signal, and a second EXOR gate for performing an exclusive OR operation on an output signal of the delay circuit and the input data signal and outputting an edge density signal ED; A clock recovery circuit including a loop filter that extracts a component equal to or less than a predetermined band from an output signal of the phase comparison circuit and sends the extracted component to the voltage-controlled oscillator. A third EXOR gate for performing an exclusive OR operation between an output signal and an output signal of the delay circuit;
A lock detector comprising: an integrator that extracts a DC component of an output signal of the EXOR gate; and a voltage comparator that compares an output signal of the integrator with a predetermined voltage.