JP2002300021A - Integrated circuit device - Google Patents

Abstract

(57) Abstract: An object is to realize stable data transfer in an integrated circuit device including a plurality of buses and a strobe signal for taking in data of the plurality of buses. SOLUTION: A strobe generation block 141 is provided,
By detecting the number of changed bits of the output latch data 102, 112, 122, and 132 and the interval between the output latch signal 140 and the strobe internal signal 142 and delaying the strobe signal 144 according to the detected value, even at the time of high-speed data transfer. Sufficient timing margin on the side for taking in the simultaneous drive output signal can be secured, and stable data transfer can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an integrated circuit device for outputting data to a plurality of buses, and a program.

[0002]

2. Description of the Related Art In recent years, LSIs have been increasing in capacity and terminals. In particular, when driving a large number of output signal terminals such as a data bus simultaneously with the increase in the number of terminals, noise is generated in the power supply / GND near the output signal terminal, and the noise is generated in the vicinity of the power supply / GND where the noise is generated. This may affect the input signal and cause a malfunction.

In order to increase the speed of an output driver circuit of a CMOS integrated circuit, switching noise generated when charging / discharging a load capacitance of the output driver is required.
Crosstalk noise and reflection noise when the output voltage changes rapidly cause circuit malfunction.

In such a case, a power supply / GND terminal may be added between consecutively arranged simultaneous drive output terminals, or the simultaneous drive output terminals may be dispersedly arranged in signal terminal groups having different power supply / GND terminals. Accordingly, a method of reducing the influence of noise on the power supply / GND and a method of avoiding the influence of noise on the input signal by arranging an input signal susceptible to noise at a distance from the simultaneous drive output terminal have been adopted. .

As a method for avoiding simultaneous drive output in a circuit, Japanese Patent Laid-Open No. 3-44108 and Japanese Patent Laid-Open No. 3-2
As disclosed in Japanese Patent No. 22518, there is a method of dividing a simultaneous drive output signal into several sets, shifting a change point using a delay element, and reducing the influence of noise on the power supply / GND.

[0006]

In the case where the ratio of the simultaneously driven output signal terminals to the total number of terminals of the LSI is large, in the above-mentioned conventional technology, a power supply / GND terminal is added between the consecutive simultaneously driven output signal terminals. And further, a method is employed in which the input signal terminals that are vulnerable to noise are arranged away from the group of simultaneously driven output signal terminals.

However, when the ratio of the simultaneously driven output signal terminals is particularly large, it is difficult to arrange the input signal terminals that are susceptible to noise at a distance, and it is impossible to avoid the influence on the input signals. I was

Further, the method of shifting the changing point of the simultaneous drive output signal reduces the timing margin on the side for taking in the simultaneous drive output signal, and has a problem that it cannot be adapted to high-speed data transfer. .

The present invention has been made in consideration of the above problems, and has as its object to provide an integrated circuit device and a program capable of avoiding an influence on an input signal even when the ratio of simultaneously driven output signal terminals is large. There is something.

Another object of the present invention is to provide an integrated circuit and a program which can be adapted to high-speed data transfer even when the ratio of simultaneous drive output signal terminals is large in consideration of the above problems. It is assumed that.

[0011]

In order to solve the above-mentioned problems, a first invention (corresponding to claim 1) comprises a plurality of bus drivers each of which drives a plurality of buses and outputs data, A strobe signal driver that drives a strobe signal for capturing the output data, a change bit number detection block that detects a different bit number between the current data output by the plurality of bus drivers and the next data, An integrated circuit device comprising: a timing generation block that controls the strobe signal driver so that a timing at which the strobe signal driver drives the strobe signal is changed according to a detection result of the change bit number detection block.

Further, the second invention (corresponding to claim 2)
Is a rewritable register, comprising a change bit number setting register in which a predetermined setting value is set, the timing generation block, when the different bit number is equal to or more than the predetermined setting value, Is the integrated circuit device according to the first aspect of the present invention, which instructs to change the following.

Further, the third invention (corresponding to claim 3)
Is a rewritable register, and has a strobe signal timing setting register in which a predetermined setting value is set. The timing generation block uses the predetermined setting value to cause the strobe signal driver to The integrated circuit device according to the first aspect of the present invention, which determines an amount by which to change the timing of the strobe signal corresponding to the data.

A fourth aspect of the present invention (corresponding to claim 4)
Has slew rate control means for controlling a slew rate for outputting data, a plurality of bus drivers for driving the plurality of buses and outputting the data, and a current data output from the plurality of bus drivers. A changed bit number detection block that detects a different number of bits from the next data, and a timing generation block that controls the plurality of bus drivers to change the slew rate according to a detection result of the changed bit number detection block. An integrated circuit device comprising:

Further, a fifth aspect of the present invention (corresponding to claim 5)
Is a rewritable register, comprising a change bit number setting register in which a predetermined set value is set, wherein the timing generation block sets the through bit when the different bit number is equal to or more than the predetermined set value. An integrated circuit device according to a fourth aspect of the present invention for instructing to reduce the rate.

A sixth aspect of the present invention (corresponding to claim 6)
Has output current control means for controlling an output current corresponding to data to be output, a plurality of bus drivers each of which drives a plurality of buses and outputs the data, and a current bus output by the plurality of bus drivers. A changed bit number detection block for detecting a different number of bits between data and the next data; and a timing generator for controlling the plurality of bus drivers to change the output current in accordance with a detection result of the changed bit number detection block. And an integrated circuit device provided with a block.

The seventh invention (corresponding to claim 7)
Is a rewritable register, comprising a changing bit number setting register in which a predetermined setting value is set, wherein the timing generation block outputs the output when the different bit number is equal to or more than the predetermined setting value. An integrated circuit device according to a sixth aspect of the present invention for instructing to reduce the current.

The eighth invention (corresponding to claim 8)
A plurality of bus drivers each of which drives a plurality of buses and outputs data; phase control means for controlling a phase of each signal of the data input to each of the plurality of bus drivers; and A change bit number detection block for detecting a different bit number between the current data output by the driver and the next data; and the phase control means for controlling the phase according to a detection result of the change bit number detection block. An integrated circuit device comprising a timing generation block for controlling.

The ninth aspect of the present invention (corresponding to claim 9)
Is a rewritable register, comprising a change bit number setting register in which a predetermined set value is set, wherein the timing generation block sets the data when the different bit number is equal to or more than the predetermined set value. The integrated circuit device according to the eighth aspect of the present invention, which instructs to control the phase so as to suppress the simultaneous change of each signal.

According to a tenth aspect of the present invention (corresponding to claim 10), a plurality of bus drivers for driving a plurality of buses to output data and a strobe signal for capturing the output data are driven. A strobe signal driver, a change interval detection block for detecting an interval between a timing at which the plurality of bus drivers output the data, and a timing at which the strobe signal driver outputs the strobe signal; and An integrated circuit device comprising: a timing generation block that controls the strobe signal driver so as to change a timing for driving a strobe signal in accordance with a detection result of the change interval detection block.

The eleventh invention (corresponding to claim 11) is a rewritable register, comprising a change interval setting register in which a predetermined set value is set, wherein the timing generation block is detected. The integrated circuit device according to a tenth aspect of the present invention, wherein the timing is changed when the interval is equal to or less than the predetermined set value.

A twelfth invention (corresponding to claim 12) is a rewritable register, comprising a strobe signal timing setting register in which a predetermined setting value is set, wherein the timing generation block comprises: The integrated circuit device according to a tenth aspect of the present invention, wherein an amount of changing a timing of the strobe signal corresponding to the data is determined based on the predetermined setting value.

A thirteenth aspect of the present invention (corresponding to claim 13) has a slew rate control means for controlling a slew rate for outputting data, and a plurality of buses each for driving a plurality of buses to output the data. A change interval detection block for detecting an interval between a timing at which the plurality of bus drivers output the data and a timing at which the strobe signal driver outputs the strobe signal; and a detection of the change interval detection block. A timing generation block for controlling the plurality of bus drivers to change the slew rate according to a result.

A fourteenth aspect of the present invention (corresponding to claim 14) is a rewritable register, comprising a change interval setting register in which a predetermined set value is set, wherein the timing generation block detects The integrated circuit device according to a thirteenth aspect of the present invention, wherein when the interval is equal to or less than the predetermined set value, an instruction is issued to reduce the slew rate.

A fifteenth aspect of the present invention (corresponding to claim 15) has output current control means for controlling an output current corresponding to data to be output, and drives each of a plurality of buses to output the data. A plurality of bus drivers, a change interval detection block for detecting an interval between a timing at which the plurality of bus drivers output the data, and a timing at which the strobe signal driver outputs the strobe signal; and the change interval detection block. And a timing generation block for controlling the plurality of bus drivers so as to change the output current in accordance with the detection result.

A sixteenth aspect of the present invention (corresponding to claim 16) is a rewritable register, comprising a change interval setting register in which a predetermined set value is set, wherein the timing generation block is detected. The integrated circuit device according to the fifteenth aspect of the present invention, wherein when the interval is equal to or less than the predetermined set value, the output current control means for reducing the output current is controlled.

According to a seventeenth aspect of the present invention (corresponding to claim 17), a plurality of bus drivers each of which drives a plurality of buses and outputs the data, and a plurality of bus drivers which are respectively input to the plurality of bus drivers. Phase control means for controlling the phase of each signal of data; a change interval detecting block for detecting an interval between a timing at which the plurality of bus drivers output the data and a timing at which the strobe signal driver outputs the strobe signal; And a timing generation block for controlling the phase control means so as to control the phase in accordance with a detection result of the change interval detection block.

An eighteenth aspect of the present invention (corresponding to claim 18) is a rewritable register, comprising a change interval setting register in which a predetermined set value is set, wherein the timing generation block detects The integrated circuit device according to a seventeenth aspect of the present invention, wherein when the interval is equal to or less than the predetermined set value, the phase is controlled so as to suppress simultaneous changes of the data signals. It is.

A nineteenth aspect of the present invention (corresponding to claim 19) is the integration according to any one of the first to eighteenth aspects of the present invention, wherein the function of the timing generation block can be externally stopped. It is a circuit device.

According to a twentieth aspect of the present invention (corresponding to claim 20), the function of the slew rate control means is as follows:
A fourth or thirteenth integrated circuit device according to the present invention, which can be stopped from the outside.

A twenty-first aspect of the present invention (corresponding to claim 21) is the integrated circuit device according to the sixth or fifteenth aspect, wherein the function of the output current control means can be externally stopped. It is.

A twenty-second aspect of the present invention (corresponding to claim 22) is the integrated circuit device according to the eighth or seventeenth aspect, wherein the function of the phase control means can be externally stopped. is there.

According to a twenty-third aspect of the present invention (corresponding to claim 23), a plurality of bus drivers for driving a plurality of buses to output data and a strobe signal for capturing the output data are driven. A strobe signal driver, a change bit number detection block that detects a different bit number between the current data output by the plurality of bus drivers and the next data, and a timing at which the plurality of bus drivers output the data. A change interval detection block for detecting an interval between the timing at which the strobe signal driver outputs the strobe signal, and a timing at which the strobe signal driver drives the strobe signal is determined by the detection result of the change bit number detection block and the change interval. The strobe signal is changed in accordance with the detection result of the detection block. An integrated circuit device including a timing generation block for controlling the driver.

According to a twenty-fourth aspect of the present invention (corresponding to claim 24), the integrated circuit device according to the first aspect of the present invention includes a plurality of bus drivers for driving a plurality of buses and outputting data, respectively. A strobe signal driver that drives a strobe signal for capturing the output data, a change bit number detection block that detects a different bit number between the current data output by the plurality of bus drivers and the next data, To cause a computer to function as all or a part of a timing generation block that controls the strobe signal driver so as to change the timing at which the strobe signal driver drives the strobe signal according to the detection result of the change bit number detection block. Program.

According to a twenty-fifth aspect of the present invention (corresponding to claim 25), the integrated circuit device according to the fourth aspect of the present invention has a slew rate control means for controlling a slew rate for outputting data. A plurality of bus drivers for driving the respective buses to output the data; a change bit number detection block for detecting a different number of bits between the current data and the next data output by the plurality of bus drivers; A program for causing a computer to function as all or a part of a timing generation block that controls the plurality of bus drivers so as to change the slew rate according to a detection result of a bit number detection block.

According to a twenty-sixth aspect of the present invention (corresponding to claim 26), the integrated circuit device according to the sixth aspect has output current control means for controlling an output current corresponding to output data. A plurality of bus drivers each of which drives a plurality of buses to output the data, a change bit number detection block that detects a different number of bits between the current data and the next data output by the plurality of bus drivers, A program for causing a computer to function as all or a part of a timing generation block that controls the plurality of bus drivers so as to change the output current according to a detection result of the change bit number detection block.

A twenty-seventh aspect of the present invention (corresponding to claim 27) is the integrated circuit device according to the eighth aspect, wherein a plurality of bus drivers for driving a plurality of buses and outputting data, respectively; Phase control means for controlling the phase of each signal of the data, which is input to each of the plurality of bus drivers, and a change detecting a different number of bits between the current data and the next data output from the plurality of bus drivers A program for causing a computer to function as all or part of a bit number detection block and a timing generation block that controls the phase control means so as to control the phase according to a detection result of the change bit number detection block. is there.

According to a twenty-eighth aspect of the present invention (corresponding to claim 28), in the integrated circuit device according to the tenth aspect, a plurality of bus drivers for driving a plurality of buses and outputting data, respectively. A strobe signal driver for driving a strobe signal for capturing the output data; a timing at which the plurality of bus drivers output the data; and an interval between timing at which the strobe signal driver outputs the strobe signal. All or a part of a change interval detection block, and a timing generation block that controls the strobe signal driver to change the timing at which the strobe signal driver drives the strobe signal in accordance with the detection result of the change interval detection block. Is a program for causing a computer to function.

According to a twenty-ninth aspect of the present invention (corresponding to claim 29), the integrated circuit device according to the thirteenth aspect of the present invention includes a slew rate control means for controlling a slew rate for outputting data. A plurality of bus drivers for driving the respective buses and outputting the data, detecting intervals between timings at which the plurality of bus drivers output the data and timings at which the strobe signal driver outputs the strobe signal. A program for causing a computer to function as all or a part of a change interval detection block and a timing generation block that controls the plurality of bus drivers to change the slew rate according to a detection result of the change interval detection block It is.

According to a thirtieth aspect of the present invention (corresponding to claim 30), the integrated circuit device according to the fifteenth aspect of the present invention has output current control means for controlling an output current corresponding to output data. A plurality of bus drivers each driving a plurality of buses to output the data; a timing at which the plurality of bus drivers output the data; and an interval between timings at which the strobe signal driver outputs the strobe signal. To cause a computer to function as all or a part of a change interval detection block to be detected and a timing generation block that controls the plurality of bus drivers to change the output current according to a detection result of the change interval detection block. Program.

According to a thirty-first aspect of the present invention (corresponding to claim 31), in the integrated circuit device according to the seventeenth aspect, a plurality of bus drivers for driving a plurality of buses and outputting the data, respectively. Phase control means for controlling a phase of each signal of the data, which are respectively input to the plurality of bus drivers, timings at which the plurality of bus drivers output the data, and a method wherein the strobe signal driver controls the strobe signal. A change interval detection block for detecting an interval with the output timing, and a timing generation block for controlling the phase control means so as to control the phase in accordance with a detection result of the change interval detection block, as all or a part of the timing generation block. It is a program for operating a computer.

According to a thirty-second aspect of the present invention (corresponding to claim 32), the integrated circuit device according to the twenty-third aspect further comprises a plurality of bus drivers for driving a plurality of buses and outputting data, respectively. A strobe signal driver that drives a strobe signal for capturing the output data, a change bit number detection block that detects a different bit number between the current data output by the plurality of bus drivers and the next data, A change interval detection block that detects an interval between a timing at which the plurality of bus drivers output the data and a timing at which the strobe signal driver outputs the strobe signal, and a timing at which the strobe signal driver drives the strobe signal. Detection result of the change bit number detection block and detection result of the change interval detection block It is a program for the causing a computer to function as all or part of the timing generation block that controls the strobe signal driver to change depending on the.

According to an embodiment of the present invention, there is provided an integrated circuit device comprising: a plurality of buses; and a plurality of bus drivers connected to the plurality of buses for driving each of the plurality of buses. And a strobe signal for taking in data of the plurality of buses, and an integrated circuit device including a driver for driving the strobe signal, wherein a different number of bits between current data and next data of the plurality of buses And means for detecting the time until the current data of the plurality of buses changes to the next data, and the timing of the strobe signal for the next data is changed according to the detection result. It is composed. This makes it possible to delay the strobe signal at the timing when switching noise generated when charging / discharging the capacity of the buffer output terminal, crosstalk noise when the output voltage changes rapidly, or reflection noise occurs. In this case, a sufficient timing margin on the side for taking in the simultaneous drive output signal can be ensured even at the time of data transfer, and an integrated circuit device capable of performing stable data transfer can be realized. Further shift the phase of the data bus or implement slew rate control,
Alternatively, by changing the output current capability, the number of drivers operating at the same time can be reduced, and the current for charging / discharging the load capacitance of the output driver can be reduced, and the maximum value of the influence on the power supply / GND near the output simultaneous change terminal is reduced. Reduced.

[0044]

Embodiments of the present invention will be described below with reference to the drawings.

As an example, the present invention provides a plurality of buses, a plurality of bus drivers connected to each of the plurality of buses for driving each of the plurality of buses, and a plurality of bus drivers for fetching data of the plurality of buses. An integrated circuit device having a strobe signal and a driver for driving the strobe signal, the integrated circuit device having change bit detection means for detecting a different number of bits between the current data and the next data of the plurality of buses; An integrated circuit device characterized in that the timing of the strobe signal for the next data is changed according to the detection result of the bit detection means, whereby switching noise generated when charging and discharging the capacity of the buffer output terminal, A strobe signal is generated at the timing when crosstalk noise and reflection noise occur when the output voltage changes suddenly. Possible to cast a becomes stable data transfer can be realized.

According to the present invention, as an example, in the integrated circuit device according to the present invention, the change bit detecting means for detecting a different number of bits between the current data and the next data of the plurality of buses includes a rewritable change. An integrated circuit device comprising a bit number setting register, wherein the timing of the strobe signal for the next data is changed by comparing the set value to the changed bit number setting register with the changing bit number. The strobe signal is generated according to the setting value set from the outside at the timing when switching noise generated when charging and discharging the capacity of the buffer output terminal, crosstalk noise when the output voltage suddenly changes, and reflection noise occur. Delay can be selected, and stable data transfer can be realized.

According to the present invention, as an example, in the integrated circuit device of the present invention, the means for changing the timing of the strobe signal includes a rewritable strobe signal timing setting register, and the setting value for the strobe signal timing setting register is provided. , An integrated circuit device comprising means for changing the amount by which the timing of the strobe signal for the next data is changed,
The strobe signal is delayed according to the externally set value at the timing when switching noise generated when charging / discharging the capacity of the buffer output terminal, crosstalk noise when the output voltage suddenly changes, or reflection noise occurs. The amount can be changed, and stable data transfer can be realized.

According to another aspect of the present invention, there is provided an integrated circuit device according to the above-mentioned invention, further comprising means for externally stopping means for changing the timing of the strobe signal. This makes it possible to control so as not to delay the strobe signal in any case.

According to another aspect of the present invention, there is provided the integrated circuit device according to the above-described invention, wherein the plurality of bus drivers are provided with a slew rate control means. The switching noise generated when discharging, the crosstalk noise when the output voltage suddenly changes, and the current that charges and discharges the load capacitance of the output driver at the timing when reflected noise occurs can be reduced. Power supply G
The maximum value of the influence on ND can be reduced, and stable data transfer can be realized.

According to another aspect of the present invention, there is provided the integrated circuit device according to the above aspect, wherein the change bit detecting means for detecting a different number of bits between the current data and the next data of the plurality of buses is adapted to detect a change in the number of bits. An integrated circuit device characterized by performing a rate control,
As a result, the switching noise generated when charging / discharging the capacity of the buffer output terminal, the current for charging / discharging the load capacity of the output driver at the timing when crosstalk noise or reflection noise occurs when the output voltage changes rapidly, are generated. Power supply and GND near the output simultaneous change terminal
Can be reduced, and stable data transfer can be realized.

According to another aspect of the present invention, in the integrated circuit device of the present invention, the change bit detecting means for detecting a different number of bits between the current data and the next data of the plurality of buses can be rewritten. An integrated circuit device comprising the change bit number setting register, and performing a slew rate control by comparing a set value to the change bit number setting register with the number of changed bits. The switching noise generated when charging and discharging the capacitor, the crosstalk noise when the output voltage suddenly changes, and the slew rate control according to the setting value set from the outside at the timing when the reflection noise occurs can be implemented. It becomes selectable, and the current that charges and discharges the load capacity of the output driver can be reduced. Simultaneous change the maximum value of the impact on the power · GND in the vicinity of the terminal becomes possible to reduce stable data transfer can be realized.

Further, the present invention is, for example, an integrated circuit device according to the above-mentioned invention, wherein the integrated circuit device has means capable of stopping the slew rate control means from the outside. Can be controlled so as not to execute the slew rate control.

According to another aspect of the present invention, there is provided an integrated circuit device according to the above-mentioned invention, wherein the plurality of bus drivers are provided with a means for controlling an output current. The switching noise generated when charging / discharging the output, the current that charges / discharges the load capacitance of the output driver at the timing when the crosstalk noise or the reflection noise occurs when the output voltage changes rapidly can be reduced, and the output changes simultaneously Power near the terminal
The maximum value of the influence on GND can be reduced, and stable data transfer can be realized.

According to another aspect of the present invention, in the integrated circuit device according to the above aspect, the output is based on a detection result of the change bit detecting means for detecting a different number of bits between the current data and the next data of the plurality of buses. An integrated circuit device characterized by implementing means for controlling current, whereby switching noise generated when charging / discharging the capacity of a buffer output terminal and crosstalk noise occurring when output voltage changes rapidly. The current that charges and discharges the load capacitance of the output driver at the timing when noise occurs and reflection noise occurs can be reduced.
The maximum value of the influence on GND can be reduced, and stable data transfer can be realized.

According to another aspect of the present invention, in the integrated circuit device according to the present invention, the change bit detecting means for detecting a different number of bits between the current data and the next data of the plurality of buses can be rewritten. An integrated circuit device comprising the change bit number setting register, and implementing means for controlling an output current by comparing a set value for the change bit number setting register with the number of changed bits. Controls the output current according to the externally set value at the timing of switching noise generated when charging and discharging the capacity of the buffer output terminal, crosstalk noise when output voltage changes rapidly, and reflection noise. Can be selected, the current that charges and discharges the load capacity of the output driver can be reduced, and the output When changing the maximum value of the impact on the power · GND in the vicinity of the terminal becomes possible to reduce stable data transfer can be realized.

The present invention also provides, by way of example, an integrated circuit device according to the above invention, further comprising means for externally stopping the means for controlling the output current. It is possible to control so as not to control the output current in any case.

According to another aspect of the present invention, in the integrated circuit device of the present invention, there is provided an integrated circuit including means for shifting the phases of signals input to the plurality of bus drivers to reduce the number of drivers operating simultaneously. Device, whereby the load capacitance of the output driver is charged at the timing when switching noise generated when charging / discharging the capacitance at the buffer output end, crosstalk noise when the output voltage suddenly changes, or reflection noise occurs. The discharge current can be reduced, the maximum value of the influence on the power supply / GND near the output simultaneous change terminal can be reduced, and stable data transfer can be realized.

According to another aspect of the present invention, in the integrated circuit device according to the above aspect, the phase is determined based on a detection result of the change bit detecting means for detecting a different number of bits between the current data and the next data of the plurality of buses. An integrated circuit device characterized by implementing means for controlling whether or not the output voltage is shifted, whereby switching noise generated when charging / discharging the capacity of the buffer output terminal and crossing when the output voltage changes abruptly are provided. The current that charges and discharges the load capacitance of the output driver at the timing when talk noise and reflection noise occur can be reduced, and the maximum value of the influence on the power supply and GND near the output simultaneous change terminal can be reduced, resulting in stable data. Transfer can be realized.

According to another aspect of the present invention, in the integrated circuit device of the present invention, the changeable bit detecting means for detecting a different number of bits between the current data and the next data on the plurality of buses is rewritable. An integrated circuit device comprising a changing bit number setting register, and implementing means for controlling whether or not to shift the phase by comparing the set value for the changing bit number setting register with the number of changing bits. Switching noise generated when charging and discharging the capacity of the buffer output end,
It is possible to select whether to shift the phase according to the set value set externally at the timing when crosstalk noise and reflection noise occur when the output voltage changes suddenly, and charge and discharge the load capacitance of the output driver Current, the maximum value of the influence on the power supply / GND near the output simultaneous change terminal can be reduced, and stable data transfer can be realized.

According to the present invention, as an example, in the integrated circuit device according to the present invention, the means for shifting the phases of the signals input to the plurality of bus drivers to reduce the number of drivers operating simultaneously is externally stopped. This is an integrated circuit device provided with means capable of controlling the phase without shifting the phase in any case.

Further, as an example, the present invention takes in a plurality of buses, a plurality of bus drivers connected to each of the plurality of buses for driving each of the plurality of buses, and the data of the plurality of buses. And a strobe signal for driving the strobe signal, a change interval detection for detecting an interval from a change in data of the plurality of buses until the output of the strobe signal. Means for changing the timing of the strobe signal for the next data in accordance with the detection result of the change interval detecting means, thereby charging / discharging the capacity of the buffer output terminal. Switching noise, crosstalk noise and reflection noise when the output voltage changes suddenly. Timing can be delayed strobe signal and becomes stable data transfer can be realized.

According to the present invention, as an example, in the integrated circuit device according to the present invention, the change interval detecting means for detecting an interval from when the data of the plurality of buses changes to when the strobe signal is output, An integrated circuit device comprising a rewritable change interval setting register, wherein the timing of the strobe signal for the next data is changed by comparing a set value for the change interval setting register with a detected change interval. This allows switching noise to be generated when charging / discharging the capacitance at the buffer output end, crosstalk noise when the output voltage changes rapidly, and strobe according to the set value set externally at the timing when reflected noise occurs. The signal delay can be selected, and stable data transfer can be realized.

According to the present invention, as an example, in the integrated circuit device according to the present invention, the means for changing the timing of the strobe signal includes a rewritable strobe signal timing setting register, and a setting value for the strobe signal timing setting register. An integrated circuit device comprising means for changing the amount by which the timing of the strobe signal for the next data is changed, whereby the switching noise and the output voltage generated when charging and discharging the capacity of the buffer output terminal are reduced. The amount of delay of the strobe signal can be changed in accordance with a setting value set from the outside at the timing when crosstalk noise or reflection noise occurs when the change occurs abruptly, and stable data transfer can be realized.

According to another aspect of the present invention, there is provided an integrated circuit device according to the above-mentioned invention, further comprising means for externally stopping means for changing the timing of the strobe signal. This makes it possible to control so as not to delay the strobe signal in any case.

According to another aspect of the present invention, there is provided the integrated circuit device according to the above-mentioned invention, wherein the plurality of bus drivers are provided with a slew rate control means. The switching noise generated when discharging, the crosstalk noise when the output voltage suddenly changes, and the current that charges and discharges the load capacitance of the output driver at the timing when reflected noise occurs can be reduced. Power supply G
The maximum value of the influence on ND can be reduced, and stable data transfer can be realized.

According to another aspect of the present invention, in the integrated circuit device of the present invention, the change interval detecting means for detecting an interval from when the data of the plurality of buses changes to when the strobe signal is output is detected. An integrated circuit device characterized in that slew rate control is performed according to the result, whereby switching noise generated when charging / discharging the capacity of the buffer output terminal and crosstalk noise occurring when the output voltage changes rapidly. The current that charges and discharges the load capacitance of the output driver at the timing when reflection noise occurs can be reduced, and the maximum value of the influence on the power supply and GND near the output simultaneous change terminal can be reduced, and stable data transfer can be achieved. realizable.

According to another aspect of the present invention, in the integrated circuit device according to the present invention, the change interval detecting means for detecting an interval from a change in the data of the plurality of buses to the output of the strobe signal includes: An integrated circuit device comprising a rewritable change interval setting register and performing a slew rate control by comparing a set value to the change interval setting register with a detected change interval. The switching noise generated when charging and discharging the capacitor, the crosstalk noise when the output voltage suddenly changes, and the slew rate control according to the setting value set from the outside at the timing when the reflection noise occurs can be implemented. It becomes selectable, and the current that charges and discharges the load capacity of the output driver can be reduced. Simultaneous change the maximum value of the impact on the power · GND in the vicinity of the terminal becomes possible to reduce stable data transfer can be realized.

Also, the present invention is, by way of example, an integrated circuit device according to the above-mentioned invention, wherein the slew rate control means is provided with means capable of being stopped from the outside. Can be controlled so as not to execute the slew rate control.

According to another aspect of the present invention, there is provided the integrated circuit device according to the above-described invention, wherein the plurality of bus drivers are provided with a means for controlling an output current. The switching noise generated when charging / discharging the output, the current that charges / discharges the load capacitance of the output driver at the timing when the crosstalk noise or the reflection noise occurs when the output voltage changes rapidly can be reduced, and the output changes simultaneously Power near the terminal
The maximum value of the influence on GND can be reduced, and stable data transfer can be realized.

According to another aspect of the present invention, there is provided the integrated circuit device according to the above aspect, wherein the change interval detecting means for detecting an interval from when the data of the plurality of buses changes to when the strobe signal is output is detected. An integrated circuit device characterized by implementing a means for controlling an output current according to a result, whereby a switching noise generated when charging and discharging a capacity of a buffer output terminal and a sudden change in an output voltage are generated. The current that charges and discharges the load capacitance of the output driver at the timing when crosstalk noise and reflection noise occur can be reduced, and the maximum value of the influence on the power supply and GND near the output simultaneous change terminal can be reduced, and it becomes stable. Data transfer can be realized.

According to the present invention, as an example, in the integrated circuit device according to the present invention, the change interval detecting means for detecting an interval from a change in the data of the plurality of buses to the output of the strobe signal includes: An integrated circuit device comprising a rewritable change interval setting register, and implementing means for controlling an output current by comparing a set value for the change interval setting register with a detected change interval. Controls the output current according to the externally set value at the timing of switching noise generated when charging and discharging the capacity of the buffer output terminal, crosstalk noise when output voltage changes rapidly, and reflection noise. Can be selected, the current that charges and discharges the load capacity of the output driver can be reduced, and the output When changing the maximum value of the impact on the power · GND in the vicinity of the terminal becomes possible to reduce stable data transfer can be realized.

Also, the present invention is, by way of example, an integrated circuit device according to the above-mentioned invention, further comprising means for externally stopping the means for controlling the output current. It is possible to control so as not to control the output current in any case.

According to another aspect of the present invention, there is provided an integrated circuit device according to the above invention, further comprising means for shifting the phases of signals input to the plurality of bus drivers to reduce the number of drivers operating simultaneously. As a result, switching noise generated when charging / discharging the capacity of the buffer output terminal, crosstalk noise when the output voltage changes abruptly, and reflection noise occur when the load capacitance of the output driver is charged / discharged. Current, the maximum value of the influence on the power supply / GND near the output simultaneous change terminal can be reduced, and stable data transfer can be realized.

According to another aspect of the present invention, in the integrated circuit device according to the present invention, the change interval detecting means for detecting an interval from when the data of the plurality of buses changes to when the strobe signal is output is detected. An integrated circuit device characterized by implementing means for controlling whether or not to shift the phase according to the result, whereby the switching noise and the output voltage generated when charging and discharging the capacity of the buffer output terminal changed abruptly. The current that charges and discharges the load capacitance of the output driver at the timing when crosstalk noise and reflection noise occur at the time can be reduced, and the maximum value of the influence on the power supply / GND near the output simultaneous change terminal can be reduced. Stable data transfer can be realized.

According to the present invention, as an example, in the integrated circuit device of the present invention, the change interval detecting means for detecting an interval from when the data of the plurality of buses changes to when the strobe signal is output, An integrated circuit device comprising a rewritable change interval setting register, and implementing means for controlling whether or not to shift the phase by comparing the set value for the change interval setting register with the detected change interval. The phase is shifted according to the set value set from the outside at the timing when switching noise generated when charging / discharging the capacity of the buffer output terminal, crosstalk noise when output voltage suddenly changes, and reflection noise occur. Can be selected to reduce the current that charges and discharges the load capacitance of the output driver. Succoth can, can maximum impact is reduced with respect to the now stable data transfer power · GND near simultaneous output changes terminals can be realized.

According to the present invention, as an example, in the integrated circuit device according to the present invention, the means for shifting the phases of the signals input to the plurality of bus drivers and reducing the number of simultaneously operating drivers is externally stopped. This is an integrated circuit device provided with means capable of controlling the phase so as not to shift the phase in any case.

Further, as an example, the present invention takes in a plurality of buses, a plurality of bus drivers connected to each of the plurality of buses for driving each of the plurality of buses, and the data of the plurality of buses. A strobe signal for driving the strobe signal, and a change bit detecting means for detecting a different number of bits between the current data and the next data of the plurality of buses, Having a change interval detecting means for detecting an interval from the current data of the bus to the next data,
According to the detection result of the number of different bits between the current data of the plurality of buses and the next data and the detection result of the interval until the next data changes from the current data of the plurality of buses,
An integrated circuit device characterized by changing the timing of the strobe signal for the next data, whereby switching noise generated when charging / discharging the capacity of the buffer output terminal, when the output voltage changes rapidly The strobe signal can be delayed at the timing when the crosstalk noise and the reflection noise occur, and stable data transfer can be realized.

(Embodiment 1) First, Embodiment 1 will be described with reference to FIGS. FIG. 1 is a block diagram showing signal processing of the integrated circuit device according to the first embodiment of the present invention, and FIG. 2 is a timing chart of main signals in FIG.

The integrated circuit device of the present embodiment operates based on the system clock shown in FIG. In FIG. 1, when the output data is ready, the output latch signal 14
0 and output internal data D0_IN100, D1_IN11
0, D2_IN120 and D3_IN130 are input. Output internal data D0_IN100, D1_IN11
0, D2_IN120 and D3_IN130 are latched by the data latches 101, 111, 121 and 131 at the timing of the output latch signal 140, respectively. The latched output latch data 102, 112, 122,
132 is an output buffer 103, 113, 12
3, 133, the output signals D0_OUT104, D1
_OUT114, D2_OUT124, D3_OUT1
It is output to the outside as 34.

The output latch signal 140 is also input to the strobe generation block 141 at the same time, and is subjected to processing for delaying the setup and hold time of the data within the normally permitted data transfer rate until the maximum time can be secured. It becomes an internal signal 142. The strobe internal signal 142 is output to the outside as the strobe signal 144 through the output buffer 143.

The strobe signal 144 includes the output signals D0_OUT104, D1_OUT114, D2_O
This signal indicates the timing at which the external device takes in the UT 124 and D3_OUT 134.

The strobe generation block 141 includes:
In addition to the output latch signal 140, the output internal data D0_IN
100, D1_IN110, D2_IN120, D3_
IN130, output latch data 102, 112, 12
2, 132, a change bit number setting register 150, a timing setting register 160, an enable signal 170, and a change interval setting register 180 are input.

The inside of the strobe generation block 141
It is composed of a change bit number detection block 151, a change interval detection block 181, and a timing generation block 161.

The change bit number detection block 151 outputs the output internal data D0_ at the timing of the output latch signal 140.
IN100, D1_IN110, D2_IN120, D
3_IN 130 and the number of different bits of the corresponding output latch data 102, 112, 122, 132 are detected.

For example, the bits of D0_IN100 and the output latch data 102 are different, and D1_IN110
And output latch data 112 have the same bit, and D2_
When the bits of IN 120 and the output latch data 122 are equal and the bits of D3_IN 130 and the output latch data 132 are different, the change bit number detection block 151 detects 2 as a different number of the above bits. Will be.

Then, the change bit number detection block 151
Indicates that the number of detected bits is changed
When the value is 0 or more, a bit timing change signal 152 is output to the timing generation block 161.

For example, the change bit number setting register 150
Is set to 3, and if the number detected by the change bit number detection block 151 is 2 or less, the change bit number detection block 151 sends a bit timing change signal 152 to the timing generation block 161. Is not output. On the other hand, the change bit number detection block 1
If the number detected by 51 is 3 or more, the change bit number detection block 151
A bit timing change signal 152 is output for 1.

The change interval detection block 181 detects the interval between the output latch signal 140 and the strobe internal signal 142. When the detected interval is smaller than the change interval setting register 180, the timing generation block 16
For one, an interval timing change signal 182 is output.

For example, when the value of the change interval setting register 180 is set to 1, the change interval detection block 18
1 is the output latch signal 140 and the strobe internal signal 14
When it is detected that the interval between the two is 0 clock, the change interval detection block 181 outputs an interval timing change signal 182 to the timing generation block 161. On the other hand, the change interval detection block 181
Are the output latch signal 140 and the strobe internal signal 142
When it is detected that the interval between them is one clock or more, the change interval detection block 181 does not output the interval timing change signal 182 to the timing generation block 161.

When the enable signal 170 is valid, the timing generation block 161 generates the bit timing change signal 152 or the interval timing change signal 182.
Is received, the output latch signal 140 is delayed for the time set in the timing setting register 160 and output as the strobe internal signal 142.

For example, when the time set in the timing setting register 160 is one clock, the timing generation block 161 outputs the bit timing change signal 152 or the interval timing change signal 182 when the enable signal 170 is valid. When accepted, the output latch signal 140 is delayed by one clock and output as the strobe internal signal 142.

The strobe internal signal 142 generated in this way is output to the outside as a strobe signal 144 through the output buffer 143.

Further, the integrated circuit device according to the present embodiment uses the enable signal 170 to generate the timing generation block 161 and the change bit detection block 15 as described above.
1. Each function of the change interval detection block 181 can be externally stopped. This makes it possible to control so as not to delay the strobe signal in any case.

The output buffer 10 according to the present embodiment
Reference numerals 3, 113, 123, and 133 denote examples of a plurality of bus drivers of the present invention, and the output buffer 143 of the present embodiment.
Is an example of the strobe signal driver of the present invention, and the timing setting register of the present embodiment is an example of the strobe signal timing setting register of the present invention.

As described above, according to the first embodiment, the switching noise generated when charging / discharging the capacity of the buffer output terminal, the crosstalk noise when the output voltage changes abruptly, and the reflection noise occur at the timing. Since the strobe signal can be delayed, stable data transfer can be realized.

(Embodiment 2) Next, Embodiment 2 will be described with reference to FIG.

FIG. 3 is a block diagram showing signal processing of the integrated circuit device according to the second embodiment of the present invention.

[0098] Various components (such as various signals, various blocks, various buffers, various clocks, and various circuits) of the integrated circuit device according to the second embodiment of the present invention are described in the second embodiment unless otherwise described. The components have the same functions as those of the first embodiment having the same names as those of the components, and detailed descriptions thereof will be omitted.

In the integrated circuit device of the present embodiment, when output data is ready in FIG.
And output internal data D0_IN300, D1_IN31
0, D2_IN320, and D3_IN330 are input. Output internal data D0_IN300, D1_IN31
0, D2_IN320 and D3_IN330 are respectively latched by the data latches 301, 311, 321 and 331 at the timing of the output latch signal 340. The latched output latch data 302, 312, 322,
332 are output buffers 303, 313, and 32, respectively.
Output signals D0_OUT304, D1
_OUT314, D2_OUT324, D3_OUT3
It is output to the outside as 34.

The output latch signal 340 is also input to the strobe generation block 341 at the same time, and is subjected to processing for delaying the setup and hold time of data within the normally permitted data transfer rate to the timing at which the maximum time can be secured. It becomes an internal signal 342. The strobe internal signal 342 is output to the outside as a strobe signal 344 through an output buffer 343.

The strobe generation block 341 has the output internal data D0_IN3 in addition to the output latch signal 340.
00, D1_IN310, D2_IN320, D3_I
N330, output latch data 302, 312, 322,
332, a change bit number setting register 350, a timing setting register 360, an enable signal 370, and a change interval setting register 380 are input. Inside, a change bit number detection block 351, a change interval detection block 381,
It comprises a timing generation block 361.

The change bit number detection block 351 outputs the output internal data D0_ at the timing of the output latch signal 340.
IN300, D1_IN310, D2_IN320, D
3_IN 330 and the number of bits of output latch data 302, 312, 322, and 332 corresponding to each other are detected. When the detected bit number is equal to or larger than the change bit number setting register 350, the bit timing change signal 352 is output to the timing generation block 361.

The change interval detection block 381 detects the interval between the output latch signal 340 and the strobe internal signal 342.
When it is smaller than 0, an interval timing change signal 382 is output to the timing generation block 361.

When the enable signal 370 is valid, the timing generation block 361 outputs the bit timing change signal 352 or the interval timing change signal 382.
Is received, the output latch signal 340 is delayed for the time set by the timing setting register 360 and output as the strobe internal signal 342.

Further, the timing generation block 361
When the bit timing change signal 352 or the interval timing change signal 382 is received while the enable signal 370 is valid, the slew rate control signal 345 is output to the output buffers 303, 313, 323, and 333.
Output to

The output buffers 303, 313, 3 shown in FIG.
23, 333 are each composed of two divided drivers, and output signals D0_OUT304, D1_
OUT314, D2_OUT324, D3_OUT33
4 is the sum of the signals output from these two drivers. Also, the output buffers 303, 313, 323, 3
The selector 33 can use a selector to switch between driving one of the two divided drivers with delay by a delay circuit or driving without delay.

The output buffers 303, 313, 323, and 333 receiving the slew rate control signal 345
By driving one of the divided drivers inside the output buffer with a delay, the output signal D0_O
UT304, D1_OUT314, D2_OUT32
4. Suppress rapid changes in D3_OUT334.

That is, when the slew rate control signal 345 is received, the output buffers 303, 313, 3
23 and 333 respectively output a signal from one of the two drivers of the driver, and
Since a signal is output from the driver driven with a delay after a lapse of a predetermined time, the output signal D0 is compared with the case where signals are output from these two drivers at the same time.
_OUT304, D1_OUT314, D2_OUT3
24, D3_OUT334 does not change rapidly.

In the integrated circuit device according to the present embodiment, the above-mentioned slew rate control means can be externally stopped by the above-mentioned enable signal 370. Therefore, it is possible to control so as not to execute the slew rate control in any case.

In the above description, an example has been described in which a driver obtained by dividing the slew rate control is delayed. However, a method of suppressing a change in output by another method can be similarly implemented.

Furthermore, in the present embodiment, the output buffers 303, 313, 323, and 333 have been described as being divided into two drivers. However, the present invention is not limited to this. , 31
As long as the slew rate can be controlled by 3, 323, 333, the driver may be divided into any number of drivers.

Further, the output buffer 30 of the present embodiment
Reference numerals 3, 313, 323, and 333 are examples of the plurality of bus drivers of the present invention, and the output buffer 343 of the present embodiment.
Is an example of the strobe signal driver of the present invention, the timing setting register of the present embodiment is an example of the strobe signal timing setting register of the present invention, and the output buffers 303, 313, 323, and 333 of the present embodiment are respectively The delay circuit and selector provided are examples of the slew rate control means of the present invention.

As described above, according to the second embodiment, the same effect as that of the first embodiment can be obtained, and further, switching noise and output voltage generated when charging and discharging the capacity of the buffer output terminal are sharply reduced. The slew rate control can be performed according to the set value set externally at the timing when crosstalk noise and reflection noise occur when it changes, and the current that charges and discharges the load capacitance of the output driver can be reduced. In addition, the maximum value of the influence on the power supply / GND near the output simultaneous change terminal can be reduced, and stable data transfer can be realized.

(Embodiment 3) Next, a third embodiment will be described with reference to FIG.

FIG. 4 is a block diagram showing signal processing of the integrated circuit device according to the third embodiment of the present invention.

Note that the various components (such as various signals, various blocks, various buffers, various clocks, and various circuits) of the integrated circuit device according to the third embodiment of the present invention are described in the third embodiment unless otherwise described. The components have the same functions as those of the first embodiment having the same names as those of the components, and detailed descriptions thereof will be omitted.

In the integrated circuit device of the present embodiment, when output data is ready in FIG.
And output internal data D0_IN400, D1_IN41
0, D2_IN420, and D3_IN430 are input. Output internal data D0_IN400, D1_IN41
0, D2_IN420, and D3_IN430 are latched by the data latches 401, 411, 421, and 431 at the timing of the output latch signal 440, respectively. The latched output latch data 402, 412, 422,
432 denotes output buffers 403, 413, and 42, respectively.
3 and 433, output signals D0_OUT404, D1
_OUT414, D2_OUT424, D3_OUT4
It is output to the outside as 34.

The output latch signal 440 is also input to the strobe generation block 441 at the same time, and is subjected to processing for delaying the setup and hold time of data within the normally permitted data transfer rate until the maximum time can be secured. It becomes an internal signal 442. The strobe internal signal 442 is output to the outside as a strobe signal 444 through an output buffer 443.

Further, the strobe generation block 441 outputs the output internal data D0_IN4 in addition to the output latch signal 440.
00, D1_IN410, D2_IN420, D3_I
N430, output latch data 402, 412, 422,
432, a change bit number setting register 450, a timing setting register 460, an enable signal 470, and a change interval setting register 480. Inside, a change bit number detection block 451, a change interval detection block 481,
It comprises a timing generation block 461.

The changed bit number detection block 451 outputs the output internal data D0_ at the timing of the output latch signal 440.
IN400, D1_IN410, D2_IN420, D
3_IN 430 and the number of bits different from the corresponding output latch data 402, 412, 422, 432 are detected. When the detected bit number is equal to or greater than the change bit number setting register 450, the bit timing change signal 452 is output to the timing generation block 461.

The change interval detecting block 481 detects the interval between the output latch signal 440 and the strobe internal signal 442.
When it is smaller than 0, an interval timing change signal 482 is output to the timing generation block 461.

When the enable signal 470 is valid, the timing generation block 461 generates the bit timing change signal 452 or the interval timing change signal 482.
Is received, the output latch signal 440 is delayed for the time set in the timing setting register 460 and output as the strobe internal signal 442.

Further, the timing generation block 461
When the bit timing change signal 452 or the interval timing change signal 482 is received when the enable signal 470 is in a valid state, the current capability control signal 44
5 is output to the output buffers 403, 413, 423, and 433.

Output buffers 403, 413, 423, 4
Reference numeral 33 denotes two divided drivers, one of which can open its output by a switch.

The output buffers 403, 413, 423, and 433, which have received the current capability control signal 445, open the output of one of the divided drivers inside the output buffer to output the output signal D0_OUT4.
04, D1_OUT414, D2_OUT424, D3
Abrupt change of _OUT434 is suppressed.

That is, the output buffers 403, 413,
When each of 423 and 433 opens the output of one of the two drivers owned by itself,
The output signal D0_OUT40
4, D1_OUT414, D2_OUT424, D3_
The current at the peak of each of the OUTs 434 is halved.
Therefore, when receiving the current capability control signal 445, the output signals D0_OUT404, D1_OUT41
4, D2_OUT 424 and D3_OUT 434 do not change abruptly as compared with the other case.

Further, in the integrated circuit device of the present embodiment, the means for controlling the output current can be externally stopped by the enable signal 470. Therefore, it is possible to control so as not to control the output current in any case.

In this embodiment, the output buffer 4
03, 413, 423, and 433 have been described as being composed of two divided drivers,
The present invention is not limited to this. For example, when the output buffers 403, 413, 423, and 433 receive the current capability control signal 445, the output signals D0_OUT
404, D1_OUT414, D2_OUT424, D
Any number of drivers may be divided as long as the current at the peak of each of the 3_OUT 434 can be reduced.

Further, the output buffer 40 of the present embodiment
3, 413, 423, and 433 are examples of a plurality of bus drivers of the present invention, and the output buffer 443 of the present embodiment is shown.
Is an example of the strobe signal driver of the present invention, the timing setting register of the present embodiment is an example of the strobe signal timing setting register of the present invention, and the output buffers 403, 413, 423, and 433 of the present embodiment are respectively The switch provided is an example of the output current control means of the present invention.

As described above, according to the third embodiment, in addition to the effects of the first embodiment, the switching noise and the output voltage generated when charging / discharging the capacity of the buffer output terminal are abruptly changed. When the crosstalk noise or reflection noise occurs, the output current can be controlled according to the set value set from the outside, and the current that charges and discharges the load capacitance of the output driver can be reduced. Since the maximum value of the influence on the power supply and GND near the simultaneous change terminal can be reduced,
Stable data transfer can be realized.

(Fourth Embodiment) Next, a fourth embodiment will be described with reference to FIG.

FIG. 5 is a block diagram showing signal processing of the integrated circuit device according to the fourth embodiment of the present invention.

Note that various components (various signals, various blocks, various buffers, various clocks, various circuits, and the like) of the integrated circuit device according to the fourth embodiment of the present invention are described in the fourth embodiment unless otherwise described. The components have the same functions as those of the first embodiment having the same names as those of the components, and detailed descriptions thereof will be omitted.

In the integrated circuit device of the present embodiment, when output data is ready in FIG.
And output internal data D0_IN500, D1_IN51
0, D2_IN520 and D3_IN530 are input. Output internal data D0_IN500, D1_IN51
0, D2_IN520, and D3_IN530 are latched by the data latches 501, 511, 521, and 531 at the timing of the output latch signal 540, respectively. The latched output latch data 502, 512, 522,
Reference numerals 532 denote output buffers 503, 513, and 52, respectively.
3, 533 and output signals D0_OUT504, D1
_OUT514, D2_OUT524, D3_OUT5
It is output to the outside as 34.

The output latch signal 540 is also input to the strobe generation block 541 at the same time, and is subjected to processing for delaying the setup and hold time of the data within the normally permitted data transfer rate until the maximum time can be secured. It becomes an internal signal 542. The strobe internal signal 542 is output to the outside as the strobe signal 544 through the output buffer 543.

Further, the strobe generation block 541 outputs the output internal data D0_IN5 in addition to the output latch signal 540.
00, D1_IN510, D2_IN520, D3_I
N530, output latch data 502, 512, 522,
532, a change bit number setting register 550, a timing setting register 560, an enable signal 570, and a change interval setting register 580 are input. Inside, a change bit number detection block 551, a change interval detection block 581,
It is composed of a timing generation block 561.

The change bit number detection block 551 outputs the output internal data D0_ at the timing of the output latch signal 540.
IN500, D1_IN510, D2_IN520, D
3_IN 530 and the number of different bits of output latch data 502, 512, 522, and 532 corresponding thereto are detected. When the detected number of bits is equal to or greater than the change bit number setting register 550, a bit timing change signal 552 is output to the timing generation block 561.

The change interval detection block 581 is a block for detecting the interval between the output latch signal 540 and the strobe internal signal 542.
When it is smaller than 0, an interval timing change signal 582 is output to the timing generation block 561.

When the enable signal 570 is valid, the timing generation block 561 generates the bit timing change signal 552 or the interval timing change signal 582.
Is received, the output latch signal 540 set in the timing setting register 560 is delayed and output as the strobe internal signal 542.

Further, the timing generation block 561
When the bit timing change signal 552 or the interval timing change signal 582 is received while the enable signal 570 is valid, the output latch signal timing control signal 545 is output to the output latch signal selector 515,
525 and 535 are output. The output latch signal selector 515, 525, 535 receiving the output latch signal timing control signal 545 outputs the output latch data 51
2, 522, and 532 are selected and output to the output buffer to output signal D0_OUT5.
04, D1_OUT514, D2_OUT524, D3
Simultaneous change of _OUT534 is suppressed.

That is, as is apparent from FIG. 5, when the output latch selectors 515, 525, 535 select the delayed signals, the output latch selectors 515, 52
5, 535 are output latch data 512, 522, 532
Are delayed so that the delay amounts are different from each other. The output latch data 502 is not delayed. Therefore, the output latch data 502, 512, 522,
532 is an output buffer 503, 513, 523, 533
Will all be different. Therefore, the output signals D0_OUT504, D1_OUT51
4, the simultaneous change of D2_OUT 524 and D3_OUT 534 can be suppressed.

In the integrated circuit device of this embodiment, the latch selectors 515 and 52 reduce the number of simultaneously operating output buffers by shifting the phases of signals input to the output buffers 503, 513, 523 and 533.
5,536, etc., using the enable signal 570 described above.
Can be stopped from outside. Therefore,
In any case, it is possible to control so as not to shift the phase.

In this embodiment, when the output latch signal timing control signal 545 is sent, the output latch data 502, 512, 522, and 532 are output.
Has been described as making all the timings input to the output buffers 503, 513, 523, and 533 different, but the present invention is not limited to this. Although the effect of suppressing the simultaneous change is somewhat inferior, the output latch data 502, 512, 522, 5
A plurality of delay amounts may be the same and / or a plurality of delay amounts may not be delayed. In short, when the output latch signal timing control signal 545 is sent, the output latch data 502, 512, 522, 53
The timing at which 2 is input to the output buffers 503, 513, 523, and 533 may not always be the same.

As described above, according to the present embodiment, the switching noise generated when charging / discharging the capacitance at the buffer output terminal, the timing at which the crosstalk noise and the reflection noise occur when the output voltage changes rapidly. The current that charges and discharges the load capacity of the output driver can be reduced,
The maximum value of the influence on the power supply / GND near the output simultaneous change terminal can be reduced, and stable data transfer can be realized.

In the above description, an example has been described in which a delay is inserted into an output latch signal. However, a method of suppressing a simultaneous change in output by inserting a delay into an output latch signal can be similarly implemented.

Further, the output buffer 50 of the present embodiment
Reference numerals 3, 513, 523, and 533 denote examples of a plurality of bus drivers of the present invention.
Is an example of the strobe signal driver of the present invention, the timing setting register of the present embodiment is an example of the strobe signal timing setting register of the present invention, and the output latch selectors 515, 525, 535, and the delay of the present embodiment. The circuit is an example of the phase control means of the present invention.

As described above, according to the present embodiment, the switching noise generated when charging / discharging the capacity of the buffer output terminal, the timing at which the crosstalk noise or the reflection noise occurs when the output voltage changes rapidly. It is possible to delay the strobe signal, secure sufficient timing margin on the side that captures the simultaneous drive output signal even during high-speed data transfer, and realize an integrated circuit device that can perform stable data transfer. Becomes Furthermore, by shifting the phase of the data bus, implementing slew rate control, or changing the output current capability, the number of drivers operating simultaneously can be reduced,
The current for charging / discharging the load capacitance of the output driver can be reduced, and the maximum value of the influence on the power supply / GND near the output simultaneous change terminal can be reduced.

The present invention is a program for causing a computer to execute the functions of all or a part of the integrated circuit device of the present invention (or devices, elements, circuits, units, blocks, and the like). It is a program that operates in cooperation with a computer.

Note that some means (or an apparatus, an element, a circuit, a unit, a block, or the like) of the present invention means some of the plurality of means, or one of them. It means some functions of the means.

The present invention also includes a computer-readable recording medium on which the program of the present invention is recorded.

[0151] One use form of the program of the present invention may be such that the program is recorded on a computer-readable recording medium and operates in cooperation with the computer.

[0152] One usage of the program of the present invention may be a mode in which the program is transmitted through a transmission medium, read by a computer, and operates in cooperation with the computer.

The recording medium includes a ROM and the like, and the transmission medium includes a transmission medium such as the Internet,
Light, radio waves, sound waves, etc. are included.

The computer of the present invention described above
It is not limited to pure hardware such as a CPU, but may include firmware, an OS, and peripheral devices.

As described above, the configuration of the present invention may be realized by software or hardware.

[0156]

As is apparent from the above description, the present invention provides an integrated circuit device and a program which can avoid the influence on the input signal even when the ratio of the simultaneously driven output signal terminals is large. Can be provided.

Further, the present invention can provide an integrated circuit and a program which can be adapted to high-speed data transfer even when the ratio of simultaneous drive output signal terminals is large.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating signal processing of an integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a timing chart of main signals of the integrated circuit device according to the first embodiment of the present invention;

FIG. 3 is a block diagram showing signal processing of an integrated circuit device according to a second embodiment of the present invention.

FIG. 4 is a block diagram illustrating signal processing of an integrated circuit device according to a third embodiment of the present invention.

FIG. 5 is a block diagram illustrating signal processing of an integrated circuit device according to a fourth embodiment of the present invention.

[Explanation of symbols]

100 300 400 500 Output internal data D0
_IN 110 310 410 410 510 Output internal data D1
_IN 120 320 420 520 Output internal data D2
_IN 130 330 430 530 Output internal data D3
_IN 140 340 440 540 Output latch signal 101 301 401 501 Output internal data D0
_I data latch 111 311 411 511 Output internal data D1
_I data latch 121 321 421 521 Output internal data D2
_I data latch 131 331 431 531 Output internal data D3
_I data latch 102 302 402 502 output latch data 112 312 412 512 output latch data 122 322 422 522 output latch data 132 332 432 532 output latch data 142 342 442 542 strobe internal signal 103 303 403 503 output buffer 113 313 413 513 13 Buffer 123 323 423 523 Output buffer 133 333 433 533 Output buffer 143 343 443 543 Output buffer 104 304 404 504 504 Output signal D0_OU
T 114 314 414 514 Output signal D1_OU
T 124 324 424 524 Output signal D2_OU
T 134 334 434 534 Output signal D3_OU
T 144 344 444 544 Strobe signal 141 341 441 541 Strobe generation block 150 350 450 550 Change bit number setting register 151 351 451 551 Change bit number detection block 152 352 452 552 Bit timing change signal 160 360 460 160 560 Timing 560 461 561 Timing generation block 170 370 470 570 Enable signal 180 380 480 580 Change interval setting register 181 381 481 581 Change interval detection block 182 382 482 582 Interval timing change signal 345 Slew rate control signal 445 Current capability control signal 515 525 525 Signal selector 545 Output latch signal tie Ring control signal

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Oka Zaki ▼ Makoto 1-8, Koshinmachi, Takamatsu City, Kagawa Prefecture Inside Matsushita Hisashi Denshi Kogyo Co., Ltd. (72) Inventor Noguchi Noguchi 8 1 F-term in Matsushita Hisashi Denshi Kogyo Co., Ltd. (Reference) 5B083 AA08 AA09 BB11 EE11 EF01 5J056 AA03 AA05 AA39 BB02 BB23 BB25 BB33 BB35 CC05 CC09 CC14 CC17 FF01 FF07 FF10 GG13 GG14 KK00

Claims (32)

[Claims] 1. A plurality of bus drivers for driving a plurality of buses to output data, a strobe signal driver for driving a strobe signal for capturing the output data, and an output from the plurality of bus drivers A change bit number detection block for detecting a different bit number between the current data and the next data; and a timing at which the strobe signal driver drives the strobe signal is changed according to a detection result of the change bit number detection block. And a timing generation block for controlling the strobe signal driver. 2. A rewritable register, comprising: a changing bit number setting register in which a predetermined setting value is set; wherein the timing generation block is configured to determine that the different bit number is equal to or more than the predetermined setting value. 2. The integrated circuit device according to claim 1, wherein the instruction is issued to change the timing. 3. A strobe signal timing setting register which is a rewritable register and in which a predetermined setting value is set, wherein the timing generation block uses the predetermined setting value to generate the strobe signal driver. 2. The integrated circuit device according to claim 1, wherein the step determines the amount by which the timing of the strobe signal corresponding to the next data is changed. 4. A plurality of bus drivers each of which has a slew rate control means for controlling a slew rate for outputting data, drives a plurality of buses and outputs the data, and a current output from the plurality of bus drivers. A change bit number detection block for detecting a different number of bits between the next data and the next data; and a timing for controlling the plurality of bus drivers to change the slew rate according to a detection result of the change bit number detection block. An integrated circuit device comprising a generation block. 5. A rewritable register, comprising: a changing bit number setting register in which a predetermined setting value is set; wherein the timing generation block is configured to determine that the different bit number is equal to or more than the predetermined setting value. 5. The integrated circuit device according to claim 4, wherein the instruction is made to reduce the slew rate. 6. An output current control means for controlling an output current corresponding to data to be output, a plurality of bus drivers each of which drives a plurality of buses and outputs the data, and wherein the plurality of bus drivers output the data. A changed bit number detection block for detecting a different bit number between the current data and the next data to be changed; and controlling the plurality of bus drivers to change the output current according to a detection result of the changed bit number detection block. An integrated circuit device comprising a timing generation block. 7. A rewritable register, comprising: a changing bit number setting register in which a predetermined setting value is set; wherein the timing generation block is configured to determine that the different bit number is equal to or larger than the predetermined setting value. 7. The integrated circuit device according to claim 6, wherein an instruction is issued to reduce said output current. 8. A plurality of bus drivers each of which drives a plurality of buses and outputs data, a phase control means for controlling a phase of each signal of the data respectively input to the plurality of bus drivers, A changed bit number detection block for detecting a different number of bits between the current data and the next data output by the plurality of bus drivers; and the phase to control the phase according to a detection result of the changed bit number detection block. An integrated circuit device comprising: a timing generation block for controlling a control unit. 9. A rewritable register, comprising: a changing bit number setting register in which a predetermined setting value is set, wherein the timing generation block is configured to determine that the different bit number is equal to or more than the predetermined setting value. 9. The integrated circuit device according to claim 8, wherein an instruction is given to control the phase so as to suppress simultaneous changes of the data signals. 10. A plurality of bus drivers for driving a plurality of buses to output data, a strobe signal driver for driving a strobe signal for taking in the output data, and wherein the plurality of bus drivers are connected to the data bus. And a change interval detecting block for detecting an interval between a timing at which the strobe signal driver outputs the strobe signal and a timing at which the strobe signal driver drives the strobe signal. A timing generation block for controlling the strobe signal driver to change according to the result. 11. A rewritable register, comprising a change interval setting register in which a predetermined set value is set, wherein the timing generation block detects that the detected interval is equal to or less than the predetermined set value. 11. The integrated circuit device according to claim 10, wherein said timing is changed. 12. A strobe signal timing setting register, which is a rewritable register, in which a predetermined setting value is set, wherein the timing generation block uses the strobe signal corresponding to the data according to the predetermined setting value. 11. The integrated circuit device according to claim 10, wherein an amount for changing the timing of the signal is determined. 13. A bus driver for controlling a slew rate for outputting data, a plurality of bus drivers for driving a plurality of buses to output the data, and a plurality of bus drivers for controlling the data. A change interval detection block for detecting an interval between an output timing and a timing at which the strobe signal driver outputs the strobe signal; and the plurality of slew rates are changed in accordance with a detection result of the change interval detection block. And a timing generating block for controlling the bus driver. 14. A rewritable register, comprising: a change interval setting register in which a predetermined set value is set, wherein the timing generation block detects that the detected interval is equal to or less than the predetermined set value. 14. The integrated circuit device according to claim 13, wherein the instruction is made to reduce the slew rate. 15. An output current control means for controlling an output current corresponding to data to be output, a plurality of bus drivers each driving a plurality of buses and outputting the data, and A change interval detection block for detecting an interval between a timing at which data is output and a timing at which the strobe signal driver outputs the strobe signal; and the output current is changed according to a detection result of the change interval detection block. An integrated circuit device comprising: a timing generation block for controlling the plurality of bus drivers. 16. A rewritable register, comprising: a change interval setting register in which a predetermined set value is set, wherein the timing generation block detects that the detected interval is equal to or less than the predetermined set value. 16. The integrated circuit device according to claim 15, wherein said output current control means for reducing said output current is controlled. 17. A plurality of bus drivers each of which drives a plurality of buses and outputs the data, a phase control means for controlling a phase of each signal of the data input to each of the plurality of bus drivers, A timing at which the plurality of bus drivers output the data, a variation interval detection block that detects an interval between the timing at which the strobe signal driver outputs the strobe signal, and a detection result of the variation interval detection block, A timing generation block for controlling the phase control means so as to control the phase. 18. A rewritable register, comprising: a change interval setting register in which a predetermined set value is set, wherein the timing generation block detects that the detected interval is equal to or smaller than the predetermined set value. 18. The integrated circuit device according to claim 17, wherein an instruction is given to control the phase so as to suppress simultaneous changes of the data signals. 19. The function of the timing generation block can be externally stopped.
9. The integrated circuit device according to any one of 8. 20. The function of the slew rate control means can be stopped externally.
Or an integrated circuit device according to item 13. 21. The integrated circuit device according to claim 6, wherein a function of said output current control means can be stopped from outside. 22. The function of the phase control means is as follows:
9. The method according to claim 8, wherein the stop can be performed externally.
8. The integrated circuit device according to 7. 23. A plurality of bus drivers for driving a plurality of buses to output data, a strobe signal driver for driving a strobe signal for capturing the output data, and an output of the plurality of bus drivers. A change bit number detection block for detecting a different bit number between the current data and the next data; a timing at which the plurality of bus drivers output the data; and a timing at which the strobe signal driver outputs the strobe signal. A change interval detection block for detecting an interval; and the strobe for changing a timing at which the strobe signal driver drives the strobe signal in accordance with a detection result of the change bit number detection block and a detection result of the change interval detection block. Timing generation block to control signal driver Integrated circuit device having a click. 24. The integrated circuit device according to claim 1, wherein the plurality of bus drivers each drive a plurality of buses to output data, and the strobe signal driver drives a strobe signal for capturing the output data. A change bit number detection block for detecting a different bit number between the current data and the next data output by the plurality of bus drivers; and a timing at which the strobe signal driver drives the strobe signal, the change bit number. A program for causing a computer to function as all or a part of a timing generation block that controls the strobe signal driver to change the strobe signal driver according to a detection result of a detection block. 25. The integrated circuit device according to claim 4, further comprising a slew rate control means for controlling a slew rate for outputting data, a plurality of bus drivers for driving a plurality of buses and outputting the data, respectively. A changed bit number detection block for detecting a different bit number between the current data and the next data output by the plurality of bus drivers; and changing the slew rate according to a detection result of the changed bit number detection block. A program for causing a computer to function as all or part of a timing generation block that controls the plurality of bus drivers. 26. The integrated circuit device according to claim 6, further comprising output current control means for controlling an output current corresponding to data to be output, and a plurality of buses each driving a plurality of buses to output the data. A driver, a changed bit number detection block for detecting a different bit number between the current data output by the plurality of bus drivers and the next data, and the output current according to a detection result of the changed bit number detection block. A program for causing a computer to function as all or part of a timing generation block that controls the plurality of bus drivers to be changed. 27. The integrated circuit device according to claim 8, wherein a plurality of bus drivers each of which drives a plurality of buses and outputs data, and a signal of each of the data signals respectively input to the plurality of bus drivers. Phase control means for controlling a phase, a changed bit number detection block for detecting a different bit number between the current data output by the plurality of bus drivers and the next data, and a detection result of the changed bit number detection block. And a program for causing a computer to function as all or part of a timing generation block that controls the phase control means so as to control the phase. 28. The integrated circuit device according to claim 10, wherein a plurality of bus drivers respectively drive a plurality of buses and output data, and a strobe signal driver which drives a strobe signal for capturing the output data. A change interval detection block that detects an interval between a timing at which the plurality of bus drivers output the data and a timing at which the strobe signal driver outputs the strobe signal; and the strobe signal driver drives the strobe signal. A program for causing a computer to function as all or a part of a timing generation block that controls the strobe signal driver so as to change the timing of the strobe signal driver according to the detection result of the change interval detection block. 29. The integrated circuit device according to claim 13, further comprising a slew rate control means for controlling a slew rate for outputting data, a plurality of bus drivers for driving a plurality of buses and outputting the data, respectively. A change interval detection block for detecting an interval between the timing at which the plurality of bus drivers output the data and the timing at which the strobe signal driver outputs the strobe signal; and And a program for causing a computer to function as all or part of a timing generation block that controls the plurality of bus drivers so as to change the slew rate. 30. The integrated circuit device according to claim 15, further comprising output current control means for controlling an output current corresponding to data to be output, and a plurality of buses each driving a plurality of buses to output the data. A change interval detection block that detects an interval between a timing at which the plurality of bus drivers output the data and a timing at which the strobe signal driver outputs the strobe signal; and a detection result of the change interval detection block. A program for causing a computer to function as all or part of a timing generation block that controls the plurality of bus drivers so as to change the output current accordingly. 31. The integrated circuit device according to claim 17, wherein a plurality of bus drivers each driving a plurality of buses to output the data, and each signal of the data input to the plurality of bus drivers, respectively. A phase control means for controlling a phase of the strobe signal; a change interval detection block for detecting an interval between a timing at which the plurality of bus drivers output the data and a timing at which the strobe signal driver outputs the strobe signal; A program for causing a computer to function as all or a part of a timing generation block that controls the phase control unit so as to control the phase according to a detection result of an interval detection block. 32. The integrated circuit device according to claim 23, wherein a plurality of bus drivers each drive a plurality of buses to output data, and a strobe signal driver drives a strobe signal for capturing the output data. A change bit number detection block for detecting a different bit number between the current data output by the plurality of bus drivers and the next data; a timing at which the plurality of bus drivers output the data; and the strobe signal driver A change interval detection block for detecting an interval between the timing at which the strobe signal is output and a timing at which the strobe signal driver drives the strobe signal. The strobe signal driver to change according to the result. Program for causing a computer to function as all or part of the timing generation block for controlling the bus.