JP2002299558A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

[PROBLEMS] To provide a semiconductor device having an MIM capacitor element with small variation in capacitance value and a large current leakage margin, and a method for manufacturing the same. SOLUTION: An upper electrode 17a and a capacitor dielectric 16 are provided.
a, the upper electrodes 17b to 17e having an area smaller than the area of the main capacitor element and the sub capacitor elements having the capacitor dielectrics 16b to 16e are electrically arranged in parallel with the lower electrode 15b as a common electrode. .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a MIM (Met).
The present invention relates to a semiconductor device equipped with an al-insulator-metal (capacitor) element and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, in order to improve the accuracy of a filter circuit and an integrating circuit built in an analog or analog / digital LSI such as an A / D converter and a D / A converter, a capacitor element having high accuracy and no voltage dependency has been developed. Is desired.

FIG. 5 is a cross-sectional view showing a manufacturing process of a semiconductor device on which a conventional MIM capacitor element is mounted, which is disclosed in Japanese Patent Application Laid-Open No. 2000-133708. In the figure, 1 is a gate electrode, 2 is a gate oxide film,
3 is a BPSG film, 4 is a first-layer metal wiring film, 41 is a first-layer metal wiring, 42 is a lower electrode, 5 is a silicon nitride film to be a capacitor insulating film, 51 is a capacitor dielectric, 6
Is an aluminum film, 61 is an upper electrode, 7 is a resist, 8
Is a PE-TEOS film, and 9 is a second aluminum film.
Layer metal wiring, 10 is a semiconductor substrate, 11 is a LOCOS oxide film, 12 is a plug buried in a contact hole, 13
Is a plug made of tungsten buried in the via hole.

As shown in FIG. 5A, first, an element is formed on a semiconductor substrate 10 by a gate electrode 1, a gate oxide film 2, and a LOCOS oxide film 11, buried with a BPSG film 3, and a plug 12 is provided. BPSG film 3 provided with plug 12
A first-layer metal wiring film 4, a silicon nitride film 5 having a thickness of about 20 nm, and an aluminum film 6 for a capacitor upper electrode are sequentially formed thereon by sputtering.

Next, as shown in FIG. 5B, the first metal wiring film 4, silicon nitride film 5, and capacitor upper electrode aluminum film 6 are patterned by dry etching. Lower electrode 42, capacitor dielectric 5
1. An upper electrode 61 and a first-layer metal wiring 41 are formed.

Next, as shown in FIG. 5C, the capacitor region is covered with a resist 7, and the aluminum film 6 for the upper electrode and the silicon nitride film 5 in the pattern other than the capacitor region are removed.

Next, as shown in FIG.
A PE-TEOS film 8 having a thickness of about 500 nm is formed, the formed PE-TEOS film 8 is polished by a CMP method to a thickness of about 500 nm, a via hole is formed on the upper electrode 61 by dry etching, and a plug 13 is formed in the via hole. And further forming an aluminum film, and then patterning the formed aluminum film to form the second-layer metal wiring 9.

[0008]

In the capacitance element mounted on the conventional semiconductor device described above, the capacitance value of the capacitor element varies due to the variation in the thickness of the silicon nitride film serving as the dielectric, and the desired performance can be obtained. There was no problem.

Further, since the creepage distance between the upper electrode and the lower electrode of the capacitor element is short, there is a problem that a margin for leakage of the capacitor element is small.

The present invention has been made to solve the above problems, and provides a semiconductor device having an MIM capacitor element having a small variation in capacitance value and a large current leakage margin, and a method of manufacturing the same. It is.

[0011]

According to a first aspect of the present invention, there is provided a semiconductor device having a capacitor element having a capacitor dielectric between surfaces of an upper electrode and a lower electrode, wherein the capacitor element is a main capacitor. An element and a plurality of sub-capacitor elements having an area smaller than the area of the main capacitor element. The main capacitor element and the plurality of sub-capacitor elements are electrically arranged in parallel and buried in the interlayer insulating film. Things.

In a second semiconductor device according to the present invention, in the first semiconductor device, the lower electrodes of the main capacitor element and the plurality of sub-capacitor elements are formed on an interlayer insulating film corresponding to the respective lower electrodes. The contact hole provided is formed in a concave shape, and a concave capacitor dielectric is formed on the lower electrode formed in each concave shape.

A third semiconductor device according to the present invention is a semiconductor device having a capacitor element having a capacitor dielectric between surfaces of an upper electrode and a lower electrode, wherein the diameter of the upper electrode is smaller than that of the capacitor dielectric. The diameter is adjusted to be smaller than the diameter of the capacitor dielectric according to the film thickness.

A first method of manufacturing a semiconductor device according to the present invention is the method of manufacturing a semiconductor device having a capacitor element having a capacitor dielectric between surfaces of an upper electrode and a lower electrode, the method being provided on a semiconductor substrate. Forming a first metal film on the insulating film, forming a capacitor dielectric film on the first metal film, and forming a second metal film on the capacitor dielectric film; Forming a film, etching the second metal film and the capacitor dielectric film to form a main capacitor element and a plurality of sub-capacitor elements having an area smaller than the area of the main capacitor element; Forming an inter-layer insulating film for embedding the main capacitor element and the sub-capacitor element, and connecting the upper electrode of the main capacitor element and the upper electrode of the sub-capacitor element to the inter-layer insulating film. Forming a contact hole to be formed, and providing a plug made of a metal filling the contact hole; forming a third-layer metal film on the interlayer insulating film and the plug; To form a third-layer metal wiring for electrically connecting the plugs.

According to a second method of manufacturing a semiconductor device according to the present invention, in the method of manufacturing a semiconductor device having a capacitor element having a capacitor dielectric between surfaces of an upper electrode and a lower electrode, the method is provided on a semiconductor substrate. Forming a first metal film on the insulating film, forming a capacitor dielectric film on the first metal film, and measuring the film thickness of the capacitor dielectric film; Forming a second metal film on the capacitor dielectric film, and changing the etching amount of the second metal film according to the thickness of the capacitor dielectric film to obtain isotropic dry etching. Forming the upper electrode, performing anisotropic dry etching of the capacitor dielectric film to form the capacitor dielectric, forming the capacitor element, an interlayer for embedding the formed capacitor element. Insulating film Forming a contact hole communicating with the upper electrode in the interlayer insulating film and providing a plug made of a metal filling the contact hole; and forming a third metal film on the interlayer insulating film and the plug. Forming a film, etching the third metal film,
A step of forming a third-layer metal wiring electrically connected to the upper electrode via the plug.

A third method of manufacturing a semiconductor device according to the present invention is the method of manufacturing a semiconductor device having a capacitor element having a capacitor dielectric between surfaces of an upper electrode and a lower electrode, the method being provided on a semiconductor substrate. Forming a first-layer metal film on the insulating film, etching the first-layer metal film to form a pad for electrically connecting to the lower electrode, Depositing a first interlayer insulating film to be filled, a first contact hole communicating with the pad, and a plurality of second contacts having an opening area smaller than the first contact hole in the first interlayer insulating film; Forming a first contact hole and a second contact hole;
Providing the lower electrode made of a concave metal contacting the inner wall of the contact hole, forming a concave capacitor dielectric on each of the lower electrodes, the capacitor dielectric and the first interlayer insulating film Forming a second metal film thereon; etching the second metal film to form an upper electrode in contact with the capacitor dielectric to form the capacitor element; Depositing a second interlayer insulating film that fills the element, forming a third contact hole in the second interlayer insulating film that communicates with the upper electrode, and plugging a metal plug that fills the third contact hole. Providing a step, forming a third-layer metal film on the second interlayer insulating film, etching the third-layer metal film, and connecting a third-layer wiring between the plugs Form Those having a step.

According to a fourth method of manufacturing a semiconductor device according to the present invention, in the method of manufacturing a semiconductor device having a capacitor element having a capacitor dielectric between surfaces of an upper electrode and a lower electrode, the semiconductor device is provided on a semiconductor substrate. Forming a first metal film on the insulating film, forming a capacitor dielectric film on the first metal film, and forming a second metal film on the capacitor dielectric film; Forming a film, etching the second metal film and the capacitor dielectric film to form a main capacitor element and a plurality of sub-capacitor elements having an area smaller than the area of the main capacitor element; Forming a first layer metal film by etching the first layer metal film and forming a lower electrode common to the main capacitor element and the slave capacitor element; The metal wiring and the top Depositing an inter-layer insulating film for embedding the main capacitor element and the sub-capacitor element, forming a first contact hole communicating with the first-layer metal wiring in the inter-layer insulating film; A second contact hole communicating with the upper electrode is formed, and a first plug made of a metal filling the inside of the first contact hole and a second plug made of a metal filling the inside of the second contact hole are provided. A third step on the interlayer insulating film, the first plug and the second plug,
Forming a third-layer metal film, etching the third-layer metal film, and connecting the third-layer metal wiring to the first-layer metal wiring through the first plug; Forming a third-layer metal wiring for electrically connecting the second metal wiring and the second plug.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a capacitor element having a capacitor dielectric between surfaces of an upper electrode and a lower electrode. Forming a first metal film on the insulating film, forming a capacitor dielectric film on the first metal film, and measuring the film thickness of the capacitor dielectric film; A step of forming a second metal film on the capacitor dielectric film, the amount of etching of the second metal film according to the thickness of the capacitor dielectric film by isotropic dry etching; By changing and etching to form the upper electrode, by anisotropic dry etching,
Forming the capacitor element by etching the capacitor dielectric film to form the capacitor element; etching the first metal film to form the first metal wiring; A step of shaping the lower electrode of the capacitor element, a step of depositing the first-layer metal wiring and an interlayer insulating film for embedding the capacitor element, and connecting the interlayer insulating film to the first-layer metal wiring. Forming a first contact hole and a second contact hole communicating with an upper electrode of the capacitor element;
Providing a first plug made of a metal filling the inside of the contact hole and a second plug made of a metal filling the inside of the second contact hole, wherein the first plug is formed on the interlayer insulating film, the first plug and the second plug. Forming a third-layer metal film, etching the third-layer metal film, and electrically connecting the third-layer metal film to the first-layer metal wiring via the first plug. A step of forming a third-layer wiring electrically connected to the lower electrode via a third-layer metal wiring and the second plug.

A sixth method of manufacturing a semiconductor device according to the present invention is the method of manufacturing a semiconductor device having a capacitor element having a capacitor dielectric between surfaces of an upper electrode and a lower electrode, the method being provided on a semiconductor substrate. Forming a first-layer metal film on the insulating film, etching the first-layer metal film to electrically connect the first-layer metal wiring and the lower electrode of the capacitor element; Forming a pad,
Depositing a first interlayer insulating film that fills the first layer of metal wiring and pads;
A first contact hole communicating with the metal wiring of the layer,
Forming a second contact hole communicating with the pad and a plurality of third contact holes having an opening area smaller than the opening area of the second contact hole, and forming a second contact hole made of metal filling the first contact hole; Providing a lower electrode of the capacitor element made of a concave metal in contact with the first plug and the inner wall of the second contact hole and the third contact hole, forming a concave capacitor dielectric on each of the lower electrodes Forming a second-layer metal film on the capacitor dielectric and the first interlayer insulating film; etching the second-layer metal film to form a second-layer metal wiring Forming an upper electrode in contact with the capacitor dielectric to form the capacitor element; forming a second layer of metal wiring and a second step of burying the capacitor element. Depositing an interlayer insulating film, the second
A fourth contact hole communicating with the second-layer metal wiring, and a fifth contact hole communicating with the upper electrode.
Forming a second plug made of a metal filling the fourth contact hole and a third plug made of a metal filling the fifth contact hole, the second interlayer insulating film; Forming a third-layer metal film on the second plug and the third plug; etching the third-layer metal film to form the second-layer metal film via the second plug; Forming a third-layer metal wiring electrically connected to the third metal wiring and a third-layer metal wiring electrically connecting the third plug.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. 1 and 2 show a first embodiment of a method for manufacturing a semiconductor device according to the present invention. FIG. 1 is a sectional view and FIG. 2 is a top view. In the figure, reference numeral 14 denotes an interlayer insulating film made of plasma TEOS or the like formed on a semiconductor substrate (on which elements are formed) not shown,
Denotes a first-layer metal film, 15a denotes a first-layer metal wiring, 1
5b is a lower electrode, 16 is a capacitor dielectric film made of a silicon nitride film, 16a to 16e are capacitor dielectrics, 1
7 is a second metal film, 17a to 17e are upper electrodes, 1
8 is an interlayer insulating film made of a plasma oxide film or the like, 19a and 19b are contact holes, 20a and 20b are plugs made of tungsten or the like, 21 is a third-layer metal film, 21a and 21b are third-layer metal wirings It is.

In this embodiment, as shown in FIG. 1F, the lower electrode 15b, the capacitor dielectric 16a
And a main capacitor element comprising upper electrode 17a, capacitor dielectrics 16b-16e and upper electrodes 17b-17
e, and a plurality of sub-capacitors having an area smaller than the area of the main capacitor element.
5b is electrically arranged in parallel with a common lower electrode.

Hereinafter, a method of manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS. First, as shown in FIG. 1A, a first-layer metal film 15, a capacitor dielectric film 16, and a second-layer metal film 17 are sequentially formed on an interlayer insulating film.

The first metal film 15 has a laminated structure.
50 nm thick TiN and 400 nm thick AlC
u, a 50 nm-thick TiN film is formed by a sputtering method. The capacitor dielectric film 16 is p-SiON having a film thickness of 50 nm, and is formed by a sputtering method. After the film formation, the film thickness is accurately measured, and the deviation from 50 nm is grasped. The second-layer metal film 17 has a laminated structure, in which AlCu having a thickness of 100 nm and TiN having a thickness of 50 nm are sequentially formed by a sputtering method.

Next, a photoresist film is formed on the second-layer metal film 17 and patterned, and using this patterned photoresist film as a mask, dry etching is performed as shown in FIG. To form upper electrodes 17a to 17e having the MIM structure and capacitor dielectrics 16a to 16e having the MIM structure, and then removing the photoresist.

In the dry etching of the second metal film 17, anisotropic etching is performed using a mixed gas obtained by adding CHF ₃ to Cl ₂ gas, and the capacitor dielectric film 1 is etched.
After stopping the etching on 6, the gas is switched to a mixed gas of CF ₄ and O ₂ to perform anisotropic etching of the capacitor dielectric film 16.

The upper electrodes 17a to 17e and the capacitor dielectrics 16a to 16e are composed of a main capacitor element having a large area of the upper electrode 17a and the capacitor dielectric 16a and a small area of the upper electrodes 17b to 17e and the capacitor dielectrics 16b to 16e. Is patterned into a slave capacitor element consisting of

Next, a photoresist film is formed on the first-layer metal film 17 and the upper electrodes 17a to 17e, patterned, and dry-etched by using the patterned photoresist film as a mask. As shown in (c), a first-layer metal wiring 15a and a lower electrode 15b common to the main capacitor element and the sub-capacitor element are formed, and then the photoresist is removed. Anisotropic etching is performed by dry etching using a mixed gas of Cl ₂ gas and BCl ₃ .

Next, as shown in FIG. 1D, an interlayer insulating film 18 is deposited by a plasma oxide film or the like, the interlayer insulating film 18 is planarized by CMP, and then the interlayer insulating film is formed by photolithography and dry etching. 18 shows a first-layer metal wiring 1
A contact hole 19a for connecting 5a to the third-layer metal wiring 21a, and a contact hole 19b for connecting the third-layer metal wiring 21b (see FIG. 1E) to the upper electrodes 17a to 17e. And are formed. Thereafter, W is deposited and CMP is performed to form contact holes 19a and 19b.
The plugs 20a and 20b are formed therein.

Next, as shown in FIG. 1E, a third-layer metal wiring film 21 is formed on the interlayer insulating film 18 and the plugs 20a and 20b, and dry-etched using a photoresist as a mask. Then, as shown in FIG. 1 (f), third-level metal wirings 21a and 21b are formed.

FIG. 2 is a top view of FIG. As shown in the figure, the upper electrodes 17b to 17e having a small area are provided.
Is connected to the third-layer metal wiring 21b via a plug 20b, and the large-area upper electrode 17a is connected to the third-layer metal wiring 21b via the plug 20a.

In FIG. 2, it is assumed that the capacitor dielectric film 16 needs to have a thickness of 50 nm and an upper electrode area of 100 μm ^{2 in} order to obtain a required capacitance.

The area of the large upper electrode is 90 μm.
m ² , the area of the small area upper electrodes 17 b to 17 e is 5
formed in the [mu] m ^2, when the film thickness of the capacitor dielectric film 16 is deposited at the target value as 50nm, as shown in FIG. 2 (b), a portion of the third layer metal wiring 21b Is cut by a laser blow or the like to obtain a small area upper electrode 17d.
And 17e are electrically separated from the large area upper electrode 17a.

When the thickness of the capacitor dielectric film 16 is 47.5 nm shifted from the target value by 5%, as shown in FIG. Wiring 2
Part 1b is cut by laser blowing or the like to electrically separate the small-area upper electrodes 17c, 17d, and 17e from the large-area upper electrode 17a.

According to the present embodiment, a main capacitor element having a large-area upper electrode 17a is connected to a sub-capacitor element having a plurality of small-area upper electrodes 17b to 17e via a third-layer metal wiring 21b. The capacitor capacitor composed of the upper electrodes 17b to 17e having a small area can be arbitrarily electrically disconnected so as to correct the variation in capacitance caused by the variation in the film thickness of the capacitor dielectric film 16 and to always obtain the desired value. A semiconductor device having a capacitor close to the capacitance of the semiconductor device can be obtained.

In this embodiment, a part of the third-layer metal wiring 21b is cut by laser blowing or the like to electrically separate the small-area upper electrodes 17b to 17e from the large-area upper electrode 17a. As described above, several types of masks for the third-layer metal wiring 21b are prepared, and the third-layer metal wiring 21b is formed only on the necessary small-area upper electrodes 17b to 17e. Electrode 17a
It is also possible to electrically connect the third-layer metal wiring 21b to only necessary ones of the upper electrodes 17b to 17e having a small area by preparing several kinds of masks for the contact holes 19b. Contact hole 1 connecting
9b may be formed.

Embodiment 2 FIG. 3 is a sectional view showing Embodiment 2 of the method for manufacturing a semiconductor device according to the present invention. In the figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts.

In this embodiment, as shown in FIG. 3A, the first-layer metal film 1 is formed on the interlayer insulating film 14.
5. A capacitor dielectric film 16 and a second metal film 17 are sequentially formed. After the capacitor dielectric film 16 is formed, its thickness is accurately measured.

The first metal film 15, the capacitor dielectric film 16, and the second metal film 17 are formed in the same manner as in the first embodiment with respect to the forming method, composition and structure.

Next, a photoresist film is formed on the second-layer metal film 17 and patterned, and as shown in FIG. 3B, dry etching is performed using the patterned photoresist film 30 as a mask. Thereby, the upper electrode 17a having the MIM structure and the capacitor dielectric 16a having the MIM structure are formed.

In the dry etching of the second metal film 17, isotropic etching is performed by using a mixed gas obtained by adding BCl ₃ gas to Cl ₂ gas, and the etching is stopped on the capacitor dielectric film 16. . At this time, according to the film thickness measured after the formation of the capacitor dielectric film 16, a considerable amount of the second metal film 17 is over-etched to adjust the diameter (area) of the upper electrode 17a. That is, when the film thickness of the capacitor dielectric film 16 varies to a large thickness, the amount of over-etching is reduced and the upper electrode 17 is removed.
When the diameter (area) of “a” is increased, and conversely, when the film thickness of the capacitor dielectric film 16 becomes thinner, the amount of over-etching is increased and the diameter (area) of the upper electrode 17a is reduced. Thereafter, anisotropic etching of the capacitor dielectric film 16 is performed by switching the etching gas to a mixed gas of CF ₄ and O ₂ , and the subsequent steps are the same as in the first embodiment to form a capacitor having the MIM structure. .

In the subsequent steps, the first layer wiring 1
5a and lower electrode 15b (FIG. 3 (c)), formation of interlayer insulating film 18, formation of contact holes 19a and 19b and plugs 20a and 20b (FIG. 3 (d)), third-layer metal film 3 (FIG. 3E) and the formation of third-layer metal wirings 21a and 21b (FIG. 3F) are described in the first embodiment.
Perform in the same manner as described above.

According to the present embodiment, the diameter (area) of the upper electrode 17a is made smaller than the diameter (area) of the capacitor dielectric 16a by over-etching according to the thickness of the capacitor dielectric film 16, thereby reducing the capacitance. Adjustment can reduce the variation in capacitance.

Since the diameter of the upper electrode 17a is smaller than the diameter of the capacitor dielectric 16a, the upper electrode 17a has a smaller diameter.
The creeping distance between the lower electrode 15a and the lower electrode 15b is increased, and the margin for current leakage can be increased.

Embodiment 3 FIG. In the present embodiment, as in the first embodiment, the capacitor element includes a main capacitor element and a plurality of sub-capacitor elements having an area smaller than the area of the main capacitor element. They are electrically arranged in parallel.

FIG. 4 is a sectional view showing Embodiment 3 of the method for manufacturing a semiconductor device according to the present invention. The same reference numerals as those in FIGS. 1 and 2 denote the same or corresponding parts. In the figure, 22 is a pad, 23 is a contact hole for forming an MIM structure, 24 is a lower electrode, 25 is a second layer metal wiring, 25a is a second layer metal wiring, 25b is an upper electrode, 26 Is an interlayer insulating film, 27a is a contact hole, 28a is a plug, and 29a and 29b are third-layer metal wirings.

In the present embodiment, first, FIG.
As shown in FIG. 4A, a first-layer metal film 15 is formed on the interlayer insulating film 14, and dry etching is performed using a photoresist as a mask, and as shown in FIG. A pad 22 for connecting to the first-layer metal wiring 15a and the lower electrode of the MIM structure is formed, and the photoresist is removed. In dry etching, Cl ₂ gas and BCl ₃
Anisotropic etching is performed using a gas mixture.

Next, as shown in FIG. 4C, an interlayer insulating film 18 is deposited by a plasma oxide film or the like, and the CMP interlayer insulating film 18 is flattened. Then, the interlayer insulating film is formed by photolithography and dry etching. A contact hole 19a for connecting the first-layer metal wiring 15a and a second-layer metal wiring 25a (see FIG. 4F) to 18 and a lower electrode 24 for contacting the pad 22 are formed. Contact hole 2
Then, W necessary to fill the contact hole 19a is deposited, and the interlayer insulating film 18 is formed by CMP.
Unnecessary W deposited on the upper surface is removed, and the plug 20a and the lower electrode 24 are formed. The lower electrode 24 is formed in a concave shape because the size of the contact hole 23 is sufficiently large with respect to the W deposited film thickness. In FIG. 4C, the pad 22
On top of contact hole 23, contact hole 2
A plurality of contact holes (not shown) having an opening area smaller than the opening area of No. 3 are formed in a direction perpendicular to the paper surface.

Next, as shown in FIG. 4D, a dielectric such as plasma TEOS is deposited, and an unnecessary plasma TEOS deposited on the interlayer insulating film 18 is removed by performing a CMP process to remove the capacitor. The dielectric 16a is formed.

Next, as shown in FIG. 4E, a second-layer metal film 25 is deposited, and a reflow process is performed.
The upper surface of the metal film 25 of the layer is flattened.

Next, a photoresist film is formed on the second-layer metal film 25, patterned, and dry-etched using the patterned photoresist film as a mask, as shown in FIG. As described above, the second-layer metal wiring 25a and the upper electrode 25b are formed.

Next, as shown in FIG. 4G, an interlayer insulating film 26 is deposited by a plasma oxide film or the like, the interlayer insulating film 26 is planarized by CMP, and then the second layer is formed by photolithography and dry etching. Contact hole 2 for connecting the third level metal wiring 29a to the third level metal wiring 25a
7a, a contact hole 27b for connecting the upper electrode 25b to the third-layer metal wiring 29b is formed, and then a W film is deposited and flattened by a CMP process to form a contact hole 27a, 27b. Plugs 28a, 28b
Then, a third-layer metal wiring film is formed on the interlayer insulating film 26, and dry etching is performed using the pattern of the photoresist film as a mask.
9a and 29b are formed, and the photoresist film is removed.

The metal wiring 29b is electrically connected to the plugs of the main capacitor element and the slave capacitor element. As in the first embodiment, by cutting a part of the metal wiring 29b, the main capacitor element is electrically connected. It is possible to adjust the capacitance by changing the number of slave capacitor elements that are connected in series.

[0053]

According to the first semiconductor device of the present invention, there is provided a semiconductor device having a capacitor element having a capacitor dielectric between surfaces of an upper electrode and a lower electrode.
The capacitor element includes a main capacitor element and a plurality of sub-capacitor elements having an area smaller than the area of the main capacitor element, and the main capacitor element and the plurality of sub-capacitor elements are electrically arranged in parallel with each other. Since it is buried in the insulating film, by connecting or disconnecting an arbitrary number of sub-capacitor elements to / from the main capacitor element, the capacitance can be adjusted and variation can be reduced.

According to the second semiconductor device of the present invention,
In the first semiconductor device, lower electrodes of the main capacitor element and the plurality of sub-capacitor elements are formed in concave shapes in contact holes provided in an interlayer insulating film corresponding to the respective lower electrodes. Since the concave capacitor dielectric is formed on the lower electrode formed in the shape, the number of masks used for etching in forming the capacitor element can be reduced.

According to the third semiconductor device of the present invention,
In a semiconductor device having a capacitor element having a capacitor dielectric between surfaces of an upper electrode and a lower electrode, the diameter of the upper electrode is adjusted to be smaller than the diameter of the capacitor dielectric according to the thickness of the capacitor dielectric. Therefore, the variation in capacitance can be reduced by adjusting the diameter of the upper electrode.

Further, since the creepage distance between the upper electrode and the lower electrode increases, the margin for current leakage increases.

According to the first method of manufacturing a semiconductor device according to the present invention, in a method of manufacturing a semiconductor device having a capacitor element having a capacitor dielectric between surfaces of an upper electrode and a lower electrode, First on the insulating film provided
A step of forming a first-layer metal film, a step of forming a capacitor dielectric film on the first-layer metal film, and a step of forming a second-layer metal film on the capacitor dielectric film Etching the second metal film and the capacitor dielectric film to form a main capacitor element and a plurality of sub-capacitor elements having an area smaller than the area of the main capacitor element; Depositing an inter-layer insulating film for embedding the main capacitor element and the sub-capacitor element, forming a contact hole in the inter-layer insulating film to communicate with each of the upper electrode of the main capacitor element and the upper electrode of the sub-capacitor element; Providing a plug made of a metal that fills the gap, a step of forming a third metal film on the interlayer insulating film and the plug, and etching the third metal film to form the plug. Since the method includes a step of forming a third-layer metal wiring for electrically connecting the capacitors, the capacitance is adjusted by connecting or disconnecting an arbitrary number of sub-capacitor elements to / from the main capacitor element. And
Variation can be reduced.

According to the second method of manufacturing a semiconductor device of the present invention, the step of forming the first metal film on the insulating film provided on the semiconductor substrate, the method of forming the first metal film Forming a capacitor dielectric film thereon, measuring the thickness of the capacitor dielectric film, forming a second metal film on the capacitor dielectric film, The amount of etching of the metal film is changed according to the thickness of the capacitor dielectric film, the upper electrode is formed by isotropic dry etching, and the anisotropic dry etching of the capacitor dielectric film is performed. Forming the capacitor dielectric, forming the capacitor element, depositing an interlayer insulating film burying the formed capacitor element, forming a contact hole in the interlayer insulating film communicating with the upper electrode; Fill the contact hole That provided a plug made of a metal step, and etching step, a third layer metal film for forming the third layer metal film on the interlayer insulating film and on the plug,
Since the method includes a step of forming a third-layer metal wiring electrically connected to the upper electrode via the plug, the diameter of the upper electrode is adjusted according to the thickness of the capacitor dielectric film. By doing so, variation in capacitance can be reduced.

Further, since the creepage distance between the upper electrode and the lower electrode increases, the margin for current leakage increases.

According to the third method of manufacturing a semiconductor device of the present invention, in the method of manufacturing a semiconductor device having a capacitor element having a capacitor dielectric between surfaces of an upper electrode and a lower electrode, First on the insulating film provided
A step of forming a metal film of a layer, a step of etching the metal film of the first layer to form a pad for electrically connecting to the lower electrode, and a first interlayer insulating filling the pad. Depositing a film, forming a first contact hole communicating with the pad and a plurality of second contact holes having an opening area smaller than the first contact hole in the first interlayer insulating film; Providing a lower electrode made of a concave metal in contact with the inner walls of the first contact hole and the second contact hole, forming a concave capacitor dielectric on each of the lower electrodes, Forming a second-layer metal film on the first interlayer insulating film; etching the second-layer metal film to form an upper electrode in contact with the capacitor dielectric; Forming a sita element, depositing a second interlayer insulating film filling the capacitor element, forming a third contact hole communicating with the upper electrode in the second interlayer insulating film, Providing a plug made of a metal filling the contact hole, forming a third metal film on the second interlayer insulating film, etching the third metal film, Is provided with a step of forming a third-layer wiring for connecting a plurality of sub-capacitor elements, and by connecting or disconnecting an arbitrary number of sub-capacitor elements to / from the main capacitor element, the capacitance is adjusted and the variation is reduced. be able to.

Further, it is possible to reduce the number of masks used for etching in forming a capacitor element.

According to the fourth method of manufacturing a semiconductor device according to the present invention, in the method of manufacturing a semiconductor device having a capacitor element having a capacitor dielectric between surfaces of an upper electrode and a lower electrode, First on the insulating film provided
A step of forming a first-layer metal film, a step of forming a capacitor dielectric film on the first-layer metal film, and a step of forming a second-layer metal film on the capacitor dielectric film Etching the second metal film and the capacitor dielectric film to form a main capacitor element and a plurality of sub-capacitor elements having an area smaller than the area of the main capacitor element; Forming a first-layer metal wiring and a lower electrode common to the main capacitor element and the sub-capacitor element by etching the first-layer metal film; Depositing an inter-layer insulating film for embedding the main capacitor element and the sub-capacitor element, the first inter-layer insulating film being connected to the first-layer metal wiring;
And a second contact hole communicating with the upper electrodes of the main capacitor element and the sub-capacitor element, and a first plug made of metal filling the first contact hole and the second plug. A step of providing a second plug made of a metal filling the inside of the contact hole; a step of forming a third-layer metal film on the interlayer insulating film, the first plug and the second plug; The metal film is etched to electrically connect the third layer metal wiring and the second plug electrically connected to the first layer metal wiring via the first plug. Since the method includes a step of forming a third-layer metal wiring,
By connecting or disconnecting an arbitrary number of sub-capacitor elements to or from the main capacitor element, the capacitance can be adjusted and variations can be reduced.

According to the fifth method of manufacturing a semiconductor device of the present invention, in the method of manufacturing a semiconductor device having a capacitor element having a capacitor dielectric between surfaces of an upper electrode and a lower electrode, First on the insulating film provided
Forming a metal film as a layer, forming a capacitor dielectric film on the metal film as the first layer, and measuring a film thickness of the capacitor dielectric film; A step of forming a second-layer metal film, and isotropically dry-etching the second-layer metal film by changing an etching amount according to a film thickness of the capacitor dielectric film; Forming an upper electrode, forming the capacitor dielectric by etching the capacitor dielectric film by anisotropic dry etching, forming the capacitor element, and etching the first metal film. The first
Forming a metal wiring of the layer, shaping the lower electrode of the capacitor element, depositing the metal wiring of the first layer and an interlayer insulating film for embedding the capacitor element, The first layer communicating with the first layer metal wiring
And a second contact hole communicating with the upper electrode of the capacitor element, and a first plug made of metal filling the first contact hole and filling the inside of the second contact hole. Providing a second plug made of metal, the interlayer insulating film,
Forming a third metal film on the first plug and the second plug, etching the third metal film,
A third-layer metal wiring electrically connected to the first-layer metal wiring via the first plug and the lower electrode through a space between the second plug and the second-layer plug. Third
Since the method includes the step of forming the wiring layer, the variation in capacitance can be reduced by adjusting the diameter of the upper electrode according to the thickness of the capacitor dielectric film.

Further, since the creeping distance between the upper electrode and the lower electrode is increased, the margin for current leakage is increased.

According to the sixth method of manufacturing a semiconductor device of the present invention, in the method of manufacturing a semiconductor device having a capacitor element having a capacitor dielectric between surfaces of an upper electrode and a lower electrode, First on the insulating film provided
Forming a metal film of the first layer, etching the metal film of the first layer to form a pad for electrically connecting to the first metal wiring and the lower electrode of the capacitor element, Depositing a first interlayer insulating film that fills the first-layer metal wiring and the pad; a first contact hole communicating with the first-layer metal wiring in the first interlayer insulating film; Forming a second contact hole communicating with the pad and a plurality of third contact holes having an opening area smaller than the opening area of the second contact hole, and forming a second contact hole made of metal filling the first contact hole; Providing a lower electrode of the capacitor element made of a concave metal in contact with the first plug and the inner wall of the second contact hole and the third contact hole, and forming a concave electrode on each of the lower electrodes Forming a capacitor dielectric,
A second layer is formed on the capacitor dielectric and the first interlayer insulating film.
Forming a metal film as a layer, etching the metal film as a second layer to form an upper electrode in contact with the metal wiring as a second layer and the capacitor dielectric, thereby forming the capacitor element. Depositing a second interlayer insulating film filling the second-layer metal wiring and the capacitor element;
A fourth contact hole communicating with the second-layer metal wiring and a fifth contact hole communicating with the upper electrode are formed in the second interlayer insulating film, and the fourth contact hole is formed. Providing a second plug made of a metal to be filled and a third plug made of a metal to fill the fifth contact hole; forming a third layer on the second interlayer insulating film, the second plug and the third plug; Forming the third metal film, etching the third metal film, and electrically connecting the third metal film to the second metal wiring through the second plug. Since the method includes a step of forming a third-layer metal wiring for electrically connecting the metal wiring and the third plug, any number of sub-capacitor elements can be connected to or disconnected from the main capacitor element. Adjust the volume by doing , It is possible to reduce the variation.

Further, the number of masks used for etching in forming the capacitor element can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view showing Embodiment 1 of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a plan view showing Embodiment 1 of the method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view showing Embodiment 2 of the method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a cross-sectional view showing Embodiment 3 of the method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view showing a semiconductor device on which a conventional capacitor element is mounted.

[Explanation of symbols]

14, 18, 26 interlayer insulating film, 15 first layer metal film, 15a first layer metal wiring, 15b, 24 lower electrode, 16 capacitor dielectric film, 16a to 16e capacitor dielectric, 17, 25th Second metal film, 17
a to 17e, 25b Upper electrode, 19a, 19b, 2
3, 27a contact holes, 20a, 20b, 28
a plug, 21 third layer metal film, 21a, 21b
Third-layer metal wiring, 22 pads, 25a Second-layer metal wiring, 29a, 29b Third-layer metal wiring,
30 Photoresist film.

Continued on the front page F-term (reference) 5F033 HH07 JJ19 KK07 KK09 KK33 PP15 QQ08 QQ09 QQ10 QQ11 QQ16 QQ21 QQ22 QQ23 QQ25 QQ37 QQ38 QQ48 QQ53 QQ75 RR04 RR06 RR08 SS04 SS08 SS15 XX00 AC10 AC33 AV03 AC03 AC18 AC33 EZ14 EZ15 EZ20

Claims (9)

[Claims] 1. A semiconductor device having a capacitor element having a capacitor dielectric between surfaces of an upper electrode and a lower electrode, wherein the capacitor element has a main capacitor element and a plurality of areas each having an area smaller than the area of the main capacitor element. A semiconductor device comprising a slave capacitor element, wherein the main capacitor element and a plurality of slave capacitor elements are electrically arranged in parallel and buried in an interlayer insulating film. 2. The lower electrodes of the main capacitor element and the plurality of sub-capacitor elements are formed in contact holes provided in the interlayer insulating film corresponding to the respective lower electrodes, and are formed in respective concave shapes. 2. The semiconductor device according to claim 1, wherein a concave capacitor dielectric is formed on the lower electrode. 3. A semiconductor device having a capacitor element having a capacitor dielectric between surfaces of an upper electrode and a lower electrode, wherein the diameter of the upper electrode is determined by the thickness of the capacitor dielectric. A semiconductor device characterized by being adjusted to be smaller than the diameter of the semiconductor device. 4. A method of manufacturing a semiconductor device having a capacitor element having a capacitor dielectric between surfaces of an upper electrode and a lower electrode, wherein a first metal film is formed on an insulating film provided on a semiconductor substrate. Forming a capacitor dielectric film on the first metal film; forming a second metal film on the capacitor dielectric film; forming the second metal film on the capacitor dielectric film; Forming a main capacitor element and a plurality of sub-capacitor elements having an area smaller than the area of the main capacitor element by etching the metal film and the capacitor dielectric film. Depositing an interlayer insulating film for embedding the device, forming a contact hole in the interlayer insulating film to communicate with each of the upper electrode of the main capacitor device and the upper electrode of the slave capacitor device; Providing a plug made of metal filling the tact hole; forming a third metal film on the interlayer insulating film and the plug; etching the third metal film to form a plug between the plugs Forming a third-layer metal wiring for electrically connecting the semiconductor device to the semiconductor device. 5. A method of manufacturing a semiconductor device having a capacitor element having a capacitor dielectric between surfaces of an upper electrode and a lower electrode, wherein the first metal film is formed on an insulating film provided on the semiconductor substrate. Forming a film, forming a capacitor dielectric film on the first metal film,
Measuring the thickness of the capacitor dielectric film; forming a second metal film on the capacitor dielectric film; and forming the second metal film on the capacitor dielectric film. The upper electrode is formed by isotropic dry etching, and the capacitor dielectric film is formed by anisotropic dry etching of the capacitor dielectric film. Forming an element, depositing an interlayer insulating film for burying the formed capacitor element, forming a contact hole communicating with the upper electrode in the interlayer insulating film, and inserting a plug made of metal filling the contact hole. Forming a third metal film on the interlayer insulating film and the plug; etching the third metal film to connect the upper electrode to the upper electrode through the plug; The method of manufacturing a semiconductor device characterized by comprising a step of forming a third layer of metal wires connected to. 6. A method of manufacturing a semiconductor device having a capacitor element having a capacitor dielectric between surfaces of an upper electrode and a lower electrode, wherein the first metal film is formed on an insulating film provided on the semiconductor substrate. A step of forming a film, a step of etching the first metal film to form a pad for electrically connecting to the lower electrode, and a step of depositing a first interlayer insulating film filling the pad. A first contact hole communicating with the pad and a plurality of second contact holes having an opening area smaller than the first contact hole are formed in the first interlayer insulating film; Providing the lower electrode made of a concave metal in contact with the inner wall of the second contact hole; forming a concave capacitor dielectric on each of the lower electrodes; A second layer is formed on the dielectric and the first interlayer insulating film.
Forming a metal film as a layer, etching the metal film as a second layer to form an upper electrode in contact with the capacitor dielectric, and forming the capacitor element, and filling the capacitor element. Depositing a third contact hole communicating with the upper electrode in the second interlayer insulating film, and providing a plug made of a metal filling the third contact hole; Forming a third-layer metal film on the second interlayer insulating film; etching the third-layer metal film to form a third-layer wiring connecting the plugs A method for manufacturing a semiconductor device, comprising: 7. A method of manufacturing a semiconductor device having a capacitor element having a capacitor dielectric between surfaces of an upper electrode and a lower electrode, wherein a first metal film is formed on an insulating film provided on a semiconductor substrate. Forming a capacitor dielectric film on the first metal film; forming a second metal film on the capacitor dielectric film; forming the second metal film on the capacitor dielectric film; Forming a main capacitor element and a plurality of sub-capacitor elements having an area smaller than the area of the main capacitor element by etching the metal film and the capacitor dielectric film; Forming a first-layer metal wiring and a lower electrode common to the main capacitor element and the sub-capacitor element by etching the film; the first-layer metal wiring, the main capacitor element and the sub-capacitor; element Depositing an interlayer insulating film that buries the first and second metal wirings in the interlayer insulating film, and a second contact hole that communicates with the upper electrodes of the main and slave capacitor elements. Forming a first plug made of a metal filling the inside of the first contact hole and a second plug made of a metal filling the inside of the second contact hole. Forming a third-layer metal film on the first plug and the second plug; etching the third-layer metal film to form the first-layer metal film via the first plug; A step of forming a third-layer metal wiring electrically connected to the metal wiring and a third-layer metal wiring electrically connecting between the second plugs. Manufacturing method. 8. A method of manufacturing a semiconductor device having a capacitor element having a capacitor dielectric between surfaces of an upper electrode and a lower electrode, wherein the first metal film is formed on an insulating film provided on the semiconductor substrate. Forming a film, forming a capacitor dielectric film on the first metal film,
Measuring the film thickness of the capacitor dielectric film, forming a second metal film on the capacitor dielectric film, and forming the second metal film by isotropic dry etching. The upper electrode is formed by changing the etching amount according to the film thickness of the capacitor dielectric film, and the capacitor dielectric film is formed by etching the capacitor dielectric film by anisotropic dry etching. Forming the first-layer metal film by etching the first-layer metal film, and shaping the lower electrode of the capacitor element; Depositing a metal wiring and an interlayer insulating film for burying the capacitor element; a first contact hole communicating with the first-layer metal wiring in the interlayer insulating film; A second contact hole communicating with the upper electrode is formed, and a first plug made of a metal filling the inside of the first contact hole and a second plug made of a metal filling the inside of the second contact hole are provided. Forming a third-layer metal film on the interlayer insulating film, the first plug, and the second plug; etching the third-layer metal film to form the first plug; A third-layer metal wiring electrically connected to the first-layer metal wiring via the first layer and a third-layer wiring electrically connected to the lower electrode via the second plug; Forming a semiconductor device. 9. A method for manufacturing a semiconductor device having a capacitor element having a capacitor dielectric between surfaces of an upper electrode and a lower electrode, wherein the first metal film is formed on an insulating film provided on the semiconductor substrate. A step of forming a film; a step of etching the first-layer metal film to form a pad for electrically connecting to the first-layer metal wiring and a lower electrode of the capacitor element; Depositing a first interlayer insulating film filling the metal wiring and the pad, the first interlayer insulating film having a first contact hole communicating with the first-layer metal wiring, and a second contact hole communicating with the pad. A first plug made of a metal that fills the first contact hole with a second contact hole and a plurality of third contact holes having an opening area smaller than the opening area of the second contact hole; Providing a lower electrode of the capacitor element made of a concave metal contacting the inner wall of the second contact hole and the third contact hole; forming a concave capacitor dielectric on each of the lower electrodes; A second layer is formed on the capacitor dielectric and the first interlayer insulating film.
Forming a second-layer metal film; etching the second-layer metal film to form an upper electrode in contact with the second-layer metal wiring and the capacitor dielectric to form the capacitor element; Depositing a second interlayer insulating film filling the second-layer metal wiring and the capacitor element; and forming a fourth interlayer insulating film communicating with the second-layer metal wiring on the second interlayer insulating film. A second plug made of a metal filling the fourth contact hole and a third plug made of a metal filling the fifth contact hole, forming a contact hole and a fifth contact hole communicating with the upper electrode; Providing a third metal film on the second interlayer insulating film, the second plug and the third plug, etching the third metal film, Through the second plug Forming a third-layer metal wiring electrically connected to the second-layer metal wiring and a third-layer metal wiring electrically connecting the third plug. A method for manufacturing a semiconductor device, comprising: