JP2002299468A - Display unit drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate withdrawal of a constant current from an organic EL element. SOLUTION: A display unit drive circuit comprises a cathode driver, and an N-channel MOS transistor connected to a ground voltage and formed of a high with stand MOS transistor. The MOS transistor has a source/drain layer formed adjacent to a gate electrode 38E, and a P-type body layer 32 formed to reduce a low on resistance to constitute a channel under the electrode 38E.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device driving circuit for driving a display device, for example, having an anode driver and a cathode driver.

[0002]

2. Description of the Related Art Here, as the display device, an LCD is used.
Display, LED display, organic EL (electroluminescence) display, inorganic EL display, PDP (plasma display), FED
There are various flat panel displays such as (field emission display).

[0003] Hereinafter, as an example, for example, an anode driver and a cathode driver are provided, and a constant current is supplied to the organic EL element.
An organic EL display driving driver for causing the organic EL element to emit light will be described. Since the EL element emits light by itself, it does not require a backlight necessary for a liquid crystal display device.
Since it has many advantages such as no limitation on the viewing angle, application to a next-generation display device is expected. In particular, it is known that an organic EL element is capable of high luminance, and is superior to an inorganic EL element in terms of high efficiency, high response characteristics, and multicoloring.

The driver for driving the organic EL display includes, for example, a logic N-channel MOS transistor and a P-channel MOS transistor, a high breakdown voltage N-channel MOS transistor and a P-channel MOS transistor, and a low on-resistance. , A high breakdown voltage N-channel MOS transistor and a P-channel MOS transistor, an N-channel MOS transistor for a level shifter, and the like.

Here, as a MOS transistor of a high withstand voltage system with a reduced on-resistance, for example, a D (double diffu
sed) A MOS transistor or the like is used. The above D
The MOS transistor structure means that a diffusion layer formed on the surface side of a semiconductor substrate is diffused with impurities of different conductivity types to form a new diffusion layer, and a difference in lateral diffusion between these diffusion layers is determined by an effective channel. The element is used as a long element, and a short channel is formed, so that the element is suitable for low on-resistance.

FIG. 14 is a cross-sectional view for explaining a conventional DMOS transistor.
A MOS transistor structure is illustrated. Note that P
Although the description of the structure of the channel type DMOS transistor is omitted, it is well known that the structure is the same except that the conductivity type is different.

In FIG. 14, reference numeral 51 denotes one conductivity type, for example, P
Reference numeral 52 denotes an N-type well (NW), in which a P-type body layer (P-Sub) is provided.
B) 53 is formed, an N + type diffusion layer 54 is formed in the P type body layer 53, and an N + type diffusion layer 55 is formed in the N type well 52. A gate electrode 57 is formed on the substrate surface via first and second gate oxide films 56 and 59, and a channel 58 is formed in a surface region of the P-type body layer 53 immediately below the gate electrode 57. I have.

Then, the N + type diffusion layer 54 is used as a source diffusion layer, the N + type diffusion layer 55 is used as a drain diffusion layer, and the N type well 52 under the LOCOS oxide film constituting the second gate oxide film 59 is used as a drift layer. And Also, 60,
Reference numeral 61 denotes a source electrode and a drain electrode, respectively.
Is a P + type diffusion layer for taking the potential of the P type body layer 53, and 63 is an interlayer insulating film.

In the above DMOS transistor, N
By diffusion-forming the mold well 52, the concentration on the surface of the N-type well 52 is increased, so that the current can easily flow on the surface of the N-type well 52 and the breakdown voltage can be increased.

[0010]

Here, the above DMOS
In the case of forming a transistor, a high-temperature heat treatment for forming the P-type body layer 53 is required after the formation of the gate electrode, so that the concentration profile in a low-voltage operation miniaturized device such as the 0.35 μm rule is disordered. For this reason, at present, after the gate electrode of the DMOS transistor is formed and the high-temperature heat treatment for forming the P-type body layer is completed, the miniaturized MOS transistor is started to be manufactured, which causes a problem that the manufacturing process becomes longer.

Further, when a plurality of types of transistor structures are required as in the above-described display device driving circuit, there is a demand to improve the workability by sharing the steps as much as possible.

In addition, the gate length of the DMOS transistor is basically determined by the diffusion coefficient and the diffusion start position of different ion species, so that there is a problem that the degree of freedom in designing the gate length is small.

[0013]

Accordingly, a display device driving circuit according to the present invention has an anode driving circuit and a cathode driving circuit,
In driving a display device, the anode driving circuit is a signal processing circuit that applies predetermined signal processing to data input from an input terminal, a level shifter circuit for converting an output of the signal processing circuit to a high voltage, A constant current control circuit for outputting a constant current according to the output of the level shifter circuit, a one-conductivity type MOS transistor through which a constant current flows according to the output of the constant current control circuit, and a source or a drain of the MOS transistor are connected. One end of the display device is connected via the external output terminal, the cathode driver circuit,
An external output terminal to which the other end of the display device is connected, and a reverse conductive type MOS transistor whose source or drain is connected to the external output terminal, at least the reverse conductive type MOS transistor, Having a source / drain layer adjacent to the gate electrode,
It is characterized by comprising a MOS transistor in which a semiconductor layer constituting a channel is formed below the gate electrode.

In addition, a low-concentration layer of the same conductivity type as the source / drain layer is formed below the gate electrode of the reverse conductivity type MOS transistor so as to be continuous with the source / drain layer and to be in contact with the semiconductor layer. MO that is formed
It is characterized by comprising an S transistor.

Further, a low-concentration layer of the same conductivity type as the source / drain layer is formed below the gate electrode of the reverse conductivity type MOS transistor so as to be continuous with the source / drain layer and to be in contact with the semiconductor layer. The semiconductor device is characterized by comprising a MOS transistor which is formed to be shallowly extended on the semiconductor surface layer.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a display device driving circuit according to the present invention will be described below with reference to the drawings. Note that, in the present embodiment, an organic E
An L display is illustrated.

FIG. 11 is a schematic circuit diagram of an organic EL display driving circuit according to this embodiment.

This organic EL display driving circuit comprises an anode driver circuit 2 for supplying a constant current to the anode of the organic EL element 1 and a cathode driver circuit 3 for drawing a constant current from the cathode of the organic EL element 1. Have been. In this figure, only one bit is shown for simplicity. However, in an actual system, a plurality of organic EL elements 1 are arranged in a matrix, and the anode driver circuit 2 and the cathode driver circuit 3 are correspondingly arranged. It has a multi-bit configuration.

The anode driver circuit 2 includes a signal processing circuit 5 for applying predetermined signal processing to data input from the input terminal Vin, a level shifter circuit 6 for converting the output of the signal processing circuit 5 to a high voltage, A constant current control circuit 7 for outputting a constant current according to the output of the level shifter circuit 6, a P-channel MOS transistor 8 through which a constant current flows according to the output of the constant current control circuit 7, and the P-channel MOS transistor 8 Is connected to the external output terminal 9 to which the drain of the organic E is connected.
The anode of L element 1 is connected.

The cathode driver circuit 3 includes the organic E
An external output terminal 11 to which the cathode of the L element 1 is connected;
It comprises an N-channel MOS transistor 10 whose drain is connected to the external output terminal 11, and a switch circuit 12 for controlling ON / OFF of the N-channel MOS transistor 10.

FIG. 12 is a detailed circuit diagram of the organic EL display driving circuit according to the present embodiment. In this circuit diagram, the configuration of the constant current control circuit 7 is specifically shown. 1
Reference numeral 3 denotes a differential amplifier to which the reference voltage Vref is applied to one input and the output of the control transistor 14 is fed back to the other input. Reference numeral 15 denotes an external terminal to which a reference resistor 16 is connected. Reference numeral 17 denotes an analog switch (MOS transistors 18, 19) to which the output of the signal processing circuit 5 is applied.
). The current flowing through the MOS transistor 8 is controlled according to the on / off state of the analog switch 17.

Next, the operation of the organic EL display driving circuit having the above configuration will be described.

A reference voltage Vref is applied to a differential amplifier 13, and a constant current i1 (Vref / Rref) flows through a resistor 16 having a resistance value Iref based on the reference voltage Vref. Then, the MOS controlled by the output of the differential amplifier 13
A constant current i1 flows through the transistor 14.

When an H level (5 V) signal is applied to the input of the analog switch 17, the N-channel MOS transistor 19 of the analog switch 17 is turned on. Then, the control MOS transistor 14 and the MOS transistor 8 form a current mirror, and the MOS transistor 8 is proportional (or equal) to the constant current i1.
The constant current i2 flows, and the organic EL element 1 is turned on by the output current.

On the other hand, when an L-level (0 V) signal is applied to the input of the analog switch 17, the P-channel MOS transistor 18 of the analog switch 17 is turned on. Then, the H level is applied to the gate of the MOS transistor 8 to turn it off. Since no current flows through the organic EL element 1, the light is turned off.

Here, the organic EL element 1 has a high forward ON voltage of 5 V to 10 V, unlike ordinary LEDs. In the circuit described above, the forward ON voltage of the organic EL element 1 is 9
V, when the ON voltage of the MOS transistor 10 of the cathode driver 3 is 1 V, the driving power supply voltage V
cc2 requires 10V + source / drain voltage (Vds) to secure the constant current characteristics of the MOS transistor 8 (for example, Vcc2 = 15V).

Therefore, the MOS transistors 8, 1
0 needs to be constituted by a high breakdown voltage type MOS transistor (for example, a structure composed of an offset type low concentration source / drain layer and a high concentration source / drain layer).

On the other hand, the power supply voltage Vcc1 of the signal processing circuit 5 is a low voltage (for example, 5 V), and its output is level-converted by the level shifter circuit 6 and applied to the constant current control circuit 7.

As described above, in the drive circuit, in the anode driver 2, the signal processing circuit 5 has a 5V power supply (Vcc1) and the drive circuit has a 15V power supply (Vcc2).
As described above, the two power supply system is employed, and the MOS transistors 8, 10 and each of the transistors constituting the constant current control circuit 7 need to have a high breakdown voltage structure.

In particular, as shown in FIG.
Are arranged, and the anode driver circuit 2 and the cathode driver circuit 3 also have a multi-bit configuration correspondingly.

Therefore, a plurality of organic Es arranged in one row
N-channel MOS transistor 1 for drawing a constant current from each anode of L elements 1A, 1B, 1C, 1D
For 0, there was a demand for a configuration with a lower on-resistance.

Therefore, a feature of the present invention is that the N-channel MOS transistor 10 connected to the ground voltage for extracting a constant current flowing through the organic EL element 1 is a high-breakdown-voltage MOS transistor having a lower on-resistance. That is, Thereby, the constant current from each organic EL element 1 is more easily extracted.

Incidentally, the P-channel type MOS transistor may be constituted by a high breakdown voltage MOS transistor whose on-resistance is reduced similarly to the N-channel type MOS transistor.

Hereinafter, a semiconductor device in which various MOS transistors constituting the organic EL display driving driver are mounted will be described.

The driver for driving the organic EL display has a logic system (for example, 3) from the left side of FIG.
V) N-channel MOS transistors and P-channel MOS transistors, for level shifters (for example, 30
V) N-channel MOS transistor, high breakdown voltage (for example, 30 V) N-channel MOS transistor, FIG.
A high breakdown voltage (eg, 30 V) N-channel MOS transistor whose on-resistance is reduced from the left side of 0 (b),
It is composed of a high-breakdown-voltage (for example, 30 V) P-channel MOS transistor and a high-breakdown-voltage (for example, 30 V) P-channel MOS transistor whose on-resistance is reduced.

For convenience of explanation, the high breakdown voltage MOS
Transistor and high breakdown voltage MO with low on-resistance
In order to differentiate the S transistor from the S transistor, in the following description, a high withstand voltage MOS transistor having a reduced on-resistance is replaced by an SLED (Slit channel by counter doping with exten).
ded shallow drain) MOS transistor.

In a semiconductor device in which various MOS transistors constituting such an organic EL display driving driver are mixedly mounted, as shown in FIG. 10, the high breakdown voltage P-channel MOS transistor and the low on-resistance are reduced. The N-type well 23 in which the illustrated high-withstand-voltage P-channel SLEDMOS transistor is formed is a high step portion, and the P-type well 22 in which other various MOS transistors are formed is in the low step portion. In other words, a fine logic (eg, 3V) N-channel MOS
The configuration is such that the transistor and the P-channel MOS transistor are arranged at the lower part of the step.

Hereinafter, a method for manufacturing the semiconductor device will be described.

First, in FIG. 1, in order to define regions for forming various MOS transistors, for example, P
A P-type well (P-sub) is formed in a P-type semiconductor substrate (P-sub) 21.
W) 22 and an N-type well (NW) 23 are formed by using the LOCOS method. That is, although the illustrated description is omitted, a pad oxide film and a silicon nitride film are formed on the N-type well formation region of the substrate 21 and, for example, boron ions are At an acceleration voltage of 80 KeV, ions are implanted under an implantation condition of 8 × 10 ¹² / cm ² to form an ion-implanted layer. Then, using the silicon nitride film as a mask,
The LOCOS film is formed by performing field oxidation by the S method. At this time, the boron ions implanted below the LOCOS film formation region are diffused into the substrate to form a P-type layer.

Next, the pad oxide film and the silicon nitride
After removing the film, the substrate surface is exposed using the LOCOS film as a mask.
Phosphorus ions are applied to the surface at an acceleration voltage of about 80 KeV,
10 ¹²/ Cm^TwoImplantation under the same implantation conditions
Form a layer. Then, after removing the LOCOS film
Then, each impurity ion implanted into the substrate is thermally diffused.
By forming a P-type well and an N-type well, FIG.
A P-type well 2 formed in the substrate 21 as shown in FIG.
2 is located at the low step, and the N-type well 23 is at the high step.
Be placed.

In FIG. 2, an element isolation film 24 of about 500 nm is formed by the LOCOS method in order to isolate an element for each MOS transistor, and a high-level element of about 80 nm is formed on an active region other than the element isolation film 24. A thick gate oxide film 25 for withstand voltage is formed by thermal oxidation.

Subsequently, the first low-concentration N-type and P-type source / drain layers (hereinafter referred to as L
These are referred to as an N layer 26 and an LP layer 27. ) Is formed. That is, first, the substrate surface in a state of covering the region other than the LN layer forming region with a resist film (not shown), for example, phosphorus ions at an acceleration voltage of approximately 120 KeV, an implantation condition of 8 × 10 ¹² / cm ² Thus, the LN layer 26 is formed. Thereafter, for example, boron ions are applied to the surface layer of the substrate at an acceleration voltage of about 120 KeV at a rate of 8.5 × 10 ¹² / cm while the area other than the area where the LP layer is formed is covered with the resist film (PR).
^The LP layer 27 is formed by ion implantation under the implantation conditions of ² .
Note that, in practice, a subsequent annealing step (for example, 1100
After 2 hours in a N ₂ atmosphere at a temperature of ₂ ° C., the ion-implanted ion species are thermally diffused to form the LN layer 26 and the LP layer 27.

Subsequently, in FIG. 3, second resistive films are used as masks between the LN layers 26 and the LP layers 27 in which the P-channel type and N-channel type SLEDMOS transistor forming regions are formed, respectively. And P-type source / drain layers (hereinafter, SLN layer 28 and SLP
Called layer 29. ) Is formed. That is, first, for example, phosphorus ions are applied to the surface of the substrate in a state of covering the region other than the SLN layer formation region with a resist film (not shown) for about 120 Ke.
At an acceleration voltage of V, ions are implanted under an implantation condition of 1.5 × 10 ¹² / cm ² to form an SLN layer 28 connected to the LN layer 26. Then, for example, boron difluoride ion ( ⁴⁹ BF ₂ ⁺ ) is applied to the surface of the substrate in a state where the region other than the region where the SLP layer is to be formed is covered with the resist film (PR).
At an acceleration voltage of V, ions are implanted under an implantation condition of 2.5 × 10 ¹² / cm ² to form an SLP layer 29 connected to the LP layer 27. The impurity concentration of the LN layer 26 and the SLN layer 28 or the impurity concentration of the LP layer 27 and the SLP layer 29 is as follows.
They are set so that they are almost the same or one of them is higher.

Further, in FIG. 4, the resist film is masked.
High-concentration N-type and P-type source / drain layers
Below, they are referred to as an N + layer 30 and a P + layer 31. ) Is formed. Immediately
First, a resist film (not shown) other than on the N + layer forming region
In the state of covering the area of the substrate, for example, phosphorus ions
At an acceleration voltage of about 80 KeV and 2 × 10¹⁵/ Cm ^Two
The N + layer 30 is formed by ion implantation under the implantation conditions described above. So
After that, the resist film (PR) is used to cover areas other than the P + layer formation area.
With the area covered, for example, boron difluoride
The ions were accelerated to about 2 × 10¹⁵
/ Cm^TwoP + layer 31 by ion implantation under the following implantation conditions
I do.

Next, referring to FIG. 5, a resist film having an opening diameter smaller than the mask opening diameter (see FIG. 3) for forming the SLN layer 28 and the SLP layer 29 is used as a mask to connect the SLN connected to the LN layer 26. The central part of the layer 28 and the LP
By injecting impurities of the opposite conductivity type into the central portion of the SLP layer 29 connected to the layer 27, respectively,
Then, a P-type body layer 32 and an N-type body layer 33 that divide the SLP layer 29 are formed. That is, first, for example, boron difluoride ions are applied to the surface of the substrate in a state in which the resist film (not shown) covers an area other than the P-type layer forming area, for example, about 120 nm.
The P-type body layer 32 is formed by ion implantation at an acceleration voltage of KeV under the conditions of 5 × 10 ¹² / cm ² . afterwards,
With the resist film (PR) covering the area other than the N-type layer forming area, for example, about 1
Ion implantation is performed at an acceleration voltage of 90 KeV under an implantation condition of 5 × 10 ¹² / cm ² to form an N-type body layer 33. still,
The order of the operation steps related to the ion implantation step shown in FIGS. 3 to 5 can be appropriately changed.
Channels are formed in the surface layers of the 2 and N-type body layers 33.

Further, in FIG. 6, a second P-type well (SPW) 34 and a second P-type well (SPW) 34 are formed in the substrate (P-type well 22) in the miniaturized N-channel type and P-channel type MOS transistor formation region for the normal breakdown voltage. N-type well (SNW) 35
To form

That is, the normal breakdown voltage N-channel MOS
A resist (not shown) having an opening on the transistor formation region
In the P-type well 22, for example,
Ion at an accelerating voltage of about 190 KeV and 1.5
× 10¹³/ Cm^TwoAfter the ion implantation under the first implantation condition of
With the acceleration voltage of about 50 KeV,
2.6 × 10¹²/ Cm^TwoImplantation under the second implantation condition
Thus, a second P-type well 34 is formed. In addition,
On P-channel MOS transistor formation region for normal withstand voltage
Using a resist film (PR) having an opening in the mask as a mask,
For example, about 380 K of phosphorus ions are
1.5 × 10 at eV acceleration voltage¹³/ Cm ^TwoInjection conditions
To form a second N-type well 35.
In addition, when there is no high acceleration voltage generator of about 380 KeV
In the case of divalent phosphorus ions, about 190 KeV
1.5 × 10 at pressure¹³/ Cm^TwoImplantation under the same implantation conditions
Double charging method may be used. Then, add phosphorus ions
4.0 × 10 at an acceleration voltage of about 140 KeV¹²/ C
m^TwoThe ion implantation is performed under the implantation conditions described above.

Next, after removing the gate oxide film 25 on the N-channel type and P-channel type MOS transistor formation regions for normal breakdown voltage and on the N-channel type MOS transistor formation region for level shifters, as shown in FIG. To
A gate oxide film having a desired thickness is newly formed on this region.

That is, first, the entire surface is about 14 nm for the N-channel type MOS transistor for the level shifter (about 7 nm at this stage, but the film thickness increases when forming a gate oxide film for normal withstand voltage described later). .)
Is formed by thermal oxidation. continue,
After removing the gate oxide film 36 of the level shifter N-channel type MOS transistor formed on the N-type and P-channel type MOS transistor formation regions for normal withstand voltage, a thin gate oxide film for normal withstand voltage is formed in this region. 37 (about 7 nm) is formed by thermal oxidation.

Subsequently, as shown in FIG.
A polysilicon film having a thickness of about 0 nm is formed, the POCl ₃ is thermally diffused into the polysilicon film using a thermal diffusion source to make the polysilicon conductive, and then a tungsten silicide film having a thickness of about 100 nm is formed on the polysilicon film. A gate electrode 38A, 38B, 38C, 38D, 38E, 38F, 3 for each MOS transistor is formed by laminating an SiO ₂ film and patterning using a resist film (not shown).
8G is formed. The SiO ₂ film functions as a hard mask during patterning.

Subsequently, in FIG. 9, low-concentration source / drain layers are formed for the normal breakdown voltage N-channel and P-channel MOS transistors.

That is, first, an N-channel type M for normal withstand voltage is used.
Low concentration source / drain layer formation area for OS transistor
Masks a resist film (not shown) that covers areas other than the area above
Then, for example, the phosphorous ion is accelerated by about 20 KeV.
By pressure, 6.2 × 10¹³/ Cm ^TwoImplantation under the same implantation conditions
To form a low concentration N- type source / drain layer 39.
You. Also, a P-channel MOS transistor for normal withstand voltage
Area other than on the low concentration source / drain layer formation area
Using a resist film (PR) covering the mask as a mask, for example,
Acceleration voltage of about 20 KeV for boron difluoride ion
And 2 × 10¹³/ Cm^TwoIon implantation under the implantation conditions of
A low concentration P- type source / drain layer 40 is formed.

Further, in FIG. 10, the gate electrodes 38A, 38B, 38C, 38D, 38E, 38
F, T of about 250 nm to cover 38G
An EOS film 41 is formed by an LPCVD method, and the TEOS film 41 is anisotropically etched using a resist film (PR) having an opening on the N-type and P-channel type MOS transistor formation regions for normal breakdown voltage as a mask. .
As a result, as shown in FIG.
A, side wall spacer films 41 on both side walls of 38B
A is formed, and the TEOS film 41 remains in a region covered with the resist film (PR).

Then, the gate electrode 38A, the sidewall spacer film 41A, and the gate electrode 38B
Using the sidewall spacer film 41A as a mask, a high-concentration source / drain layer is formed for the normal breakdown voltage N-channel and P-channel MOS transistors.

That is, by using a resist film (not shown) covering a region other than the region where the high-concentration source / drain layer is formed for an N-channel MOS transistor for normal breakdown voltage as a mask, for example, arsenic ions are accelerated at about 100 KeV. Then, ion implantation is performed under an implantation condition of 5 × 10 ¹⁵ / cm ² ,
A high concentration N + type source / drain layer 42 is formed. Also, using a resist film (not shown) covering a region other than the region for forming the high-concentration source / drain layer for the normally-breakdown-voltage P-channel MOS transistor as a mask, for example, boron difluoride ion is accelerated at an acceleration voltage of about 40 KeV. , 2 ×
Ion implantation is performed under an implantation condition of 10 ¹⁵ / cm ² to form a high concentration P + type source / drain layer 43.

Hereinafter, although illustration is omitted, the entire surface is made of a TEOS film, a BPSG film, etc.
After forming an interlayer insulating film of about the same degree, a metal wiring layer is formed to be connected to each of the high-concentration source / drain layers 30, 31, 42, and 43 to form the organic EL display driving driver. N-channel MOS transistor and P-channel MOS transistor for breakdown voltage, N-channel MOS transistor for level shifter, N-channel MOS transistor and P-channel MOS transistor for high breakdown voltage, high breakdown voltage with reduced on-resistance N-channel SLEDMOS transistor and P-channel SLEDMOS transistor are completed (see FIG. 10).

When an organic EL display drive circuit is formed using the transistors configured as described above, the transistors are arranged as follows.

That is, the signal processing circuit 5 comprises an N-channel MOS transistor and a P-channel MOS transistor for the normal breakdown voltage, and a level shifter circuit 6
Is composed of an N-channel type MOS transistor for the level shifter, the constant current control circuit 7 is composed of an N-channel type MOS transistor and a P-channel type MOS transistor for high withstand voltage, and the MOS transistor 8 of the anode driver 2 is turned on low. P-channel type SLED with resistance
It is composed of MOS transistors and the MO of the cathode driver 3
The S-transistor 10 is formed of an N-channel SLEDMOS transistor for high withstand voltage with a reduced on-resistance. The P-channel MOS transistor 8 is, for example, a high breakdown voltage P-channel type MOS composed of an offset type low concentration source / drain layer and a high concentration source / drain layer.
An S transistor may be used.

As described above, in the present invention, at least the cathode driver 3 is constituted, and the N-channel type MOS transistor 8 connected to the ground voltage is replaced with a high withstand voltage MOS transistor (SLEDMOS transistor) with a lower on-resistance. , Each organic E arranged in one row
Extraction of the constant current from the L element 1 becomes easier. In particular, the SLEDMOS transistor of the present invention
It is effective to employ the MOS transistor for extracting a current from an element through which a large current flows, such as the organic EL element 1.

Further, in the structure of the present invention, in the N-type MOS transistor and the P-channel MOS transistor for high withstand voltage in which the on-resistance is reduced, the P-type body layer 32 or the N-type body layer 33 is connected to the gate electrode. 38
E, formed only under 38G, so that P
Junction capacitance can be reduced as compared with the case where a high-concentration source layer is wrapped in a mold body layer or an N-type body layer.

Further, in the above structure, since the P-type body layer 32 or the N-type body layer 33 is formed by ion implantation, miniaturization becomes possible as compared with a conventional diffusion-formed one.

Further, according to the above-mentioned manufacturing method, when forming a DMOS transistor as in the conventional method, a high-temperature heat treatment after forming a gate electrode for forming a body layer is not required, so that it can be combined with a miniaturization process. Will be possible.

Further, in a conventional channel forming method by thermal diffusion of impurity ions as in a DMOS transistor,
Although the channel length is uniquely determined, in the method of manufacturing a high-breakdown-voltage MOS transistor with a reduced on-resistance according to the present invention, the P-type body layer 32 or the N-type Since it is formed through an implantation process, various settings can be made, and the degree of freedom in designing the gate length is increased as compared with the conventional method.

The body layer is preferably formed by an ion implantation method, but other steps can be changed as appropriate, such as a gas phase or diffusion from a solid phase.

Further, when a high breakdown voltage MOS transistor is formed as in the conventional method, a high-temperature heat treatment after forming the gate electrode for forming the body layer is not required, so that it can be mixed with a miniaturization process. A driver for driving various display devices (for example, the driver for driving the EL display) and a controller can be integrated into one chip.

[0066]

According to the present invention, a cathode drive circuit is constituted, and a MOS transistor for drawing a constant current from a display device is constituted by a high breakdown voltage MOS transistor having a lower on-resistance. The constant current from the display device is more easily extracted.

In the above MOS transistor, the semiconductor layer is formed only under the gate electrode.
Junction capacitance can be reduced as compared with a structure in which a semiconductor layer surrounds a high concentration source layer like a structure.

Further, since the semiconductor layer is formed by ion implantation, miniaturization is possible as compared with the conventional diffusion-formed one.

Further, since high-temperature heat treatment after forming a gate electrode for forming a semiconductor layer is not required, it is possible to carry out mixed mounting with a miniaturization process.

Although the channel length is uniquely determined in the channel forming method based on the thermal diffusion of impurity ions as in the conventional DMOS transistor, the present invention employs the ion implantation step for the semiconductor layer as described above. Since it is formed after passing through, various settings can be made, and the degree of freedom in designing the gate length is increased as compared with the conventional method.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 6 is a sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 7 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 8 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 9 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 10 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 11 is a schematic circuit diagram showing a display device driving circuit according to one embodiment of the present invention.

FIG. 12 is a detailed circuit diagram showing a display device driving circuit according to one embodiment of the present invention.

FIG. 13 is a detailed circuit diagram showing a display device driving circuit according to one embodiment of the present invention.

FIG. 14 is a sectional view showing a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Organic EL element 1A Organic EL element 1B Organic EL element 1C Organic EL element 1D Organic EL element 2 Anode driver 3 Cathode driver 5 Signal processing circuit 6 Level shifter circuit 7 Constant current control circuit 8 P channel type MOS transistor 10 N channel type MOS transistor 13 Differential amplifier

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification FI FI Theme Court ゛ (Reference) H04N 5/70 H01L 29/78 301H 27/08 321B (72) Inventor Takanori Kubota Sakata Oizumi-cho, Ouraku-gun, Gunma Prefecture 1-1-1 1-1 Sanyo LSI Design System Software Co., Ltd. F-term (reference) 5C058 AA12 BA01 BA35 5C094 AA05 AA25 BA03 BA29 CA19 EA04 EA07 FB14 5F048 AA01 AA05 AB10 AC01 AC03 BA19 BB16 BC06 BC07 BD04 BE03 DA25 5F140 BB BB13 BD05 BE03 BE07 BE14 BF04 BF11 BF18 BG08 BG12 BG31 BG39 BH15 BH17 BH30 BK02 BK13 CB01 CB08 CC01 CC03 CC07 5G435 AA17 BB05 CC09 EE34 EE40 EE41 HH13

Claims (3)

[Claims] An anode drive circuit and a cathode drive circuit,
In a display device driving circuit for driving a display device, the cathode driving circuit includes at least an external output terminal connected to an end of the display device, and a MOS transistor whose source or drain is connected to the external output terminal. Wherein at least the MOS transistor comprises a MOS transistor having a source / drain layer adjacent to a gate electrode and a semiconductor layer constituting a channel formed below the gate electrode. Device drive circuit. 2. A low concentration layer of the same conductivity type as the source / drain layer is formed below the gate electrode so as to be continuous with the source / drain layer and to be in contact with the semiconductor layer below the gate electrode. 2. The display device drive circuit according to claim 1, wherein the display device drive circuit is configured by a MOS transistor. 3. A low-concentration layer of the same conductivity type as the source / drain layer connected to the source / drain layer below the gate electrode of the MOS transistor below the gate electrode so as to be in contact with the semiconductor layer. 2. The display device drive circuit according to claim 1, wherein the display device drive circuit is configured by a MOS transistor formed to be shallowly expanded.