JP2002289833A - Electronic circuit - Google Patents

Abstract

(57) Abstract: A voltage gain is increased without limiting an operating temperature of a single-electron transistor logic circuit to a low temperature region. Further, a multi-value storage circuit is realized with a simple configuration. SOLUTION: A drain electrode D of a single electron transistor 1 is provided.
Is connected to the source electrode of the field effect transistor 21 so that the source-drain voltage V _{ds of} the single-electron transistor 1 becomes low enough to maintain the Coulomb blockade state irrespective of the voltage V _out of the output terminal 9. keep. Moreover, a large voltage gain is obtained by suppressing the negative feedback effect on the potential of the single electron island 5 from the output terminal 9. Further, a multi-valued storage circuit is realized by short-circuiting the input terminal 8 and the output terminal 9 to form a storage node.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic circuit formed using single electron transistors.

[0002]

2. Description of the Related Art A single-electron transistor controls the potential of a small conductive island called a single-electron island sandwiched between two tunnel junctions via a gate capacitor.
This transistor controls the current between the source and the drain by controlling the on / off state of the Coulomb blockade state (the state in which the tunneling of electrons is prohibited due to the large charging energy of the island).

FIG. 11 is an equivalent circuit diagram of a general single-electron transistor. The single-electron transistor 1 has a structure in which tunnel junctions 3 and 2 are provided between each of the source electrode S and the drain electrode D and the single-electron island 5, and the gate electrode G is capacitively coupled to the single-electron island 5. . FIG. 12 shows a current I flowing between the source and the drain of the single-electron transistor 1.
FIG. 4 is a characteristic diagram showing the dependence of _{d on} the gate-source voltage V _gs . When the gate-source voltage V _gs is swept in a state where the minute voltage V _ds is applied between the source electrode S and the drain electrode D, the value of the drain current I _d periodically increases and decreases as shown in FIG. . Hereinafter, the principle will be described.

A single electron island 5 is sandwiched between tunnel junctions 2 and 3.
Because one electron enters the single-electron island 5
Energy level corresponding to energy increase is created
(Hereafter, all energy levels are for electrons
). Gate-source voltage V _gsChange the game
Due to the capacitive coupling between the electrode G and the single electron island 5,
The energy level goes up and down while maintaining a certain gap.
Source-drain voltage V_dsIs less than this gap
If both the source and drain conduct within the gap,
When an effective level enters, the current I_dFlow
Will not be in Coulomb blockade state. Meanwhile, the source
One of the levels of single-electron island 5 is between
When entering, between source and drain via the level of single electron island 5
Current I_dFlows.

Therefore, at a certain gate-source voltage V _gs , the number of electrons in the single-electron island 5 is stabilized at n (n is an integer) due to the effect of the blockade, and no current _Id flows. When the voltage V _gs increases, the blockade is broken, and another electron can be increased. When the gate-source voltage V _gs enters the latter region, the number of electrons in the single electron island 5 can take both values of n and n + 1.
By entering the individual island 5 and then exiting (the number of electrons in the island 5 reciprocates between n and n + 1), the current _Id flows. Therefore, when the gate-source voltage V _gs is changed, the source-drain current I _d oscillates. Since the single-electron transistor 1 operates at a low voltage and a small current, the power consumption is extremely small, and the element area is extremely small. .

An example of a conventional logic circuit application of the single-electron transistor 1 is disclosed in IBM J. Res. Develop. Vol. 32, p. 144.1988 (KKL
ikharev). FIG. 13 is a circuit diagram showing a configuration of a resistance load type inverter using the single electron transistor 1. The drain electrode D of the single-electron transistor 1 is connected to the power supply terminal 106 via the load resistor 119, and the source electrode S is connected to the ground terminal 107. Further, the input terminal 108 is connected to the gate electrode G and the source electrode S
The output terminal 109 is connected to a connection point between the output terminal 109 and the load resistor 119. This circuit configuration is obtained by simply replacing a conventionally used field effect transistor or bipolar transistor with a single-electron transistor 1, and can realize the same function as a conventional inverter under the following conditions.

That is, the source of the single-electron transistor 1
・ Drain voltage V_dsBut e / C_{to tal}Place smaller than
In this case, a Coulomb blockade state appears and the source
Non-conduction is established between the rains. Where e is the elementary charge
Yes, C_totalIs the total capacity of the single-electron transistor 1
The capacitance C of the capacitor 4_g, Source electrode S and drain
Capacitance C of tunnel junction 3 and 2 of electrode D_s, C_dSum of
It is. Therefore, Coulomb blockade state appears
Power supply voltage V_ddTo e / C_totalSmaller
Need to be The drain of the single-electron transistor 1
Current I_dIs the gate-source voltage as shown in FIG.
V_gsIncreases or decreases periodically with respect to
For use as an inverter, the drain current I_dBut
The gate-source voltage V is monotonically increasing._gsSand
Input voltage V_inNeed to be set.

An example of a conventional storage circuit application of the single-electron transistor 1 can be found in Japanese Patent Application Laid-Open No. 7-86614. FIG. 14 is a circuit diagram showing a main configuration of a storage circuit using the single-electron transistor 1. This storage circuit is shown in FIG.
3 is configured by cross-connecting two inverters, and binary information can be statically held.

[0009]

SUMMARY OF THE INVENTION Single electron transistor 1
The capacitance C of the tunnel junction 2 of the drain electrode D
_dThe drain through the single electron island 5
Voltage gain (absolute
Value) is C_g/ C_dIs limited to Where voltage gain and
Changes the amplitude of the drain voltage (output voltage) to the gate voltage (input
Force voltage). Generally in logic circuits
Has a voltage gain of 1 so that the signal can propagate to the next and subsequent stages.
Need to take bigger. Attenuation of voltage during signal propagation
Considering design margins, etc., voltage gain
The larger the better. To do this, as shown in FIG.
In a simple single-electron transistor logic circuit, C_gIncrease
Or C_dThere is no choice but to reduce. C_dIs
This is the capacity of the tunnel junction 2 and it is difficult to reduce it.
Therefore, C_gWill be increased.

On the other hand, the single-electron transistor 1 can operate.
The temperature T is given by: k is Boltzmann's constant.^Two/ 2 / C_total> KT must be satisfied. Therefore, single electron transformer
In order for the transistor 1 to operate at high temperatures, a single electron transistor
Total capacity C of the data 1_totalNeeds to be set small. I
Scarecrow, C_totalIs C_gVoltage gain
C _gWhen C is increased, C_totalIs bigger
Operating temperature T is limited to the low temperature range.
There was a problem.

The storage circuit using single-electron transistors shown in FIG. 14 can statically hold only binary information. When configuring a multi-valued static memory circuit of three or more values using the single-electron transistor 1,
As in the case of using a bipolar transistor or a MOS transistor, there is a problem that a large number of elements are required.

The present invention has been made to solve such a problem, and an object of the present invention is to increase the voltage gain without limiting the operating temperature T of a logic circuit using single-electron transistors to a low temperature region. Is to do. Another object is to realize a multi-value storage circuit with a simple configuration.

[0013]

In order to achieve the above object, an electronic circuit according to the present invention is provided with a tunnel junction between each of a source electrode and a drain electrode and a single electron island and a gate electrode. It has a single electron transistor capacitively coupled to a single electron island and first to third terminals, and controls a current flowing between the first terminal and the second terminal by a signal supplied to the third terminal. A three-terminal element; and a load element for flowing a current smaller than the maximum value and smaller than the maximum value of the current flowing between the source electrode and the drain electrode of the single-electron transistor. 1, the gate electrode of the single-electron transistor is connected to the input terminal, the second terminal of the three-terminal element and one end of the load element are connected to the output terminal, and the other end of the load element is connected to the power supply terminal. Then, the source electrode of the single-electron transistor is connected to the ground terminal, and the voltage of the first terminal of the three-terminal element is equal to or less than the value obtained by dividing the elementary charge by the total capacity of the single-electron transistor. The voltage of the third terminal is set.

In the single-electron transistor, when the Coulomb blockade state is developed and turned off, a sufficient current does not flow between the first terminal and the second terminal of the three-terminal element, and the voltage of the output terminal becomes It becomes almost equal to the voltage of the power supply terminal. On the other hand, when the Coulomb blockade state does not appear and turns on, a sufficient current flows between the first terminal and the second terminal of the three-terminal element, and the voltage of the output terminal becomes the first terminal of the three-terminal element. It is almost equal to the voltage of the terminal. Therefore, the difference between the voltage of the power supply terminal and the voltage of the first terminal of the three-terminal element becomes the output amplitude. Even if the voltage at the power supply terminal is increased to increase the output amplitude, the drain voltage of the single-electron transistor is fixed to a value equal to or less than the value obtained by dividing the elementary charge by the total capacity of the single-electron transistor. For this reason, the voltage gain determined by the ratio between the output amplitude and the input amplitude is not limited to C _g / C _d by the negative feedback effect on the potential of the single electron island. Here, C _g is the capacitance of the gate capacitor, and C _d is the capacitance of the tunnel junction of the drain electrode.

Here, the three-terminal element is a field-effect transistor, the first terminal of the three-terminal element is a source electrode, the second terminal is a drain electrode, and the third terminal is a gate electrode. The gate electrode may be connected to a bias voltage terminal for applying a voltage higher than the voltage of the source electrode by a voltage for turning on the field effect transistor. In particular, the field effect transistor may be of a depletion type, and the bias voltage terminal connected to the gate electrode of the field effect transistor may be a ground terminal. In this case, there is no need to provide a separate bias voltage terminal.

The load element may be a constant current source. The constant current source has a high internal resistance and can output a wide voltage range from near zero to the voltage of the power supply terminal, so that the output amplitude and the voltage gain can be increased. Further, the load element may be a depletion-type field-effect transistor in which the gate electrode and the source electrode are short-circuited to one end and the drain electrode is the other end. Since the depletion type field effect transistor operates as a pseudo constant current source, the voltage gain and the like can be increased as in the case of using the constant current source.

Further, the input terminal and the output terminal may be short-circuited to form a storage node. The circuit current I flowing from the power supply terminal to the ground terminal via the load element, the three-terminal element, and the single-electron transistor periodically increases and decreases with respect to the storage node voltage V. The intersection of the load curve of the load element and the periodically increasing / decreasing IV characteristic becomes a stable point, and functions as a multi-value storage circuit. Further, a switch for switching connection / disconnection between the bit line and the storage node by a voltage applied to the word line may be further provided. A multi-level memory cell is composed of the switch and the function as the multi-level storage circuit. The switch may be a field-effect transistor in which one source / drain electrode is connected to a bit line, the other source / drain electrode is connected to a storage node, and the gate electrode is connected to a word line.

[0018]

Next, an embodiment of an electronic circuit according to the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a circuit diagram showing a configuration of a single-electron transistor logic circuit according to a first embodiment of the present invention. This single-electron transistor logic circuit includes a single-electron transistor 1 having the same configuration as that shown in FIG.
And a load element 10. The drain electrode D of the single electron transistor 1 is a field effect transistor 21
And the drain electrode (second terminal) of the field-effect transistor 21 is connected to one end of the load element 10. Field effect transistor 2
A bias voltage terminal 22 for applying a constant voltage _Vgg is connected to one gate electrode (third terminal), and the load element 10
The power supply terminal for applying the voltage _Vdd is connected to the other end of the power supply, and the ground terminal is connected to the source electrode S of the single-electron transistor 1. The input terminal 8 is connected to the gate G of the single-electron transistor 1, and the output terminal 9 is connected to a connection point between the drain electrode of the field-effect transistor 21 and the load element 10.

Turning on the field effect transistor 21
Threshold voltage V_thThen, the field effect transistor 21
Source voltage is V_gg-V_thBecomes Field effect transistors
Gate voltage V_ggIs constant and the field-effect
The source voltage of the transistor 21 is the drain voltage (output terminal
Voltage V_out) Is hardly affected.
Pressure is V_gg-V_thIs almost fixed. Single electron transistor
1 is the source of the field effect transistor 21
Voltage V_gg-V_thAnd the saw of single-electron transistor 1
Since the source voltage is zero, the source
-Drain voltage V_dsAlso V_gg-V_thIs almost fixed to
You. Therefore, V_gg-V_thIs e / C_{tota l}Becomes
By setting as described above, the single-electron transistor 1
Can maintain the Coulomb blockade state
You.

FIG. 2 is a circuit diagram showing a configuration of a single-electron transistor logic circuit when a constant current source is used as the load element 10. FIG. 3 is a characteristic diagram of the logic circuit shown in FIG. 2A shows the I _d -V _gs characteristics of the single-electron transistor 1, and FIG. 2B shows the input / output characteristics (V _out -V _in characteristics) of the logic circuit shown in FIG. It is. Drain current I of single electron transistor 1
_d periodically increases and decreases as shown in FIG. FIG.
Current I ₀ of the constant current source 11 shown in is smaller than the maximum value of the single-electron transistor 1 drain current I _d, is set to the minimum value is greater than value. In FIG. 3A, the current I ₀
It is set to an intermediate value between the maximum value and the minimum value of the drain current I _d is.

In FIG. 3A, a single electron transistor
1 gate-source voltage V_gs(= Input terminal voltage V_in)
Is V₁If smaller, the drain of single electron transistor 1
Current I_dIs the current I of the constant current source 11₀Less than
For this reason, as shown in FIG.
Drain voltage (= output terminal voltage V_out) Is the power terminal
Pressure V_ddIs almost equal to At this time, a single electron transistor
Source-drain voltage V_dsIs the output terminal voltage V
_out= V_ddIs almost unaffected by_gg-V
_th(<E / C_total), So the drain current
I_dState (Coulomb blockade state) is maintained
Is done.

In FIG. 3A, V _gs (=
When V _in ) is larger than V ₁ , I _d can be larger than I ₀ , so that the drain voltage (= V _out ) of the field-effect transistor 21 is equal to the source voltage V _gg −V as shown in FIG. _It is almost equal to _th . Accordingly, the output terminal voltage V _out before and after the V ₁ was switched from high level to low level. In FIG. 3A, V _gs (= V _in )
When There greater than V _2, as shown in FIG. 3 (b), again the drain voltage of the field effect transistor 21 (=
V _out ) becomes substantially equal to the power supply terminal voltage V _dd . Accordingly, the output terminal voltage V _out before and after the V ₂ is switched from the low level to the high level.

Thereafter, this is repeated, and V ₃ ,..., V ₁₁
, The output terminal voltage V _out switches from a high level to a low level, and before and after V ₄ ,..., V ₁₂ , the output terminal voltage V _out switches from a low level to a high level.
Therefore, the logic circuit shown in FIG.
By utilizing between zero and V ₂ as _in, functions as an inverter binary. For a multi-valued R value input, a predetermined input level is set to zero level or (R−
1) Functions as a kind of literal gate that outputs a level.

In this logic circuit, as described above, even when the output terminal voltage _Vout is at a high level equal to the power supply terminal voltage _Vdd , the source-drain voltage _Vds of the single-electron transistor 1 is substantially equal to _Vgg- V. _th remains less state (Coulomb blockade state) of the drain current I _d is maintained. Therefore, the power supply terminal voltage _Vdd can be increased, and the output amplitude, which is the difference between the high-level voltage _Vdd and the low-level voltage _Vgg - _Vth , can be increased.

Even if the power supply terminal voltage _Vdd is increased in order to increase the output amplitude, the single-electron transistor 1
Is substantially fixed at V _gg −V _th . Therefore, the voltage gain determined by the ratio between the output amplitude and the input amplitude is C _g due to the negative feedback effect on the potential of the single electron island 5.
It is not limited to / _Cd . Therefore, even if the capacitance C _g of the gate capacitor 4 is kept small, the voltage gain can be increased, so that the voltage gain can be increased without limiting the operating temperature T of the logic circuit to a low temperature region.

The logic circuit shown in FIG. 2 uses a constant current source 11 as the load element 10. Since the constant current source 11 has a high internal resistance and can output a wide voltage range from near zero to the power supply terminal voltage _Vdd , the output amplitude and the voltage gain can be increased. However, the same function can be realized by using other types of load elements 10 such as a resistance load, for example, as long as the current / voltage characteristics increase monotonously.

In the logic circuits shown in FIGS. 1 and 2,
Although the field effect transistor 21 is used to fix the drain voltage of the single-electron transistor 1, the reciprocal of the transconductance is different from the tunnel junction 2 of the single-electron transistor 1.
3, the output resistance of the second terminal connected to the load element 10 is sufficiently larger than the resistance of the tunnel junctions 2 and 3 of the single-electron transistor 1, and the third terminal serving as an input terminal. As long as the leak current of the second terminal in the off state and the leak current of the second terminal in the off state are sufficiently smaller than the drain current of the single-electron transistor 1 in the on state, another type of three-terminal element may be used. Here, the three-terminal element is an element that controls a current flowing between the first terminal and the second terminal by a signal given to the third terminal. For example, a bipolar transistor can be used. is there.

In the logic circuit shown in FIGS. 1 and 2,
The source electrode S of the single-electron transistor 1 is connected to the ground terminal 7, which means that the source voltage of the single-electron transistor 1 is used as a reference for the voltage level of the logic circuit. Therefore, in this sense, the ground terminal 7
Need not be at zero potential.

(Second Embodiment) FIG. 4 is a circuit diagram showing a configuration of a single-electron transistor logic circuit according to a second embodiment of the present invention. In this figure, the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals. In this single-electron transistor logic circuit, in order to fix the drain voltage of the single-electron transistor 1, a depletion type, that is, a threshold voltage V _th
Is used, and the gate electrode of the field effect transistor 23 is connected to the ground terminal 7.
To zero potential.

In this case, the source of the field effect transistor 23 is
Source voltage is the threshold voltage V_thIs almost fixed to the absolute value of. single
The drain voltage of the electron transistor 1 is a field effect transistor.
The source voltage (the threshold voltage V_thThe absolute value of
The source voltage of the single-electron transistor 1 is zero
From the source-drain voltage V of the single-electron transistor 1
_dsAlso the threshold voltage V_thIs almost fixed to the absolute value of. Single electron
Transistor 1 can maintain Coulomb blockade state
As shown, the threshold voltage V_thIs the absolute value of e / C_{to tal}Less than
Is set to the value of Thus, the depletion type
When the field effect transistor 23 is used, a field effect transistor
It is only necessary to ground the gate electrode of the
Ias voltage V_ggIt is not necessary to supply
The configuration can be simplified.

In the logic circuit shown in FIG. 4, the depletion type field effect transistor 1 is used as the load element 10.
2 is used. The field effect transistor 12 is connected to the drain electrode and the output terminal 9 of the field effect transistor 23 by short-circuiting the gate electrode and the source electrode, and the drain electrode is connected to the power supply terminal 6. This allows
Since the field effect transistor 12 operates as a pseudo constant current source having a high internal resistance, the output amplitude and the voltage gain can be increased. By using the depletion type field effect transistors 12 and 23 in this manner, a logic circuit can be configured with two types of elements and three elements. Therefore, the manufacturing process of the logic circuit can be simplified, and the area occupied by the logic circuit can be reduced.

(Third Embodiment) FIG. 5 is a circuit diagram showing a configuration of a multilevel storage circuit according to a third embodiment of the present invention. In this figure, the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals. In this multi-value storage circuit, the input terminal 8 and the output terminal 9 of the single-electron transistor logic circuit shown in FIGS. The drain voltage of the single-electron transistor 1 is equal to that of the field-effect transistor 2
1, the IV characteristic of the multi-valued storage circuit is substantially equal to the I _d -V _gs characteristic of the single-electron transistor 1 with the drain voltage fixed, and the circuit current I Periodically increases or decreases with respect to the storage node voltage V. When a load element 10 whose load curve intersects the IV characteristic is connected, the IV which periodically increases and decreases
A number of stable points occur corresponding to the characteristics.

FIG. 6 is a diagram showing an IV characteristic between a circuit current and a storage node voltage of the multilevel storage circuit shown in FIG.
The broken load curve represents the characteristic of the constant current source 11 of the current I ₀ used as the load element 10. The points P ₁ , P ₂ ,... Where the broken load curve intersects the solid line IV characteristic
・, P ₆ is the stable point. The point where the slope of the IV characteristic intersects at a negative portion is not realized because it is unstable. In the logic circuit shown in FIGS. 1 and 2, the output amplitude which is the voltage amplitude of the output terminal 9 can be increased. Therefore, in the multi-level storage circuit shown in FIG. voltage to correspond to a stable point voltage of P ₁ to P _6, and it is possible to hold the voltage of their stable point statically. As described above, by utilizing the characteristic characteristic of the single-electron transistor 1 that the drain current I _d periodically increases and decreases with respect to the gate-source voltage V _gs , it is possible to realize a multi-value storage circuit with a simple configuration. Can be.

(Fourth Embodiment) FIG. 7 is a circuit diagram showing a configuration of a multilevel storage circuit according to a fourth embodiment of the present invention. In this figure, the same parts as those in FIG. 4 are denoted by the same reference numerals. In this multi-value storage circuit, the input terminal 8 and the output terminal 9 of the single-electron transistor logic circuit shown in FIG. Similar to the logic circuit shown in FIG. 4, the supply of the bias voltage V _gg is not necessary, and the logic circuit can be configured with a small number of types and a small number of elements. FIG. 8 is a diagram showing an IV characteristic between a circuit current and a storage node voltage of the multi-level storage circuit shown in FIG. The broken load curve represents the characteristic of the depletion-type field effect transistor 12 used as the load element 10 with the gate electrode and the source electrode short-circuited. Since the load curve deviates from the ideal constant current characteristic, a stable point P _1, P _2, · · ·, the phenomena such voltage generated of P ₅ is no longer equal intervals it is necessary to pay attention.

(Fifth Embodiment) FIG. 9 is a circuit diagram showing a configuration of a multilevel memory cell according to a fifth embodiment of the present invention. In this figure, the same parts as those in FIG. 7 are denoted by the same reference numerals. The multi-level memory cell 40 shown in FIG. 9 includes the multi-level storage circuit shown in FIG. 7 and an access control field effect transistor 41. One source / drain electrode of the field effect transistor 41 is connected to a bit line 42 to which a multi-level signal is applied, and the other source / drain electrode of the field effect transistor 41 is connected to the storage of the multi-level storage circuit shown in FIG. The gate electrode of the field effect transistor 41 connected to the node 31 is connected to a word line 43 to which a selection voltage is applied. This field-effect transistor 41 includes a bit line 42 and a storage node 31.
It functions as a switch for switching connection / disconnection with the word line 43 by a voltage applied to the word line 43.

As shown in FIG. 10, by arranging a large number of bit lines 42 and word lines 43 so as to intersect with each other and arranging a multi-valued memory cell 40 in each of the intersecting regions, a large number of multi-valued memories are provided. A desired cell can be selected and read / written from the cells 40, and a large-scale multi-valued memory circuit can be realized. Similarly, FIG.
A multi-level memory cell may be configured using the multi-level storage circuit shown in FIG.

[0038]

As described above, according to the present invention, the drain voltage of a single-electron transistor can be reduced by Coulomb blockade regardless of the output terminal voltage by the action of a three-terminal element cascode-connected to the drain electrode of the single-electron transistor. It is kept low enough to maintain the condition. In addition, the negative feedback effect on the potential of the single electron island from the output terminal can be suppressed. As a result, a single-electron transistor logic circuit having a large output amplitude and a large voltage gain can be realized. Since a high voltage gain can be obtained even if the gate capacitance of the single-electron transistor is kept small, the restriction on an increase in operating temperature is relaxed.

In the single-electron transistor logic circuit described above, a depletion type field effect transistor is used as a three-terminal element. This eliminates the need to supply a bias voltage. Further, a depression type field effect transistor is used as the load element. As a result, a circuit configuration with a small number of types and numbers of elements can be obtained, the manufacturing process of the logic circuit can be simplified, and the area occupied by the logic circuit can be reduced.

Further, in the above-described single-electron transistor logic circuit, a multi-value storage circuit can be realized with a simple configuration by short-circuiting the input terminal and the output terminal to form a storage node. Further, by connecting the storage node of the above-described multi-valued storage circuit to a bit line and a word line via a switch, a large-scale multi-valued storage circuit that can be selected from a large number of cells and can be read and written can be realized. .

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a single-electron transistor logic circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a single-electron transistor logic circuit when a constant current source is used as a load element.

FIG. 3 is a characteristic diagram of the logic circuit shown in FIG. 2;

FIG. 4 is a circuit diagram showing a configuration of a single-electron transistor logic circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating a configuration of a multilevel storage circuit according to a third embodiment of the present invention.

6 is a diagram showing IV characteristics between a circuit current and a storage node voltage of the multi-level storage circuit shown in FIG.

FIG. 7 is a circuit diagram showing a configuration of a multilevel storage circuit according to a fourth embodiment of the present invention.

8 is a diagram showing an IV characteristic between a circuit current and a storage node voltage of the multilevel storage circuit shown in FIG.

FIG. 9 is a circuit diagram showing a configuration of a multilevel memory cell according to a fifth embodiment of the present invention.

FIG. 10 is a block diagram illustrating a configuration of a multi-level memory cell array including a plurality of multi-level memory cells.

FIG. 11 is an equivalent circuit diagram of a general single-electron transistor.

FIG. 12 is a characteristic diagram showing gate-source voltage dependence of a current flowing between a source and a drain of a single-electron transistor.

FIG. 13 is a circuit diagram showing a configuration of a resistance load type inverter using a single electron transistor.

FIG. 14 is a circuit diagram illustrating a main configuration of a storage circuit including a single-electron transistor.

[Explanation of symbols]

1. Single electron transistor, 2. Drain tunnel junction,
3: Source tunnel junction, 4: Gate capacitor, 5:
Single electron island, 6 power supply terminal, 7 ground terminal, 8 input terminal, 9 output terminal, 10 load element, 11 constant current source,
12. Field effect transistor (depletion type), 2
1: Field effect transistor, 22: bias voltage terminal,
23 ... field effect transistor (depletion type), 3
DESCRIPTION OF SYMBOLS 1 ... Storage node, 40 ... Multi-value memory cell, 41 ... Field effect transistor, 42 ... Bit line, 43 ... Word line.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03K 19/0944 G11C 17/00 641 19/173 101 H03K 19/094 A F-term (Reference) 5B025 AA07 AB01 AC01 AE06 AE07 5F083 FZ01 GA05 ZA21 5J042 AA10 BA02 CA10 CA20 DA01 DA04 5J055 AX62 BX17 CX27 DX12 DX53 DX55 EX02 EX07 EX12 EY21 EZ29 FX22 FX37 GX01 GX02 5J056 AA03 AA32.

Claims (8)

[Claims] 1. A single-electron transistor in which a tunnel junction is provided between each of a source electrode and a drain electrode and a single-electron island, and a gate electrode is capacitively coupled to the single-electron island; A three-terminal element that controls a current flowing between the first terminal and the second terminal by a signal supplied to the third terminal; and between a source electrode and a drain electrode of the single-electron transistor. A load element for flowing a current smaller than the maximum value and smaller than the maximum value of the current flowing through the drain electrode of the single-electron transistor is connected to the first terminal of the three-terminal element, and the gate electrode of the single-electron transistor is A second terminal of the three-terminal element and one end of the load element are connected to an output terminal; the other end of the load element is connected to a power supply terminal; The source electrode of the transistor is connected to a ground terminal, and the third terminal of the three-terminal element is controlled so that the voltage of the first terminal of the three-terminal element is equal to or less than a value obtained by dividing the elementary charge by the total capacity of the single-electron transistor. An electronic circuit, wherein the voltage of the terminal is set. 2. The electronic circuit according to claim 1, wherein the three-terminal element is a field-effect transistor, a first terminal of the three-terminal element is a source electrode, and the second terminal is a drain electrode. The third terminal is a gate electrode, and the gate electrode is connected to a bias voltage terminal for applying a voltage higher than the voltage of the source electrode by a voltage for turning on the field effect transistor. Electronic circuit featuring. 3. The electronic circuit according to claim 2, wherein the field-effect transistor is a depression type, and the bias voltage terminal is the ground terminal. 4. The electronic circuit according to claim 1, wherein the load element is a constant current source. 5. The depletion-type electric field according to claim 1, wherein the load element has a short-circuit between a gate electrode and a source electrode to serve as the one end, and a drain electrode to the other end. An electronic circuit, which is an effect transistor. 6. The electronic circuit according to claim 1, wherein the input terminal and the output terminal are short-circuited to form a storage node. 7. The electronic circuit according to claim 6, further comprising a switch for switching connection / disconnection between a bit line and said storage node by a voltage applied to a word line. 8. The electronic circuit according to claim 7, wherein the switch has one source / drain electrode connected to the bit line, the other source / drain electrode connected to the storage node, and a gate electrode connected to the word line. An electronic circuit, wherein the electronic circuit is a field-effect transistor connected to the electronic device.