JP2002286803A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Problem] To provide a semiconductor integrated circuit capable of performing a scan path test at high speed. A semiconductor integrated circuit including scan path circuits (SC1) to (SC4) is provided.
A first memory circuit M1 and a second memory circuit M2 for storing data to be supplied to C2, and scan path circuits SC1 to SC4
And a switching circuit SEL for supplying data stored in the second memory circuit M2 in parallel to a plurality of scan path circuits SC1 and SC2 selected from the circuits constituting the semiconductor integrated circuit. Provide a circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit including a circuit forming a scan path.

[0002]

2. Description of the Related Art Conventionally, in order to inspect the quality of a semiconductor integrated circuit formed on a chip, a scan path test using a flip-flop (FF) provided on the chip has been performed. Here, the scan path test is widely used for the purpose of simplifying a test pattern used at the time of manufacturing and shipping the semiconductor integrated circuit to facilitate failure diagnosis of the integrated circuit. .

According to the scan path test, even for a complicated and large-scale sequential circuit, a flip-flop and a combinational circuit are separated, and a test pattern is input / output using the flip-flop. The test of the semiconductor integrated circuit can be easily executed.

However, in this semiconductor integrated circuit to be tested, the arrangement and wiring of combinational circuits other than flip-flops are preferentially designed.
There is a problem that the flip-flop forming the scan path cannot have an ideal circuit configuration.

Further, since the scale of a semiconductor integrated circuit is increasing recently, there is a problem that the number of test patterns becomes enormous. From these problems, a large test time is required when specifying a manufacturing failure of the LSI by using the tester device, and a problem that a test cost is finally caused is caused.

In this scan path test, an operation of supplying test data to flip-flops constituting a scan path (this is also called "scan shift") and an operation of reading data indicating a test result from the flip-flop are performed. Takes the most time. In other words, these operations require clock cycles for the number of flip-flops constituting the scan path even if they are simply calculated.

Therefore, conventionally, in order to reduce the number of flip-flops constituting the scan path, a method of dividing the circuit constituting the scan path to shorten the test time has been adopted. While it is necessary to provide a large number of external pins for supply on the chip, there is a problem that the number of external pins that can be provided on the chip is limited.

FIG. 7 is a diagram showing a configuration of a conventional semiconductor integrated circuit. As shown in FIG. 7, this semiconductor integrated circuit includes an address decoder 1 and a flip-flop (F
F) It comprises 3a, 3b, 4a, 4b, 5a, 5b, combinational circuits 7, 8, 9, data bus lines 10, 11, and pad PD. Here, FF3a, FF3b, FF
4a and FF4b, and FF5a and FF5b are respectively connected in series.

The FFs 3a, 4a and 5a are all connected to the address decoder 1, the FFs 3b and 4b are connected to the data bus line 10, and the FF 5b is connected to the data bus line 11, respectively. The above “combination circuit”
This means a logic circuit whose output signal is uniquely determined according to the input signal. The same applies to the following.

The FFs 3a and 3b are both connected to the pad PD, and the combination circuit 7 is connected to the FFs 3a and 3b. The FFs 4a and 4b are connected to the combination circuit 7, and the combination circuit 8 is connected to the FFs 4a and 4b. The FFs 5a and 5b are connected to a combination circuit 8, and the combination circuit 9 is connected to the FFs 5a and 5b.
The pad PD is connected to the combination circuit 9.

In the semiconductor integrated circuit having the above configuration, the data bus line 1
Test data D1 and D2 are supplied to 0 and 11 respectively, and address signals AD1 and AD2 for specifying the supply destination of the test data are supplied to the address decoder 1. Then, the address decoder 1 receives the supplied address signal A.
D1 and AD2 are decoded and a decode signal is selectively supplied to one of flip-flops 3a, 4a and 5a. At this time, the flip-flops 3a, 4a, 5a supplied with the decode signal and the flip-flops 3a, 4
a, 5a flip-flops 3b, 4 connected in series
b and 5b take in test data D1 and D2 from the data bus lines 10 and 11 individually or in parallel.

The test data is supplied to a combination circuit connected to the next stage, and output data of the combination circuit corresponding to the test data is supplied to a flip-flop connected to the next stage of the combination circuit. You.

Next, the address decoder 1 is supplied with address signals AD1 and AD2 designating a flip-flop to which the test data is to be output. The address decoder 1 supplies the supplied address signals AD1, AD2
To decode the decoded signal into flip-flops 3a,
4a and 5a are selectively supplied. Then, the selected flip-flop 3a, 4a, 5a and the flip-flop 3 connected in series to the flip-flop 3a, 4a, 5a
From b, 4b and 5b, the output data is output to the data bus lines 10 and 11 individually or in parallel. In this way, a desired test for any combinational circuit is performed.

[0014]

However, in the above-mentioned conventional semiconductor integrated circuit, the flip-flops 3a, 3b, 4a, 4b, 5a, 5b are directly or indirectly connected to the data bus lines 10, 11. The test data D 1,
Since D2 is supplied, when various test data are selectively supplied to a large number of flip-flops 3a, 3b, 4a, 4b, 5a, 5b, there is a problem that the test time cannot be sufficiently reduced. is there.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor integrated circuit capable of performing a scan path test at high speed.

[0016]

The present invention relates to a semiconductor integrated circuit including a plurality of circuits constituting a scan path,
Storage means for storing data to be supplied to a plurality of circuits, and selection and supply means for supplying data stored in the storage means to a circuit selected among the plurality of circuits in parallel. This is achieved by providing a semiconductor integrated circuit that:

According to the present invention, the storage means stores the data to be supplied to the plurality of circuits according to its own specifications, and the selection and supply means stores the data stored in the storage means to the selected circuit. Since the data is supplied in parallel, the test time can be reduced by setting desired data to a plurality of circuits constituting the scan path at high speed.

In the above, the storage means is a first storage means for taking in data from outside the semiconductor integrated circuit, and a second storage means connected to the first storage means for holding the data stored in the first storage means. Storage means, and the selection supply means may supply the data held in the second storage means to the plurality of circuits.

According to the present invention as described above, the first storage means can start a new operation from the outside of the semiconductor integrated circuit from the timing when the data stored in the first storage means is held in the second storage means. Since data can be taken in, data can be efficiently set to circuits constituting a scan path.

According to the present invention, there is provided a semiconductor integrated circuit including a plurality of circuits constituting a scan path, wherein a circuit to be fetched data is selected from the plurality of circuits, and data is read from the selected circuit. The present invention is attained by providing a semiconductor integrated circuit, comprising: a data capturing unit that captures data in parallel; and a storage unit that stores data captured by the data capturing unit.

According to the present invention, the data fetching means fetches data in parallel from the selected circuit, and the storage means stores the fetched data according to its own specifications. By reading desired data at high speed from a plurality of circuits constituting the above, the test time can be reduced.

Here, the storage means is connected to the first data storage means and the first storage means, and is connected to the first storage means and holds the data stored in the first storage means. Second storage means for outputting the data to the outside of the semiconductor integrated circuit, and the data capturing means,
The captured data may be stored in the first storage means.

According to the present invention as described above, the first storage means is newly provided from the circuit constituting the scan path from the timing when the data stored in the first storage means is held in the second storage means. Since such data can be taken in, data can be efficiently read out from the circuits constituting the scan path.

[0024]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to one embodiment of the present invention. As shown in FIG. 1, the semiconductor integrated circuit according to the present embodiment includes a control circuit 20 and a circuit (hereinafter also referred to as a “scan path circuit”) SC forming a scan path, in addition to the combinational circuit 30.
1 to SC4, switching circuit SEL, first memory circuit M
1 and a second memory circuit M2.

Here, the input data SI and the clock signal CK are supplied to the first memory circuit M1, and the second memory circuit M2 is connected to the first memory circuit M1. The switching circuit SEL is connected to the second memory circuit M2, and the scan path circuits SC1 and SC2 are connected to the switching circuit SEL.

The control circuit 20 includes a first memory circuit M1
And the second memory circuit M2, the switching circuit SEL, and the scan path circuits SC1 to SC4, and the clock signal CK is supplied. Then, the control circuit 20 sends the internal clock signal ICK to the second memory circuit M2 and the switching circuit S
The control signal CT2 is supplied to the EL from the scan path circuits SC1 to SC
4 to supply control signals CT3 and CT4, respectively.

The enable signal EN is supplied to the first memory circuit M1, the second memory circuit M2, and the switching circuit SEL. Further, the scan path circuits SC1 to SC1
The scan clock signal SCK is supplied to SC4.

In the above, the scan path circuit S
C1 to SC4 are connected to each other in series and connected to the combinational circuit 30 respectively. In the semiconductor integrated circuit according to the present example having the above-described configuration, test data is supplied from the scan path circuits SC1 and SC2 to the combination circuit 30, and output data of the combination circuit 30 corresponding to the test data is converted into scan path circuits SC3 and SC3.
By outputting to the outside via SC4, it is tested whether or not the operation of the semiconductor integrated circuit is normal.

Here, conventionally, in a semiconductor integrated circuit having a configuration as shown in FIG. 1, when the combination circuit 30 is tested, the test data is sequentially and serially input to the scan path circuit SC2 to perform the scan path test. The test data has been supplied to the circuits SC1 and SC2. However, as the number of flip-flops constituting the scan path circuits SC1 and SC2 increases, the time required to set the test data in each flip-flop increases. There was a problem that the test time was long.

On the other hand, in the semiconductor integrated circuit according to the present embodiment, first, test data supplied to the scan path circuits SC1 and SC2 are collectively serially transferred to the first memory circuit M1 having predetermined characteristics as hardware. Remembered,
The test data stored in the first memory circuit M1 is stored in the second memory M2. Then, the test data stored in the second memory M2 is supplied to the switching circuit SEL, and is supplied in parallel to the scan path circuit selected by the control circuit 20.

Therefore, according to the semiconductor integrated circuit of the present embodiment which realizes the above operation, the test data can be set to each flip-flop constituting the scan path at a high speed. Test time can be significantly reduced.

Further, as described above, the second memory circuit M2 is provided, and the test data input to the first memory circuit M1 is
By directly storing the test data in the second memory circuit M2, the next test data can be externally supplied to the first memory circuit M1 from the time when the test data is stored in the second memory circuit M2. Efficiency in supplying the data to the flip-flop can be improved.

In the semiconductor integrated circuit according to the present embodiment shown in FIG. 1, the number of flip-flops constituting a scan path formed for the combinational circuit 30 is one.
Since the number of flip-flops constituting the first memory circuit M1 and the second memory circuit M2 is a fraction or a tenth of the number, Until the test data is supplied, the test data stored in the second memory circuit M2 is repeatedly and selectively supplied by the switching circuit SEL.

FIG. 2 shows the first memory circuit M shown in FIG.
FIG. 3 is a circuit diagram showing a configuration of a first memory circuit M2. The first memory circuit M1 is configured according to the scale of the semiconductor integrated circuit, and includes a plurality of memory elements connected in series. Here, the “memory element” includes an element that stores data, such as a flip-flop and a register.

Then, for example, the first memory circuit M1
D circuit 31 and a delay flip-flop (DF)
F) 34-37. Here, the clock signal CK and the enable signal EN are supplied to the AND circuit 31. Also,
The D-FFs 34 to 37 are connected in series, and each clock input pin (CF) is connected to the output node of the AND circuit 31. The test data SI is input to the data input pin (D) of the D-FF 34.

The second memory M2 includes an AND circuit 39 and D-FFs 41 to 44. Here, the internal clock signal ICK and the enable signal EN are supplied to the AND circuit 39. The clock input pins of the D-FFs 41 to 44 are connected to output nodes of the AND circuit 39. And
The data input pin of the D-FF 41 is connected to the data output pin (Q) of the D-FF 34, and the data input pin of the D-FF 42 is connected to the data output pin of the D-FF 35.

The data input pin of the D-FF 43 is
-Connected to the data output pin of the FF 36 and the D-FF 44
Is connected to the data output pin of the D-FF 37. Then, data output from the data output pins of the D-FFs 41 to 44 is supplied to the switching circuit SEL.

In the first memory circuit M1 having the above configuration, the AND signal 31 is activated by activating the enable signal EN. At this time, the clock signal CK is applied to the clock input of the D-FFs 34 to 37. Supplied to the pin. As a result, the test data SI supplied to the data input pin of the D-FF 34 is sequentially transmitted to the DF in synchronization with the clock signal CK supplied to the clock input pin.
F34 to F37.

In a semiconductor integrated circuit in which a sufficient number of external pins can be provided, the D-
The test data may be directly supplied to the FFs 34 to 37.

On the other hand, in the second memory circuit M2, similarly, when the enable signal EN is activated,
D circuit 39 is activated. At this time, internal clock signal I
CK is supplied to the clock input pins of the D-FFs 41 to 44. As a result, the D-
The data output from the data output pins of the FFs 34 to 37 are stored in the D-FFs 41 to 44, respectively.

At this time, the test data SI input to the first memory circuit M1 is supplied to the D-FFs 34 to 37 by activating the AND circuit 39 when the test data is input to the second memory circuit M1. The data may be stored in the circuit M2 collectively, or when the test data is input to each of the D-FFs 34 to 37, the data may be sequentially stored in the corresponding D-FFs 41 to 44. .

FIG. 3 shows the switching circuit SE shown in FIG.
FIG. 3 is a circuit diagram showing a configuration of a scan path circuit SC and L. Note that the scan path circuit SC2 has the same configuration as the scan path circuit SC1, but is omitted in FIG.

As shown in FIG. 3, the switching circuit SE
L includes an AND circuit 51 and 1 to N selectors 52 to 55. Here, the enable signal EN and the control signal CT2 are supplied to the AND circuit 51, and the output signal is supplied to the 1 to N selectors 52 to 55. The data output from the D-FF 41 shown in FIG. 2 is supplied to the 1 to N selector 52, and the D-FF shown in FIG.
The data output from the FF 42 is supplied. Similarly,
The 1-to-N selectors 54 and 55 have the D-FF shown in FIG.
The data output from 43 and 44 are respectively supplied.

As shown in FIG. 3, the scan path circuit SC1 includes selectors 56, 61 to 64 and D-FFs.
57 to 60. Here, the control signal CT4 and the scanning clock signal SCK are supplied to the selector 56,
The control signal CT3 is supplied to the selector 56 and the selectors 61 to 64. The selector 61 has a 1 to N selector 5
2, the test data is supplied to the selector 62, and the test data is supplied to the selector 62 from the 1 to N selector 53. Similarly, selectors 63 and 64 each have 1 to
The test data is supplied from the N selectors 54 and 55.

Each of the 1 to N selectors 52 to 55 converts the test data supplied from the second memory circuit M2 to A
The signal is supplied to a scan path circuit selected from N scan path circuits in accordance with the signal supplied from the ND circuit 51. Here, in the semiconductor integrated circuit according to the present example, the case where N is 2 is shown.

The output node of the selector 56 is D-
The output nodes of the selectors 61 to 64 are connected to the input nodes I of the corresponding D-FFs 57 to 60, respectively.

The output node O of the D-FF 60 is connected to the input node of the selector 63, and the output node O of the D-FF 59 is connected to the input node of the adjacent selector. Similarly, the output node O of the D-FF 58 is connected to the selector 6
1 input node. Also, D-FF57-6
The data output pin of 0 is connected to the combination circuit 30 shown in FIG.

The operation of the switching circuit SEL and the scan path circuit SC1 shown in FIG. 3 having the above configuration will be described below. First, when the enable signal EN is activated, the switching circuit SEL is activated, and the control signal CT2 output from the control circuit 20 becomes 1 to
The signals are supplied to N selectors 52 to 55. And each 1 to N
The selectors 52 to 55 supply the test data supplied from the second memory circuit M2 to the scan path circuit selected according to the supplied control signal CT2.

Here, a case where the test data is selectively supplied to the scan path circuit SC1 will be described as an example. First, when the control signal CT3 supplied to the scan path circuit SC1 is activated, the selector 56 is deactivated, and the selectors 61 to 64 select the signals supplied from the 1 to N selectors 52 to 55, respectively. Therefore, in this case, the test data stored in the second memory circuit M2 includes the DFs constituting the scan path circuit SC1.
F57 to F60. As a result, the test data serially supplied to the first memory circuit M1 is
Combination circuit 3 to be tested from FFs 57-60
0 are supplied in parallel.

On the other hand, when the control signal CT3 is inactivated, the scan path circuit SC1 operates as a shift register. That is, while the selector 56 is activated, the selectors 61 to 64 are connected to the D-FFs 58 to 60
Selectively output the data output from. Thereby, in the selector 56, the supplied control signal CT
4 is activated, the scan path clock signal SCK is supplied to the D-FFs 57 to 60, and the D-FFs 57 to 60 are supplied with D-FFs 57 to 60 in accordance with the supplied scan path clock signal SCK.
The FFs 57 to 60 sequentially shift the stored data serially. Therefore, by such an operation, the output data SO indicating the test result obtained from the combination circuit 30 according to the test data can be extracted from the scan path circuit SC4 as shown in FIG.

As described above, according to the semiconductor integrated circuit of the present embodiment, the first memory circuit M1 in which hardware characteristics such as the operating frequency of writing and reading are determined in advance.
Test data can be batch-inputted serially according to the operation characteristics, and the test data can be supplied in parallel to each flip-flop constituting the scan path circuit by the switching circuit SEL. The test time of the semiconductor integrated circuit can be reduced.

Since the first memory circuit M1 as described above is provided in the semiconductor integrated circuit, a desired memory can be obtained without depending on the arrangement of the flip-flops constituting the semiconductor integrated circuit and the wiring of the flip-flops. Test data can be supplied to the flip-flop at a stable speed.

Further, according to the semiconductor integrated circuit of the present embodiment, since it is unnecessary to divide the scan path circuit into a plurality of parts, the number of external input / output pins required for performing a test using the scan path circuit is reduced. Can be greatly reduced.

As described above, the semiconductor integrated circuit according to the embodiment can set test data to the scan path circuit at high speed. According to the present invention, the test data stored in the scan path circuit can be set. A semiconductor integrated circuit capable of reading data indicating the result of (1) at high speed can be obtained. Hereinafter, a semiconductor integrated circuit according to another example of such an embodiment will be described in detail.

FIG. 4 is a diagram showing a configuration of a semiconductor integrated circuit according to another example of the embodiment of the present invention. As shown in FIG. 4, the test data SI set in the scan path circuits SC1 and SC2 is supplied to the combinational circuit 30 to be tested, and data indicating a test result corresponding to the test data SI is output. The signals are output to the scan path circuits SC3 and SC4 by the combination circuit 30.

As shown in FIG. 4, a semiconductor integrated circuit according to another example of the present embodiment has the same configuration as the semiconductor integrated circuit according to the example of the embodiment shown in FIG. The difference is that the switching circuit SEL is connected to scan path circuits SC3 and SC4 from which data indicating a test result is read, and output data SO indicating the test result is output from the first memory circuit M1 to the outside. is there. The scan path clock signal SCK is supplied to the scan path circuits SC1 to SC4.

FIG. 5 is a circuit diagram showing a configuration of the first memory circuit M1b and the second memory circuit M2b shown in FIG. As shown in FIG. 5, the first memory circuit M1
b and the second memory circuit M2b are respectively the first memory M1 and the second memory M according to the first embodiment shown in FIG.
2, but the data input pins of the D-FFs 41 to 44 included in the second memory circuit M2b are connected to the switching circuit SEL.

The first memory circuit M1b is provided with each DF
Selectors 81 to 84 provided corresponding to F34 to F37
And a selector 33. And the D-FF
The data output pins 41 to 44 are connected to the first input nodes of the corresponding selectors 81 to 84, respectively. The second input node of the selector 81 is grounded, and the output node is connected to the data input pin of the D-FF 34. On the other hand, the second input node of the selector 82 is connected to the data output pin of the D-FF 34, and the output node is connected to the data input pin of the D-FF 35. Similarly, the second input node of the selector 83 is connected to the data output pin of the D-FF 35,
The output node is connected to the data input pin of the D-FF 36. The second input node of the selector 84 is a D-FF
36, and the output node is DF
Connected to the data input pin of F37.

The control signal CTK is supplied to the first input node of the selector 33 from the control circuit 20, the clock signal CK is supplied to the second input node, and the output nodes are the D-FFs 34 to 37. Connected to clock input pin. Further, to the selector 33,81～84 data enable signal EN _D is supplied from the control circuit 20.

In the semiconductor integrated circuit according to the other example having the above-described configuration, the output data SO is serially output from the data output pin of the D-FF 37 to the outside.

FIG. 6 shows the switching circuit SE shown in FIG.
FIG. 4 is a circuit diagram showing a configuration of a scan path circuit SC and a scan path circuit SC3. As shown in FIG. 6, the switching circuit SEL and the scan path circuit SC3 according to the present other example are each configured as shown in FIG.
Circuit SEL according to an example of the embodiment shown in FIG.
And the same configuration as the scan path circuit SC1,
D-FFs 57 to 60 included in scan path circuit SC3
Are supplied with the data output from the combinational circuit 30, the input nodes I of the D-FFs 57 to 60 are connected to the output nodes of the previous selectors 65 to 67, and the output node O is connected to the corresponding selector. 65-68
Is connected to the input terminal of

The scan path circuit SC3 includes an inverting circuit INV and an AND circuit 85. Here, the scan circuit clock signal SCK is supplied to the AND circuit 85, and the output node of the inverting circuit INV is connected to the AND circuit 85.
The output nodes of the AND circuit 85 are D-FF57-
60 clock input pins. A control signal CT3 is supplied from the control circuit 20 to the input terminal of the inverting circuit INV and the selectors 65 to 68.

On the other hand, the switching circuit SEL is different in that Nto1 selectors 72 to 75 are provided instead of the 1 to N selectors 52 to 55. The Nto1 selectors 72 to 7
Reference numeral 5 denotes N (N is 2 in the semiconductor integrated circuit according to the second embodiment) inputted according to the supplied control signal.
Is a circuit for selecting one signal from among the above signals, and supplies the selected signal to the second memory circuit M2b.

The operation of the semiconductor integrated circuit according to the other example having the above-described configuration will be described below. When control signal CT3 output from control circuit 20 shown in FIG. 4 is at an inactive level, scan path circuit SC3 operates as a shift register. That is, the control signal CT
3 is inactive, the AND circuit 85 is activated, so that the scan path clock signal SCK becomes D-FF.
Supplied to clock input pins 57-60. Therefore,
From the D-FFs 57 to 60, the scan clock signal S
In response to CK, the data is output to the selectors 65 to 68, and each of the selectors 65 to 68 sequentially outputs the data to the DF of the next stage.
The data is supplied to F58-60.

On the other hand, when control signal CT3 is activated by control circuit 20, AND circuit 56 is inactivated.
Further, the selectors 65 to 68 are respectively D-FF 57 to
The data supplied from 60 is supplied in parallel to Nto1 selectors 72 to 75 included in the switching circuit SEL. As shown in FIG. 4, each of the Nto1 selectors 72 to 7
5, data is supplied from both the scan path circuit SC3 and the scan path circuit SC4.

Then, each of the Nto1 selectors 72 to 75
In response to a control signal supplied from the AND circuit 51, data supplied from either the scan path circuit SC3 or the scan path circuit SC4 is selectively supplied to the second memory circuit M2b.

The signals supplied from the switching circuit SEL in this manner are held in the D-FFs 41 to 44 shown in FIG. 5 and are selected according to the internal clock signal ICK supplied from the AND circuit 39. The data is supplied to the D-FFs 34 to 37 included in the first memory circuit M1b via 84.
At this time the data data enable signal EN _D is inactivated, the signal input to the first input node is selectively output in the selector 33-37.

Each of the D-FFs 34 to 37 sequentially shifts the data to the next D-FF in synchronization with the clock signal CK supplied from the selector 33 in response to the control signal CTK. Output data SO is externally output serially from the data output pin. At this time, the data enable signal EN _D is activated, the selector 33-37
In, the signal input to the second input node is selectively output.

Therefore, according to the semiconductor integrated circuit of this other example, the switching circuit SEL takes in the data indicating the test result output from the combinational circuit 30 and stored in the scan path circuits SC3 and SC4 in parallel, Since the data is stored in the second memory circuit M2b and the first memory circuit M1b and the data is serially output from the first memory circuit M1b, the test time can be shortened by reading the data to the outside at high speed.

Here, the switching circuit SEL can arbitrarily select the destination of the data from the scan path circuits SC3 and SC4, and the second memory circuit M2b immediately starts copying the data to the first memory circuit M1b. , The data can be read efficiently according to the characteristics of the combinational circuit 30.

As described above, one example of the above-described embodiment is a semiconductor integrated circuit that can set (write) test data to a predetermined flip-flop at a high speed, and another example of the above-described embodiment is that data indicating a test result is stored. Although the semiconductor integrated circuit can be read at high speed from a predetermined flip-flop, an example of the above embodiment and another example of the embodiment can be combined.

That is, the switching circuit SEL, the first memory circuit M1, and the second memory circuit M shown in FIG. 1 are provided for the scan path circuits SC1 and SC2.
2 and the switching circuit SEL shown in FIG. 4 and the first memory circuit M1b and the second memory circuit M2b for the scan path circuits SC3 and SC4, so that both the write operation and the read operation can be performed. A semiconductor integrated circuit that can operate at high speed can be easily realized.
However, in this case, the scan path is not used in both cases of supplying the test data to the combinational circuit 30 and reading out the data indicating the test result from the combinational circuit 30.

[0074]

According to the semiconductor integrated circuit of the present invention,
The storage means stores data to be supplied to the circuits constituting the scan path according to its own specifications, and the selection supply means supplies the data stored in the storage means to the selected circuits in parallel. By setting desired data to the above-described circuit at high speed, the test time can be reduced.

Here, by providing the storage means with the first and second storage means, desired data can be efficiently set in the circuits constituting the scan path.

According to the semiconductor integrated circuit of the present invention, the data fetching means fetches data in parallel from the selected circuit, and the storage means stores the fetched data according to its own specifications. Therefore, the test time can be shortened by reading desired data from a plurality of circuits constituting the scan path at high speed.

Here, by providing the storage means with the first and second storage means, data can be efficiently read from the circuits constituting the scan path.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration of a semiconductor integrated circuit according to an example of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a first memory circuit and a second memory circuit shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of a switching circuit and a scan path circuit shown in FIG.

FIG. 4 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to another example of an embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a first memory circuit and a second memory circuit shown in FIG. 4;

6 is a circuit diagram showing a configuration of a switching circuit and a scan path circuit shown in FIG.

FIG. 7 is a diagram showing a configuration of a conventional semiconductor integrated circuit.

[Explanation of symbols]

1 @ address decoder, 3a, 3b, 4a, 4b, 5
a, 5b flip-flop (FF), 7-9, 30
{Combination circuit, 10, 11} data bus line, 20} control circuit, 31, 39, 51, 85 ‥‥ A
ND circuit, 33, 56, 61 to 68, 81 to 84 ° selector, 34 to 37, 41 to 44, 57 to 60 ° delay flip-flop (D-FF), 52 to 55 ° 1
toN selector, 72-75 ‥‥ Nto1 selector, SC1
~ SC4 {scan path circuit, SEL} switching circuit, M1, M1b {first memory circuit, M2, M2b}
{Second memory circuit, PD pad, INV} Inverting circuit

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[Procedure amendment]

[Submission date] April 5, 2001 (2001.4.5)

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] Figure 3

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[Procedure amendment 2]

[Document name to be amended] Drawing

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[Correction method] Change

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FIG. 4

[Procedure amendment 3]

[Document name to be amended] Drawing

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[Procedure amendment 4]

[Document name to be amended] Drawing

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FIG. 6

Claims (4)

[Claims] 1. A semiconductor integrated circuit including a plurality of circuits forming a scan path, comprising: a storage unit configured to store data to be supplied to the plurality of circuits; and a circuit selected from among the plurality of circuits. A semiconductor integrated circuit comprising: a selection supply unit that supplies the data stored in the storage unit in parallel. 2. The data storage device according to claim 1, wherein the storage unit is a first storage unit that takes in the data from outside the semiconductor integrated circuit; 2. The semiconductor integrated circuit according to claim 1, further comprising: a second storage unit configured to store the data, wherein the selection supply unit supplies the data stored in the second storage unit to the plurality of circuits. 3. A semiconductor integrated circuit including a plurality of circuits constituting a scan path, wherein a circuit to be fetched data is selected from the plurality of circuits, and the data is parallelized from the selected circuit. A semiconductor integrated circuit, comprising: a data capturing unit that captures data; and a storage unit that stores the data captured by the data capturing unit. 4. The storage means is connected to the first data storage means, and the first data storage means is connected to the first data storage means and holds the data stored in the first storage means. And a second storage unit that outputs the held data to the outside of the semiconductor integrated circuit, wherein the data capturing unit stores the captured data in the first storage unit. 3. The semiconductor integrated circuit according to claim 1.