JP2002280407A - Semiconductor chip and semiconductor device, circuit board, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor chip and semiconductor device that can prevent an alloy layer from being formed excessively largely at the time of performing brazing and soldering, and to provide a circuit board and electronic equipment. SOLUTION: The semiconductor device includes a semiconductor chip 30 having bumps 24 formed on pads 12 and a substrate 40 having a wiring pattern 42 to which the surface of the chip 30 with the bumps 24 is faced and the bumps 24 are brazed and soldered with a tin-containing brazing material 50. The bumps 24 are formed of a nickel-containing metal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor chip, a semiconductor device, a circuit board, and an electronic device.

[0002]

2. Description of the Related Art When a semiconductor chip is mounted face-down on a substrate, a form in which a bump of the semiconductor chip and a wiring pattern of the substrate are soldered is known. In that case, the bump was often formed of gold.

In recent years, it has been desired to use lead-free solder (lead-free solder). Lead-free solders often contain a higher proportion of tin than conventional solders. For this reason, diffusion between the gold bump and tin is promoted more than ever, and a thick alloy layer may be formed between the two. Since the mechanical properties of the alloy layer are fragile, there is a possibility of causing an electrical connection failure between the semiconductor chip and the wiring pattern of the substrate.

An object of the present invention is to solve this problem, and an object of the present invention is to provide a semiconductor chip and a semiconductor device which prevent an alloy layer from being excessively formed at the time of brazing.
It is to provide a circuit board and an electronic device.

[0005]

(1) A semiconductor chip according to the present invention includes a bump formed on a pad, wherein the bump includes a first metal layer formed of a metal other than nickel, A second metal layer formed on the surface of the first metal layer and containing nickel.

According to the present invention, the second metal layer is formed of a metal containing nickel, and has a property of hardly diffusing into tin contained in the brazing material. Therefore, for example, when the semiconductor chip is solder-bonded to the wiring pattern of the substrate, it is possible to prevent the alloy layer formed at the interface between the bump and the brazing material from being excessively formed. Therefore,
It is possible to suppress the formation of a brittle alloy layer having mechanical properties and to increase the reliability of the electrical connection between the bump and the wiring pattern.

(2) In this semiconductor chip, the first metal layer may be formed of a metal softer than the second metal layer.

According to this, since the first metal layer is softer than the second metal layer, it is possible to effectively reduce the stress concentrated on the bumps of the semiconductor chip.

(3) In this semiconductor chip, the bump may further include a third metal layer formed thinner than the second metal layer on a surface of the second metal layer.

According to this, for example, the third metal layer can prevent the second metal layer from being oxidized.

(4) In this semiconductor chip, the first metal layer may be formed of a metal containing copper.

According to this, copper has more flexibility than nickel.

(5) In this semiconductor chip, the third metal layer may be formed of a metal containing gold.

According to this, gold is less likely to be oxidized than nickel.

(6) In the semiconductor device according to the present invention, the semiconductor chip and the surface of the semiconductor chip having the bump are opposed to each other, and the bump has a wiring pattern joined by a brazing material containing tin. And

According to the present invention, the second metal layer is formed of a metal containing nickel, and has a property of hardly diffusing into tin contained in the brazing material. Therefore, it is possible to prevent the alloy layer formed at the interface between the bump and the brazing material from being excessively formed. Therefore, the formation of an alloy layer having weak mechanical properties can be suppressed, and the reliability of electrical connection between the bump and the wiring pattern can be increased.

(7) In the semiconductor device according to the present invention, a semiconductor chip having a bump formed on a pad is opposed to a surface of the semiconductor chip having the bump, and the bump is joined by a brazing material containing tin. Wherein the bumps are formed of a metal including nickel.

According to the present invention, the bump is formed of a metal containing nickel, and has a property of hardly diffusing into tin contained in the brazing material. Therefore, it is possible to prevent the alloy layer formed at the interface between the bump and the brazing material from being excessively formed. Therefore, the formation of an alloy layer having weak mechanical properties can be suppressed, and the reliability of electrical connection between the bump and the wiring pattern can be increased.

(8) In this semiconductor device, the bump is formed of a first metal layer containing nickel and a second metal layer formed on the surface of the first metal layer so as to be thinner than the first metal layer.
And a metal layer.

According to this, for example, the first metal layer can be prevented from being oxidized by the second metal layer.

(9) In this semiconductor device, the second
May be formed of a metal containing gold.

According to this, gold is less likely to be oxidized than nickel.

(10) In this semiconductor device, the bump may be formed by electroless plating.

If electroless plating is used, a bump made of a metal containing nickel can be easily formed.

(11) In this semiconductor device, the brazing material may be a brazing material containing no lead.

According to this, compared to the brazing material containing lead,
The formation of the alloy layer can be suppressed even when a lead-free brazing material having a characteristic that the alloy layer is easily formed is used.
Therefore, the reliability of the electrical connection between the bump and the wiring pattern can be improved.

(12) A circuit board according to the present invention has the semiconductor device described above.

(13) An electronic apparatus according to the present invention includes the above semiconductor device.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. However, the present invention
The present invention is not limited to the following embodiment.

(First Embodiment) FIGS. 1-2 (C)
FIG. 3 is a diagram illustrating a method of forming a bump according to the present embodiment, and FIGS. 3 and 4 are diagrams illustrating a semiconductor device according to the present embodiment.

As shown in FIG. 1, a semiconductor wafer 10 is prepared. In the present embodiment, the bump formation process is collectively processed in a wafer state. Alternatively, the bump formation process may be processed in a chip state.

The semiconductor wafer 10 has a plurality of pads 12
Having. The pad 12 becomes an electrode of an integrated circuit formed inside the semiconductor wafer 10. The pads 12 may be arranged at the end or the center of the semiconductor chip formed by cutting, or may be arranged in a plurality of rows and a plurality of columns in an area array. Pads 12 may be formed inside and / or outside the area where the integrated circuit is formed. The pad 12 is formed of aluminum, copper, or the like.

An insulating film 14 is formed on the surface of the semiconductor wafer 10 having the pads 12. The insulating film 14
It may be a single layer or a plurality of layers, and may be a general passivation film. The insulating film 14 is made of, for example, SiO ₂ ,
It is formed of SiN or polyimide resin.

An opening 16 for opening at least a part of the pad 12 is formed in the insulating film 14. The opening 16 preferably opens the center of the pad 12. In that case, a part of the insulating film 14 is placed on the end of the pad 12. That is, at least a part of each pad 12 is exposed on the surface of the semiconductor wafer 10 having the pad 12, and the insulating film 14 is provided on the other part.

As shown in FIGS. 2A to 2C, bumps 24 electrically connected to the respective pads 12 are formed.
The bump 24 is formed of a metal layer containing nickel (the first metal layer 2).
0). For example, bump 2 is formed by electroless plating.
4 may be formed. If electroless plating is used, a metal layer containing nickel can be easily formed.

As shown in FIG. 2A, a metal film 18 is formed on the pad 12. For example, when the pad 12 is made of aluminum, zincate treatment is performed on the pad 12 to replace and deposit zinc on the surface on aluminum. Thus, the metal film 16 made of zinc is formed. Alternatively, the metal film 18 may be formed of chromium.

As shown in FIG. 2B, the first metal layer 2
0 is formed on the pad 12. The first metal layer 20 contains nickel. For example, in an electroless nickel plating solution,
The pad 12 subjected to the zincate treatment is immersed, and nickel is deposited through a substitution reaction between the metal film 16 made of zinc and nickel. The first metal layer 20 may be a single layer or a plurality of layers. Also, the first metal layer 20
May contain another metal (for example, phosphorus) in addition to nickel. In this embodiment, an example of a mushroom type bump formed without using a mask is shown. However, as described later, a straight wall type bump formed using a mask (resist layer) is applied. Is also good. In the case of forming without using a mask, the step of forming a mask is unnecessary, and thus the step can be simplified.
Also, when a mask is used, the shape of the bumps can be controlled, which is particularly effective when the distance between adjacent pads 12 is small (at a narrow pitch).

As shown in FIG. 2C, if necessary,
On the surface of the first metal layer 20, a second metal layer 22 is formed. The second metal layer 22 may be formed on the entire surface of the first metal layer 20, or may be formed on a part thereof. The second metal layer 22 is formed thinner than the first metal layer 20.

The second metal layer 22 may include gold. Since gold is harder to oxidize than nickel, oxidation of the bumps can be prevented. When the bumps 24 are joined by brazing, the second metal layer (gold layer) 22 is positively diffused into the brazing material, and an appropriate amount of the alloy layer is formed between the first metal layer 20 and the brazing material. Can be formed.

Thus, the first and second metal layers 20, 2
2 are formed. Semiconductor wafer 10
Is then cut into a predetermined shape and singulated into a plurality of semiconductor chips. The semiconductor chip 30 (see FIG. 4) includes the bump 24.

Apart from the above-described example, the bumps 24 may be formed by electrolytic plating, or may be formed by a combination of electrolytic plating and electroless plating. Alternatively, the bumps 24 may be formed by a method using a dry method (such as sputtering) instead of the wet method (plating), or a method combining them may be applied.

As shown in FIG. 3, the semiconductor device according to the present embodiment includes a semiconductor chip 30 and a substrate 40. The semiconductor chip 30 is mounted face-down on the substrate 40, and both are electrically connected by a brazing material 50.

The substrate 40 may be a flexible substrate made of a polyimide resin or the like, or may be a rigid substrate such as a glass epoxy substrate. The substrate 40
Wiring pattern 4 electrically connected to semiconductor chip 30
2 The wiring pattern 42 may have a land. In that case, the bump 24 of the semiconductor chip 30 is joined to the land.

An insulating film 44 is often formed on the surface of the substrate 40 having the wiring pattern 42. Insulating film 44
Is provided so as to cover the wiring pattern 42 so as to avoid a joint portion with the bump 24 such as a land. In other words, the opening 46 that exposes the joint (for example, land) with the bump 24 is formed in the insulating film 44. The wall surface of the opening 46 may be tapered so that the opening width increases in the opening direction from the joint. By doing so, the bump 24
Can improve the self-alignment effect.
Note that the insulating film 44 may be a general solder resist.

The brazing material 50 may be a hard brazing material,
It is preferably a soft wax such as solder that can be melted at a low melting point. The brazing material 50 contains tin (Sn). In addition, in addition to tin, copper (Cu), silver (Ag), zinc (Zn),
It may include at least one material selected from the group consisting of bismuth (Bi), indium (In), lead (Pb), and the like. The brazing material 50 may be provided on the substrate 40 side, or may be provided on the semiconductor chip 30 side.
In addition, you may apply a flux as needed.

The brazing material 50 may be a brazing material containing no lead, for example, a lead-free solder. Lead-free solders often contain a high proportion of tin and have the feature of a higher melting point than the most commonly used eutectic solders of lead and tin.

As shown in FIG. 3, the bump 24 is in direct contact with the brazing material 50. Therefore, an alloying reaction occurs between the bump 24 and the brazing material 50. That is, bump 2
An unillustrated intermetallic compound (alloy layer) is formed between 4 and brazing material 50. The alloy layer is formed thicker as the ratio of tin contained in the brazing material 50 and the temperature at the time of diffusion (the temperature applied to the brazing joint) are higher, and the time is longer. According to this, when the brazing material 50 containing tin at a high ratio and having a relatively high melting point and not containing lead is used, the alloy layer is easily formed thick. Since the mechanical properties of the alloy layer are brittle, if the alloy layer is formed thick between the bump 24 and the brazing material 50, there is a possibility that electrical connection failure between the two may occur. The occurrence of electrical connection failures becomes more remarkable as the brazed portion becomes smaller with the recent reduction in the pitch between pads. Therefore, it is preferable that the alloy layer formed between the bump 24 and the brazing material 50 be as thin as possible.

Here, the alloy layer is composed of the bump 24 and the brazing material 5.
It is formed by diffusion occurring at both 0 and 0. More specifically, the metal of the bump 24 diffuses into the tin of the brazing material 50, or the tin of the brazing material 50 diffuses into the metal of the bump 24, and an alloy layer is formed between the two. Since the thickness of the alloy layer is proportional to the square root of the diffusion coefficient, the smaller the diffusion coefficient, the thinner the alloy layer. In other words, the less the diffusion between the bump 24 and the brazing material 50 occurs, the thinner the alloy layer formed between them can be.

In this embodiment, a metal containing nickel is used as the bump
The alloy layer formed between the solder and the brazing material 50 is thinned.

Generally, the diffusion coefficient D is represented by a frequency term D ₀ (m ²
/ S), activation energy Q for the diffused metal
(J / mol), gas constant R = 8.31451 (J /
(K · mol)) and the temperature at the time of diffusion T (K). Specifically, from the Arrhenius equation, D = D ₀ × exp (−Q / RT).

Here, the diffusion coefficient D _{1 of} tin with respect to gold,
Assuming that the diffusion coefficient of tin to copper is D ₂ and the diffusion coefficient of tin to nickel is D ₃ , the following values are calculated from the Arrhenius equation.

For the diffusion coefficient D ₁ , D ₀ = 4.1 × 10
^-6 , Q = 189 × 10 ³ , for example, T = 423.
Assuming that D ₁ = 1.91763 × 10 ⁻²⁹ diffusion coefficient D ₂ , D ₀ = 11 × 10 ⁻⁶ and Q = 188
Assuming that T = 423.15 from the value of × 10 ³ , for a diffusion coefficient D ₃ of D ₂ = 6.831 × 10 ⁻²⁹ , D ₀ = 3 × 10 ⁻³ , and Q = 274 ×.
Assuming that T = 423.15 from the value of 10 ³ , for example, D ₃ = 4.51611 × 10 ^−37, and comparing the respective diffusion coefficients, the relationship of D ₂ > D ₁ > D ₃ is established. That is, the diffusion from the brazing material 50 to the bumps 24 is less likely to occur when the bumps 24 including nickel are used than when the bumps 24 include gold or copper. Therefore, when a metal containing nickel is used for the bump 24, the alloy layer formed between the bump 24 and the brazing material 50 can be made thinner than a gold bump or a copper bump.

Similarly, when the value is calculated from the Arrhenius equation, the diffusion coefficient of nickel for tin is smaller than the diffusion coefficient of gold for tin or the diffusion coefficient of copper for tin. That is, the use of the bump 24 containing nickel is more effective than the bump 24 containing gold or copper.
Diffusion into the brazing material 50 hardly occurs. Therefore,
When a metal containing nickel is used as the bump 24,
The alloy layer formed between the brazing material 50 and the gold bump or the copper bump can be made thinner.

Further, nickel is self-diffusion (same type of
The diffusion coefficient of metal (diffusion of metal atoms) is larger than that of gold or copper.
It has the characteristic of being small. For details, see Gold Self-Proliferation
Number X ₁, Copper self-diffusion coefficient X_Two, Nickel self-diffusion coefficient
X_Three, The following value is calculated from the Arrhenius equation.
It is.

In the self-diffusion coefficient X ₁ , D ₀ = 91 × 1
From the values of 0 ⁻⁶ and Q = 175 × 10 ³ , for example, T = 42
Assuming that 3.15, X ₁ = 2.2599 × 10 ^{−26 and} self-diffusion coefficient X ₂ , D ₀ = 20 × 10 ⁻⁶ and Q = 1
From the value of 97 × 10 ³ , for example, assuming that T = 423.15, when X ₂ = 9.62711 × 10 ^-30 self diffusion coefficient X ₃ , D ₀ = 34 × 10 ^-6 and Q = 2
Assuming that T = 423.15 from the value of 92 × 10 ³ , for example, X ₃ = 3.07054 × 10 ^−41, and comparing the respective self-diffusion coefficients, the relationship X ₁ > X ₂ > X ₃ is established. I do. That is, nickel has a characteristic that it is harder to diffuse than gold and copper. This also indicates that the use of a metal containing nickel as the bump 24 enables the alloy layer formed between the bump 24 and the brazing material 50 to be thinner than that of a gold bump or a copper bump.

When the second metal layer 22 containing gold is formed on the surface of the first metal layer 20, gold and brazing material 50 are used.
However, in the present embodiment, the second metal layer 22 is formed to be extremely thin, and does not affect the thickness of the alloy layer.

As shown in FIG. 4, a resin 48 may be filled between the semiconductor chip 30 and the substrate 40.
By doing so, the two can be sealed without gaps, so that the moisture resistance and the like are improved. Further, the resin 48 may be used as an underfill material.
The stress concentrated on 4 (joint portion with the wiring pattern) can be reduced.

An external terminal 52 may be provided on the substrate 40. The external terminal 52 is electrically connected to the wiring pattern 42 via a through hole (not shown) or the like. The external terminals 52 are often solder balls. Also, instead of actively forming the external terminals 52, a solder cream applied to the circuit board side when mounting the circuit board (motherboard) is used, and the external terminals are eventually formed by the surface tension at the time of melting. Is also good. In that case, the lands connected to the wiring patterns 42 are exposed on the surface of the substrate 40 opposite to the semiconductor chip 30. Note that the package form of the semiconductor device is not limited, and examples thereof include a CSP type and a BGA type.

Further, the semiconductor device according to the present embodiment
The semiconductor chip 30 may be a bare chip mounted on a circuit board (mother board).

According to the semiconductor device of this embodiment,
The bump 24 is formed of a metal including nickel,
It has the property of not easily diffusing into tin contained in the brazing material 50. Therefore, the alloy layer formed at the interface between the bump 24 and the brazing material 50 can be made thin. Therefore, the formation of an alloy layer having a brittle mechanical property is suppressed, and the bump 2
4 and the reliability of the electrical connection between the wiring pattern 42 can be improved.

(Second Embodiment) FIGS. 5A to 5
(C) is a diagram showing a bump forming method according to the present embodiment. FIG. 6 is a diagram illustrating a semiconductor chip according to the present embodiment, and FIG. 7 is a diagram illustrating a semiconductor device according to the present embodiment.

The bump 66 according to the present embodiment includes a first metal layer 60 made of a metal other than nickel and a second metal layer 62 containing nickel. Each metal layer may be formed by electroless plating.

As shown in FIG. 5A, a first metal layer 60 is formed on the pad 12. First metal layer 60
Is preferably a metal softer than the second metal layer 62 (nickel). By using such a first metal layer 60 as a part of the bump 66, stress applied to the semiconductor device and concentrated on the bump can be reduced, and the bump 66 can be prevented from being broken.

The first metal layer 60 may be copper (Cu). In this case, for example, a copper plating solution may be used to reduce copper ions in the solution using palladium as a catalyst as a nucleus to deposit copper (first metal layer 60).

As shown in FIG. 5B, the first metal layer 2
A second metal layer 62 containing nickel is formed on the surface of the "0". For example, in order to activate the catalyst, a catalytic treatment with palladium may be performed to deposit nickel (the second metal layer 62).

As shown in FIG. 5C, if necessary,
A third metal layer 64 is formed on the surface of the second metal layer 62. The third metal layer 64 may be formed on the entire surface of the second metal layer 62 or may be formed on a part thereof. The third metal layer 64 is formed thinner than the second metal layer 62.
The third metal layer 64 may include gold, which can prevent oxidation of the bump. Further, when the bumps 66 are brazed, the third metal layer (gold layer) 64 is actively diffused into the brazing material, so that an appropriate amount of the alloy layer is formed between the second metal layer 62 and the brazing material. Can be formed.

Thus, as shown in FIG. 6, a bump 66 including the first to third metal layers 60, 62, 64 is formed. This semiconductor chip 130 includes the bump 66. Further, as shown in FIG. 7, the semiconductor device according to the present embodiment includes a semiconductor chip 130 and a substrate 40. The effects of the present embodiment include the contents described in the above embodiment.

(Third Embodiment) FIGS. 8A to 8
(C) is a diagram showing a bump forming method according to the present embodiment. In the present embodiment, the mask (the resist layer 7
0) using a straight wall type bump 124
To form In other forms, the contents described in the first embodiment can be applied.

As shown in FIG. 8A, a resist layer 70 is provided on the surface of the semiconductor wafer 10 having the pads 12. The resist layer 70 has a through hole 7 above the pad 12.
2 For example, after providing the resist layer 70 on the entire surface of the semiconductor wafer 10, the through hole 72 may be formed by applying photolithography technology. It is preferable that the wall surface of the through hole 72 rises perpendicularly to the surface of the semiconductor wafer 10. By doing so, the bumps 124 that rise vertically can be formed.

As shown in FIG. 8B, a first metal layer 120 containing nickel is formed on the pad 12. Since the through hole 72 is formed on the pad 12, the first metal layer 120 can be formed according to the planar shape of the through hole 72. Therefore, even if the pitch between the pads 12 is extremely narrow, it is possible to prevent the bumps 124 from contacting each other, and to prevent a short circuit between the pads 12.

As shown in FIG. 8C, if necessary,
On the surface of the first metal layer 120, a second metal layer 122 is formed. The second metal layer 122 may be formed after removing the resist layer 70, or may be formed before removing. Apart from the example shown, if the second metal layer 122 is formed with the resist layer 70 left, the second metal layer 12
2 is formed on the upper surface of the first metal layer 120. In addition,
The second metal layer 122 may include gold.

Thus, the first and second metal layers 120,
A bump 124 including 122 is formed. According to this, in addition to the above-described effects, the bump 1 having a desired width and height is provided.
24 can be provided.

The bump 66 described in the second embodiment may be formed by a method using the resist layer 70 described in the third embodiment.

FIG. 9 shows a circuit board 1000 on which the semiconductor device 1 according to the present embodiment is mounted. Generally, an organic substrate such as a glass epoxy substrate is used for the circuit board 1000. Wiring patterns made of, for example, copper or the like are formed on the circuit board 1000 so as to form a desired circuit, and the electrical connection between the wiring patterns and the external terminals 52 of the semiconductor device 1 is made by mechanical connection. Conduct continuity.

As an electronic apparatus having the semiconductor device 1 to which the present invention is applied, FIG. 10 shows a notebook personal computer 1100, and FIG. 11 shows a mobile phone 1200.

[Brief description of the drawings]

FIG. 1 is a diagram showing a method for forming a bump according to a first embodiment of the present invention.

FIGS. 2A to 2C are views showing a bump forming method according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a semiconductor device according to the first embodiment of the present invention.

FIGS. 5A to 5C are diagrams illustrating a bump forming method according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating a semiconductor chip according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a semiconductor device according to a second embodiment of the present invention.

FIGS. 8A to 8C are diagrams showing a bump forming method according to a third embodiment of the present invention.

FIG. 9 is a diagram showing a circuit board having a semiconductor device according to an embodiment of the present invention.

FIG. 10 is a diagram illustrating an electronic apparatus including the semiconductor device according to the embodiment of the present invention;

FIG. 11 is a diagram illustrating an electronic apparatus including a semiconductor device according to an embodiment of the present invention.

[Explanation of symbols]

 12 pad 20 first metal layer 22 second metal layer 24 bump 30 semiconductor chip 40 substrate 42 wiring pattern 50 brazing material 60 first metal layer 62 second metal layer 64 third metal layer 66 bump 120 first Metal layer 122 Second metal layer 124 Bump 130 Semiconductor chip

Claims (13)

[Claims] A first metal layer formed of a metal other than nickel, and a second metal layer formed on a surface of the first metal layer and including nickel. And a metal layer. 2. The semiconductor chip according to claim 1, wherein said first metal layer is formed of a metal softer than said second metal layer. 3. The semiconductor chip according to claim 1, wherein the bump is formed on a surface of the second metal layer to be thinner than the second metal layer. A semiconductor chip further comprising: 4. The semiconductor chip according to claim 1, wherein the first metal layer is formed of a metal containing copper. 5. The semiconductor chip according to claim 1, wherein the third metal layer is formed of a metal containing gold. 6. The semiconductor chip according to claim 1, wherein a surface of the semiconductor chip having the bump is opposed to the semiconductor chip.
A substrate having a wiring pattern in which the bumps are joined by a brazing material containing tin. 7. A semiconductor chip having a bump formed on a pad, and a surface of the semiconductor chip having the bump is opposed to the semiconductor chip.
A substrate having a wiring pattern joined by a brazing material containing tin, wherein the bump is formed of a metal containing nickel. 8. The semiconductor device according to claim 7, wherein the bump is formed of a first metal layer containing nickel and a second metal layer formed on a surface of the first metal layer to be thinner than the first metal layer. A semiconductor device comprising: a second metal layer; 9. The semiconductor device according to claim 8, wherein the second metal layer is formed of a metal containing gold. 10. The semiconductor device according to claim 6, wherein the bump is formed by electroless plating. 11. The semiconductor device according to claim 6, wherein said brazing material is a brazing material containing no lead. 12. A circuit board having the semiconductor device according to claim 6. 13. An electronic apparatus having the semiconductor device according to claim 6. Description: