JP2002278645A - Integrated circuit - Google Patents

Abstract

(57) Abstract: By dynamically calculating the internal clock frequency of an integrated circuit, the same boot program can be used even for integrated circuits that operate at different internal clock frequencies. A CPU (190) executes a boot program (111) stored in an instruction memory (110).
Is set to 1, the selectors 180 and 181 select a signal output from the oscillator 130 which oscillates at a known constant frequency, and supplies this signal to the timer 150. The timer 150 counts the number of internal clocks of the integrated circuit 100 supplied from the clock generator 1100 during the period from the rise to the fall of this signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an integrated circuit having a serial communication function.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a conventional integrated circuit having a serial communication function.

The integrated circuit 500 includes an instruction memory 510,
A serial interface 520, a timer 530, an input terminal 540 for connecting the inside and outside of the integrated circuit 500 when performing serial communication, and an output terminal for connecting the inside and outside of the integrated circuit 500 when performing serial communication 541
And input terminals 542 and 543 for connecting the inside and outside of the integrated circuit 500 when controlling the timer with a signal from the external input means 551; a CPU 560; and a clock generator 570. Stores a boot program 511. The serial interface 520 includes a frequency divider 521.

The input signal 1 input from the input terminal 542
Is output to the timer 530. The input signal 2 input from the input terminal 543 is output to the timer 530. The interrupt signal output from timer 530 is output to CPU 560. The internal clock generated by clock generator 570 is output to frequency divider 521 and timer 530 inside serial interface 520. The serial interface 520 performs serial communication with the external communication unit 550 via the input terminal 540 and the output terminal 541.

[0005]

SUMMARY OF THE INVENTION A conventional integrated circuit 500
When the CPU 560 activates the boot program 511 stored in the instruction memory 510 and performs serial communication with the external communication means 550, the integrated circuit 500 side operates the serial interface 520 to perform communication at a predetermined transfer rate. It is necessary to set the operation clock appropriately. Therefore, the CPU 560 sets the boot program 5
By setting an appropriate frequency division ratio in the frequency divider 521 in the serial interface 520 according to 11, the internal clock generated by the clock generator 570 is frequency-divided, and the operation clock of the serial interface 520 is determined. At this time, the boot program 511 has been created on the assumption that the internal clock frequency is known.
However, the internal clock frequency of the integrated circuit actually varies depending on the use of the integrated circuit. Therefore, different boot programs are required for the integrated circuits operating at different internal clock frequencies, and there is a problem in that the number of steps of program development increases and productivity decreases.

Accordingly, it is an object of the present invention to provide an integrated circuit that can use the same boot program even if the integrated circuits operate at different internal clock frequencies.

[0007]

An integrated circuit according to claim 1, wherein a memory for storing a start program, an instruction executing means for executing the start program, and a serial communication means capable of executing serial communication with the outside. An oscillator that oscillates at a constant cycle, a clock generation unit that generates an internal clock, a counter unit that can count the internal clock, and a first input unit that inputs a signal necessary to control the counter unit. An input terminal, first holding means for holding a value of a first control signal set by the instruction execution means, and a signal output from the oscillator and a signal input from the first input terminal, the first control signal A first selection means for switching by a control signal and outputting the first input signal to the counter means, wherein the counter means comprises:
When the input signal is a signal output from the oscillator, the internal clock in a certain cycle of the oscillator is counted based on the signal, and the frequency of the internal clock is calculated from the count number of the counter means. Things.

According to the integrated circuit of the first aspect, it is possible to dynamically calculate the frequency of an unknown internal clock signal by using a signal output from an oscillator that oscillates at a known constant frequency. As a result, the same boot program can be used even for integrated circuits operating at different internal clock frequencies.

According to a second aspect of the present invention, there is provided an integrated circuit, comprising: a memory for storing a start-up program; an instruction execution unit for executing the start-up program; a serial communication unit capable of executing serial communication with the outside; An oscillator for generating an internal clock, a clock generating means for generating an internal clock, a counter means capable of counting the internal clock, a first input terminal for inputting a signal necessary for controlling the counter means, and the counter A second input terminal for inputting a signal necessary for controlling the means, a first holding means for holding a value of a first control signal set by the instruction execution means, and an output from the oscillator according to the first control signal And a signal input from the first input terminal to output a first input signal to the counter means.
Selecting means, and a second selecting means for switching between a signal output from the oscillator and a signal input from the second input terminal by the first control signal and outputting the signal as a second input signal to the counter means, The counter means outputs a second control signal at the timing of the first input signal and outputs the second control signal.
(2) a counter control unit that outputs a third control signal at the timing of the input signal; a counter that starts counting the internal clock by the second control signal; and a second holding unit that holds the value of the counter by the third control signal. Means,
The frequency of the internal clock is calculated from the value of the counter.

According to the integrated circuit of the second aspect, the same effect as that of the first aspect is obtained.

According to a third aspect of the present invention, in the integrated circuit according to the second aspect, the instruction execution means selects the first selection means and the second selection means to a signal output from the oscillator according to the start program. The first holding means is set so as to output the first control signal, and the counter means starts a counting operation by the counter with the signal selected by the first selecting means, and the second selecting means The value of the counter is changed to the second signal at the timing of the selected signal.
It is held by holding means.

According to the integrated circuit of the third aspect, the same effect as that of the second aspect is obtained.

According to a fourth aspect of the present invention, there is provided an integrated circuit, comprising: a memory for storing a start-up program; an instruction executing unit for executing the start-up program; a serial communication unit capable of executing serial communication with the outside; A first input terminal for inputting a signal used for communication, a clock generation unit for generating an internal clock, a counter unit capable of counting the internal clock, and a signal necessary for controlling the counter unit A second input terminal for inputting a signal, a first holding unit configured to hold a value of a first control signal set by the instruction execution unit, a signal input from the first input terminal by the first control signal, and 2 The signal input from the input terminal is switched to the counter means.
First selecting means for outputting as one input signal, wherein the counter means, when the first input signal is a signal inputted from the first input terminal, based on the signal, the counter at a certain period of the signal. The internal clock is counted, and the frequency of the internal clock is calculated from the count number of the counter means.

According to the integrated circuit of the fourth aspect, it is possible to dynamically calculate the frequency of an unknown internal clock signal by inputting a known constant frequency pulse from an external input terminal. As a result, the same boot program can be used even for integrated circuits operating at different internal clock frequencies.

According to a fifth aspect of the present invention, there is provided an integrated circuit, comprising: a memory for storing a start-up program; an instruction execution unit for executing the start-up program; a serial communication unit capable of executing serial communication with the outside; A first input terminal for inputting a signal for performing communication using the first communication terminal, a first output terminal for outputting a signal for performing communication using the serial communication unit, a clock generation unit for generating an internal clock, and counting the internal clock. A second input terminal for inputting a signal necessary for controlling the counter means, a third input terminal for inputting a signal required for controlling the counter means, A first control signal set by the instruction execution means and holding a value of the first control signal;
Holding means, and first selecting means for switching between a signal input from the first input terminal and a signal input from the second input terminal by the first control signal and outputting the signal as a first input signal to the counter means; Switching between a signal input from the first input terminal and a signal input from the third input terminal in accordance with the first control signal;
And a second control means for outputting a second control signal at the timing of the first input signal, and a third control signal for outputting a third control signal at the timing of the second input signal. , A counter that starts counting the internal clock by the second control signal, and a second that holds the value of the counter by the third control signal.
Holding means for calculating the frequency of the internal clock from the value of the counter.

According to the integrated circuit of the fifth aspect, the same effect as that of the fourth aspect is obtained.

According to a sixth aspect of the present invention, there is provided the integrated circuit according to the fifth aspect, wherein the instruction executing means is configured to execute the first one according to a start program.
The first holding means is set so as to output a first control signal for selecting the 1 selection means and the second selection means to a signal input from the first input terminal, and the counter means is selected by the first selection means. The counting operation is started by the counter in response to the signal, and the value of the counter is held in the second holding means at the timing of the signal selected by the second selecting means.

According to the integrated circuit of the sixth aspect, the same effect as that of the fifth aspect is obtained.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an integrated circuit according to a first embodiment of the present invention. The integrated circuit 100 includes an instruction memory 110, a serial interface 120, and an oscillator 1 oscillating at a certain frequency.
30, a 1-bit register 140, and a timer 150
An input terminal 160 for connecting the inside and the outside of the integrated circuit 100 when performing serial communication, an output terminal 161 for connecting the inside and outside of the integrated circuit 100 when performing serial communication, and a signal from the outside. For example, when the timer 150 is controlled by a signal from the external input unit 171, the input terminals 162 and 16 for connecting the inside and the outside of the integrated circuit 100 are connected.
3 and a signal output from the oscillator 130 when the enable signal output from the register 140 is 1,
Selector 180 that selects a signal input from input terminal 162 when the enable signal output from register 140 is 0, and selects a signal output from oscillator 130 when the enable signal output from register 140 is 1 When the enable signal output from the register 140 is 0, the selector 181 selects a signal input from the input terminal 163, the CPU 190, and the clock generator 1100. Is stored. The serial interface 120 includes a frequency divider 121.

The input signal 1 selected by the selector 180 is output to the timer 150. The input signal 2 selected by the selector 181 is output to the timer 150. The interrupt signal output from timer 150 is output to CPU 190. The internal clock generated by clock generator 1100 is output to frequency divider 121 and timer 150 inside serial interface 120.
The serial interface 120 performs serial communication with the external communication unit 170 via the input terminal 160 and the output terminal 161.

As shown in FIG. 2, the timer 150 includes a count control unit 200 and a counter 21 for performing a counting operation.
0 and a register 220 capable of storing the value of the counter 210.
The clock signal output from 00 is supplied to the counter 210. The output signal of the selector 180 is supplied to the count control unit 200 as the input signal 1. Selector 181
Is supplied as an input signal 2 to the count control unit 200. The count control unit 200 outputs a count permission signal to the counter 210 when detecting the rising edge of the input signal 1, and outputs a control signal to the register 220 when detecting the falling edge of the input signal 2. Counter 21
When the count permission signal is input to 0, the count operation is started by the internal clock supplied from the clock generator 1100. The register 220 stores the value of the counter 210 when the control signal is input. Register 220
When the value of the counter 210 is stored in the CPU, an interrupt signal is output.

The operation of the integrated circuit according to the first embodiment of the present invention configured as described above will be described. The operation starts when the CPU 190 executes the boot program 111 stored in the instruction memory 110. It is assumed that the register 140 is set to 0 at startup. The CPU 190 sets the register 140 to 1 according to the boot program 111, and then enters a wait state until an interrupt signal is input from the timer 150. The selector 180 selects a signal output from the oscillator 130 because the output of the register 140 is 1. Selector 181
Since the output of the register 140 is 1, the signal output from the oscillator 130 is selected. This allows the timer 150
Is input with a signal as shown in FIG. The count control unit 200 detects a rising edge of the input signal 1 and outputs a count permission signal. As a result, the counter 210 performs a counting operation by one every one cycle of the internal clock supplied from the clock generator 1100. Further, count control section 200 detects a falling edge of input signal 2 and outputs a control signal. As a result, the register 220 stores the value of the counter 210 at that time. At this time, an interrupt signal is output. The CPU 190 is a timer 150
When the interrupt signal is input, the value of the register 220 is read. Here, since both the input signal 1 and the input signal 2 are signals output from the oscillator 130, the counter 21
0 starts the counting operation from the rising edge of the signal output from the oscillator 130, and the register 220 stores the value of the counter 210 at that time on the falling edge of the signal output from the oscillator 130. 1
It is possible to know how many cycles of the internal clock have occurred during 30 half cycles of the output signal. Since the frequency of the oscillator 130 is known, the CPU 190 can calculate the frequency of the internal clock from the value of the register 220.

The CPU 190 sets an appropriate frequency division ratio in the frequency divider 121 according to the calculated frequency and communication speed. Thereby, the serial interface 120 is connected to the input terminal 16.
0, it is possible to perform serial communication with the external communication means 170 via the output terminal 161. After calculating the frequency of the internal clock, the CPU 190 sets 0 to the register 140.

Here, the count controller 200 outputs a count enable signal by detecting the rising edge of the input signal 1 and outputs a control signal by detecting the falling edge of the input signal 2. Input signal 1
The control signal may be output by detecting the falling edge of the input signal 2 and detecting the rising edge of the input signal 2.

(Embodiment 2) Although the unknown internal clock frequency can be calculated in the first embodiment of the present invention, an oscillator that oscillates at a constant frequency is required exclusively. Embodiment 2 solves this.

FIG. 4 is a block diagram of an integrated circuit according to the second embodiment of the present invention. The integrated circuit 400 includes an instruction memory 410, a serial interface 420,
A 1-bit register 430, a timer 440, an input terminal 450 for connecting the inside and the outside of the integrated circuit 400 when performing serial communication, and a connection between the inside and outside of the integrated circuit 400 when performing serial communication. An output terminal 451,
Input terminals 452 and 453 for connecting the inside and outside of the integrated circuit 400 when the timer is controlled by a signal from the outside, for example, a signal from the external input means 461;
When the enable signal output from the terminal 30 is 1, the signal input from the input terminal 450 is selected, and the register 430 is selected.
Input terminal 4 when the enable signal output from
A selector 470 for selecting a signal input from the input terminal 52;
A selector that selects a signal input from the input terminal 450 when the enable signal output from the register 430 is 1, and selects a signal input from the input terminal 453 when the enable signal output from the register 430 is 0. 471, the CPU 480, and the clock generator 49
The instruction memory 410 stores a boot program 411. The serial interface 420 includes a frequency divider 421. Selector 4
The input signal 1 selected by 70 is output to the timer 440. The input signal 2 selected by the selector 471 is output to the timer 440. The interrupt signal output from timer 440 is output to CPU 480. The internal clock generated by clock generator 490 is output to frequency divider 421 and timer 440 inside serial interface 420. The serial interface 420 performs serial communication with the external communication unit 460 via the input terminal 450 and the output terminal 451.

As shown in FIG. 2, the timer 440 includes a count control unit 200 and a counter 21 that performs a counting operation.
The clock generator 49 is composed of 0 and a register 220 capable of storing the value of the counter 210.
The clock signal output from 0 is supplied to the counter 210. The output signal of the selector 470 is supplied to the count control unit 200 as the input signal 1. The output signal of the selector 471 is supplied to the count control unit 200 as the input signal 2. When detecting the rising edge of the input signal 1, the count control unit 200 outputs the count permission signal to the counter 2.
10 to output a control signal to the register 220 when the falling edge of the input signal 2 is detected. Counter 210
When a count permission signal is input, the count operation is started by the internal clock supplied from the clock generator 490. The register 220 stores the value of the counter 210 when the control signal is input. When the value of the counter 210 is stored in the register 220, an interrupt signal is output.

The operation of the integrated circuit according to the second embodiment of the present invention configured as described above will be described. The operation starts when the CPU 480 executes the boot program 411 stored in the instruction memory 410. It is assumed that the register 430 is set to 0 at startup. The CPU 480 sets the register 430 to 1 according to the boot program 411, and then enters a wait state until an interrupt signal is input from the timer 440. The selector 470 selects a signal input from the input terminal 450 because the output of the register 430 is “1”. Selector 47
The output terminal of the register 430 is also 1 so that the input terminal 45
Select a signal input from 0. This allows timer 4
A signal as shown in FIG. The count control unit 200 detects a rising edge of the input signal 1 and outputs a count permission signal. Thus, the counter 21
“0” performs a counting operation by one every one cycle of the internal clock supplied from the clock generator 490. Further, count control section 200 detects a falling edge of input signal 2 and outputs a control signal. As a result, the register 220 stores the value of the counter 210 at that time. At this time, an interrupt signal is output. CPU 480 is timer 4
When an interrupt signal from 40 is input, the value of the register 220 is read. Here, since both the input signal 1 and the input signal 2 are signals input from the input terminal 450, the counter 210 starts the counting operation from the rising edge of the signal input from the input terminal 450, and
Will store the value of the counter 210 at that time at the falling edge of the signal input from the input terminal 450, and determine how many cycles the internal clock has performed during the half cycle of the input signal from the input terminal 450. It becomes possible to know.
By transmitting a pulse with a known frequency from the external communication means 460, the CPU 480 can calculate the frequency of the internal clock from the value of the register 220. CPU
480 sets an appropriate frequency division ratio in the frequency division 421 according to the calculated frequency and communication speed. Thus, the serial interface 420 can perform serial communication with the external communication unit 460 via the input terminal 450 and the output terminal 451. CPU 480 sets 0 in register 430 after calculating the frequency of the internal clock.

Here, the count controller 200 outputs the count enable signal by detecting the rising edge of the input signal 1 and outputs the control signal by detecting the falling edge of the input signal 2. Alternatively, the count control signal may be output by detecting the falling edge of the input signal 1, and the control signal may be output by detecting the rising edge of the input signal 2.

[0031]

According to the integrated circuit of the first aspect, it is possible to dynamically calculate the frequency of an unknown internal clock signal by using a signal output from an oscillator that oscillates at a known constant frequency. . As a result, the same boot program can be used even for integrated circuits operating at different internal clock frequencies.

According to the integrated circuit of the second aspect, the same effect as that of the first aspect is obtained.

According to the integrated circuit of the third aspect, the same effect as that of the second aspect is obtained.

According to the integrated circuit of the fourth aspect, the frequency of the unknown internal clock signal can be dynamically calculated by inputting a known constant frequency pulse from the external input terminal. As a result, the same boot program can be used even for integrated circuits operating at different internal clock frequencies.

According to the integrated circuit of the fifth aspect, the same effect as that of the fourth aspect is obtained.

According to the integrated circuit of the sixth aspect, the same effect as that of the fifth aspect is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of an integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a timer of the integrated circuit according to the first embodiment.

FIG. 3 is a diagram illustrating a correlation between an input signal 1 and an input signal 2 according to the first embodiment and an internal clock whose frequency is unknown.

FIG. 4 is a block diagram of an integrated circuit according to a second embodiment.

FIG. 5 is a block diagram of a conventional integrated circuit.

[Explanation of symbols]

 Reference Signs List 100 integrated circuit 110 instruction memory 111 boot program 120 serial interface 121 divider 130 oscillator 140 register 150 timer 160 input terminal 161 output terminal 162, 163 input terminal 170 external communication means 171 external input means 180, 181 selector 190 CPU 1100 clock generator 200 count control unit 210 counter 220 register 400 integrated circuit 410 instruction memory 411 boot program 420 serial interface 421 frequency divider 430 register 440 timer 450 input terminal 451 output terminal 452,453 input terminal 460 external communication means 461 external input means 470,471 Selector 480 CPU 490 clock generator 500 integrated circuit 510 instruction memo 511 boot program 520 serial interface 521 divider 530 timer 540 input terminal 541 output terminal 542 and 543 input terminal 550 external communication unit 551 external input unit 560 CPU 570 Clock Generator

Claims (6)

[Claims] 1. A memory for storing a startup program, an instruction execution unit for executing the startup program, a serial communication unit capable of executing serial communication with the outside, an oscillator oscillating at a constant cycle, and an internal clock. Clock generating means for generating, a counter means capable of counting the internal clock, a first input terminal for inputting a signal required for controlling the counter means, and a first input terminal set by the instruction executing means. A first holding unit for holding a value of the first control signal, a signal output from the oscillator and a signal input from the first input terminal are switched by the first control signal, and a first input signal is supplied to the counter unit. And a first selection unit that outputs the first input signal when the first input signal is a signal output from the oscillator. An integrated circuit, wherein the internal clock is counted at a certain cycle of the oscillator, and a frequency of the internal clock is calculated from a count number of the counter means. 2. A memory for storing a startup program, an instruction execution unit for executing the startup program, a serial communication unit capable of executing serial communication with the outside, an oscillator oscillating at a constant cycle, and an internal clock. Clock generating means for generating, a counter means capable of counting the internal clock, a first input terminal for inputting a signal necessary for controlling the counter means, and a first input terminal required for controlling the counter means A second input terminal for inputting a first signal, a first holding means for holding a value of a first control signal set by the command execution means, a signal output from the oscillator by the first control signal, and a first signal. Switch between the signal input from the input terminal and the counter means.
A first selecting means for outputting as an input signal, and switching between a signal output from the oscillator and a signal input from the second input terminal by the first control signal, and outputting the signal as a second input signal to the counter means. And a second selector, wherein the counter outputs a second control signal at the timing of the first input signal, and outputs a second control signal at the timing of the second input signal.
(3) a counter control unit that outputs a control signal, a counter that starts counting the internal clock according to the second control signal, and a second holding unit that holds a value of the counter according to the third control signal. An integrated circuit for calculating a frequency of an internal clock from a value of a counter. 3. The instruction execution means sets the first holding means to output a first control signal for selecting the first selection means and the second selection means to be a signal output from the oscillator, according to a start program, The counter means starts a count operation by a counter with a signal selected by the first selection means, and holds the value of the counter in a second holding means at a timing of a signal selected by the second selection means. 3. The integrated circuit according to 2. 4. A memory for storing a startup program, an instruction execution unit for executing the startup program, a serial communication unit capable of executing serial communication with the outside, and a signal for performing communication using the serial communication unit. First to enter
An input terminal, clock generation means for generating an internal clock, counter means capable of counting the internal clock, a second input terminal for inputting a signal required to control the counter means, and the command A first holding unit that is set by an execution unit and holds a value of a first control signal; and switches between a signal input from the first input terminal and a signal input from the second input terminal by the first control signal. First selecting means for outputting the first input signal to the counter means as a first input signal, wherein the counter means, when the first input signal is a signal input from the first input terminal, based on the signal, An integrated circuit which counts the internal clock in a certain cycle, and calculates the frequency of the internal clock from the count number of the counter means. 5. A memory for storing a startup program, an instruction execution unit for executing the startup program, a serial communication unit capable of executing serial communication with the outside, and a signal for performing communication using the serial communication unit. First to enter
An input terminal, a first output terminal for outputting a signal for performing communication using the serial communication unit, a clock generation unit for generating an internal clock, a counter unit capable of counting the internal clock, and the counter A second input terminal for inputting a signal necessary for controlling the means, a third input terminal for inputting a signal necessary for controlling the counter means, and a first input terminal set by the instruction execution means.
First holding means for holding a value of a control signal, and switching between a signal input from the first input terminal and a signal input from the second input terminal in accordance with the first control signal; First selection means for outputting as a signal,
A second control unit that switches between a signal input from the first input terminal and a signal input from the third input terminal according to the first control signal and outputs the signal as a second input signal to the counter unit;
Selecting means, wherein the counter means outputs a second control signal at the timing of the first input signal and outputs a second control signal at the timing of the second input signal.
(3) a counter control unit that outputs a control signal, a counter that starts counting the internal clock according to the second control signal, and a second holding unit that holds a value of the counter according to the third control signal. An integrated circuit for calculating a frequency of an internal clock from a value of a counter. 6. An instruction execution means for outputting a first control signal for selecting a first selection means and a second selection means to a signal input from a first input terminal according to a start program.
The holding means is set, and the counter means starts the counting operation by the counter with the signal selected by the first selecting means, and holds the value of the counter in the second at the timing of the signal selected by the second selecting means. 6. The integrated circuit according to claim 5, wherein said integrated circuit is held by a means.