JP2002270703A5 - - Google Patents

Description

Step 3: As shown in FIG. 5C, the conductive film 56 is etched into a long strip in the direction orthogonal to the element separation membrane 54 to form a gate electrode 56a as a word line (however, the etched region is on a paper surface). It is not shown because it is made on a plane parallel to it). Next, using the gate electrode 56a as a mask, P-type impurities such as boron are ion-implanted to form a source region and a drain region (the source region and the drain region are formed under both ends of the gate electrode in a direction perpendicular to the paper surface). So not shown).

Step 3: As shown in FIG. 1 (c), the conductive film 6 and the VDD film 7 are etched in a long strip in the direction orthogonal to the element separation film 4 to form the gate electrode 8 as a word line (however, the gate electrode 8 is formed as a word line). The etching area is made parallel to the paper surface, so it is not shown).

Step 4: As shown in FIG. 2A, a metal film made of an Al film or the like is formed on the interlayer insulating film 14, and the metal film is patterned to form an Al wiring 15 to be a bit wire.

This step is a step characteristic of the present invention. First, a metal film made of an Al film or the like is formed on the interlayer insulating film 14 at 500 nm, a titanium film is formed on the metal film at 70 nm, and then titanium knight is formed. A protective film formed by forming a ride film at 35 nm is formed, and these films are patterned to form an Al wiring 15 which becomes a bit wire. As described above, in the present invention, the protective film 17 is formed on the Al wiring 15, and when the interlayer insulating film is etched using the Al wiring 15 described later as a mask, the Al wiring 15 is etched by the protective film 17. The side wall depot 66 is not formed in the opening 65a of the interlayer insulating film as in the conventional case (see FIG. 7).

Step 5: As shown in FIG. 2B, a second interlayer insulating film 23 composed of a three-layer film of a silicon oxide film 20, an SOG film 21, and a silicon oxide film 22 is formed at 600 nm for flattening the entire surface. A metal film made of an Al film or the like is formed on the interlayer insulating film 23, and the metal film is patterned to form a second Al wiring 24.