JP2002261326A - Method of manufacturing gallium nitride based compound semiconductor device - Google Patents

Abstract

(57) Abstract: Provided is a method for recovering damage caused in a gallium nitride-based compound semiconductor by plasma etching and manufacturing a gallium nitride-based compound semiconductor device having good electric characteristics. SOLUTION: After partially etching a semiconductor layer in a plasma containing a reactive gas such as chlorine or boron trichloride,
After exposing the semiconductor layer exposed by the etching to an inert gas plasma, an electrode is formed on the semiconductor layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a gallium nitride-based compound semiconductor device, and more particularly to a gallium nitride-based compound semiconductor electronic device, a gallium nitride-based compound semiconductor light-emitting device, and a gallium nitride-based compound semiconductor light-receiving device. On how to do it.

[0002]

2. Description of the Related Art A gallium nitride-based compound semiconductor represented by In _x Ga _1-x N (0 ≦ x ≦ 1) is a direct transition type compound semiconductor in all regions and has a band gap of 3.4e.
Since it continuously changes from V to 1.9 eV, active research has been made on light emitting element materials from the ultraviolet region to orange. At present, this material is used as a light-emitting layer on a sapphire substrate and has a high brightness blue LED with a double heterostructure (App
l. Phys. Lett, 64 (1994) 1687) and a high-brightness green LED have been put to practical use. Also, recently, a continuous oscillation of the semiconductor laser to In x _Ga 1-x _N well layer of the light emitting layer fabricated on a sapphire substrate (Appl.Phys.Lett, 69 (1996) 4056 ) is realized.

[0003] _{Further, Al y Ga 1-y N} (0 ≦ y ≦
The gallium nitride-based compound semiconductor represented by 1) has a very large band gap of 3.4 eV or more in all regions, a large saturation electron transfer, a large breakdown voltage, and the like. It is expected to be applied to high frequency electronic devices, and has been actively studied. Recently,
HEM using _{Al y Ga 1-y N /} GaN heterostructures
T (Appl. Phys. Lett, 6 (1996) 1438) and HBT (Solid-Stat
eElectronics, 44 (2000) 239).

Since such a gallium nitride-based compound semiconductor is chemically stable, plasma etching using a chlorine-based gas is used for forming an electrode.
For example, a plasma etching method using boron trichloride (BCl ₃ ) (Appl. Phys. Lett, 66 (1995) 2475) has been reported. In addition, Japanese Patent Application Laid-Open No. H8-17803 discloses a plasma etching method using chlorine and silicon tetrachloride.

A conventional method of manufacturing a gallium nitride LED will be described with reference to a laminated structure shown in a sectional view of FIG. 18 and an LED electrode structure shown in a sectional view of FIG. First, as shown in FIG. 18, on a sapphire substrate 11, a low-temperature buffer layer 12, an n-type contact layer 13 made of n-GaN, a quantum well type active layer 14 made of InGaN / GaN, and a clad made of p-AlGaN Layer 15, p-
After forming a film having a laminated structure having a p-type contact layer 16 made of GaN in sequence, the following process is performed.

First, annealing is performed at a temperature of 400 to 800 ° C. for about 20 minutes to activate the p-type cladding layer.
Next, in order to form the n-type electrode 17, a resist is applied and patterned, and the n-type GaN layer is exposed by plasma etching using a chlorine-based gas, and Ti / Al / Au or the like is exposed on the surface. By vapor deposition, an n-type electrode 17 is formed. Next, in order to form the p-type electrode 18, a resist is applied again, patterning is performed, and Ni / Au or the like is deposited to form the p-type electrode 18. Further, in order to obtain an ohmic contact between the electrode metal and the gallium nitride-based compound semiconductor, heat treatment is performed at a temperature of about 400 to 700 ° C.

A method of manufacturing a conventional gallium nitride MODFET having a recess gate structure will be described with reference to a laminated structure shown in a sectional view of FIG. 20 and an electrode structure shown in a sectional view of FIG. First, on a sapphire substrate 21, a GaN low-temperature buffer layer 22, an i-GaN layer 23, an i-Al
_0.26 Ga _0.74 N layer 24, n ⁺ -Al _0.26 G
a _{0 . 74} N layer ^25, after forming a film of a laminated structure sequentially having n + -GaN layer 26 performs the following steps as shown.

First, isolation between elements is performed. Thereafter, a source electrode 28 and a drain electrode 29 are patterned by applying a resist, and Ti / Al (25/150 nm) is deposited to form the source electrode 28 and the drain electrode 29. Next, in order to form a gate electrode 27 having a recess gate structure, a resist is applied and patterned, and a groove is formed by plasma etching using a chlorine-based gas. Next, patterning for forming a gate electrode 27 by applying a resist is performed, and Pt / Ti / Au is formed.
(10/40/100 nm) and deposit the gate electrode 27.
To form

[0009]

In conventional electronic devices such as FETs, bipolar transistors, and diodes using gallium nitride-based compound semiconductors, and semiconductor light emitting devices such as LEDs and LDs, the semiconductor layer is etched to form electrodes. There is a need. Gallium nitride based compound semiconductors
Since it is chemically very stable, wet etching is difficult. Therefore, a plasma etching method using a reactive gas (reactive ion etching method) is generally employed.

However, in plasma etching, ions having a large kinetic energy collide with the film, so that crystal disorder and impurity contamination occur near the surface. Damage due to plasma etching causes deterioration of electrical characteristics and reduction of luminous efficiency.

Accordingly, the present invention is directed to a gallium nitride-based compound semiconductor element having good electrical characteristics, such as a gallium nitride-based compound semiconductor electronic device or a gallium nitride-based compound, which recovers damage caused in a gallium nitride-based compound semiconductor by plasma etching. It is an object of the present invention to provide a method for manufacturing a gallium nitride-based compound semiconductor device capable of manufacturing a semiconductor light-emitting device and a gallium nitride-based compound semiconductor light-receiving device.

[0012]

In order to achieve the above object, a gallium nitride-based compound semiconductor device of the present invention, that is, a gallium nitride-based compound semiconductor electronic device (FE)
T, bipolar transistors, diodes, etc.), gallium nitride-based compound semiconductor light emitting devices and gallium nitride-based compound semiconductor light-receiving devices (LED, LD) are manufactured by stacking gallium nitride-based compound semiconductors on a substrate. A method for manufacturing a gallium nitride-based compound semiconductor device, in which a part of a semiconductor layer is plasma-etched and an electrode is formed on the electrode contact gallium nitride-based compound semiconductor layer exposed by the etching, wherein a part of the semiconductor layer is chlorine-free. Or after etching in a plasma containing a reactive gas such as boron trichloride, the semiconductor layer exposed by the etching is exposed to an inert gas, for example, an inert gas plasma using a nitrogen gas or the like, more preferably Heat treatment at a temperature of 300 ° C or higher in an atmosphere containing an inert gas as a main component. After the inert gas plasma treatment and heat treatment al, it is characterized in that the electrodes are formed on the semiconductor layer.

The time of the heat treatment varies depending on the processing temperature. At a processing temperature of 700 ° C., the effect can be obtained in about 5 to 20 minutes. If the temperature is low, the processing time will be longer,
For example, at 500 ° C., a heat treatment of 40 minutes or more is preferable to obtain a sufficient effect, and at 300 ° C., a heat treatment of 5 hours or more is preferable to obtain a sufficient effect.

The gas species of the inert gas plasma treatment is as follows:
Nitrogen, helium, neon, krypton, xenon, hydrogen, or a mixed gas containing two or more of them is desirable. Further, even if a gas such as a chlorine-based gas, oxygen, water, perfluorocarbon, or nitrogen trifluoride is contained in the gas for the inert gas plasma treatment, it is preferable that the concentration of these gases be 3% or less. Electrical characteristics can be obtained.

When the inert gas plasma treatment is performed, the film exposed by the ions constituting the plasma is etched. However, in order to minimize the damage caused by the plasma, the power supplied to the plasma is reduced and the etching rate is reduced. Is preferably suppressed to 0.5 μm / hour or less.

According to the above-described manufacturing method, by performing the exposure treatment with the inert gas plasma after the plasma etching step, the exposed surface layer near the surface of the semiconductor layer containing a large amount of impurities and damage is removed. The electric characteristics between the semiconductor device and the electrode contact semiconductor layer are improved. Further, by performing a heat treatment at a temperature of 300 ° C. or more after the inert gas plasma exposure treatment, the electric characteristics between the electrode and the contact semiconductor layer are further improved. Although the cause of the effect of the heat treatment is not clear, it is considered that the crystallinity near the semiconductor surface has been recovered.

[0017]

EXAMPLE 1 FIG. 1 shows an example in which n-type GaN whose entire surface is plasma etched is used.
A Schottky diode having a structure shown in a sectional view was manufactured, and the diode characteristics were measured. Normally, Schottky diodes do not require plasma etching,
An ohmic electrode and a Schottky electrode are formed on the surface of the n-type GaN semiconductor layer.

The sapphire substrate 31 is formed by MOCVD.
A 30-nm-thick low-temperature buffer layer 32 and a Si-doped n-type GaN layer (layer thickness 2.5 μm, carrier density 2 × 1
0 to form a ^{1 7} cm ^-3) 33. Next, BCl ₃ and C
n ₂ as a reactive gas and the n-type GaN layer 33
nm plasma etching. The etching of the n-type GaN layer 33 was performed for about 25 minutes in an RF plasma having a total flow rate of the etching gas of 10 sccm, a pressure of 3 Pa, and an RF power of 10 W. After etching the n-type GaN layer with a thickness of 200 nm, the etching gas was continuously switched to N ₂ gas and exposed to nitrogen plasma at a pressure of 5 Pa and RF power of 3 W for about 5 minutes.

After the nitrogen plasma treatment, a resist is applied and patterned to form an ohmic electrode material Ti (25).
nm) / Al (150 nm) was deposited. Further, after removing and cleaning the resist and the like, heat treatment was performed at 700 ° C. for 1 minute in a nitrogen atmosphere in order to obtain an ohmic contact. N-type G which is an exposed electrode contact semiconductor layer
After the ohmic electrode 34 is formed on the aN layer 33, a resist is applied and patterning for forming a Schottky electrode is performed, and Pd (100 nm) of a Schottky electrode material is formed.
Was deposited to form a Schottky electrode 35. Finally,
The resist and the like were removed and washed.

IV of the Schottky diode fabricated
FIG. 2 shows the measurement results of the characteristics. In addition, for comparison, a Schottky diode manufactured without performing a plasma treatment on the n-type GaN layer and a Schottky diode manufactured without performing the plasma etching on the n-type GaN layer after performing plasma etching on the n-type GaN layer by 200 nm, respectively. I
FIG. 2 also shows the -V characteristics.

Further, Table 1 shows that a Schottky diode manufactured by the method of the present invention, a Schottky diode manufactured without nitrogen plasma treatment, and an as-grown n-type GaN without plasma etching of the n-type GaN layer were used. Ideality factor (n), Schottky barrier height (φ _b ) with the Schottky diode manufactured by
Shows the reverse voltage at a reverse current 0.1μA a _{(V R),} respectively. The calculation of the ideality factor and the Schottky barrier height was performed with an electrode area of 1.77 × 10 ⁻⁸ m ² and a Richardson constant of 2.64 × 10 ⁵ Am ⁻² K ⁻² .

[0022]

[Table 1]

As is clear from the comparison with the characteristics of a Schottky diode manufactured without etching from FIG. 2 and Table 1, in a Schottky diode manufactured without nitrogen plasma processing, damage due to plasma etching and the influence of impurities cause The diode ideality factor increases, the Schottky barrier height decreases, and the reverse current increases. On the other hand, in the Schottky diode manufactured by the method of the present invention, a result closer to the characteristics of the Schottky diode manufactured without etching is obtained as compared with the Schottky diode manufactured without the nitrogen plasma treatment. From this, it is clear that the manufacturing technique of the present invention reduces the damage caused at the GaN interface and the film by plasma etching and the adverse effect due to impurities.

According to the present embodiment, it is clear that the manufacturing technique of the present invention is effective not only for manufacturing Schottky diodes but also for manufacturing LEDs, LDs, and FETs that require plasma etching.

Example 2 As in Example 1, a low-temperature buffer layer 32 having a thickness of 30 nm was formed on a sapphire substrate 31 by MOCVD.
A doped n-type GaN layer (layer thickness 2.5 μm, carrier density 2 × 10 ¹⁷ cm ⁻³ ) 33 was formed. Next, BCl
N-type GaN 33 was etched by about 200 nm by plasma etching using ₃ and Cl ₂ as reactive gases.
For etching the n-type GaN 33, the total flow rate of the etching gas is 10 sccm, the pressure is 3 Pa, and the RF power is 10 W.
For about 25 minutes. After the n-type GaN etching of 200 nm was performed, the etching gas was continuously switched to N ₂ gas and exposed to nitrogen plasma at a pressure of 5 Pa and RF power of 3 W for about 5 minutes. After nitrogen plasma treatment,
Further, annealing was performed at 700 ° C. for 20 minutes in a nitrogen atmosphere.

After the annealing, a resist is applied and patterned to form an ohmic electrode material Ti (25n).
m) / Al (150 nm) is deposited, and after removing and cleaning the resist and the like, in order to obtain an ohmic contact,
Heat treatment was performed at 700 ° C. for 1 minute in a nitrogen atmosphere. After forming the ohmic electrode, a resist was applied and patterned for forming a Schottky electrode, Pd (100 nm) of a Schottky electrode material was deposited, and the resist and the like were removed and washed.

FIG. 3 shows the results of the IV characteristics of the Schottky diode manufactured by using the method of the present invention. For comparison, a Schottky diode manufactured by performing only an annealing process without performing a nitrogen plasma process after performing plasma etching of an n-type GaN layer and a Schottky diode manufactured without performing a plasma etching of an n-type GaN layer FIG. 3 also shows the IV characteristics of the above.

Further, Table 2 shows that the Schottky diode manufactured by the method of the present invention, the Schottky diode manufactured by performing only the annealing process without performing the nitrogen plasma process after the plasma etching of the n-type GaN layer, and the n-type Ga
As Grown n without plasma etching of N layer
Ideality factor (n) representing the diode characteristics between a Schottky diode and a Schottky diode fabricated using GaN
Schottky barrier height (φ _b ), reverse current 0.1 μA
Respectively reverse voltage _{(V R)} in the.

[0029]

[Table 2]

In FIG. 3 and Table 2, it is clear from the comparison with the characteristics of the Schottky diode manufactured without etching that the Schottky diode manufactured by performing only the annealing treatment without performing the nitrogen plasma processing after the etching is: Due to the damage due to plasma etching and the influence of impurities, the diode ideality factor increases, the Schottky barrier height decreases, and the reverse current increases. On the other hand, in the Schottky diode manufactured by the method of the present invention, a result equivalent to the characteristic of the Schottky diode manufactured without etching is obtained.

Table 3 shows the characteristics of the Schottky diode produced by replacing the nitrogen plasma treatment with a helium plasma treatment, a neon plasma treatment, a xenon plasma treatment, a krypton plasma treatment, a hydrogen plasma treatment and a mixed gas plasma treatment thereof. Is shown. The process conditions other than the gas type are all the same.

[0032]

[Table 3]

From the results shown in Table 3, it was confirmed that the nitrogen plasma treatment was effective even when it was replaced with helium plasma treatment, neon plasma treatment, xenon plasma treatment, krypton plasma treatment, hydrogen plasma treatment, or a mixed gas plasma treatment. Was. From these facts, it is clear that the manufacturing technique of the present invention reduces the damage caused in the GaN interface and the film by plasma etching and the adverse effect due to impurities.

According to the present embodiment, it is clear that the manufacturing technique of the present invention is effective not only for manufacturing Schottky diodes but also for manufacturing LEDs, LDs, FETs and the like that require plasma etching.

Example 3 A gallium nitride-based compound semiconductor LED as shown in the plan view of FIG. 4 and the cross-sectional view of FIG. 5 (cross-sectional view taken along line VV of FIG. 4)
Was prepared. First, a 30-nm-thick low-temperature buffer layer 42 and a Si film were formed on a sapphire substrate 41 by MOCVD.
Doped n-type GaN layer (2.5 nm) 43, InGaN
(3 nm) / GaN (7 nm) three-period quantum well active layer 4
4. Mg-doped AlGaN cladding layer (20 nm) 4
5. Mg-doped GaN contact layer (200 nm) 46
Was formed.

Next, Ni as a mask for plasma etching is vapor-deposited on the entire surface, a resist is applied and patterned to form an n-type electrode, unnecessary portions are removed by wet etching, and a part of the film is removed. The n-type GaN layer 43 was exposed by plasma etching. Plasma etching is performed by flowing BCl ₃ gas at a flow rate of 10 sccm and a pressure of 3 Pa,
The test was performed for 7 minutes under the condition of RF power of 100 W. The etching depth at this time is 450 nm. After etching with BCl ₃ plasma, the gas was switched to N ₂ and the pressure
It was exposed to nitrogen plasma of Pa and RF power of 3 W for 5 minutes.
The sample was taken out of the etching apparatus, and Ni was removed by wet etching.
A heat treatment for 0 minutes was performed. After the heat treatment, patterning for forming an n-type electrode is performed, and the n-type electrode Ti (15n
m) / Al (80 nm) / Ni (10) / Au (80n
m) 47 was formed.

After forming the n-type electrode 47, the resist was removed. Note that heat treatment for alloying the n-type electrode and the n-type semiconductor may be performed as needed. Next, a resist was applied to perform patterning for forming a p-type electrode. After forming a p-electrode Ni (10 nm) / Au (150 nm) 48 by vapor deposition, the resist was removed. The heat treatment for alloying the p-type electrode 48 and the p-type semiconductor may be performed as needed.

Further, in the present embodiment, n
In order to evaluate between the mold electrodes, a test pattern (test electrode) of the LED structure electrode and the n-type electrode was simultaneously formed.
FIG. 6 is a plan view of the test electrode, and FIG. 7 is a cross-sectional view taken along the line VII-VII of FIG.

FIG. 8 shows the I of the LED manufactured by the method of the present invention.
-V curve (solid line) and IV of LED manufactured by the conventional method
Curve (dashed-dotted line). The conventional LED has p
This was fabricated by performing the Mg activation heat treatment of the mold layer before the electrode forming process, without performing the nitrogen plasma treatment after the plasma etching and the heat treatment at 700 ° C. in the nitrogen atmosphere. In the conventional method, aqua regia cleaning is performed after the plasma etching process. In the LED manufactured by the method of the present invention, the p-type layer was not subjected to the Mg activation heat treatment before the electrode forming process. As is clear from the results of FIG. 8, it was found that the forward voltage was improved by 0.7 V from 4.5 V to 3.8 V by manufacturing the LED by the method of the present invention.

From the evaluation using the test pattern of the n-type electrode shown in FIGS. 6 and 7, it was found that the resistance between the electrodes was improved from 17.6Ω to 10.1Ω by using the method of the present invention. Was. From this example, it is clear that the manufacturing method of the present invention is very effective for forming ohmic contacts.

Example 4 An npn bipolar transistor was manufactured through the steps shown in the sectional views of FIGS. 9 to 12, and its evaluation was performed. First, MOC
By the VD method, a film thickness of 30 n is formed on the sapphire substrate 51.
m low-temperature buffer layer 52, 2 μm-thick n ⁺ -GaN
Sub-collector layer (Si concentration 1 × 10 ¹⁹ cm ⁻³ ) 5
3. An n ⁻ -GaN collector layer (carrier density: 6 × 10 ¹⁶ cm ⁻³ ) 54 having a thickness of 700 nm, and a thickness of 100 nm
GaN base layer (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) 5
5. 500 nm-thick n ⁺ -GaN emitter layer (Si
Concentrations of 1 × 10 ¹⁹ cm ⁻³ ) 56 were sequentially formed (FIG. 9).

Next, a Ni (nickel layer) 57 serving as a mask for plasma etching is vapor-deposited on the entire surface, a resist is applied to form a collector electrode, patterning is performed, and unnecessary portions of Ni 57 are removed by wet etching. Then, a part of the film was subjected to plasma etching to expose the GaN subcollector layer 53. Plasma etching is B
This was performed for about 17 minutes under the conditions of a flow of Cl ₃ gas at 10 sccm, a pressure of 3 Pa, and an RF power of 100 W. The etching depth at this time is 1.11 μm (FIG. 10).

After etching to a predetermined depth, the base
Apply resist and pattern to form
Is performed, and Ni57 is removed by wet etching.
A portion of the film is plasma etched to form a GaN base layer 55
Was exposed. Plasma etching is BCl₃Gas
Flow at 10sccm, pressure 3Pa, RF power 100W
Approximately 8 minutes under the above conditions. The etching depth at this time is 51
0 μm. BCl ₃Finish etching by plasma
After completion, gas is N₂, Pressure 5Pa, RF power
It was exposed to a 3 W nitrogen plasma for 5 minutes (FIG. 11). Sample
Take it out of the etching equipment and remove Ni57
And removed in a nitrogen atmosphere at 700 ° C. for 20 minutes.
For a minute.

Finally, a resist is applied and patterned, and a collector electrode 58, an emitter electrode 59, and a base electrode 60 are formed by vapor deposition (FIG. 1).
2). At this time, the structure of the collector electrode 58 and the emitter electrode 59 is Ti (15 nm) / Al (80 nm) /
Ni (10 nm) / Au (80 nm), and the structure of the base electrode 60 is Ni (10 nm) / Au (150 n).
m). The heat treatment for alloying the electrodes may be performed as needed.

In this embodiment, a test electrode shown in a plan view in FIG. 13 was formed at the same time to check the ohmic properties of the base electrode 60.

FIG. 14 shows the IV characteristics between the test electrodes 60 formed on the base layer 55. Compared with the sample manufactured by the conventional method (dashed line), the method of the present invention (solid line) is used. It is clear that the ohmic contact properties have been greatly improved. According to the conventional technique, the heat treatment for activating Mg is performed in a nitrogen atmosphere before forming the Ni mask.
The plasma treatment and the heat treatment were not performed after the etching at 20 ° C. for 20 minutes.

Table 4 shows the current amplification factors of the npn transistor manufactured by the conventional method and the npn transistor manufactured by the method of the present invention. The transistor was measured with a grounded emitter, a base current of 1 mA, and a collector-emitter voltage of 12 V. By adopting the manufacturing technique of the present invention, the current amplification factor has been dramatically improved from 1.7 times to 4.2 times.

[0048]

[Table 4]

From the above results, it is clear that the present invention is effective for manufacturing a bipolar transistor. It is needless to say that the method of the present invention is effective for manufacturing heterobipolar transistors and diodes.

Example 5 A recess gate structure type modulation doped FET (MODFET) was manufactured by the steps shown in the sectional views of FIGS. 15 to 17, and its evaluation was performed. First, by MOCVD method,
A low-temperature buffer layer 62 having a thickness of 30 nm, an i-GaN layer 63 having a thickness of 2.5 μm, and a film thickness of 10
nm i-Al _0.26 Ga _0.74 N spacer layer 6
4. n ⁺ -Al _0.26 Ga _0.74 N with a thickness of 20 nm
Layer (Si concentration 1 × 10 ¹⁸ cm ⁻³ ) 65, film thickness 20 n
m n ⁺ -GaN layer (Si concentration 1 × 10 ¹⁹ cm ⁻³ )
66 were sequentially formed (FIG. 15).

First, isolation between elements is performed. Next, a resist was applied and patterned, and a source electrode 67 and a drain electrode 68 were formed by vapor deposition. Thereafter, unnecessary portions were removed by lift-off. Next, a resist was applied to perform patterning for forming a gate electrode 69 having a recess gate structure, and a part of the film was plasma-etched to expose the n ⁺ -Al _0.26 Ga _0.74 N layer 65. (FIG. 16). In the plasma etching, BCl ₃ gas is
The flow was performed at 0 sccm, the pressure was set to 3 Pa, and the RF power was set to 10 W for about 10 minutes. The etching depth at this time is 30
nm. After the etching with BCl ₃ plasma was completed, the gas was switched to N ₂ , the pressure was 5 Pa, and the RF power was 3
Exposure to W nitrogen plasma for 5 minutes. Remove the sample from the etching device, remove the resist, and in a nitrogen atmosphere,
Heat treatment was performed at 500 ° C. for 40 minutes. Next, a resist was applied to perform patterning for forming the gate electrode 69, and the gate electrode 69 was formed by vapor deposition.

The structure of the source electrode 67 and the drain electrode 68 is Ti (25 nm) / Al (150 nm), and the structure of the gate electrode 69 is Pt (10 nm) / Ti (40
nm) / Au (100 nm). The gate structure was 2 μm in gate length and 15 μm in gate width (FIG. 1).
7).

Table 5 shows the maximum mutual conductance between the MODFET manufactured by the conventional method and the MODFET manufactured by using the method of the present invention, in which the nitrogen plasma treatment and the heat treatment in a nitrogen atmosphere (500 ° C., 40 minutes) are not performed after the etching. And drain-source current. The source-
The drain current is the current at the time of the maximum transconductance.

[0054]

[Table 5]

As is clear from Table 5, the maximum transconductance of the MODFET is significantly improved to 146 mS / mm by employing the method of the present invention.

[0056]

As described above, according to the method of manufacturing a gallium nitride-based compound semiconductor device of the present invention, damage caused on a gallium nitride-based compound semiconductor by plasma etching is recovered, and the nitrided semiconductor having good electric characteristics is obtained. A gallium-based compound semiconductor device can be manufactured.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of a Schottky diode manufactured in Example 1.

FIG. 2 is a diagram showing an IV characteristic of the Schottky diode manufactured in Example 1.

FIG. 3 is a diagram showing IV characteristics of a Schottky diode manufactured in Example 2.

FIG. 4 is a plan view showing a gallium nitride-based compound semiconductor LED manufactured in Example 3.

FIG. 5 is a sectional view taken along line VV of FIG. 4;

FIG. 6 is a plan view of a test electrode manufactured in Example 3.

FIG. 7 is a sectional view taken along line VII-VII of FIG. 6;

8 is a diagram showing an IV curve of a gallium nitride-based compound semiconductor LED manufactured in Example 3. FIG.

FIG. 9 is a cross-sectional view showing a first manufacturing step of an npn bipolar transistor in Example 4.

FIG. 10 is a cross-sectional view showing a second manufacturing step of the npn bipolar transistor in the fourth embodiment.

FIG. 11 is a sectional view showing a third manufacturing step of the npn bipolar transistor in the fourth embodiment.

FIG. 12 is a sectional view of the npn bipolar transistor manufactured in Example 4.

FIG. 13 is a plan view of a test electrode manufactured in Example 4.

FIG. 14 is a diagram showing the IV characteristics of the npn bipolar transistor manufactured in Example 4.

FIG. 15 is a cross-sectional view showing a first manufacturing step of the recessed gate structure type modulation doped FET in Example 5.

FIG. 16 is a cross-sectional view showing a second manufacturing step of the recessed gate type modulation doped FET in the fifth embodiment.

FIG. 17 is a sectional view of a recessed gate structure type modulation doped FET manufactured in Example 5.

FIG. 18 is a cross-sectional view showing a laminated structure of a gallium nitride-based LED.

FIG. 19 is a cross-sectional view showing an electrode structure of a gallium nitride-based LED.

FIG. 20: Gallium nitride MODF with recess gate structure
It is sectional drawing which shows the laminated structure of ET.

FIG. 21: Gallium nitride based MODF with recess gate structure
It is sectional drawing which shows the electrode structure of ET.

[Explanation of symbols]

31: sapphire substrate, 32: low-temperature buffer layer, 33
... Si-doped n-type GaN layer, 34 ... Ohmic electrode, 3
5 Schottky electrode 41 Sapphire substrate 42
Low-temperature buffer layer, 43... Si-doped n-type GaN layer, 4
4 ... InGaN / GaN three-period quantum well active layer, 45 ...
Mg-doped AlGaN cladding layer, 46 ... Mg-doped G
aN contact layer, 47 ... n-type electrode, 48 ... p electrode, 5
1: sapphire substrate, 52: low temperature buffer layer, 53:
n ⁺ -GaN sub-collector layer, 54 ... n ^-- GaN collector layer, 55 ... GaN base layer, 56 ... n ⁺ -Ga
N emitter layer, 57 Ni (nickel layer), 58 collector electrode, 59 emitter electrode, 60 base electrode, 61 sapphire substrate, 62 low-temperature buffer layer,
63 ... i-GaN layer, 64 ... i-Al _0.26 Ga
_0.74 N spacer layer, 65... N ⁺ -Al _0.26 G
a _0.74 N layer, 66 ... n ⁺ -GaN layer, 67 ... source electrode, 68 ... drain electrode, 69 ... gate electrode

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/737 H01L 29/72 H 21/331 29/80 F 21/338 29/812 (72) Inventor Takashi Egawa Nagoya Institute of Technology, Nagoya Institute of Technology, Showa-ku, Nagoya City, Aichi Prefecture (72) Inventor Hiroyasu Ishikawa Nagoya Institute of Technology, Nagoya City, Aichi Prefecture, Nagoya Institute of Technology (72) Inventor Nakao Akutsu 1, Nishishinbashi, Minato-ku, Tokyo -16-7 Nippon Sanso Co., Ltd. (72) Isao Matsumoto Inventor 1-16-7 Nishi-Shimbashi, Minato-ku, Tokyo F-term (reference) 4M104 AA04 BB05 BB06 BB07 BB14 CC01 CC03 DD22 DD34 DD68 DD71 DD78 DD83 FF03 FF17 FF31 GG03 GG04 GG06 GG12 HH11 HH15 HH17 5F003 BA92 BC08 BE90 BH08 BH99 BM02 BM03 BP12 BP32 BZ01 BZ03 5F004 DA01 DA04 DA11 DA17 DA22 DA24 DA26 DB19 EB04 FA01 FA08 A01A44 A 12 CA22 CA40 CA49 CA57 CA65 CA73 CA75 CA77 CA82 CA92 CA99 5F102 FA02 GB01 GC01 GD01 GJ10 GK04 GK08 GL04 GM04 GN04 GR04 GT03 HC01 HC15

Claims (3)

[Claims] 1. A gallium nitride-based compound in which a gallium nitride-based compound semiconductor is laminated on a substrate, a part of the laminated semiconductor layer is plasma-etched, and an electrode is formed on the etched electrode contact semiconductor layer. In a method for manufacturing a semiconductor element, after partially etching the semiconductor layer in a plasma containing a reactive gas such as chlorine or boron trichloride, the semiconductor layer exposed by the etching is exposed to an inert gas plasma. And forming an electrode on the semiconductor layer. 2. The method of manufacturing a gallium nitride-based compound semiconductor device according to claim 1, wherein a heat treatment is further performed at 300 ° C. or more after said inert gas plasma treatment. 3. The gas used in the inert gas plasma treatment is one of nitrogen, helium, neon, krypton, xenon, and hydrogen, or a mixed gas of two or more of these. The method for producing a gallium nitride-based compound semiconductor device according to claim 1.