JP2002231906A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a connection hole 27 for connecting a storage node to a semiconductor substrate 1 to a bit line 24 in self-alignment manner, in a DRAM semiconductor device that provides the bit line 24 in a direction for crossing a word line 17 in the upper layer of the word line 17, and additionally provides the storage node of a capacitor in the farther upper layer thereof. SOLUTION: An opening 21 opened in self-alignment manner is buried between the word lines 18 for forming a plug electrode 22. By reactive ion etching using an Ar/C5F8/CH2F2 gas, interlayer oxide films 23 and 26 are opened in self-alignment manner to the bit line 24 covered with a silicon nitride film 25 for forming the connection hole 27 that reaches the plug electrode 22. Contact area is secured by allowing the end section of the connection hole 27 to deviate from the plug electrode 22 in a direction parallel with a bit line wiring direction when the connection hole is opened. Etching stop is carried out by a silicon nitride film 19 for covering the work line 17 in a lower layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a connection hole in a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art With miniaturization and high integration of semiconductor devices,
The margin for misalignment in the photomechanical process has decreased. Therefore, as a method of forming a contact hole, an etching mask pattern larger than the actual contact hole size is used, and a lower layer pattern such as a wiring layer is covered and protected by a film serving as an etching stopper, so that a self-aligned opening is performed. Self alignment (S
AC) system is drawing attention. In this method, a fine contact hole can be formed between the wiring layers (lower layer patterns), and is used for forming a bit line contact hole of a DRAM where high integration is remarkable. FIG.
Discloses a conventional semiconductor device structure and manufacturing method for a DRAM.
FIG. 4 is a cross-sectional view showing the memory cell of FIG.

Hereinafter, a conventional method for manufacturing a semiconductor device will be described with reference to the drawings. First, a semiconductor substrate 1 (hereinafter, substrate 1)
After forming an isolation oxide film 2 for element isolation, a gate electrode 4 composed of a silicon nitride film / silicide film / polysilicon film is formed via a gate oxide film 3. The gate electrode 4 is a thin line pattern which becomes a word line of the memory cell and is formed at a predetermined interval. Next, after a diffusion layer 5 is formed on the substrate 1 on both sides of the gate electrode 4, the surface and side walls of the gate electrode 4 are covered with a silicon nitride film 6 to form an interlayer oxide film 7. The interlayer oxide film 7 is subjected to a flattening process after being formed.

Next, a contact hole 8 reaching the diffusion layer 5 is opened in the interlayer oxide film 7 with respect to the gate electrode 4 by the SAC method. This is performed by, for example, etching the interlayer oxide film 7 using the silicon nitride film 6 covering the gate electrode 4 as an etching stopper film by reactive ion etching using a fluorocarbon-based gas such as Ar / C ₄ F ₈ gas. A doped polysilicon film 9 is buried in the contact hole 8 by using the CMP technique. Next, a bit line 10 connected to the doped polysilicon film 9 is formed.
To form The bit lines 10 are fine line patterns formed at predetermined intervals in a direction intersecting with the word lines (gate electrodes 4). Next, an interlayer oxide film 11 is formed on the entire surface covering the bit line 10, the interlayer oxide films 11 and 7 are opened, and a storage node contact hole 12 is opened. Subsequently, a storage node 13 connected to the diffusion layer 5 of the substrate 1 via the storage node contact hole 12 is formed. Next, although not shown, a capacitor insulating film and a cell plate serving as a capacitor upper electrode are further formed, and then an interlayer oxide film is formed on the entire surface to form an electrode wiring layer. Thereafter, predetermined processing is performed to complete the semiconductor device.

[0005]

Since the conventional DRAM is configured as described above, the contact hole 8 for connecting the bit line 10 is formed by the SAC method for the gate electrode 4. Formation of the contact hole 12 for connecting the storage node 13
The opening was formed by etching using an ordinary fine resist pattern instead of the SAC method. This is because, in the SAC method, since the etching has a selectivity with respect to the etching stopper film, the contact hole tends to be tapered due to the deposition of a reaction product during the etching. This is because, when the depth is deep, a reaction product is deposited on the bottom of the hole to stop etching, and a contact area cannot be secured. Such a storage node contact hole 12 is formed between the diffusion layer 5 between the gate electrodes 4.
It is formed on the upper layer, but is disposed between the bit lines 10 arranged in a direction crossing the gate electrode 4 in the upper layer. Therefore, in order to prevent a short circuit, the hole 12 and the gate electrode 4
In addition to this, a dimensional margin between the hole 12 and the bit line 10 is required, and it is difficult to form the hole with high reliability due to the limit of the fine hole pattern formation in lithography and the limit of the alignment.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has a deep etching depth, such as a storage node contact hole, and a first wiring layer and an upper layer. It is desirable to form a connection hole provided with sufficient dimensional margin with each of the two types of wiring layers with the second wiring layer with good controllability and to secure a contact area to reduce contact resistance. Aim.

[0007]

Means for Solving the Problems Claim 1 according to the present invention.
In the semiconductor device described above, a first wiring layer having a first silicon nitride film formed on a surface and a side wall on a semiconductor substrate; and a first interlayer oxide formed on the entire surface of the first wiring layer. A plug electrode formed by embedding an opening that is opened in a self-aligned manner with respect to the first wiring layer in the first interlayer oxide film; and a plug electrode formed on the entire surface of the plug electrode. Two interlayer oxide films, a second wiring layer provided on the second interlayer oxide film and having a second silicon nitride film formed on the surface and side walls thereof, and a second wiring layer formed on the entire surface of the second wiring layer. A third interlayer oxide film formed; and a connection hole formed in the third interlayer oxide film in a self-aligned manner with respect to the second wiring layer and reaching the plug electrode.

According to a second aspect of the present invention, there is provided a semiconductor device according to the first aspect, wherein the first wiring layer and the second wiring layer are linear patterns arranged in a direction crossing each other. The hole is formed such that an end of the second wiring layer in a direction parallel to the wiring direction steps off the plug electrode, and the first silicon nitride film is opened as an etching stopper film at a portion where the step is removed.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the first wiring layer is a gate electrode, the second wiring layer is a bit line, and the connection hole is a storage electrode. This is for connecting a node to a semiconductor substrate via a plug electrode.

According to a fourth aspect of the present invention, there is provided a semiconductor device, comprising: a gate electrode having a first silicon nitride film formed on a surface and a side wall of the semiconductor substrate and disposed linearly at predetermined intervals; A first interlayer oxide film formed on the entire surface of the gate electrode, and a plug electrode formed by filling the first interlayer oxide film with an opening that is self-aligned with respect to the gate electrode. A second interlayer oxide film formed on the entire surface of the plug electrode, and linearly disposed on the second interlayer oxide film at predetermined intervals in a direction intersecting with the gate electrode; A bit line having a second silicon nitride film formed on a side wall, a third interlayer oxide film formed on the entire surface of the bit line, and a third interlayer oxide film formed in a self-aligned manner with respect to the bit line. A connection hole opened to the plug electrode to reach the plug electrode. Diameter in the direction parallel to the wiring direction of the bit lines in the connection hole is longer than the diameter of the direction parallel to the wiring direction of the gate electrode.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to any one of the first to fourth aspects.
The openings and the connection holes that are opened in a self-aligned manner are formed by a reactive ion etching process using a fluorocarbon-based gas and having an etching selectivity to a silicon nitride film.

According to a sixth aspect of the present invention, in the method for manufacturing a semiconductor device according to the fifth aspect, Ar / C ₅ F ₈ / CH _{2 is used} as a fluorocarbon-based gas in the reactive ion etching process at the time of forming the connection hole. it is to use an F ₂ gas.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention for a memory cell of a DRAM. FIG. 1A is a cross-sectional view cut in parallel to the wiring direction of a gate electrode 17 serving as a word line of a memory cell, and FIG. 1B is a cross-sectional view of the gate electrode 17 (the direction of the bit line 24). Wiring direction)
FIG. For convenience, illustration of the capacitor portion and the upper layer is omitted.

In FIG. 1, reference numeral 14 denotes a semiconductor substrate (hereinafter, referred to as a substrate 14), 15 denotes an isolation oxide film for element isolation,
Reference numeral 16 denotes a gate oxide film, 17 denotes a gate electrode (word line) as a first wiring layer which is formed on the substrate 14 via the gate oxide film 16 and is linearly arranged at predetermined intervals, and 18 denotes a substrate. Reference numeral 19 denotes a diffusion layer formed on the first silicon nitride film formed on the surface and side walls of the gate electrode 17;
Is the gate electrode 1 covered with the first silicon nitride film 19
7, a first interlayer oxide film 21 formed on the entire surface
An opening formed in the interlayer oxide film 20 by the SAC method with respect to the gate electrode 17; a plug electrode 22 formed by embedding a doped polysilicon film in the opening 21 to be connected to the diffusion layer 18 of the substrate 1; Reference numeral 23 denotes a second interlayer oxide film formed on the entire surface of the first interlayer oxide film 20, and reference numeral 24 denotes a second interlayer oxide film formed on the second interlayer oxide film 23 at predetermined intervals in a direction intersecting the gate electrode 17. Bit line 25 as a second wiring layer provided, 25 is a second silicon nitride film formed on the surface and side wall of bit line 24, 26 is second silicon nitride film 25
A third interlayer oxide film 27 formed on the entire surface of the bit line 24 covered with the oxide film 27 is connected to the third interlayer oxide film 20 and opened to the bit line 24 by the SAC method to reach the plug electrode 22. The hole is a storage node contact hole for connecting a storage node formed in a later process.

A method of manufacturing the semiconductor device having the above structure will be described below with reference to FIGS. FIG. 2 is a cross-sectional view cut in parallel to the wiring direction of the bit line 24 as in FIG. 1B, and FIG. 3 is a cross-sectional view cut in parallel to the wiring direction of the gate electrode 17 as in FIG. FIG. First,
As shown in FIG. 2A, after an isolation oxide film 15 is formed on a substrate 14 to perform element isolation, a gate electrode 17 is formed via a gate oxide film 16. The gate electrode 17 is a thin line pattern which is formed at a predetermined interval and becomes a word line of a memory cell, and uses a laminated film 17 in which a low-resistance refractory metal film or a silicide film thereof is formed on a polysilicon film. Further, a silicon nitride film 19a is formed thereon to a thickness of 70 nm.
After being formed with a film thickness of about a degree, patterning is performed. Next, using the gate electrode 17 and a resist pattern (not shown) as a mask, a diffusion layer 18 serving as a source / drain region is formed on the substrate 1 by ion implantation. Thereafter, a silicon nitride film 19b is deposited on the entire surface to a thickness of about 50 nm by, for example, a low pressure CVD method, and a first interlayer oxide film 20 made of a BPTEOS film or a TEOS film is deposited on the entire surface. The surface is flattened by etch back or CMP. The ion implantation for forming the diffusion layer 18 may be performed after the formation of the silicon nitride film 19b.

Next, as shown in FIG. 2B, an opening 21 is formed in the first interlayer oxide film 20 with respect to the gate electrode 17 by the SAC method. This is, for example, Ar / C ₄ F ₈
By reactive ion etching using a fluorocarbon-based gas such as a gas, the first silicon oxide film 19 (19a, 19b) covering the gate electrode 17 is used as an etching stopper film, and the first interlayer oxide film 20 is formed using a resist mask. Anisotropic etching is performed, and subsequently, the silicon nitride film 19b is removed by anisotropic etching to form an opening 21 reaching the diffusion layer 18. In this case, the silicon nitride film 19b at the bottom of the opening was removed when the opening 21 was formed.
After the formation of the silicon nitride film 19b, the first interlayer oxide film 20 is formed.
May be removed by etch-back before forming.

Next, as shown in FIG. 2C, a polysilicon film doped with phosphorus at a high concentration is deposited on the entire surface by burying the opening 21 and then the first interlayer oxide film 20 is etched back. The upper polysilicon film is removed and the plug electrode 2 is removed.
Then, a second interlayer oxide film 23 made of a TEOS film is deposited on the entire surface. Next, the second interlayer oxide film 2
3, a contact hole (not shown) for a bit line is opened. In this case, the plug electrode 22 is formed below both the contact hole for the bit line and the contact hole for the storage node, and the contact hole for the bit line reaches the plug electrode 22 by anisotropic etching. It is formed as follows. The plug electrode 22 for the contact hole for the bit line is not formed, and the bit line contact hole is opened with respect to the gate electrode 17 by the SAC method until reaching the diffusion layer 18 as shown in FIG. You can also.

Next, as shown in FIG. 3, a bit line 24 which is a fine line pattern formed at a predetermined interval in a direction intersecting with the word line (gate electrode 17) is formed, and the first and second bit lines 24 are formed on the surface and the side wall. 2 silicon nitride films 25 (25a, 25a).
b) is formed. The bit line 24 is formed by using a laminated film 24 in which a low-resistance refractory metal film or its silicide film is formed on a polysilicon film, and further forming a silicon nitride film 25a thereon, followed by patterning. Then, a silicon nitride film 25b is deposited on the entire surface to a thickness of about 50 nm, and the silicon nitride film 25b is provided on the side wall of the bit line 24 by etching back.

Next, a BPTEOS film or TE
After depositing the third interlayer oxide film 26 made of an OS film, a surface flattening process is performed by annealing, etchback, CMP, or the like. Next, on the third interlayer oxide film 26,
A contact hole 27 for connecting a storage node formed in a later step is opened to the bit line 24 by the SAC method. The formation of the contact hole 27 will be described in detail below with reference to FIG.

First, a resist pattern (not shown) is formed, and using the resist pattern as a mask, reactive ion etching using Ar / C ₅ F ₈ / CH ₂ F ₂ gas as a fluorocarbon-based gas is carried out to about several tens mTorr. At a pressure of about Rf1500 W, the third interlayer oxide film 26 and the second interlayer oxide film 23 thereunder are anisotropically etched using the second silicon nitride film 25 covering the bit line 24 as an etching stopper film, thereby forming a plug. A contact hole 27 reaching the electrode 22 is opened. In this etching, the planar shape of the contact hole 27 is such that the radial dimension in the direction parallel to the wiring direction of the bit line 24 is the gate electrode 1.
7 is longer than the diameter in the direction parallel to the wiring direction, and the end in the longitudinal direction is so set as to step off the plug electrode 22. That is, in the etching at the time of forming the contact hole 27, in the portion where the plug electrode 22 is stepped off,
Further, the lower first interlayer oxide film 20 is etched to stop the etching on the first silicon nitride film 19 on the gate electrode 17.

In a memory cell of a DRAM, the dimensional allowance that a storage node contact hole 27 has with another adjacent contact hole can usually be relatively large in a direction parallel to the bit line 24 wiring direction. . Further, since the opening of the contact hole 27 is opened by the SAC method with respect to the bit line 24, the size is reduced by the second silicon nitride film 25 in the direction crossing the bit line 24, and the size of the opening surface is increased. However, there is a limit in increasing the contact dimension on the plug electrode 22.
On the other hand, in the wiring direction of the bit line 24, the size is not reduced by the second silicon nitride film 25, and an opening large enough to step off the plug electrode 22 becomes possible. In addition, even if the plug electrode 22 is stepped off in the wiring direction of the bit line 24, the first silicon nitride film 19 on the gate electrode 17 serves as an etching stopper because the gate electrode 17 is wired so as to intersect the lower layer. There is no short circuit with the gate electrode 17. For this reason, the storage node contact hole 27 can make contact not only with the surface of the plug electrode 22 but also with the side surface, and the contact area can be increased and a good contact can be formed.

As described above, in forming the storage node contact hole 27, the dimensional allowance with the adjacent contact hole is relatively large, and by increasing the opening surface size, the contact size on the plug electrode 22 can be effectively increased. By increasing the diameter in the direction (the direction parallel to the wiring direction of the bit line 24), the contact area can be increased as described above. In addition, the contact hole 27 may be configured such that the plug electrode 22 is reliably stepped off at the end, or may be formed with a dimensional allowance that allows stepping off.

By the way in the above embodiment, when the storage node contact hole 27 formed, Ar _/ C 5 _{F 8}
Reactive ion etching using / CH ₂ F ₂ gas was used. In the Ar / C ₄ F ₈ gas system generally used conventionally, if a selectivity with respect to the silicon nitride film serving as an etching stopper is secured, the etching is easily stopped by the deposition of the fluorocarbon film which is a reaction product. In particular, in the storage node contact hole 27, the etching depth of the inter-wiring slit is deep, and even when the plug electrode 22 is provided as described in the above embodiment, not only the third interlayer oxide film 26 but also the bit line 24 is formed. It is necessary to further etch the lower second interlayer oxide film 23. Since the thickness of the second silicon nitride film 25 at the shoulder of the bit line 24 is smaller than the thickness of the first silicon nitride film 19 at the shoulder of the gate electrode 17, the thickness of the second silicon nitride film is higher than that of the silicon nitride film. A selectivity is required.

Ar / C ₅ F as a fluorocarbon-based gas
The results of a comparative experiment in which the storage node contact hole 27 was formed using four kinds of gases including ₈ / CH ₂ F ₂ gas are shown below. Using a parallel plate type RIE apparatus, pressure: about 30 to 50 mTorr, Rf about 1500 W, etching depth of oxide film: 650 nm, thickness of silicon nitride film: 40 nm 1. Ar / C ₄ F ₈ / CH ₂ F ₂ to SiN selectivity; 20-30 etch stop in hole; 2. Ar / C ₄ F ₈ / CH ₂ F ₂ / CO selectivity to SiN; 20 (short) Etch stop in hole; none Ar _/ C 5 _{F 8} to-SiN selection ratio; 40 hole etch stop; Yes 4. _{Ar / C 5 F 8 / CH} 2 F 2 pairs SiN selection ratio; the 40 hole etch stop; no

Thus, without stopping etching,
Ar / C of the two gases that could be opened₄F₈/ CH₂F
₂In / CO, the shoulder of the silicon nitride film 25 is etched.
Been short. C with high C / F ratio₅F₈System gas
And using CH as an additive gas ₂F₂Ar / C using₅
F₈/ CH₂F₂Then, stop etching in the hall
And selectivity with silicon nitride film is ensured
Thus, a good contact hole 27 was formed.

[0026]

As described above, in the semiconductor device according to the first aspect of the present invention, a first wiring layer having a first silicon nitride film formed on a surface and a side wall on a semiconductor substrate; A first interlayer oxide film formed on the entire surface of the first wiring layer;
A plug electrode formed by embedding an opening opened in a self-aligned manner with respect to the first wiring layer in the first interlayer oxide film, and a second interlayer formed on the entire surface of the plug electrode An oxide film, a second wiring layer disposed on the second interlayer oxide film and having a second silicon nitride film formed on the surface and side walls thereof, and formed on the entire surface of the second wiring layer. Since the third interlayer oxide film and the third interlayer oxide film have a connection hole which is opened in a self-aligned manner with respect to the second wiring layer and reaches the plug electrode, the third interlayer oxide film has: And in the upper layer, fine connection holes arranged between the second wiring layers can be provided on the semiconductor substrate with good controllability via plug electrodes,
A structure of a semiconductor device suitable for miniaturization and high integration can be provided.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the first wiring layer and the second wiring layer are linear patterns arranged in a direction crossing each other. Since the end of the hole in the direction parallel to the wiring direction of the second wiring layer stepped off the plug electrode and opened the first silicon nitride film as an etching stopper film in the stepped off portion, the connection hole and the plug electrode Can be increased, and the contact resistance can be reduced.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the first wiring layer is a gate electrode, the second wiring layer is a bit line, and the connection hole is a storage electrode. Since the node is connected to the semiconductor substrate via the plug electrode, the connection hole for the storage node can be opened in a self-aligned manner with respect to the bit line, and the fine connection hole can secure a contact area. With good controllability, miniaturization and high integration of the DRAM can be promoted.

According to a fourth aspect of the present invention, there is provided a semiconductor device, comprising: a gate electrode having a first silicon nitride film formed on a surface and a side wall of the semiconductor substrate and disposed linearly at predetermined intervals; A first interlayer oxide film formed on the entire surface of the gate electrode, and a plug electrode formed by filling the first interlayer oxide film with an opening that is self-aligned with respect to the gate electrode. A second interlayer oxide film formed on the entire surface of the plug electrode, and linearly disposed on the second interlayer oxide film at predetermined intervals in a direction intersecting with the gate electrode; A bit line having a second silicon nitride film formed on a side wall, a third interlayer oxide film formed on the entire surface of the bit line, and a third interlayer oxide film formed in a self-aligned manner with respect to the bit line. A connection hole opened to the plug electrode to reach the plug electrode. Since the diameter of the connection hole in the direction parallel to the wiring direction of the bit line is longer than the diameter of the gate electrode in the direction parallel to the wiring direction, a fine connection hole can be obtained with good controllability and contact. The area can be effectively increased, and the contact resistance can be reduced.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to any one of the first to fourth aspects.
Since the opening and the connection hole that are opened in a self-aligned manner are formed by a reactive ion etching process having an etching selectivity to a silicon nitride film using a fluorocarbon-based gas, the first wiring layer and the upper layer thereof are formed. Then the second
Fine connection holes arranged between the wiring layers can be formed on the semiconductor substrate with good controllability via the plug electrodes.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fifth aspect, Ar / C ₅ F ₈ / CH _{2 is used} as a fluorocarbon-based gas in the reactive ion etching treatment at the time of forming the connection hole. since the use of F ₂ gas, a connecting hole reaching the plug electrode, while securing the selectivity between the silicon nitride film can reliably formed.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure and a manufacturing method of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a structure of a conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 14 semiconductor substrate, 17 gate electrode as first wiring layer, 19 first silicon nitride film, 20 first interlayer oxide film, 21 opening, 22 plug electrode, 23 second
An interlayer oxide film of 24, a bit line as a second wiring layer,
25 second silicon nitride film, 26 third interlayer oxide film, 27 storage node contact hole as connection hole.

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 21/768 H01L 27/10 621C F-term (Reference) 4M104 BB01 CC01 DD02 DD04 DD08 DD16 DD17 DD65 DD72 EE05 EE09 EE12 EE17 FF04 FF13 FF14 GG16 HH12 HH14 HH15 HH20 5F033 HH04 HH17 HH26 JJ04 KK01 LL04 MM07 MM15 NN12 NN40 QQ09 QQ13 QQ15 QQ16 QQ25 QQ31 QQ37 QQ48 QQ58 QQ65 QQ74 RR02 RR06 SS04 XXXXX3 MA17 MA20 PR03 PR29 PR39 PR40

Claims (6)

[Claims] 1. A first wiring layer having a first silicon nitride film formed on a surface and a side wall on a semiconductor substrate, and a first interlayer oxide film formed on the entire surface of the first wiring layer. A plug electrode formed by embedding an opening that is self-aligned with respect to the first wiring layer in the first interlayer oxide film; and a second electrode formed on the entire surface of the plug electrode. An interlayer oxide film, a second wiring layer provided on the second interlayer oxide film and having a second silicon nitride film formed on the surface and side walls thereof, and formed on the entire surface of the second wiring layer And a connection hole which is opened in a self-aligned manner with respect to the second wiring layer and reaches the plug electrode in the third interlayer oxide film. Semiconductor device. 2. The wiring pattern according to claim 1, wherein the first wiring layer and the second wiring layer are linear patterns arranged in a direction intersecting each other, and the connection holes are formed in a direction parallel to the wiring direction of the second wiring layer. 2. The semiconductor device according to claim 1, wherein an end portion of the semiconductor device is formed by stepping off the plug electrode and opening the first silicon nitride film as an etching stopper film at the stepped portion. 3. The method according to claim 1, wherein the first wiring layer is a gate electrode,
3. The semiconductor device according to claim 1, wherein said wiring layer is a bit line, and said connection hole is for connecting a storage node to a semiconductor substrate via a plug electrode. 4. A gate electrode having a first silicon nitride film formed on a surface and a side wall of a semiconductor substrate and linearly arranged at predetermined intervals, and a first electrode formed on the entire surface of the gate electrode. A plug electrode formed by embedding an opening opened in a self-aligned manner with respect to the gate electrode in the first interlayer oxide film; and a plug electrode formed on the entire surface of the plug electrode. Two interlayer oxide films, and linearly disposed on the second interlayer oxide film at predetermined intervals in a direction intersecting with the gate electrode, and a second silicon nitride film is formed on the surface and the side wall. A bit line, a third interlayer oxide film formed on the entire surface of the bit line, and a connection hole opened in the third interlayer oxide film in a self-aligned manner with respect to the bit line and reaching the plug electrode. A direction parallel to the wiring direction of the bit line in the connection hole. A semiconductor device, wherein a diameter dimension in a direction is longer than a diameter dimension in a direction parallel to a wiring direction of the gate electrode. 5. The method according to claim 1, wherein the opening and the connection hole that are opened in a self-aligned manner are formed by a reactive ion etching process using a fluorocarbon gas and having an etching selectivity to a silicon nitride film. Item 5. The method for manufacturing a semiconductor device according to any one of Items 1 to 4. 6. In a reactive ion etching process for forming a connection hole, Ar / C _{5 is used} as a fluorocarbon-based gas.
6. The method of manufacturing a semiconductor device according to claim 5, wherein F ₈ / CH ₂ F ₂ gas is used.