JP2002230904A - Information playback device - Google Patents

Abstract

(57) [Problem] To appropriately reproduce information from a medium on which data is recorded at a high density by performing an appropriate waveform equalization process on a signal read from a recording medium. An apparatus for reproducing information digitally recorded on a recording medium, which equalizes a reproduction signal corresponding to the information read from the recording medium and outputs a first equalized signal. A first waveform equalization circuit and a second waveform equalization circuit having an equalization characteristic different from that of the first waveform equalization circuit and outputting a second equalization signal, and extracts a reproduction clock. And a second waveform equalizing circuit selectively used for the

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a reproducing apparatus for reading information written on a recording medium such as an optical disk and a magnetic disk.

[0002]

2. Description of the Related Art In recent years, storage devices for recording digital information, such as HDDs (hard disk devices), optical disk devices, and magneto-optical disk devices, have been widely used in AV equipment, personal computers, digital recording type camera-integrated VTRs, and the like. ing. In these storage devices, a further increase in storage capacity is desired. In order to increase the storage capacity, it is necessary to record data at high density on a recording medium such as a hard disk, an optical disk, and a magneto-optical disk, and to correctly reproduce the recorded data.

[0003] Among high-density signal processing techniques, in particular, HDDs
PRML (Partial
Response Maximum Likelihood method is known (for example, "Signal processing technology for high-density digital magnetic recording" by Osawa et al. (IEICE C-II, Vol. J81-CII, N
o.4, pp.393-412 (1998-04))). In the PRML system, data recording and reproduction are performed in consideration of occurrence of intersymbol interference when the recording density is high. More specifically, when reproducing a signal, after generating a signal (digital data) having a partial response equalized to a predetermined frequency characteristic using an equalizer or the like, the signal is subjected to Viterbi decoding or the like. Decode into the most likely (most likely) binary data. In this way, it is possible to decode data having a low error rate even from a reproduced signal having a low S / N (signal-to-noise) or a reproduced signal having relatively large jitter due to intersymbol interference.

A conventional PRM will now be described with reference to FIG.
A magnetic disk reproducing apparatus (HDD) adopting the L system will be described. The magnetic disk reproducing device 200 includes a magnetic head 12, an automatic gain controller (AGC) 3, a waveform equalizing circuit 40, a clock generating circuit 6, an A / D (analog-digital) converter 8, a PRML circuit 10, and the like. The digital information recorded on the magnetic disk 11 is reproduced.

The signal read from the magnetic disk 11 by the magnetic head 12 is adjusted by the AGC 3 so that its amplitude becomes a predetermined value. The amplitude-adjusted signal is then shaped by the waveform equalization circuit 40 so that its high-frequency component is emphasized. The output signal 41 from the waveform equalization circuit 40 is input to the A / D converter 8 and the clock generation circuit 6.

The clock generation circuit 6 includes a PLL (Phase Locked Loop) circuit, and generates a clock signal using a VCO (Voltage Controlled Oscillator) or the like. The generated clock signal is supplied to a phase adjustment circuit 7 as described later.
Is output to the A / D converter 8 after the phase adjustment is performed.

[0007] The A / D converter 8 samples the output signal 41 from the waveform equalization circuit 40 using the clock signal received from the phase adjustment circuit 7, thereby generating a digital signal (digital sample) 81. A / D
Digital signal 81 output from converter 8 has a value in a limited range. For example, for an 8-bit resolution,
The values that the digital signal 81 can represent are 0 to 255 (d
ecimal display).

The digital signal 8 thus obtained is
1 is a PRML circuit 10 and a phase control signal generation circuit 9
Is input to The phase control signal generation circuit 9 is a circuit for appropriately controlling the phase of the clock signal 61, and a phase adjustment signal 91 based on the received digital signal 81.
And outputs this to the phase adjustment circuit 7. A more detailed configuration of the phase control signal generation circuit 9 is described in, for example, Japanese Patent Application Laid-Open No. H10-228733.

The PRML circuit 10 includes a digital equalizer 1
0a and a maximum likelihood (ML) detector 10b such as a Viterbi decoder. The digital signal 81 input to the PRML circuit 10 is
After being equalized to a predetermined PR characteristic by 0a, it is decoded into binary data by the ML detector 10b. In this way, the PRML circuit 10 can reproduce data relatively correctly even if the signal has relatively large jitter due to intersymbol interference.

Next, the waveform equalization circuit 40 will be described in more detail with reference to FIG. As shown in FIG. 9, the waveform equalizing circuit 40 includes delay circuits 42a and 42b, amplifiers 43a and 43b, and an adder 44, and functions to amplify a high frequency band of an input signal. This makes it possible to amplify a signal (that is, a signal with a high frequency) corresponding to a recording pattern in which transitions occur continuously at short time intervals,
It is possible to reduce the influence of intersymbol interference in such a signal pattern and improve jitter.

As shown in FIG. 8, a signal 41 output from a waveform equalization circuit 40 is converted into digital data by an A / D converter 8 and then decoded in a PRML circuit 10 and generated by a clock generator. The circuit 6 is also used to extract a reproduced clock. In any of the circuits, it is preferable that a high-frequency signal is amplified to some extent and signal jitter is reduced.

For example, the PRML circuit 10 decodes the binary data from the sample data.
By amplifying the high frequency signal by 0, A /
The quantization accuracy when sampling such a signal in the D converter 8 can be sufficiently ensured. Also,
The clock generation circuit 6 extracts a reproduction clock from the reproduction signal. If the reproduction clock is extracted using a high-frequency signal with reduced jitter, an appropriate reproduction clock can be generated.

As described above, using the waveform equalizing circuit 40,
By pre-equalizing the signals input to the PRML circuit 10 and the clock generation circuit 6, it is possible to reproduce information more accurately.

[0014]

However, when the recording density is further increased and the influence of intersymbol interference is increased, it becomes more difficult to correctly reproduce the signal. In particular, when an attempt is made to realize further high-density recording in the field of an optical disc device, the reproducing apparatus having the configuration shown in FIG. 8 may not be able to sufficiently reduce the error occurrence rate.

For example, digital information is recorded as marks and spaces on an optical disk, but generally shorter marks (or spaces) are read as signals having smaller amplitudes. In order to appropriately identify such a signal (that is, a high-frequency signal having a small intensity), it is necessary to appropriately set the equalization characteristics in the waveform equalization circuit 40. However, in the reproducing apparatus as shown in FIG.
It is not easy to adjust the equalization characteristic of the signal so that the characteristic becomes optimal for signal reproduction. Hereinafter, the reason will be described.

When the PRML decoding method is employed as described above, it is necessary to perform A / D conversion by sampling a reproduced signal with a channel clock. In order to obtain an appropriate sampling clock corresponding to the channel clock, It is necessary to sufficiently suppress the jitter of the reproduction signal supplied to the clock generation circuit. When the jitter of the reproduction signal is large, the clock generation circuit 6 cannot extract an appropriate reproduction clock.

Further, when the recording medium is an exchangeable medium such as an optical disk, it becomes more difficult to generate a clock signal. This is because, in an optical disk, the drive device may be different between recording and reproduction, and a wobble (small fluctuation in transfer speed) may occur in a reproduction signal during reproduction. In order to generate a clock signal from a reproduced signal having such wow, the gain of the PLL circuit must be set high enough to follow the reproduced signal. However, when the gain of the PLL circuit is increased, if the jitter of the reproduced signal is large, a bit slip is caused, and an error that cannot be corrected even if the PRML processing is performed thereafter occurs.

Therefore, in order to generate a clock signal, it is desirable to perform waveform equalization so that the jitter of the reproduced signal can be reduced to the maximum. However, the equalization characteristics of the waveform equalization circuit 40 are set so as to be optimal for jitter reduction (specifically, the amplifier 4 in the equalization circuit 40).
3a and 43b), the error rate may be increased instead of being compatible with the PRML method. In the PRML decoding method, a signal input to an ML detector is obtained by equalizing a reproduced signal such that a frequency response characteristic of a recording / reproducing signal processing system including a recording medium such as an optical disk has a predetermined PR equalization. Is desirable. If the equalization characteristics of the equalization circuit 40 do not match the desired PR equalization, it becomes difficult to reproduce a correct signal. Therefore, the equalization characteristics of the equalization circuit 40 must be appropriately selected so as to be compatible with a predetermined PRML decoding method and reduce the jitter of the reproduced signal.

When phase error information is obtained from the reproduced digital signal in the phase control signal generation circuit 9, the phase control signal generation circuit 9 determines an undesired phase shift of the reproduction clock from the amplitude level of the reproduction digital signal.
At this time, if the equalization amount K of the waveform equalization circuit 40 is too small, the detected phase is actually the same between the reproduction of the short mark and the reproduction of the long mark despite the same phase error. A difference occurs in the error. Therefore, it is necessary to increase the equalization amount K of the waveform equalization circuit 40 to some extent. However, if the equalization amount K is excessively increased, inter-symbol interference will increase, and a problem will occur that PR equalization in the subsequent stage will not be performed properly.

As described above, in the conventional reproducing apparatus, it is necessary to select the equalization characteristics of the waveform equalizing circuit so as to be appropriate for various elements such as generation of a clock and decoding of an information signal. This has become more difficult as the recording density has increased, especially in optical disk devices.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and reproduces data having a lower error rate by performing an appropriate equalization process on a signal read from a recording medium. It is an object of the present invention to provide a playback device that performs

[0022]

SUMMARY OF THE INVENTION A reproducing apparatus according to the present invention is a reproducing apparatus for reproducing information digitally recorded on a recording medium, wherein the information read from the recording medium is provided. A first waveform equalizing circuit for equalizing a corresponding reproduced signal and outputting a first equalized signal; and a second equalized signal having an equalizing characteristic different from that of the first waveform equalizing circuit. A second waveform equalizing circuit for outputting, wherein the second waveform equalizing circuit is selectively used to extract a reproduced clock.

In one preferred embodiment, the second
Is used only for extracting the reproduction clock, and the information is not reproduced from the second equalization signal.

In one preferred embodiment, the second
The waveform equalizing circuit has an equalizing characteristic such that the high frequency component of the input signal is emphasized more strongly than the first waveform equalizing circuit.

In one preferred embodiment, the second
And a decoding circuit for generating binary data from the first equalized signal.

In a preferred embodiment, a phase adjustment circuit that shifts the phase of the reproduced clock output from the clock generation circuit according to a phase control signal, and outputs the phase-shifted reproduced clock as a sampling clock; An A / D converter for converting the first equalized signal into a reproduced digital signal by sampling the first equalized signal with the sampling clock output from the phase adjustment circuit; A phase control signal generation circuit that detects a clock phase shift based on the reproduced digital signal output from the device and outputs the phase control signal for reducing the clock phase shift to the phase adjustment circuit; A decoder for generating the binary data from the reproduced digital signal output from the A / D converter. And a circuit.

[0027] In a preferred embodiment, the decoding circuit performs decoding based on a pattern of a reproduced digital signal obtained by sampling the first equalized signal.

In a preferred embodiment, the decoding circuit is a circuit to which a PRML system is applied.

[0029] In a preferred embodiment, the recording medium is an optical disk.

In this specification, "equalizing a signal" refers to adjusting the degree of signal enhancement or attenuation in accordance with the frequency band, and adjusting the overall frequency characteristics of the signal. An electric circuit that performs such an operation is widely called an “equalization circuit”.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an optical disc reproducing apparatus according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of an optical disk reproducing apparatus 100 according to the present embodiment. The optical disc reproducing apparatus 100 includes an optical head 2, an automatic gain controller (A
GC) 3, a first waveform equalization circuit 4, a second waveform equalization circuit 5 having an equalization characteristic different from that of the first waveform equalization circuit 4,
A clock generation circuit 6, an A / D converter 8, and a digital equalizer 10a for extracting a clock synchronized with a reproduction signal
And a PRML circuit 10 including a ML detector 10b and the like. The optical disk reproducing device 100 is an optical disk 1
The digital data recorded as a mark or space is reproduced using the PRML decoding method.

The optical head 2 reads digital data from the optical disk 1 and outputs a reproduction signal corresponding to the digital data. An output signal from the optical head 2 is input to an AGC 3 for adjusting the signal amplitude to a predetermined value. The AGC 3 is provided for removing an undesired amplitude fluctuation in a reproduction signal caused by, for example, a change in the reflectance of the optical disc 1. The reproduced signal whose amplitude is adjusted by the AGC 3 is supplied to a first waveform equalizing circuit (E
Q1) 4 and the second waveform equalization circuit (EQ2) 5.

FIGS. 2A and 2B show the circuit configurations of the first waveform equalizing circuit 4 and the second waveform equalizing circuit 5, respectively. As shown in FIG. 2A, the first waveform equalizing circuit 4 includes delay circuits 20a and 20b, and amplifiers 22a and 22a.
b, an adder 24, and outputs an equalized signal 41. As shown in FIG. 2B, the second waveform equalizing circuit 5 includes delay circuits 26a and 26b, an amplifier 28a,
28b, an adder 24, and an equalized signal 51
Is output.

Although these waveform equalization circuits 4 and 5 have similar structures, the amplifiers 22a,
Reference numeral 22b denotes an amplifier having an equalization amount K1, and the amplifiers 28a and 28b of the waveform equalization circuit 5 differ in that they have an equalization amount K2. Thus, the equalization characteristics of the waveform equalization circuit 4 and the equalization characteristics of the waveform equalization circuit 5 are different. In the present embodiment, the equalization amount K1 is smaller than the equalization amount K2, that is, the second waveform equalization circuit 5
Is larger than the equalization amount of the first waveform equalization circuit 4. The waveform equalization circuit 5 can perform equalization so as to emphasize a high-frequency signal more than the waveform equalization circuit 4.

In this embodiment, as shown in FIGS. 2A and 2B, the delay circuit 20 of the waveform equalizer 4
a, 20b and the delay circuits 26a, 26 of the waveform equalization circuit 5
b, the delay parameter T is the same, but the delay parameter T may be different for each of the waveform equalizing circuits 4 and 5 if necessary. Also, the waveform equalizing circuit 4
Although the description has been given by taking a three-tap waveform equalizing circuit as an example as 5 and 5, the waveform equalizing circuits 4 and 5 may have other configurations, and may have an appropriate number of taps as desired. A waveform equalization circuit can be used.

FIG. 3 shows the first waveform equalizing circuit 4 and the second waveform equalizing circuit 4.
Signals 41 output from each of the waveform equalization circuits 5 of
51 is a graph illustrating a frequency characteristic of a frequency 51. In this graph, the characteristic C0 of the reproduced signal before being input to the waveform equalization circuits 4 and 5, the characteristic C1 of the signal equalized by the first waveform equalization circuit 4, and the second waveform equalization The characteristic C2 of the signal equalized by the circuit 5 is shown. As can be seen from the figure, in the present embodiment, any of the waveform equalization circuits amplifies the high frequency band of the input signal. However, the second waveform equalization circuit 5 has a higher level than the first waveform equalization circuit 4. The reproduction signal is equalized so that the equalization amount is large and the high frequency component is emphasized.

Referring back to FIG. The reproduced equalized signal 41 equalized by the first waveform equalizing circuit 4 is input to the A / D converter 8, where it is converted into a digital signal 81, and then the phase control signal generating circuit 9 and the PRML circuit 10 is input. The PRML circuit 10 includes the digital equalizer 1
0a and a maximum likelihood detector (ML detector) 10b such as a Viterbi decoder. The digital signal 81 input to the PRML circuit 10 is a digital equalizer 10a
Is equalized to a predetermined PR characteristic by the ML detector 1
The data is decoded into binary data “1” and “0” by 0b and output. More specifically, the ML detector 10b
Based on the pattern of the equalized digital samples,
The binary data recorded on the disc is decoded.

On the other hand, the equalized signal 51 output from the waveform equalizing circuit 5 is input to a clock generating circuit 6 for extracting a reproduced clock corresponding to a channel clock. The clock generation circuit 6 includes, for example, a PLL circuit.
A clock signal (reproduction clock) 61 synchronized with the reproduction signal is generated using a VCO or the like. Reproduction clock 6
1 is used for defining the sampling timing in the A / D converter 8.

Hereinafter, a first waveform equalizing circuit 4 is provided for each of a reproduced signal decoding system including a PRML circuit 10 and the like and a reproduced clock extracting system including a clock generating circuit 6 and the like.
The reason for inputting signals equalized with different equalization characteristics using the second waveform equalization circuit 5 and the second waveform equalization circuit 5 will be described.

In general, the equalization amount optimized in the PRML decoding method is different from the equalization amount capable of minimizing jitter. For example, (1, 7) RLL (Run Length Limite)
d) When the modulated signal is decoded by the PR (1, 2, 2, 1) ML method, the signal corresponding to the shortest mark in the reproduction signal has a relatively small amplitude (an accurate clock is generated by binarization). Is difficult), correct data can be decoded from marks before and after the mark. Also, when decoding is performed by the PR (1, 2, 2, 2, 1) ML method, even if the waveform change of the signal corresponding to the shortest mark has completely disappeared, correct data is decoded from the preceding and following marks. It is possible to The importance of PRML processing is not the amplitude of the shortest mark, but the MT of the reproduction system.
F (amplitude passage characteristic) and response coefficient (for example, PR
(1, 2, 2, 1) method).

For this reason, the equalization characteristic of the first waveform equalization circuit 4 is set so that the high frequency range of the reproduced signal is not excessively emphasized as compared with that of the second waveform equalization circuit 5. PRM
In the L decoding method, occurrence of intersymbol interference is considered in advance, and correct binary data can be decoded based on a digital signal pattern generated from a signal including intersymbol interference. It is not necessary to emphasize the territory completely. First waveform equalization circuit 4
Is preferably set such that a digital signal input to the ML detector is equalized with a predetermined PR characteristic.

On the other hand, when generating a clock,
When the waveform change of the signal corresponding to the shortest mark disappears,
Since the edge (at the point when the signal changes) cannot be detected, the jitter is remarkably deteriorated, or in the worst case, a bit slip occurs. Therefore, the signal supplied to the clock generation circuit 6 must have the shortest mark amplitude that can be binarized. Therefore, the equalization amount K2 is boosted to a sufficiently large amount in the second waveform equalization circuit 5. The equalization amount K2 is preferably optimized so that the jitter of the signal input to the clock generation circuit 6 is minimized.

As described above, the equalization characteristic of the first waveform equalization circuit 4 is set so as to conform to the predetermined PRML decoding method, and the equalization characteristic of the second waveform equalization circuit 5 is set as follows. By making settings so as to be compatible with the reproduction clock extraction, more accurate information reproduction can be performed.

The optical disc reproducing apparatus 100 has a phase control signal generating circuit 9. The phase control signal generation circuit 9 generates a phase control signal 91 based on the digital signal 81 output from the A / D converter 8, and outputs this to the phase adjustment circuit 7. In the phase adjustment circuit 7, the phase control signal 91 is used for adjusting the phase of the reproduced clock 61 obtained from the clock generation circuit 6. The clock signal 7 thus adjusted in phase
1 is input to the A / D converter 8 and is used as a sampling clock for determining the timing of performing A / D conversion.

The phase control signal generation circuit 9 adjusts the phase of the reproduction clock 61 so that a digital sample suitable for the PRML system employed in the PRML circuit 10 is obtained. FIG. 4 shows a configuration example of the phase control signal generation circuit 9. As shown, the phase control signal generation circuit 9 includes a phase reference position detection circuit 92, a phase error detection circuit 93, a low-pass filter 94, and a D / A converter 95.

FIGS. 5A to 5C show the relationship between the input waveform in the A / D converter 8 and the signal detection timing (phase of the clock 71). MSB and L in the figure
SB indicates the most significant bit and the least significant bit of the D range of the A / D converter 8, respectively. TW in the figure is
It shows the interval of one channel bit.

FIG. 5A shows a case where A / D conversion is performed on the clock signal 61 output from the clock generation circuit 6 at an initial phase clock timing whose phase is not controlled.

On the other hand, in FIG. 5B, the phase control reference position is set to the center of the D range of the A / D converter 8 (for example, 8 bi
In the case of t resolution, a case where 128 (decimal notation) is set is shown. In the phase control signal generation circuit 9, the phase reference position detection circuit 92
When a sample having a level close to a preset phase reference position is input, the phase reference position detection circuit 92 outputs a trigger signal to the phase error detection circuit 93. Output. Only when the trigger signal is input, the phase error detection circuit 93 outputs the value of the sample data as phase error information. The reason that the phase error information can be obtained in this manner is that when the phase of the clock signal is shifted from the desired phase at a predetermined phase reference position, the shift amount is as follows.
This is because the difference is reflected in the difference between the phase reference position and the sample value. The obtained phase error information is output to the phase adjustment circuit 7 via the low-pass filter 94 and the D / A converter 95. This feedback loop is controlled so that the phase error is reduced.

FIG. 5 (c) shows that the phase control reference position is shifted from the center of the D range described with reference to FIG. 5 (b) by ± 180 ° in clock phase. This shows a case where the position is set. In this case, A / D
The digital signal 81 output from the converter 8 is | A |
= | B | (where A represents the difference between the center of the D range and one of the phase control reference positions, and B represents the difference between the center of the D range and the other phase control reference position. It is necessary to feedback-control the phase of the clock. Further, since the phase position in FIG. 5 (c) is exactly 180 ° out of phase from the phase position in FIG. 5 (b), sampling at the phase position in FIG. , While controlling the phase position of FIG.
Similar control is possible even if the sampling clock is inverted. However, in this case, the condition is that the duty ratio of the sampling clock is 50%.

Such a phase control is based on the PRML employed.
It is desirable to perform it so as to be optimal for the system.
Hereinafter, the relationship between the PRML method and the clock phase will be described. For example, if the modulation rule is a minimum code length such as EFM (Eight to Fourteen) or EFM-Plus code of 3T
PR (a, b, a) M with a PR length of 3
When the L system is adopted, there are four signal levels (0, a, a
+ B, 2a + b), and it is desirable to control the phase to the phase control reference position as shown in FIG. Also, when the PR (a, b, b, a) ML system with a PR length of 4 is adopted, there are five signal levels (0, a, a + b, a +
2b, 2a + 2b), as shown in FIG.
It is desirable to control the phase at the phase control reference position.

When the modulation rule adopts a code word having a minimum code length of 2T such as (1,7) RLL modulation and a PR (a, b, a) ML system having a PR length of 3, Similarly to the code word having the minimum code length of 3T, the signal level has four values and is located at the phase control reference position as shown in FIG.
It is desirable to control the phase. In addition, P of PR length 4
When the R (a, b, b, a) ML system is adopted, there are seven signal levels (0, a, 2a, a + b, 2b, a + 2b,
It is desirable to have a value of 2a + 2b) and to control the phase to the phase control reference position as shown in FIG. Under the condition that the mark and the space have the same run length, if the number of signal levels is an odd number, the phase control reference position is as shown in FIG. 5B, and if the number of signal levels is an even number, as shown in FIG. What is necessary is just to set it as a phase control reference position.

The phase adjustment circuit 7 changes the amount of phase delay according to the voltage change indicated by the phase control signal 91 output from the phase control signal generation circuit 9. Thus, the clock (sampling clock) 71 after the phase adjustment input to the A / D converter 8 is feedback-controlled so that the processing in the processing blocks after the A / D converter 8 is appropriately performed. . By using the phase control signal generation circuit 9 and the phase adjustment circuit 7 as described above, the phase of the clock can be adjusted according to the selected PRML system, and the waveform suitable for the processing in the PRML circuit 10 can be converted into a P
It can be input to the RML circuit 10.

Next, a case where a waveform equalization circuit different from the above-described waveform equalization circuit 5 is used to obtain a reproduced clock will be described.

In the optical disk device, the rotating disk is tilted due to the warpage of the disk or the like, and the waveform amplitude of the reproduced signal changes due to the tilt. The degree of the change in the waveform amplitude varies depending on the frequency band. In an optical disk, a recording mark is written larger or smaller than a reference due to an undesired change in laser power at the time of recording, thereby causing asymmetry of amplitude in a reproduced signal. The degree of the asymmetry also differs depending on the frequency band. The change in the signal waveform thus generated does not have linearity with respect to the frequency. If the nonlinear characteristic peculiar to such an optical disk becomes strong, especially when high-density recording is performed and the influence of intersymbol interference is large, it becomes more difficult to extract a reproduction clock, and it becomes impossible to obtain sufficient reproduction performance.

On the other hand, if a waveform equalizing circuit 50 having an amplitude limiting circuit as shown in FIG. 6 is used instead of the second waveform equalizing circuit 5 shown in FIG. Since the jitter can be further improved, the clock can be extracted more accurately. The waveform equalizing circuit having the amplitude limiting circuit is described in, for example, Japanese Patent Application No. 11-3.
No. 08867, JP-A-11-259985 and the like.

First, the waveform equalization circuit 50 shown in FIG. 6 will be described. The waveform equalizing circuit 50 includes a resistor 52, a diode 53
a, 53b, buffers 54a, 54b, buffer 55,
The circuit includes delay circuits 56a and 56b, amplifiers 57a and 57b, and an adder 58, and inputs to the buffers 54a and 54b are input with signals X1 and X2 for specifying the upper limit voltage and the lower limit voltage of the input waveform.

Using the waveform equalization circuit 50, after the reproduction amplitude is intentionally limited by the signals X1 and X2, equalization can be performed with a relatively large equalization coefficient.
With this configuration, it is possible to avoid a problem that the jitter is increased by the high frequency emphasis by the waveform equalizing circuit. Therefore, a significant improvement in jitter can be expected.

The reason why jitter can be improved by using the waveform equalizing circuit 50 will be briefly described with reference to the output waveforms of the waveform equalizing circuits shown in FIGS.

For example, in the waveform equalization circuit 40 as shown in FIG. 9, when the reproduced signal is not equalized (when the waveform is passed without any processing) or when the equalization amount K is weak. The output signal from the waveform equalizing circuit 40 has a waveform as shown in FIG. That is,
The point where the reproduced signal of the long mark crosses the threshold potential Vth and the point where the reproduced signal of the short mark crosses the threshold potential Vth coincide. However, in this case, since the high band of the signal is not sufficiently emphasized, a significant improvement in jitter cannot be expected.

On the other hand, the equalization amount K in the waveform equalization circuit 40
As shown in FIG. 7B, the point at which the reproduced signal of the long mark intersects with the threshold potential Vth is determined by the shift amount g.
And a new jitter occurs in the reproduced signal due to this deviation. This new jitter appears more remarkably as the recording density increases and the equalization amount K increases.

That is, if the equalization amount K is increased within a certain range in order to reduce the intersymbol interference, the jitter can be reduced within a limited range.
Even if is increased, the new jitter as described above is generated, and the jitter is rather increased. Because of such a trade-off, when a circuit such as the waveform equalization circuit 40 is also used, it may be difficult to greatly reduce jitter.

On the other hand, as a second waveform equalizing circuit,
If the amplitude of the long mark is limited to a predetermined range before performing waveform equalization using the waveform equalization circuit 50 as shown in FIG. As shown in FIG. 7C, generation of new jitter g in the output signal of the waveform equalization circuit 50 is avoided. As a result, it is possible to greatly improve the jitter of the reproduced signal.

However, as shown in FIG.
The output waveform when the waveform equalization circuit 50 is used has a long mark having an "M" shape as a result of the amplitude limitation. Therefore, when a PRML circuit is provided at the subsequent stage of the waveform equalization circuit 50 and data is to be decoded from this output signal, it is difficult to perform appropriate decoding. This is because PRML signal processing utilizes the characteristic that an input reproduced waveform ideally draws only a limited pattern, and selects the pattern closest to the input waveform by applying information theory. This is because the most probable data series is decoded. For this reason, if an “M” -shaped waveform that is not in the pattern of the predicted input waveform as described above is input, it cannot be correctly decoded by the PRML signal processing. Therefore, it is desirable that the signal input to the PRML signal processing is not equalized by the waveform equalization circuit 50.

On the other hand, in this embodiment, a waveform equalization circuit 50 as shown in FIG. 6 is used only as a waveform equalization circuit used for clock extraction, and a waveform for a signal on which PRML signal processing is performed. FIG. 2 (a) shows an equalizing circuit.
The use of another waveform equalization circuit 4 as shown in FIG. 1 makes it possible to significantly reduce jitter and appropriately perform PRML signal processing. Therefore, more accurate information reproduction can be performed.

As described above, according to the reproducing apparatus of the present embodiment, by providing at least two waveform equalizing circuits, that is, a waveform equalizing circuit for generating a clock and a waveform equalizing circuit for decoding data, Separately, it is possible to set an optimum equalization characteristic for each purpose. Therefore, information can be reproduced with a low error rate and high reliability even from an optical disc on which high-density recording has been performed.

In the above-described embodiment, an example has been described in which a total of two waveform equalizing circuits are provided: a waveform equalizing circuit for clock extraction and a waveform equalizing circuit for data decoding and phase adjustment. The playback device of the present invention is not particularly limited to this configuration, and may have another configuration. For example, a total of three waveform equalizing circuits may be provided: a waveform equalizing circuit for extracting a clock, a waveform equalizing circuit for decoding data, and a waveform equalizing circuit for adjusting a phase. That is, the number of waveform equalization circuits is not limited, and a waveform equalization circuit suitable for each application may be used.

In each waveform equalizing circuit,
The number of taps, the amount of equalization, and the circuit configuration need not be the same, and the number of taps, the amount of equalization, and the circuit configuration suitable for each application may be selected. The equalization characteristics (for example, equalization amount, boost center frequency, etc.) in the waveform equalization circuit can be arbitrarily set for each waveform equalization circuit.

In the above embodiment, the A / D converter 8
In the example shown, the PRML circuit 10 (digital equalizer 10a and ML detector 10b) is provided at the subsequent stage, but the digital equalizer 10a is not provided, and the ML detector 10b is provided at the subsequent stage of the A / D converter 8. Only one may be provided. In this case, for example, by appropriately setting the equalization characteristics of the first waveform equalization circuit 4 so that the frequency characteristics of the signal reproduction system have a predetermined PR equalization, the decoding operation by the PRML method is appropriately performed. Can be implemented.

Also, as shown in FIG.
0 is the equalization characteristic (equalization amount K1) of the first waveform equalization circuit 4 from the binarized data using the equalization characteristic adjustment circuit 4a.
, Etc.) may be configured to perform feedback control. In this case, since the equalization characteristics of the first waveform specialization circuit 4 are appropriately controlled, it is not necessary to provide a digital equalizer in a stage preceding the ML detector 10b. Further, by using the equalization characteristic adjustment circuit 5a, the second
The feedback control may be performed on the equalization characteristics (equalization amount K2 and the like) of the waveform equalization circuit 5 described above. The configuration other than the above may be the same as that of the playback device 100 shown in FIG.

Hereinafter, an example of the equalization characteristic adjusting circuit 4a of the reproducing apparatus 110 will be described.

The equalization characteristic adjusting circuit 4a is provided with the ML detector 10
b and the detection result D of the ML detector 10b (that is, a binary signal of “0” or “1”). The equalization characteristic adjustment circuit 4a, based on the detection result D received from the ML detector 10b,
A partial PA of the state transition path having the minimum Euclidean distance is detected from the state transition paths determined in b in the maximum likelihood. If this state transition path part PA is detected, another possible state transition path part PB is also found.

Here, the equalization characteristic adjusting circuit 4a expects the square value JPA of the difference between the signal S and the value of the reproduction signal expected in the path part PA, and the signal S and the path part PB. And the squared value JPB of the difference from the value of the reproduced signal. Further, the difference between the squared value JPA and the squared value JPB (JP
A-JPB) is calculated, and the average value and standard deviation of the distribution of the difference (JPA-JPB) are calculated. The average value and standard deviation value SE obtained in this way are calculated by the ML detector 10b.
This is a value correlated with the error rate of the binarization result. That is, S
As the E value decreases, the error rate of the result determined by the ML detector 10b also decreases.

Using the SE value, the equalization characteristic adjustment circuit 10a performs feedback control of the equalization characteristic of the first waveform equalization circuit 4. More specifically, the equalization characteristic (for example, the equalization amount K1) of the waveform equalization circuit 4 is controlled so that the SE value is minimized. Thereby, data with a lower error rate can be obtained.

Next, an example of the equalization characteristic adjusting circuit 5a of the reproducing apparatus 110 will be described. The clock generation circuit 6 detects when the reproduction signal crosses a predetermined level,
A clock signal is being generated. Equalization characteristic adjustment circuit 5a
Is the time error (jitter) between the clock signal generated from the clock generation circuit 6 and the time when the reproduced signal is detected.
Receive. The equalization characteristic adjustment circuit 5a performs feedback control of the equalization characteristic of the second waveform equalization circuit 5 so that the jitter is minimized. Thereby, a more accurate reproduction clock can be obtained.

Further, as shown in FIG.
0 is the first waveform equalizing circuit 4 for the A / D converter 8.
While inputting the signal 41 equalized only by
The clock generation circuit 6 is configured to receive a signal equalized by both the first waveform equalization circuit 4 and the second waveform equalization circuit 5 connected to the subsequent stage. You can also. The configuration other than the above may be the same as that of the reproduction circuit 100 shown in FIG.

The reproducing apparatus of the present invention includes a waveform equalization circuit (ie, a second waveform equalization circuit 5) which is selectively used for clock extraction separately from at least one waveform equalization circuit. As long as there is, it can have various circuit configurations.

In the above embodiment, the PRML circuit 10 using the PRML signal processing method is used as the decoding circuit.
Although a decoding circuit using another signal processing method may be used. For example, Osawa et al., "Signal processing technology for high-density digital magnetic recording", IEICE C-II, J81-C
-II, 4, FDTS / DF (Fixed-Delay Tree Search with D) introduced in pp.393-412 (April 1998)
(ecision Feedback) method.

Further, the optical disk device has been described as an embodiment of the present invention by way of example.
The present invention can be applied to various other types of information reproducing devices such as a magnetic disk device and a magneto-optical disk device.

[0080]

As described above, according to the present invention, a waveform equalizing circuit for generating a clock is provided separately from a waveform equalizing circuit for decoding data, a waveform equalizing circuit for detecting a phase error, and the like. This makes it possible to extract an appropriate reproduction clock and use it to decode data appropriately. As described above, by setting the optimum equalization characteristic for each purpose for each application, more reliable data reproduction can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an optical disc playback device according to an embodiment of the present invention.

2A is a circuit diagram showing a configuration of a first waveform equalization circuit shown in FIG. 1, and FIG. 2B is a circuit diagram showing a configuration of a second waveform equalization circuit shown in FIG. FIG.

FIG. 3 is a graph showing frequency characteristics of a reproduced signal before waveform equalization, an equalized signal output from a first waveform equalizer, and an equalized signal output from a second waveform equalizer; is there.

FIG. 4 is a block diagram of a phase control signal generation circuit shown in FIG. 1;

FIG. 5 is a diagram illustrating a relationship between an input waveform of an A / D converter and a phase control reference position.

FIG. 6 shows a second embodiment of another embodiment used in the embodiment of the present invention.
FIG. 3 is a circuit diagram showing a waveform equalization circuit of FIG.

FIG. 7 is a waveform diagram of a signal obtained from the waveform equalizing circuits shown in FIGS. 6 and 9;

FIG. 8 is a block diagram showing a conventional magnetic disk reproducing device.

FIG. 9 is a circuit diagram of a conventional waveform equalization circuit.

FIG. 10 is a block diagram showing a configuration of an optical disc reproducing device according to another embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of an optical disc reproducing device according to still another embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 optical disk 2 optical head 3 automatic gain controller (AGC) 4 first waveform equalization circuit (EQ1) 5 second waveform equalization circuit (EQ2) 6 clock generation circuit 7 phase adjustment circuit 8 A / D converter 9 Phase control signal generation circuit 10 PRML circuit 100 Optical disk device

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Hirodori Ishibashi 1006 Oaza Kadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Masahito Nakao 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture F-term in Matsushita Electric Industrial Co., Ltd. (reference)

Claims (8)

[Claims] 1. A reproducing apparatus for reproducing information digitally recorded on a recording medium, comprising: a reproducing signal corresponding to the information read from the recording medium; A first waveform equalization circuit for outputting an equalization signal; and a second waveform equalization circuit having an equalization characteristic different from that of the first waveform equalization circuit;
A second waveform equalizing circuit that outputs the equalized signal of the above, and a second waveform equalizing circuit selectively used for extracting a reproduced clock. 2. The reproducing apparatus according to claim 1, wherein the second equalized signal is used only for extracting the reproduction clock, and the information is not extracted from the second equalized signal. 3. The first waveform equalizer according to claim 1, wherein the second waveform equalizer has an equalization characteristic that emphasizes a high-frequency component of an input signal more strongly than the first waveform equalizer. A playback device according to claim 1. 4. The apparatus according to claim 1, further comprising: a clock generation circuit that outputs the recovered clock from the second equalized signal; and a decoding circuit that generates binary data from the first equalized signal. 3. The reproducing apparatus according to any one of 3. 5. A phase shift of the reproduced clock output from the clock generation circuit according to a phase control signal,
A phase adjustment circuit that outputs the phase-shifted reproduction clock as a sampling clock; and a first equalization signal by sampling the first equalization signal with the sampling clock output from the phase adjustment circuit. An A / D converter for converting a clock phase shift based on the reproduced digital signal output from the A / D converter, and detecting the clock phase shift with respect to the phase adjustment circuit. And a phase control signal generation circuit that outputs the phase control signal for reducing the phase control signal, wherein the decoding circuit generates the binary data from the reproduced digital signal output from the A / D converter. 5. The playback device according to 4. 6. The reproducing apparatus according to claim 4, wherein the decoding circuit performs decoding based on a pattern of a reproduced digital signal obtained by sampling the first equalized signal. 7. The reproducing apparatus according to claim 6, wherein the decoding circuit is a circuit to which a PRML method is applied. 8. The reproducing apparatus according to claim 1, wherein the recording medium is an optical disk.