JP2002222892A - Multilayer wiring board - Google Patents

Abstract

(57) Abstract: In a multilayer wiring board, electrical noise, simultaneous switching noise, and EMI noise are reduced while the propagation delay time of each signal wiring is made substantially the same. SOLUTION: A first signal wiring group 3 having a wiring length L1 is formed on a surface of an insulating substrate 2, a second signal wiring group 6 having a wiring length L2 is formed therein, and a power supply layer or a ground layer 7 is formed. , 9 and 10 are a multilayer wiring board provided with the built-in capacitor is formed by opposed first and second signal line group 3, 6 is 0.8 × (0.670 / εr + 0.475 ) 1/2
≦ L2 / L1 ≦ 1.2 × (0.670 / εr + 0.475) ^1/2 (L1
> L2 and εr satisfy the relationship of the relative dielectric constant of the insulating layer on which the signal wiring is formed), and the built-in capacitor has a plurality of resonance frequencies different from each other in the range from the operating frequency band of the semiconductor element 13 to the frequency band of the harmonic component. Are connected in parallel, and the combined impedance value at the anti-resonance frequency is set to a predetermined value or less.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-layer wiring board used for a semiconductor element housing package for housing a semiconductor element or an electronic circuit board on which a semiconductor element or an electronic component is mounted. The present invention relates to a multilayer wiring board having a wiring structure suitable for housing or mounting a semiconductor element.

[0002]

2. Description of the Related Art Conventionally, microprocessors and ASICs (Appl.
In a multilayer wiring board used for an electronic circuit board or the like, on which electronic components such as a semiconductor element typified by an ication specific integrated circuit) are mounted. Insulating layers made of ceramics and wiring conductor layers made of a high melting point metal such as tungsten (W) are alternately laminated to form a multilayer wiring board.

On the other hand, as the demand for improving the information processing capability increases, as the operating speed of the semiconductor element increases and the number of simultaneous switching increases, the signal wiring among the wiring conductors for internal wiring has characteristic impedance. There has been a demand for improvements in electrical characteristics such as matching of signals and reduction of crosstalk noise between signal wirings. Therefore, in order to meet such a demand, the wiring structure of the signal wiring is a strip line structure, and a wide-area power supply layer or a ground (ground) layer is formed above and below the signal wiring via an insulating layer.

Further, with the increase in the speed of electric signals handled by the multilayer wiring board, a glass epoxy resin base material having a relatively small relative dielectric constant of 3 to 5 is used instead of an alumina ceramic having a relative dielectric constant of about 10 for an insulating layer. Is formed using an organic material such as polyimide, epoxy resin, or the like, and a conductive film for internal wiring made of copper (Cu) is formed on the insulating layer by using a thin film forming technique such as plating, vapor deposition, or sputtering. Then, a fine pattern of wiring conductors is formed by photolithography or etching, and the insulating layer and the wiring conductors are alternately laminated in multiple layers to achieve high density,
Production of a multi-layer wiring board having high performance and capable of high-speed operation of a semiconductor element is also performed.

In addition, the number of signals has been increasing with the increase in the operation speed of semiconductor devices, and the number of signal wirings has been required to increase on a multilayer wiring board on which the semiconductor elements are mounted. In contrast,
A signal wiring having a strip line structure has an advantage that it can easily form a plurality of signal wiring layers and thus can easily cope with an increase in the number of signal wirings.

As a new problem arising in such a situation, there is a time difference in input timing between electric signals input to a semiconductor element. This time difference is a difference in time required for each electric signal to pass through the signal wiring, that is, a difference in propagation delay time, and occurs because the wiring length of each signal wiring is different. If the difference in the propagation delay time increases, the input timing between the electric signals input to the semiconductor element differs, which causes a malfunction of the semiconductor element.

In order to solve such a problem, in a conventional multilayer wiring board, as shown in a plan view of FIG. 8, wiring of signal wirings of a signal wiring group 102 formed on an insulating layer 101 is performed. By making the length the same, the propagation delay time of each signal wiring is made the same, and the semiconductor element 103 to which these are connected is
A design has been made in which the input timing of an electric signal to the signal wiring is the same for each signal wiring. Specifically, the distance connecting the start point and the end point of the signal wiring is reduced by making the wiring length of the signal wiring having a short distance connecting the start point and the end point of the signal wiring a structure in which a detour portion is provided in a part of the signal wiring. A method has been adopted in which the wiring length is made equal to the long signal wiring.

Further, as a line structure for reducing the propagation delay time of the signal wiring, a signal wiring is formed on the surface of the multilayer wiring board, and a power supply layer or a ground layer is formed so as to face the signal wiring. A microstrip line structure in which air is adjacent to the air has also been adopted. This is because the propagation delay time of the signal wiring is defined by the relative dielectric constant of the insulating material adjacent to the signal wiring. This is to reduce the dielectric constant and the propagation delay time.

On the other hand, a problem of simultaneous switching noise has arisen as a problem relating to power supply to a semiconductor element. This is because the power supply voltage required for switching the semiconductor element is supplied from the outside of the semiconductor element through the power layer and the ground layer, so that noise is generated due to the inductance component of the power layer or the ground layer of the multilayer wiring board. It is. Specifically, a transient current generated at the time of switching of a semiconductor element flows into a power supply layer or a ground layer in the multilayer wiring board, and a voltage variation occurs due to an inductance component of the power supply layer or the ground layer, which becomes noise and causes a semiconductor element. May cause malfunctions.

In order to solve such a problem, a method of incorporating a capacitor in which a large-area power supply layer and a ground layer are opposed to each other via an insulating layer in a multilayer wiring board has been performed. By forming the power supply layer and the ground layer having a large area so as to face each other, a capacitor having a large capacitance value of several nF can be built in the multilayer wiring board,
Since the impedance value of the built-in capacitor becomes small, it is possible to reduce simultaneous switching noise. Here, the impedance value is proportional to the square root of the inductance value, and is inversely proportional to the square root of the capacitance value. In general, it is known that simultaneous switching noise is reduced when the impedance value of the built-in capacitor is reduced. Further, in order to obtain a larger capacitance value, a plurality of capacitors are formed in a multilayer wiring board.

[0011]

However, as the information processing capability is required to be further improved, the operating speed of the semiconductor device exceeds 1 GHz and the number of simultaneous switching of the semiconductor device is rapidly increased. On the other hand, in the multilayer wiring board having the conventional structure, the distance connecting the start point and the end point of the signal wiring is short, the wiring length of the signal wiring is changed to a structure in which a detour portion is provided in a part of the signal wiring. By adopting a configuration in which the distance connecting the start point and the end point of the signal wiring is made equal to the wiring length of the signal wiring, the wiring length of the signal wiring having a short wiring length becomes unnecessarily long. as a result,
In proportion to the wiring length of the signal wiring, the electromagnetic coupling between the signal wirings and between the signal wiring and the power supply layer or the ground layer, that is, the capacitance and the inductance of the signal wirings increase, and electric noise such as signal noise and crosstalk noise increases. There is a problem that noise increases and a malfunction of the semiconductor element is caused.

Further, in order to make the wiring length uniform, a detour portion is provided in a part of the signal wiring which has a short distance connecting the start point and the end point of the signal wiring. Has also been problematic.

Further, when the signal wiring has a microstrip line structure, since the signal wiring is formed on the surface of the multilayer wiring board, it is difficult to form a plurality of signal wiring layers. There was a problem that it was not easy to cope with the increase in the number.

It has been found that in order to reduce simultaneous switching noise, it is necessary to reduce the impedance value even in a frequency band up to about five times the operating frequency of the semiconductor device.

Since the transient current generated at the time of switching of the semiconductor element contains various harmonic components in addition to the operating frequency of the semiconductor element, the harmonic component is required to effectively reduce the simultaneous switching noise. Need to be considered.

This harmonic component is generally an nth-order (n is an integer of 2 or more) frequency component when the operating frequency of the semiconductor element is a fundamental wave, and the higher-order harmonic component has a higher intensity. Is reduced. It is known that this harmonic component has a large component especially up to about five times the operating frequency. In order to reduce simultaneous switching noise, it is necessary to consider this harmonic component.

At this time, since the conventional multilayer wiring board has a structure in which a plurality of built-in capacitors having a single capacitance value are formed, the resonance frequency of the impedance characteristic of the built-in capacitor is changed to the operating frequency of the semiconductor element. By setting it near, the impedance value near the operating frequency could be reduced, but no consideration was given to the impedance value in the frequency band corresponding to higher-order harmonic components. Therefore, simultaneous switching noise can be reduced in a region where the operating frequency of the semiconductor element is low, but in a high frequency region where the operating frequency is several GHz or more, the impedance value of the built-in capacitor increases, and the simultaneous switching noise increases. Had problems.

Also, due to the parasitic inductance component contained in the multilayer wiring board, an anti-resonance frequency other than the self-resonance frequency is generated in the built-in capacitor, and EMI (Electro Magnetic Interference) noise at that frequency is increased. I also know that there are points.

The present invention has been completed to solve the above problems, and an object of the present invention is to reduce the electrical noise of signal wiring while making the propagation delay time of each signal wiring substantially the same, and to reduce the number of signal wiring. Provided is a multilayer wiring board suitable for an electronic circuit board or the like on which electronic components such as a semiconductor element operating at a high speed can be increased and the simultaneous switching noise and the EMI noise can be reduced. It is in.

[0020]

According to the present invention, there is provided a multilayer wiring board comprising a semiconductor element mounted on an upper surface thereof and a plurality of insulating layers laminated thereon, and a first wiring length provided on a surface of the insulating substrate. A microstrip line including a first signal line group formed by forming a plurality of signal lines having L1 and a power supply layer or a ground layer formed to face the first signal line group with the insulating layer interposed therebetween. And a second signal wiring group formed by forming a plurality of signal wirings having a second wiring length L2 inside the insulating substrate, and a second signal wiring group opposed to the second signal wiring group via the insulating layer. A strip line portion composed of a power supply layer or a ground layer formed on the upper and lower sides, and a built-in capacitor formed inside the insulating substrate and having a power layer and a ground layer opposed to each other with the insulating layer interposed therebetween. Multilayer A linear substrate, the first wiring length L1 and the second wiring length L2 is, 0.8 × (0.670 / εr
+0.475) ^1/2 ≦ L2 / L1 ≦ 1.2 × (0.670 / εr + 0.47
5) ^1/2 (where, L1> L2, with εr meet the relative dielectric constant of the insulating layer signal lines are formed), the embedded capacitor may harmonic components from the operating frequency band of the semiconductor element A plurality of components having different resonance frequencies in a frequency band range are formed so as to be connected in parallel, and a combined impedance value at an anti-resonance frequency generated between the different resonance frequencies is equal to or less than a predetermined value. .

According to the multilayer wiring board of the present invention, an insulating substrate having a semiconductor element mounted on the upper surface and a plurality of insulating layers laminated thereon, and a first wiring length L on the surface of the insulating substrate.
A first signal wiring group formed by a plurality of signal wirings each having 1 and a microstrip line portion formed by a power supply layer or a ground layer formed to face the first signal wiring group with an insulating layer interposed therebetween; A second signal wiring group formed by forming a plurality of signal wirings having a second wiring length L2 inside the insulating substrate, and a second signal wiring group formed above and below the second signal wiring group via an insulating layer. With a structure having a strip line portion composed of a power supply layer or a ground layer, the wiring length of each signal wiring for each of the first and second signal wiring groups becomes equal, and the propagation delay time is reduced. Since it is proportional to the length, the propagation delay time of each signal wiring of the first and second signal wiring groups is substantially the same for each signal wiring group.

Further, the first signal wiring group has a microstrip line structure, and the second signal wiring group has a strip line structure, each having a power supply layer or a ground layer formed to face each signal wiring group. Therefore, electromagnetic interference between the first and second signal wiring groups is cut off. Therefore, the propagation delay time Tpdl of the signal wiring for each of the first and second signal wiring groups is determined by the wiring length L of the signal wiring of each signal wiring group, the insulating layer in which each signal wiring group is formed, and air. Tpdl = {(εreff) ^1/2 / c} × L using the effective relative permittivity εreff defined by the relative permittivity of
(C is the speed of light).

Further, the relative dielectric constant of the insulating layer in which the first and second signal wiring groups are formed and the ratio of each wiring length are set to the relationship shown in the above equation, so that the first wirings having different wiring lengths are obtained. In addition, the propagation delay time of the second signal wiring group can be made substantially the same within a range of ± 20%, which is a range in which a malfunction of the semiconductor element does not easily occur.

Since the relative dielectric constant of the insulating layer is substantially the same in the insulating substrate, the wiring length L2 of the signal wiring of the second signal wiring group having the strip line structure is determined by the above equation. Is set shorter than the wiring length L1 of the signal wiring of the first signal wiring group having the following. From this, particularly in the second signal wiring group, it is possible to avoid that the wiring length of the signal wiring becomes unnecessarily long, so that electromagnetic coupling between the signal wirings and between the signal wiring and the power supply layer or the ground layer, that is, The capacitance and inductance of the signal wiring can be reduced, and electric noise such as signal noise and crosstalk noise can be reduced.

In addition, since it is possible to avoid an unnecessary increase in the wiring length of the signal wiring, particularly in the second signal wiring group, the wiring area of other signal wirings can be increased, and the wiring flexibility can be improved. .

Furthermore, since the microstrip line structure and the strip line structure are provided, a plurality of signal wiring layers having the strip line structure can be easily formed. The number of wirings can be easily increased.

Further, according to the multilayer wiring board of the present invention, there is provided a built-in capacitor in which the power supply layer and the grounding layer are opposed to each other with the insulating layer interposed therebetween inside the insulating substrate, and the built-in capacitor is connected to the semiconductor element. Since a plurality of components having different resonance frequencies are formed in parallel in the range of the frequency band of the harmonic component from the operating frequency band,
The resonance frequency with the lowest impedance value can be set for each built-in capacitor by dispersing it within the frequency band of the harmonic component from the operating frequency of the semiconductor element, and furthermore, the anti-resonance frequency generated between different resonance frequencies , The combined impedance value in the frequency band from the operating frequency of the semiconductor element to the harmonic component can be reduced over a wide frequency band.

When the combined impedance value at the anti-resonance frequency is 1 Ω or less, the inductance components of the power supply layer and the ground layer become small, and even in the high frequency region where the operating frequency of the semiconductor element is several GHz or more, the harmonic component thereof becomes high. , It is possible to reduce simultaneous switching noise including the above frequency band.

Further, since the power supply layer and the ground layer have a large area and a built-in capacitor having a large capacitance value of several nF can be formed, simultaneous switching noise can be reduced even when the operating frequency of the semiconductor element is as low as several MHz. It becomes possible to reduce.

Further, by controlling the capacitance values of the plurality of built-in capacitors, the anti-resonance frequency included in the impedance characteristics of the built-in capacitors can be set to a frequency that does not match the frequency of the harmonic component included in the electric signal. EMI noise can also be reduced.

Further, the wiring length of the signal wiring is shortened, and the voltage of the power supply layer and the grounding layer is stabilized due to the presence of the built-in capacitor. Thus, the electrical noise and the crosstalk noise of the signal wiring can be reduced.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a multilayer wiring board according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a sectional view showing an example of an embodiment of a multilayer wiring board of the present invention. FIG. 2 is a plan view showing an example of each wiring layer in the multilayer wiring board of the present invention.
(E) is a plan view of each wiring layer formed on the upper surface of the insulating layers 2a to 2e, and (f1) and (f2) are plan views of the upper surface and the lower surface of the insulating layer 2f. In this figure, 1 is a multilayer wiring board, 2 is an insulating board, and the insulating board 2 is formed by laminating a plurality of insulating layers 2a to 2f. In the multilayer wiring board 1 of the present invention, the insulating layers 2a to 2f are made of an insulating material having the same relative dielectric constant. A first signal wiring group 3 is formed on the insulating layer 2a, and a wide-area power supply layer or ground layer 4 is formed on the insulating layer 2b so as to face the first signal wiring group 3. The first signal wiring group 3 constitutes a microstrip line section 5 having a microstrip line structure. On the insulating layer 2c, a second signal wiring group 6 is formed, and on the insulating layers 2b and 2d, a large-area power supply layer or grounding layer 4 and 7 is provided facing the second signal wiring group 6. Are formed, and the second signal wiring group 6 constitutes a strip line section 8 having a strip line structure.

The first and second signal wiring groups 3 and 6
May have different signal transmissions.

In this example, a semiconductor element 13 such as a microprocessor or an ASIC is mounted on the upper surface of the multilayer wiring board 1, and a conductive bump 14 and a semiconductor element 13 made of solder such as tin (Sn) -lead (Pb) are used. It is electrically connected to the multilayer wiring board 1 through the connection electrode 12 for connecting the semiconductor element. On the surface (lower surface) of the multilayer wiring substrate 1 opposite to the surface on which the semiconductor element 13 is mounted, external electrodes 11 for electrically connecting to another wiring substrate are formed.

As shown in FIG. 2, the wiring lengths of the signal wirings of the first signal wiring group 3 and the second signal wiring group 6 are substantially the same for each signal wiring group. .

In general, the propagation delay time Tpd per unit wiring length of signal wiring is Tpd = (εreff) ^1/2 / c (εref
f is the effective relative permittivity defined by the relative permittivity of the insulating layer on which the signal wiring is provided and the air, and c is the speed of light). That is, the propagation delay time Tpd per unit wiring length of the signal wiring is proportional to the square root (1/2) of the effective relative permittivity refreff.
In a signal wiring having a large reff, the propagation delay time Tpd per unit wiring length of the signal wiring becomes large. On the contrary, in a signal wiring having a small effective relative permittivity εreff, the propagation delay per unit wiring length of the signal wiring becomes large. The time Tpd becomes smaller.

Here, the effective relative dielectric constant εreff in the microstrip line structure is generally obtained from the relative dielectric constant εr of the insulating layer in which the signal wiring is formed and the air (specific dielectric constant = 1) where the signal wiring is adjacent. As an empirical formula, εreff = 0.475εr +
0.670 is applied, and the effective relative dielectric constant εreff in the strip line structure is controlled by the power supply layer or the ground layer formed above and below the signal wiring so that the influence of the relative dielectric constant of air is cut off. A value equivalent to the relative dielectric constant εr of the insulating layer on which the signal wiring is formed, εreff = εr
It is.

From this, since the effective relative dielectric constant εreff of the microstrip line structure is smaller than the effective relative dielectric constant εreff of the stripline structure, the propagation delay time Tpd per unit wiring length of the signal wiring is smaller than that of the microstrip line structure. The strip line structure is larger than the strip line structure.

In this embodiment, the line structure of the first signal line group 3 is a microstrip line structure, and the line structure of the second signal line group 6 is a strip line structure. The propagation delay time Tpd2 per unit wiring length of the signal wiring of the second signal wiring group 6 is larger than the propagation delay time Tpd1 per unit wiring length of the signal wiring. Therefore, even if the wiring length L2 of the signal wiring of the second signal wiring group 6 is shorter than the wiring length L1 of the signal wiring of the first signal wiring group 3, the propagation delay time of the signal wiring is substantially the same. Can be

Next, a method of calculating the set value of the relative dielectric constant of the insulating layer for making the propagation delay time of the signal wiring of the microstrip line structure equal to the propagation delay time of the signal wiring of the strip line structure will be described. I do.

The propagation delay time Tpdl of the signal wiring is expressed by Tpdl =
{(Εreff) ^1/2 / c} × L (εreff is the effective relative permittivity defined by the relative permittivity of the insulating layer on which the signal wiring is provided and air, c is the speed of light, and L is the signal wiring group. Is the signal wiring length), the propagation delay time Tpdl1 of the signal wiring of the first signal wiring group 3 having the microstrip structure is given by Tpdl1 = L1 when the first wiring length is L1.
Can be defined by ^{{(0.475εr + 0.670) 1/2 /} c} × L1. Similarly, assuming that the second wiring length is L2, the propagation delay time Tpdl2 of the signal wiring of the second signal wiring group 6 having the strip structure is Tpdl2 = Tpdl2 =
{(Εr) ^1/2 / c} × L2.

Here, since the propagation delay time of each of the signal wiring groups 3 and 6 is made equal, when the equation is solved with Tpdl1 = Tpdl2, L2 / L1 = (0.670 / εr + 0.475) ^1/2
(Where L1> L2) is obtained. Further, the relative permittivity εr of the insulating layer and the first signal wiring group 3 are set so that the propagation delay time difference of ± 20%, which is a range in which the semiconductor element can be operated accurately and stably without causing malfunction, is obtained. The set values of the wiring length L1 of the signal wiring and the wiring length L2 of the signal wiring of the second signal wiring group 6 can be defined by the following equations. 0.8 × (0.670 / εr + 0.475 ) 1/2 ≦ L2 / L1 ≦ 1.2 ×
(0.670 / εr + 0.475) ^1/2 (where L1> L2) When L2 / L1 is out of the above range, the semiconductor element is likely to malfunction.

Preferably, the following equation: 0.9 × (0.670 / εr + 0.475) ^1/2 ≦ L2 / L1 ≦ 1.1 ×
(0.670 / εr + 0.475) ^1/2 (provided that L1> L2), the propagation delay time of each signal wiring should be the same even within the range of ± 10% difference in propagation delay time. Therefore, it is possible to cope with a further increase in the operation speed of the semiconductor element.

By making the first and second signal wiring groups 3 and 6 satisfy the above equation, the propagation delay times of the first and second signal wiring groups 3 and 6 can be made substantially the same. Not only that, since it is possible to avoid an unnecessary increase in the wiring length of the signal wiring particularly in the second signal wiring group 6, electromagnetic coupling between the signal wirings and between the signal wiring and the power supply layer or the ground layer can be prevented. That is, the capacitance and inductance of the signal wiring can be reduced, and electric noise such as signal noise and crosstalk noise can be reduced.

In this embodiment, the power supply or ground layers 7, 9, and 10 having a large area allow two layers in the multilayer wiring board.
The number of built-in capacitors is formed.

At this time, the power supply layer or the ground layer 7, 9,
10 makes layers of different functions alternately overlap. That is, when 7 and 10 are power supply layers, 9 is a ground layer and 7
If and 10 are ground layers, 9 is a power layer.

Here, the built-in capacitor will be described in detail with reference to FIGS.

FIG. 6A is a cross-sectional view of an essential part showing an example of an embodiment of the multilayer wiring board of the present invention. In FIG. 1, ground layers 4 and 9 and power supply layers 7 and 10 are shown. . In FIG. 6A, the power supply layers 63 and 65 correspond to the power supply layers 7 and 10 shown in FIG. The ground layers 70 and 72 correspond to the ground layers 4 and 9 shown in FIG.

In FIG. 6A, the power supply wiring is an external electrode.
From 61, it is connected to a power supply layer 63 through a via hole 62, connected to a power supply layer 65 through a via hole 64, and connected to a semiconductor element connection electrode 67 through a via hole 66. The ground wiring is connected from the external electrode 68 to the ground layer 70 through the via hole 69, is connected to the ground layer 72 through the via hole 71, and is connected to the semiconductor element connection electrode 74 through the via hole 73. By these,
Since a first built-in capacitor is formed between the power supply layer 63 and the ground layer 70 and a second built-in capacitor is formed between the power supply layer 65 and the ground layer 70, these electric circuits are illustrated in FIG. This can be represented by an electric circuit diagram shown in FIG. FIG.
As can be seen from (b), the two built-in capacitors are connected in parallel.

FIG. 7 is a cross-sectional view of an essential part showing an example of an embodiment of the multilayer wiring board of the present invention. In FIG. 1, power supply layers 4 and 9 and ground layers 7 and 10 are shown. FIG.
In FIG. 1, the ground layers 90 and 92 correspond to the ground layers 7 and 10 shown in FIG. The power supply layers 83 and 85 correspond to the power supply layers 4 and 9 shown in FIG.

In FIG. 7, the ground wiring is connected from the external electrode 88 to the ground layer 90 through the via hole 89,
Connected to ground layer 92 through 91 and via hole
It is connected to a semiconductor element connection electrode 94 through 93.
The power supply wiring is connected from the external electrode 81 to the power supply layer 83 through the via hole 82, is connected to the power supply layer 85 through the via hole 84, and is connected to the semiconductor element connection electrode 87 through the via hole 86. Thereby, the ground layer 90
And a first built-in capacitor is formed between the power supply layer 83 and
A second built-in capacitor is formed between the ground layer 92 and the power supply layer 83, and these electric circuits can be represented by an electric circuit diagram similar to FIG. 6B. Therefore, also in this case, the two built-in capacitors are connected in parallel.

In the example shown in FIG. 1, the thickness of the insulating layer 2e having the power supply layer or the ground layer 9 formed on the upper surface is larger than the thickness of the insulating layer 2d having the power supply layer or the ground layer 7 formed on the upper surface. It is set large. Thereby, the first built-in capacitor formed between the power supply layer or the ground layer 9 and the power supply layer or the ground layer 10 and the first built-in capacitor formed between the power supply layer or the ground layer 7 and the power supply layer or the ground layer 9 The capacitance value of the second built-in capacitor is different from that of the second built-in capacitor, and as shown in FIG. 3, each built-in capacitor has an impedance characteristic including a different resonance frequency.

FIG. 3 is a diagram showing an example of the impedance characteristic of the built-in capacitor in the multilayer wiring board of the present invention. In FIG. 3, the horizontal axis represents the frequency, and the vertical axis represents the impedance value of the built-in capacitor. Here, in the built-in capacitor formed in the multilayer wiring board 1,
The impedance characteristic in a region lower in frequency than the resonance frequency tends to show a capacitance component, and the impedance characteristic in a region higher in frequency than the resonance frequency tends to show an inductance component. Further, when a plurality of capacitors having different resonance frequencies are formed in parallel, the resonance frequencies of the respective built-in capacitors remain unchanged.
The impedance characteristics are synthesized at the intersection (anti-resonance point) of the impedance characteristics, and the frequency at the anti-resonance point, that is, the anti-resonance frequency is the frequency at which the respective impedance characteristics intersect.

Further, the simultaneous switching noise can be reduced as the impedance value of the built-in capacitor formed by the power supply layer or the ground layers 7, 9, 10 having a large area becomes smaller. In particular, when the operating frequency of the semiconductor element 13 is several GH
In a high frequency region of z or more, a harmonic component having a large component at a frequency that is an integral multiple of the operating frequency is included,
In particular, a semiconductor element that operates at high speed by reducing the impedance value in a frequency region including a frequency band up to about five times the operating frequency of the semiconductor element 13 in which the harmonic component increases.
Thirteen simultaneous switching noises can be reduced.

Here, the impedance value of the built-in capacitor becomes the smallest at the resonance frequency. According to the multilayer wiring board of the present invention, by forming a plurality of built-in capacitors having different resonance frequencies in parallel, the resonance frequency of each built-in capacitor is changed from the operating frequency band of the semiconductor element 13 to the frequency band of the harmonic component. Can be set arbitrarily in the range between. In the example shown in FIG. 3, the resonance frequency included in the impedance characteristic of the first internal capacitor is adjusted to the operating frequency band of the semiconductor element 13, and the resonance frequency included in the impedance characteristic of the second internal capacitor is adjusted to the frequency of the harmonic component. Match the band. The resonance frequency included in the impedance characteristics of the built-in capacitor can be arbitrarily set by changing the capacitance value of the built-in capacitor formed by the power supply layer or the ground layers 7, 9, and 10. In this example, the resonance frequency included in the impedance characteristic of the built-in capacitor is changed by changing the thickness of the insulating layer 2d or 2e on which the power supply layer or the ground layers 7 and 9 are formed, thereby changing the capacitance value of the built-in capacitor. Is set to a value. In this example, the thickness of the insulating layer 2e on which the first built-in capacitor is formed is the same as the thickness of the insulating layer 2d on which the second built-in capacitor is formed.
1.5 times the thickness of

Furthermore, since the combined impedance value at the anti-resonance frequency generated between these resonance frequencies is set to a predetermined value or less, the combined impedance value in the range from the operating frequency band of the semiconductor element 13 to the frequency band of the harmonic component is reduced. It can be reduced over a wide frequency band. Here, the combined impedance value at the anti-co-frequency generated between the resonance frequencies included in the impedance characteristics of the plurality of built-in capacitors can be arbitrarily set according to the capacitance value of each built-in capacitor and the number of the built-in capacitors. It is possible. The predetermined value of the combined impedance value in the multilayer wiring board of the present invention is appropriately set from the operating frequency of the semiconductor element 13 and the required simultaneous switching noise amount so as to satisfy the required characteristics.

Further, by setting the combined impedance value at the anti-resonance frequency to 1 Ω or less, the inductance component of the power supply layer or the ground layers 7, 9, and 10 can be extremely reduced, and the operating frequency of the semiconductor element 13 becomes several GHz.
It is possible to sufficiently effectively reduce simultaneous switching noise even in a high frequency region of z or more. Here, the effective operating frequency of the semiconductor element 13 for which the combined impedance value is 1 Ω or less is about 1 to 10 GHz, and the frequency of the harmonic component at that time is converted into five times the operating frequency of the semiconductor element 13. It is about 5 to 50 GHz.

Note that the anti-resonance frequency included in the impedance characteristics of the built-in capacitor formed by the power supply layer or the ground layers 7, 9, and 10 formed in the multilayer wiring board 1 depends on the operating frequency of the semiconductor element 13 and its harmonics. When the components match, the EMI noise tends to increase. Therefore, it is preferable to set the anti-resonance frequency of the impedance characteristic of the built-in capacitor to a frequency that does not match the operating frequency of the semiconductor element 13.

Next, another example of the embodiment of the multilayer wiring board of the present invention will be described with reference to FIGS.

FIG. 4 is a sectional view similar to FIG. In FIG. 4, 21 is a multilayer wiring board, 22 is an insulating substrate, and the insulating substrate 22 is formed by laminating a plurality of insulating layers 22a to 22f. Also in the multilayer wiring board 21 of this example, the insulating layer 22
a to 22f are made of an insulating material having the same relative dielectric constant. A first signal wiring group 23 is formed on the insulating layer 22a, and a wide-area power supply layer or ground layer 24 is formed on the insulating layer 22b so as to face the first signal wiring group 23. The first signal wiring group 23 constitutes a microstrip line section 25 having a microstrip line structure. On the insulating layer 22c, a second signal wiring group 26 is formed, and on the insulating layers 22b, 22d, a large-area power supply layer or ground layer 24, facing the second signal wiring group 26, is formed.
27, and the second signal wiring group 26 constitutes a strip line section 28 having a strip line structure.

The first and second signal wiring groups 23 and 26
May have different signal transmissions.

The signal wiring lengths of the first signal wiring group 23 and the second signal wiring group 26 have substantially the same wiring length for each signal wiring group.

In this example, the semiconductor element 33 is mounted on the upper surface of the multilayer wiring board 21, and the conductor bump 34 and the semiconductor element
33, it is electrically connected to the multilayer wiring board 21 via the connection electrode 32 for connecting the semiconductor element. Furthermore, the semiconductor element 33
An external electrode 31 for wiring board connection is formed on the surface of the multilayer wiring board 21 opposite to the surface on which is mounted.

The power supply layer or grounding layer 29, 30 is similar to the wide area power supply layer or grounding layer 27. In this example, the power supply layer or grounding layer 27, 29, 30 forms a multilayer wiring board. Two built-in capacitors are formed in parallel in 21.

At this time, the power supply layer or the ground layer 27, 29,
30 makes layers of different functions alternately overlap. That is, the power supply layers 27 and 30 are the ground layers 29 and the ground layers 27 and 30
In this case, the power supply layer 29 is used.

In this example, the power supply layer or ground layer 27, 29 is a wide area wiring having substantially the same area, and the power supply layer or ground layer 30 is a large area having a smaller area than the power supply layer or ground layer 27. It is formed by wiring. This allows
A first built-in capacitor is formed between the power supply layer or the ground layer 29 and the power supply layer or the ground layer 30, and a power supply from the first built-in capacitor is provided between the power supply layer or the ground layer 27 and the power supply layer or the ground layer 29. The second built-in capacitor having a small area where the layer and the ground layer face each other is formed. Each of the built-in capacitors has a different capacitance value because the opposing areas of the power supply layer and the ground layer are different, and each built-in capacitor has an impedance characteristic including a different resonance frequency.

In this example, the resonance frequency included in the impedance characteristics of the first built-in capacitor is adjusted to the operating frequency band of the semiconductor element 33, and the resonance frequency included in the impedance characteristics of the second built-in capacitor is adjusted to the frequency of the harmonic component. Match the band. The resonance frequency included in the impedance characteristics of the built-in capacitor can be arbitrarily set by changing the capacitance value of the built-in capacitor formed by the power supply layer or the ground layers 27, 29, and 30. In this example, the resonance frequency included in the impedance characteristics of the built-in capacitor is set to a desired value by changing the area of the wide area wiring of the power supply layer or the ground layer 30, thereby changing the capacitance value of the built-in capacitor.

Further, the combined impedance value at the anti-resonance frequency generated between these resonance frequencies is set to a predetermined value or less, and the combined impedance value in the frequency band of the harmonic component from the operating frequency of the semiconductor element 33 is increased over a wide frequency band. I'm making it smaller. In particular, by setting the combined impedance value at the anti-resonance frequency to 1 Ω or less, the inductance component of the power supply layer or the ground layers 27, 29, and 30 can be extremely reduced, and the operating frequency of the semiconductor element 33 becomes higher than several GHz. Even in the region, it is possible to sufficiently reduce simultaneous switching noise.

With such a structure, the set frequency range of the resonance frequency included in the impedance characteristics can be made wider than in the case where a plurality of built-in capacitors having different resonance frequencies are formed by changing the thickness of the insulating layer. It is easy to respond by increasing the operating frequency of the semiconductor element 33.

In this example, the power supply layer or the ground layer 27 is used.
Although the area of the wide area wiring layer of the power supply layer or the ground layer 30 is reduced, the area of the wide area wiring layer of the power layer or the ground layer 27 is reduced with respect to the power layer or the ground layer 30. Similar effects can be obtained.

Next, another embodiment of the multilayer wiring board of the present invention shown in FIG. 5 will be described.

FIG. 5 is a sectional view similar to FIG. In FIG. 5, 41 is a multilayer wiring board, 42 is an insulating substrate, and the insulating substrate 42 is formed by laminating a plurality of insulating layers 42a to 42f. In the multilayer wiring board 41 of this example, the insulating layer 42a
42d and 42f are made of an insulating material having the same relative dielectric constant. A first signal wiring group 43 is formed on the insulating layer 42a, and a first signal wiring group 43 is formed on the insulating layer 42b.
A power supply layer or ground layer 44 having a large area is formed so as to face 43, and the first signal wiring group 43 constitutes a microstrip line section 45 having a microstrip line structure. On the insulating layer 42c, a second signal wiring group 46 is formed, and on the insulating layers 42b, 42d, a large-area power supply layer or ground layer 4 is disposed facing the second signal wiring group 46.
4 and 47 are formed, and the second signal wiring group 46 constitutes a strip line section 48 having a strip line structure.

The first and second signal wiring groups 43 and 46
May have different signal transmissions.

The wiring lengths of the signal wirings of the first signal wiring group 43 and the second signal wiring group 46 have the same wiring length for each signal wiring group.

A semiconductor element 53 is mounted on the upper surface of the multilayer wiring board 41, and is electrically connected to the multilayer wiring board 41 via the conductor bumps 54 and the semiconductor element connecting electrodes 52 for connecting the semiconductor element 53. I have. Further, an external electrode 51 for connecting the wiring board is formed on the surface of the multilayer wiring board 41 opposite to the surface on which the semiconductor element 53 is mounted.

The power supply layer or grounding layer 49, 50 is similar to the wide area power supply layer or grounding layer 47. In this example, the power supply layer or grounding layer 47, 49, 50 forms a multilayer wiring board 41. Inside, two built-in capacitors are formed in parallel.

At this time, the power supply layer or the ground layer 47, 49,
50 makes layers of different functions alternately overlap. That is, the power supply layers 47 and 50 are the ground layers 49, and the ground layers 47 and 50
In this case, the power supply layer 49 is used.

In this example, the insulating layer 42e having the power supply layer or the ground layer 49 formed on the upper surface is made of an insulating material having a higher relative dielectric constant than the insulating layer 42d having the power supply layer or the ground layer 47 formed on the upper surface. Is formed. Thereby, the first built-in capacitor formed between the power supply layer or the ground layer 49 and the power supply layer or the ground layer 50 and the first built-in capacitor formed between the power supply layer or the ground layer 47 and the power supply layer or the ground layer 49 The capacitance value of the second built-in capacitor is different from that of the second built-in capacitor, and each built-in capacitor has an impedance characteristic including a different resonance frequency.

In this example, the resonance frequency included in the impedance characteristic of the first built-in capacitor is adjusted to the operating frequency band of the semiconductor element 53, and the resonance frequency included in the impedance characteristic of the second built-in capacitor is adjusted to the frequency of the harmonic component. Match the band. The resonance frequency included in the impedance characteristic of the built-in capacitor can be arbitrarily set by changing the capacitance value of the built-in capacitor formed by the power supply layer or the ground layers 47, 49, and 50. In this example, the resonance frequency included in the impedance characteristics of the built-in capacitor is changed by changing the relative permittivity of the insulating layers 42d and 42e on which the power supply layer or the ground layers 47 and 49 are formed, thereby changing the capacitance value of the built-in capacitor. It is set to the desired value.

Further, by setting the combined impedance value at the anti-resonance frequency generated between these resonance frequencies to a predetermined value or less, the combined impedance value in the frequency band from the operating frequency of the semiconductor element 53 to the harmonic component is widened. I'm making it smaller. In particular, by setting the combined impedance value at the anti-resonance frequency to 1Ω or less, the inductance component of the power supply layer or the ground layers 47, 49, and 50 can be extremely reduced, and the operating frequency of the semiconductor element 53 becomes higher than several GHz. Even in the region, it is possible to sufficiently reduce simultaneous switching noise.

With such a structure, the capacitance value of the built-in capacitor can be further increased, so that the impedance value can be further reduced.

In this example, the relative permittivity of the insulating layer 42e is larger than the relative permittivity of the insulating layer 42d. However, the relative permittivity of the insulating layer 42d may be larger than the relative permittivity of the insulating layer 42e. Similar effects can be obtained.

In the multilayer wiring board of the present invention, a similar wiring structure may be further laminated to form a multilayer wiring board.

The structure of the signal wiring may be a coplanar structure in which a power supply layer or a ground layer is formed adjacent to the signal wiring, and may be appropriately selected and used according to the specifications required for the multilayer wiring board. be able to.

A multilayer wiring board may be constructed by attaching a chip resistor, a thin film resistor, a coil inductor, a cross inductor, a chip capacitor or an electrolytic capacitor, or the like.

The shape of each insulating layer in plan view is as follows:
The shape may be a square, a rectangle, a diamond, a hexagon, an octagon, or the like.

The multilayer wiring board of the present invention can be used as a package for storing electronic parts such as a package for storing semiconductor elements, a substrate for mounting electronic parts, a so-called multichip module or multichip on which a large number of semiconductor elements are mounted. Used as a package or motherboard.

In the multilayer wiring board of the present invention, each insulating layer is formed by, for example, a ceramic green sheet laminating method.
Using an inorganic insulating material such as aluminum oxide sintered body, aluminum nitride sintered body, silicon carbide sintered body, silicon nitride sintered body, mullite sintered body or glass ceramics, or polyimide, epoxy Electricity such as a composite insulating material using an organic insulating material such as resin, fluororesin, polynorbornene or benzocyclobutene, or combining an inorganic insulating powder such as a ceramic powder with a thermosetting resin such as an epoxy resin. It is formed using an insulating material.

These insulating layers are manufactured as follows. For example, in the case of a sintered body of aluminum oxide, first, an appropriate organic binder, a solvent and the like are added to and mixed with a raw material powder such as aluminum oxide, silicon oxide, calcium oxide or magnesium oxide to form a slurry. This is formed into a sheet by employing a conventionally known doctor blade method to obtain a ceramic green sheet. Then, a metal paste to be used for each signal wiring group and each wiring conductor layer is printed and applied in a predetermined pattern, and is laminated on top and bottom. Finally, the laminated body is fired at a temperature of about 1600 ° C. in a reducing atmosphere. Is done.

In the case of an epoxy resin, for example, an insulating layer made of a glass epoxy resin or the like formed by impregnating a ceramic or a glass fiber woven cloth with an epoxy resin in general. An insulating layer made of an organic resin such as an epoxy resin formed by applying an organic resin precursor by a coating technique such as a spin coating method or a curtain coating method and performing a thermosetting treatment on the upper surface thereof, and copper. It is manufactured by alternately laminating thin film wiring conductor layers formed by adopting thin film forming technology such as electroless plating method and vapor deposition method and photolithography technology, and heating and curing at a temperature of about 170 ° C. .

The thickness of these insulating layers is appropriately set according to the characteristics of the material to be used so as to satisfy the conditions such as mechanical strength and electrical characteristics corresponding to required specifications.

As a method for obtaining insulating layers having different relative dielectric constants, for example, an inorganic insulating material such as aluminum oxide, aluminum nitride, silicon carbide, silicon nitride, mullite or glass ceramics, or a polyimide or epoxy resin Add powder of high dielectric material such as barium titanate, strontium titanate, calcium titanate or magnesium titanate to organic insulating material such as PTFE, fluororesin, polynorbornene or benzocyclobutene, and heat and cure at appropriate temperature By doing so, a material having a desired relative permittivity may be obtained.

At this time, the particle size of the high dielectric material to be added to and mixed with the inorganic insulating material or the organic insulating material is determined by the ratio in the insulating layer caused by adding and mixing the high dielectric material to the inorganic or organic insulating material. In order to reduce the occurrence of variation in the dielectric constant and the decrease in workability due to the change in the viscosity of the insulating layer, the thickness is preferably in the range of 0.5 μm to 50 μm.

The content of the high dielectric material to be added to and mixed with the inorganic insulating material and the organic insulating material is set to make the relative dielectric constant of the insulating layer large, and to make the inorganic insulating material and the organic insulating material highly compatible with the high dielectric material. In order to prevent a decrease in the adhesive strength of the material, the content is desirably 5% by weight to 75% by weight.

The wide area pattern as each signal wiring group or power supply layer or ground layer is, for example, tungsten (W), molybdenum (Mo), molybdenum manganese (M
o-Mn), metal powder such as copper (Cu), silver (Ag) or silver palladium (Ag-Pd), or copper (Cu), silver (Ag), nickel (Ni), chromium (C
r), titanium (Ti), gold (Au) or niobium (N
b) or a thin film of a metal material such as an alloy thereof.

Specifically, when a wide area pattern for each signal wiring group or power supply layer or ground layer is formed by metallizing metal powder of W, an appropriate organic binder, a solvent or the like is added to and mixed with W powder. The metal paste can be formed by printing and applying a predetermined pattern on a ceramic green sheet serving as an insulating layer, and firing this together with a laminate of ceramic green sheets.

On the other hand, when a thin film of a metal material is formed,
For example, after a metal film is formed by a sputtering method, a vacuum evaporation method, or a plating method, a predetermined wiring pattern can be formed by a photolithography method.

In such a multilayer wiring board, by appropriately setting the wiring width of each signal wiring group in accordance with the relative dielectric constant of the insulating layer in which each signal wiring group is provided, The characteristic impedance values of the signal wirings can be the same.

The present invention is not limited to the above embodiment, and various changes may be made without departing from the scope of the present invention. For example, three or more signal wiring groups may be formed between different insulating layers. Further, the number of built-in capacitors formed in the multilayer wiring board may be three or more. further,
The pattern of the power supply layer or the ground layer may be a so-called mesh pattern having a large number of openings.

In the present invention, with respect to the first signal wiring group in which a plurality of signal wirings having the first wiring length L1 are formed, the wiring length of each signal wiring in the first signal wiring group is substantially equal to the first wiring length. What is necessary is just the wiring length L1. The same applies to the second wiring length L2.

[0102]

According to the present invention, there is provided a multilayer wiring board comprising a semiconductor element mounted on an upper surface thereof and a plurality of insulating layers laminated thereon, and a signal wiring having a first wiring length L1 on the surface of the insulating substrate. And a microstrip line portion composed of a power supply layer or a ground layer formed so as to face the first signal wiring group with a plurality of first signal wiring groups and an insulating layer interposed therebetween, and the inside of the insulating substrate. Signal wiring group having a second wiring length L2 and a power supply layer or a ground layer formed above and below the second signal wiring group via an insulating layer so as to face the second signal wiring group. And a built-in capacitor formed by arranging a power supply layer and a ground layer inside the insulating substrate so as to face each other with the insulating layer interposed therebetween, the first wiring comprising: Length L1 and second arrangement Long L2 is, 0.8 × (0.670 / εr + 0.475) 1/2 ≦ L2 / L1 ≦ 1.2 ×
^{(0.670 / εr + 0.475) 1} /2 ( although, L1> L2, εr
Is the relative dielectric constant of the insulating layer on which the signal wiring is formed), and a plurality of built-in capacitors having different resonance frequencies in the range from the operating frequency band of the semiconductor element to the frequency band of the harmonic component are arranged in parallel. Since the combined impedance value at the anti-resonance frequency generated between different resonance frequencies is set to be equal to or less than a predetermined value, the wiring length of each signal wiring for each of the first and second signal wiring groups is Thus, the propagation delay time of each signal wiring of the first and second signal wiring groups becomes substantially the same for each signal wiring group.

Further, the propagation delay times of the first and second signal wiring groups having different wiring lengths can be made substantially the same within a range of ± 20%, which is a range in which a malfunction of the semiconductor element hardly occurs.

In addition, the capacitance and inductance of the signal wiring can be reduced, the electrical noise such as signal noise and crosstalk noise can be reduced, and the wiring length of the signal wiring particularly in the second signal wiring group can be reduced. Since unnecessary lengthening can be avoided, the wiring area of other signal wirings can be widened, and the wiring flexibility is improved.

Further, it is possible to easily increase the number of signal wirings in response to the increase in the number of signals of the semiconductor element.

Further, it is possible to reduce the combined impedance value in the frequency band of the harmonic component from the operating frequency of the semiconductor element in a wide frequency band. When the combined impedance value at the anti-resonance frequency is 1 Ω or less, simultaneous switching noise can be reduced even in the high frequency band where the operating frequency of the semiconductor element is several GHz or more, including the frequency band of its harmonic component. .

The operating frequency of the semiconductor device is several MHz.
And simultaneous switching noise can be reduced even in a low frequency band.

Further, EMI noise can be reduced.

Further, it is possible to more effectively reduce electric noise and crosstalk noise of signal wiring.

As a result, according to the present invention, it is possible to reduce the electric noise of the signal wiring while increasing the propagation delay time of each signal wiring and to increase the number of signal wirings, A multilayer wiring board which can reduce switching noise and EMI noise and is suitable for an electronic circuit board on which electronic parts such as semiconductor elements operating at high speed are mounted can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an example of an embodiment of a multilayer wiring board of the present invention.

FIGS. 2A to 2F are plan views showing an example of each wiring layer of the multilayer wiring board of the present invention.

FIG. 3 is a diagram showing an example of an impedance characteristic of a built-in capacitor in the multilayer wiring board of the present invention.

FIG. 4 is a sectional view showing another example of the embodiment of the multilayer wiring board of the present invention.

FIG. 5 is a sectional view showing another example of the embodiment of the multilayer wiring board of the present invention.

FIG. 6A is a cross-sectional view of an essential part showing an example of an embodiment of a multilayer wiring board of the present invention, and FIG. 6B is a circuit diagram of a built-in capacitor of the multilayer wiring board of the present invention.

FIG. 7 is a cross-sectional view of a principal part showing an example of an embodiment of a multilayer wiring board of the present invention.

FIG. 8 is a plan view showing an example of a signal wiring group in a conventional multilayer wiring board.

[Explanation of symbols]

1, 21, 41: multilayer wiring board 2, 22, 42: insulating board 2a to 2f, 22a to 22f, 42a to 42f: insulating layer 3, 23, 43: first signal wiring group 4, 7, 9, 10 , 24, 27, 29, 30, 44, 47, 49, 50: power supply layer or ground layer 5, 25, 45: microstrip line section 6, 26, 46: second signal wiring group 8, 28, 48: Strip line section 13, 33, 53: Semiconductor element 63, 65, 83, 85: Power supply layer 70, 72, 90, 92: Ground layer

Claims (2)

[Claims] 1. An insulating substrate having a semiconductor element mounted on an upper surface thereof and a plurality of insulating layers laminated thereon, and a plurality of signal wirings having a first wiring length L1 formed on a surface of the insulating substrate. A microstrip line section including a power supply layer or a ground layer formed to face one of the signal wiring groups and the first signal wiring group with the insulating layer interposed therebetween; A second signal line group formed by forming a plurality of signal lines having a line length L2, and a power supply layer or a ground layer formed above and below the second signal line group via the insulating layer so as to face the second signal line group. A multi-layer wiring board, comprising: a strip line portion, and a built-in capacitor formed by arranging a power supply layer and a ground layer inside the insulating substrate so as to face each other with the insulating layer interposed therebetween. With the wiring length L1 The second wiring length L2 is 0.8 × (0.670 / εr + 0.475) ^1/2 ≦ L2 / L1 ≦ 1.2 ×
^{(0.670 / εr + 0.475) 1} /2 ( although, L1> L2, εr
Is the relative dielectric constant of the insulating layer on which the signal wiring is formed), and the built-in capacitor has a plurality of resonance frequencies different from each other in a range from an operating frequency band of the semiconductor element to a harmonic component frequency band. Are formed so as to be connected in parallel, and a combined impedance value at an anti-resonance frequency generated between the different resonance frequencies is equal to or less than a predetermined value. 2. The multilayer wiring board according to claim 1, wherein a combined impedance value at the anti-resonance frequency is 1Ω or less.