JP2002222862A - High speed high density cell array structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a customizable function cell array having a high density, high driving capacity. SOLUTION: An integrated circuit comprising a plurality of first circuit elements having a first width is provided. These circuit elements are arranged in a plurality of rows in a semiconductor substrate. The integrated circuit further comprising a plurality of second circuit elements having a width equal to two times that of the first circuit element. The second circuit elements are arranged in a plurality of rows and occupy the width of two first circuit elements.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD This invention relates to custom integrated circuits or application specific integrated circuits (ASICs).
In the field. In particular, the present invention relates to a structure that provides a customized device for a specific application that has a high functional density and operates at high speed.

(Description of Related Art) ASIC manufacturers have many demands which are mutually incompatible. Customers demand shorter development times while demanding increasingly complex features. In integrated circuit design, the layout density (and thus the maximum complexity per integrated circuit) is maximized for a full custom specification. However, customization of integrated circuits is very time consuming. It is impossible to meet the customer's demand for instant delivery with custom specifications. Standard cell arrays have begun to be used as a useful structure to meet this requirement while maintaining a reasonable functional density.

[0003] In general, a standard cell array is composed of a plurality of rows of fixed width. The length of each cell may be different to provide the required cell functionality. For example, the simplest cell is an inverter. In a CMOS design, the inverter includes one N-channel transistor and one P-channel transistor. Between the rows, wirings for cell connection (r
(outing) area is provided. Further, the power lead passes through the wiring region or includes an upper layer region of the cell region. Standard cells have traditionally achieved high functional density and short delivery times by using computer design tools. An example of this type of device is the GS30 series from Texas Instruments.

[0004]

However, standard cell systems inherently require a design compromise. For higher densities, arrays are designed with a minimum row width. For example, the minimum width is 6 square (square). □ (square) is a standardized unit equal to the smallest feature size that can be formed on an integrated circuit. A 6 □ (square) row provides a very high density array. However, if half of the rows are used for P-type transistors and the other half are used for N-type transistors, the maximum transistor width is approximately 2 squares (after including the isolation structure between devices). Such a small transistor cannot have a driving capability suitable for high-speed operation. On the other hand, widening the row for high drive transistors reduces the array density. The present invention provides a structure intended for high density, high drive transistors,
Solve this trade-off.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to provide a customizable high-density, high-drive-capability functional cell array.

It is another object of the present invention to provide a structure which maximizes the width of a P-channel transistor in a standard cell array to compensate for the low speed operation of a P-type device.

[0007]

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects are achieved by one embodiment of the present invention that includes an integrated circuit having a plurality of first circuit elements having a first width. These circuit elements are arranged in a plurality of rows in a semiconductor substrate. Further, the integrated circuit includes a plurality of second circuit elements, and the width of the second circuit element is equal to the first circuit element.
It is twice the circuit element. The second circuit elements are arranged in a plurality of rows and occupy the width of two first circuit elements.

According to another embodiment of the present invention, an integrated circuit having a plurality of first circuit elements having a first width is included.
The first circuit element is composed of a plurality of rows in a semiconductor substrate. The row is divided into a first region of a first conductivity type and a second region of a second conductivity type. The first and second regions are alternately arranged for at least two adjacent rows, and the first regions of at least two adjacent rows are adjacent to each other. The integrated circuit includes a plurality of second circuit elements, wherein the width of the second circuit element is twice the width of the first circuit element. The second circuit elements are arranged in a plurality of rows and occupy the width of two first circuit elements. At least one second circuit element spans two adjacent rows. For a better understanding of the present invention and its features, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a layout diagram of a conventional cell array. Array 10 includes a plurality of rows 12 for circuit element placement, often referred to as standard cells. FIG. 2 is a layout diagram of an exemplary cell as used in the prior art. Cell 20 is designed for high density. The row width of the array including the cells 20 is 6 square (square). Cell 20
Is indicated by the length of 4 □ (square). However, cells used with cell 20 may be longer. Cell 30 is designed for high speed arrays. Cell 30
Has a width of 8 square (square) and a length of 5 square (square). Further, the cell 30 and the cell 20 are functionally equivalent, but the transistor of the cell 30 is wider. As is customary in the art, the transistor width is the surface dimension perpendicular to the carrier flow in the transistor channel region. As the width of the transistor increases, the current driving capability increases. As the current driving capability increases, the operation of the cell 30 is correspondingly faster than that of the cell 20. However, the array containing cells 30 will be larger for the same function, and the function must be somewhat sacrificed for the same array size. The present invention does not require a compromise between array size and array speed.

FIG. 3 is a layout diagram of an array designed in accordance with the principles of the present invention. Array 40 is described, for example, in US Pat. It is preferably a CMOS or bipolar CMOS integrated circuit manufactured by the process described in US Pat. No. 5,767,551. This patent is assigned to the assignee of the present application and is hereby incorporated by reference. FIG. 3 shows that a portion of array 40 has two rows 4 of a standard cell array.
1, 43. Cells 42, 44, 46 and 48
Are shown. Further, cell 5
Part of 0, 52 is shown. These cells are compact cells of 6 square width. Wiring areas 58 and 60 are provided at appropriate positions for inter-cell wiring of leads such as a power lead (V _DD ) and a ground lead (V _SS ).

Array 40 includes 12 □ wide cells 54, 56 spanning both rows 41, 43. These cells are
Included in arrays when high drive capability is required to maintain circuit speed. For example, a cell may be needed to drive an input to some other cell. Assuming that a low drive cell, such as cell 46, is used for this function, the drive current will be low and it will take a long time to charge and discharge the input of the downstream cell to the desired signal value.
The use of cells 54, 56 allows for the use of higher drive cells when speed needs to be maintained, but for the majority of the array functions small cells (42, 44,
46, 48, 50, 52) can be used. In this way, a high-density, high-speed array is obtained.

FIG. 4 is another diagram illustrating the array 40,
Grid lines have been omitted to more clearly show the cell layout and wiring area. FIG. 5 is a layout of an array 140, illustrating another embodiment of the present invention. Parts having the same reference numerals in FIGS. 5 and 3 have the same functions. The embodiment of FIG. 5 includes an N-well 142 that spans rows 41 and 43. Further, a P-well 144 is formed in row 41,
Well 146 is formed in row 43. N-well 142
Is a region for forming a P-channel transistor by a well-known P-channel transistor fabrication method as described in the Smyling et al. Patent.

In practice, N well 142 is two N wells formed adjacently. One is for row 41 and the other is for row 43. The important point is that in cells 54 and 56, N-well 142 forms one continuous region. As a result, it is possible to form a transistor having a width obtained by subtracting a region required for isolation from devices formed in the P wells 144 and 146 from the entire width of the N well 142. With this structure, a very wide P-channel transistor can be provided in the cells 54 and 56. As is well known in the art, P-channel transistors are inherently less drivable than N-channel transistors because the main carrier of the P-channel transistor is a hole. The primary carrier for N-channel devices is electrons. Holes have lower mobility than electrons. Therefore, if the size, characteristics and drive voltage of the transistor are the same, the drive current of the N-channel transistor is low. The advantage of using a wide P-channel transistor in the embodiment of FIG. 5 will be described in detail below.

FIG. 6 is a layout diagram showing another embodiment of the present invention. The same reference numerals in array 240 have the same functions as in array 40. Like array 140 of FIG. 5, array 240 is designed for CMOS cells. The area for the P-channel transistor in row 41 is N well 2
42. The area for the N-channel transistor in row 41 is included in P-well 244. The area for the P-channel transistor in row 43 is included in N-well 248. The region for the N-channel transistor in row 43 is included in P-well 246. Therefore, a complete CMOS cell can be formed in each row.

FIG. 7 is a layout diagram of a D-type flip-flop cell 300 suitable for use in the present invention. The row width of the flip-flop 300 is 7 square (square), which is suitable for use in a single row having a width of 7 square. V _DD is supplied to the wiring region 58. V _SS at the ground bus that overlaps the boundary between rows
Is supplied. Terminal 310 is for D input signal, terminal 312
Is for a clock signal, and terminal 316 is for Q output. Region 344 is an N-well for a P-channel transistor, and region 342 is a P-well for an N-channel transistor.

FIG. 8 shows an inverter 400 suitable for use in one row in the present invention. Inverter 400
Are the P-channel transistor 410 and the N-channel transistor 412. P channel transistor 410 is formed in N well 444. N-channel transistor 412 is formed in P well 442. V _DD is provided to the source of transistor 410.
V _SS is provided to the source of transistor 412. The drains of transistors 410 and 412 are coupled together by lead 414 and are connected to output terminal 416. A gate 420 is coupled to the input terminal 418, and both transistors 4
10 and 412 function as gates.

In contrast to inverter 400, inverter 500 of FIG. 9 is a high drive inverter suitable for use in a two row cell. The source of P-channel transistor 510 is connected to V _DD via lead 516. The lead 516 is a common bus overlapping the boundary between the rows 541 and 543. The sources of transistors 512, 514 are connected to V _SS via leads 518, 520, respectively. The gate 522 functions as a common gate of the transistors 510, 512, and 514 and also functions as an input terminal. The drains of transistors 510, 512, 514 are interconnected by leads 524, 526 and function as output terminals. In the preferred embodiment, the leads 52
Reference numerals 4 and 526 denote one lead formed of a multilayer metal system. P-channel transistor 510 is N-well 542
Formed. N-channel transistors 512, 51
4 are formed in the P wells 544 and 546, respectively.
The important point is that the width W of the P-channel transistor 510 is equal to a value obtained by subtracting the area used for separation from the transistors 512 and 514 from the full width of one row. Since the width does not need to separate between the two halves of transistor 510, transistor 4 in FIG.
10 or more times the channel width. On the other hand, transistor 410 must have isolation devices above and below its source and drain diffusions. Therefore,
In the disclosed embodiment of the present invention, the width that can be achieved by the prior art is 2
More than twice as many selected transistors can be used.

Although specific embodiments of the present invention have been described herein, they do not limit the scope of the invention. For example, although specific circuits and device fabrication techniques are described and referenced herein, many specific devices and fabrication techniques may be utilized within the scope of the invention.
Many embodiments will be apparent to those skilled in the art from the teachings herein. For example, in the disclosed embodiment a wide P
Although adjacent N-well regions are used to provide channel transistors, the teachings of the invention can be utilized to provide wider N-channel transistors in adjacent P-well regions. As another example, while the disclosed embodiments use CMOS transistors, the teachings of the invention can be effectively applied to circuits using bipolar transistors or circuits using only P-type or N-type transistors. The scope of the invention is limited only by the claims.

With respect to the above description, the following items are further disclosed. (1) A plurality of first circuit elements having a first width and arranged in a plurality of rows in a semiconductor substrate, and at least two circuit elements having a width equal to an integral multiple of the first width and arranged in a plurality of rows. Minute first
An integrated circuit having a plurality of second circuit elements occupying the width of the circuit element. (2) The integrated circuit according to (1), wherein the integral multiple is equal to twice. (3) The integrated circuit according to (1) or (2), wherein the first and second circuit elements include both P-type and N-type transistors. (4) The integrated circuit according to any one of the above items, wherein the first circuit element is an inverter. (5) The integrated circuit according to any one of the above items, wherein the second circuit element is an inverter. (6) The first circuit element in which the first circuit element is a flip-flop
4. The integrated circuit according to any one of items 3 to 3. (7) A plurality of first standard cells having a first width and arranged in a plurality of rows in a semiconductor substrate, and a plurality of rows having a width equal to an integral multiple of the first width and extending at least over a width of two rows. An integrated circuit comprising: a plurality of second standard cells arranged in the above. (8) At least one first circuit element having a first width and arranged in a plurality of rows in the semiconductor substrate, wherein the row is the first circuit element.
Divided into a first region of a conductivity type and a second region of a second conductivity type,
The first and second regions are alternately arranged for at least two adjacent rows, and the first regions of at least two adjacent rows are adjacent to each other with the first circuit element and at least two times the first width. And at least one second circuit element occupying at least two widths of the first circuit element and arranged in a plurality of rows over at least two adjacent rows. (9) At least one first standard cell having a first width and arranged in a plurality of rows in the semiconductor substrate, wherein the row is the first standard cell.
Divided into a first region of a conductivity type and a second region of a second conductivity type,
First and second regions are alternately arranged for at least two adjacent rows, and a first region of at least two adjacent rows has a first standard cell adjacent to each other and a second region equal to at least twice the first width. Integrated circuit having at least one second standard cell occupying a plurality of rows and occupying the width of two first standard cells, the second standard cell spanning at least two adjacent rows.

(10) forming a plurality of first circuit elements having a first width in a plurality of rows in a semiconductor substrate;
Forming a plurality of second circuit elements having a width equal to an integral multiple of the width of the first circuit element and occupying at least two first circuit elements in a plurality of rows. (11) The method according to (10), wherein the integer multiple is equal to twice. (12) The method according to (10) or (11), wherein the first and second circuit elements include both P-type and N-type transistors. (13) The method according to any one of items 10 to 12, wherein the first circuit element is an inverter. (14) The method according to any one of items 10 to 13, wherein the second circuit element is an inverter. (15) The method according to any one of items 10 to 12, wherein the first circuit element is a flip-flop. (16) forming a plurality of first standard cells having a first width in a plurality of rows in a semiconductor substrate; and forming a plurality of second standard cells having a width equal to an integral multiple of the first width by at least two.
Forming a plurality of rows over a row width.

(17) A step of forming at least one first circuit element having a first width in a plurality of rows in a semiconductor substrate, wherein the rows have a first region of a first conductivity type and a second region of a second conductivity type. Forming first circuit elements such that the first regions are divided into second regions and the first regions of at least two adjacent rows are adjacent to each other, and the first and second regions are alternately arranged in at least two adjacent rows. Forming at least one second circuit element having a second width equal to at least twice the first width and occupying the width of two first circuit elements in a plurality of rows over at least two adjacent rows. And forming an integrated circuit. (18) forming at least one first standard cell having a first width in a plurality of rows in a semiconductor substrate,
A row is divided into a first region of a first conductivity type and a second region of a second conductivity type, and the first and second regions are alternately arranged for at least two adjacent rows, and the first of the at least two adjacent rows. Forming first standard cells such that the regions are adjacent to each other; and defining at least one second standard cell having a width equal to an integer multiple of the first width and occupying the width of two first standard cells. Forming a plurality of rows over at least two adjacent rows. (19) The method for forming an integrated circuit according to (42), wherein the second width is equal to twice the first width. (20) The integrated circuit forming method according to Item 42, wherein the first conductivity type is P-type and the second conductivity type is N-type. (21) The method of forming an integrated circuit according to item 42, wherein the first standard cell is an inverter. (22) The method of forming an integrated circuit according to item 42, wherein the second standard cell is an inverter. (23) The method of forming an integrated circuit according to item 42, wherein the first standard cell is a flip-flop. (24) The disclosed embodiment of the present invention includes an integrated circuit having a plurality of first circuit elements having a first width. These circuit elements are formed in a plurality of rows in the semiconductor substrate. The integrated circuit also includes a plurality of second circuit elements having a width equal to an integral multiple of the width of the first circuit element. The second circuit elements are formed in a plurality of rows and occupy the width of two first circuit elements. Another embodiment of the present invention includes an integrated circuit having a plurality of first circuit elements having a first width. The first circuit element is formed in a plurality of rows in the semiconductor substrate. The rows are the first region of the first conductivity type and the second region.
It is divided into a conductive type second region. The first and second regions are alternately arranged in at least two rows with the first regions of at least two adjacent rows adjacent to each other. The integrated circuit includes a plurality of second circuit elements that are twice as wide as the first circuit elements. The second circuit element is arranged in a plurality of rows,
Occupies the width of two first circuit elements.

[Brief description of the drawings]

FIG. 1 is a layout diagram of an array according to the related art.

FIG. 2 is a layout diagram comparing two prior art cells of a standard cell array.

FIG. 3 is a layout diagram showing a part of a standard cell array according to an embodiment of the present invention.

FIG. 4 is a view obtained by removing grid lines from FIG. 3;

FIG. 5 is a layout diagram showing another embodiment of the present invention.

FIG. 6 is a layout diagram showing another embodiment of the present invention.

FIG. 7 is a layout diagram of a standard cell suitable for use in the present invention.

FIG. 8 is a layout diagram of another standard cell suitable for use in the present invention.

FIG. 9 is a layout diagram of a high drive cell suitable for use in the present invention.

[Explanation of symbols]

 40 array 42 cell 44 cell 46 cell 48 cell 54 cell 56 cell 58 wiring area 60 wiring area 140 array 142 N well 144 P well 146 P well 240 array 242 N well 244 P well 246 P well 248 N well 300 D flip-flop 400 Inverter 410 P-channel transistor 412 N-channel transistor 416 Output terminal 418 Input terminal 420 Gate 442 P-well 444 N-well 500 Inverter 510 P-channel transistor 512 N-channel transistor 514 N-channel transistor 542 N-well 544 P-well 546 P-well

Claims (2)

[Claims] 1. A plurality of first circuit elements having a first width and arranged in a plurality of rows in a semiconductor substrate; and having a width equal to an integral multiple of the first width and arranged in a plurality of rows, at least An integrated circuit having a plurality of second circuit elements occupying the width of two first circuit elements. 2. A method for forming a plurality of first circuit elements having a first width in a plurality of rows in a semiconductor substrate, the method comprising: forming a first circuit element having a width equal to an integral multiple of the first width; Forming a plurality of second circuit elements occupying the width of the circuit elements in a plurality of rows.