JP2002222768A - Jig for semiconductor - Google Patents
Jig for semiconductorInfo
- Publication number
- JP2002222768A JP2002222768A JP2001016243A JP2001016243A JP2002222768A JP 2002222768 A JP2002222768 A JP 2002222768A JP 2001016243 A JP2001016243 A JP 2001016243A JP 2001016243 A JP2001016243 A JP 2001016243A JP 2002222768 A JP2002222768 A JP 2002222768A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- jig
- semiconductor
- light
- shielding layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 238000010438 heat treatment Methods 0.000 claims abstract description 21
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 15
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 229910052724 xenon Inorganic materials 0.000 description 10
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 10
- 239000007770 graphite material Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000003754 machining Methods 0.000 description 3
- 239000011162 core material Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- AVGQTJUPLKNPQP-UHFFFAOYSA-N 1,1,1-trichloropropane Chemical compound CCC(Cl)(Cl)Cl AVGQTJUPLKNPQP-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- YGZSVWMBUCGDCV-UHFFFAOYSA-N chloro(methyl)silane Chemical compound C[SiH2]Cl YGZSVWMBUCGDCV-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
Description
【0001】[0001]
【技術分野】本発明は,CVD法により生成させた炭化
珪素(以降,CVD−SiCと省略表記する)よりな
り,エピタキシャル成長工程をはじめとする,主として
半導体デバイスの製造プロセスにおいてウエハを熱処理
する際に用いられるサセプタ等の半導体用治具に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is made of silicon carbide (hereinafter abbreviated as CVD-SiC) produced by a CVD method, and is mainly used for heat treatment of a wafer in a semiconductor device manufacturing process including an epitaxial growth process. The present invention relates to a jig for semiconductor such as a susceptor used.
【0002】[0002]
【従来技術】半導体デバイスの製造プロセス中におい
て,エピタキシャル成長工程,CVD工程,アニール工
程等のウエハに熱処理を施す各種の熱処理工程がある。
エピタキシャル成長工程は,基材となるウエハ上に半導
体結晶を成長させるプロセスで,シリコン半導体よりな
るデバイス製造の場合には,ウエハ上にシリコン単結晶
膜を析出成長させる。上記エピタキシャル成長工程にお
いてウエハはサセプタ等の半導体用治具に載置される。
上記半導体用治具の構成材料としては,高純度黒鉛材の
表面を高純度の炭化珪素で被覆した材料が従来より広く
用いられていた。また,上記CVD工程,アニール工程
等の各種熱処理工程においても同様の半導体用治具が用
いられていた。2. Description of the Related Art In a semiconductor device manufacturing process, there are various heat treatment steps for subjecting a wafer to heat treatment such as an epitaxial growth step, a CVD step, and an annealing step.
The epitaxial growth step is a process of growing a semiconductor crystal on a wafer serving as a base material. In the case of manufacturing a device made of a silicon semiconductor, a silicon single crystal film is deposited and grown on the wafer. In the epitaxial growth step, the wafer is placed on a semiconductor jig such as a susceptor.
As a constituent material of the jig for semiconductor, a material in which the surface of a high-purity graphite material is coated with high-purity silicon carbide has been widely used. Also, similar semiconductor jigs have been used in various heat treatment steps such as the CVD step and the annealing step.
【0003】ところが,黒鉛材の表面に炭化珪素を被覆
して構成した半導体用治具は,炭化珪素と黒鉛材との物
性値(熱膨張率)が異なるため,熱処理工程途中で熱応
力による炭化珪素膜の剥離やクラックが発生し,使用不
能となる場合があった。また,炭化珪素の被膜厚みは5
0〜200μm程度と薄く,腐食性の強い雰囲気下で熱
処理工程を行なう場合は,炭化珪素被膜にピンホールが
発生し,そこから黒鉛材中の不純物が放出されてしまう
という問題があった。However, in a jig for a semiconductor formed by coating the surface of a graphite material with silicon carbide, the physical properties (coefficient of thermal expansion) of the silicon carbide and the graphite material are different. In some cases, the silicon film was peeled off or cracked, making it unusable. The thickness of the silicon carbide film is 5
When the heat treatment process is performed in an atmosphere as thin as about 0 to 200 μm and highly corrosive, there is a problem that pinholes are generated in the silicon carbide film and impurities in the graphite material are released therefrom.
【0004】近年コストダウンを目的としたウエハの処
理サイクル向上のため,半導体用治具の熱容量を低減す
ることが考えられている。これについて,半導体用治具
の厚みを薄くすることが検討されているが,黒鉛材を基
材とする場合,強度面を鑑みて,厚みを所定の値より薄
くすることは困難であった。In recent years, it has been considered to reduce the heat capacity of a semiconductor jig in order to improve the processing cycle of a wafer for cost reduction. Regarding this, it has been studied to reduce the thickness of the semiconductor jig. However, when a graphite material is used as a base material, it is difficult to make the thickness smaller than a predetermined value in view of strength.
【0005】このため,CVD−SiCより構成した半
導体用治具が提案されている。CVD−SiCは,CV
Dプロセスを利用して製作した半導体用治具で,非常に
緻密な炭素組織をもっており,硬度が高い。そのため,
強度的に強く,単なる黒鉛材を用いた半導体用治具より
も,より厚みを薄く,熱容量を小さくすることができ
る。For this reason, a semiconductor jig made of CVD-SiC has been proposed. CVD-SiC is CV
A jig for semiconductors manufactured using the D process, which has a very dense carbon structure and high hardness. for that reason,
The strength is strong, and the thickness and the heat capacity can be reduced as compared with a semiconductor jig using a mere graphite material.
【0006】[0006]
【解決しようとする課題】しかしながら,CVD−Si
Cよりなる半導体用治具には次のような問題がある。C
VD−SiC製の半導体用治具において,CVD−Si
Cの性質上,熱処理の際に熱源として用いるキセノンラ
ンプの光が,半導体用治具を透過して,ウエハに到達す
るおそれがある。However, CVD-Si
The semiconductor jig made of C has the following problems. C
In a jig for semiconductor made of VD-SiC, CVD-Si
Due to the nature of C, light from a xenon lamp used as a heat source during heat treatment may pass through a semiconductor jig and reach a wafer.
【0007】また,半導体用治具のウエハポケットは機
械加工により形成するため,ウエハポケット内の載置面
にはカッターマークよりなる凹凸が多数存在する。従っ
て,上記凹凸によってキセノンランプの光の透過量にバ
ラツキが発生し,ウエハの処理品質が大きく低下した
り,処理の歩留率が低下することがあった。もちろん半
導体用治具を肉厚とすれば上記問題は回避できるが,半
導体用治具の熱容量が大となって,熱がウエハに届き難
くなるため,この方法は好ましくない。Further, since the wafer pocket of the semiconductor jig is formed by machining, there are many irregularities formed of cutter marks on the mounting surface in the wafer pocket. Therefore, the unevenness may cause variations in the amount of light transmitted by the xenon lamp, resulting in a significant reduction in wafer processing quality and a reduction in processing yield. Of course, if the thickness of the semiconductor jig is increased, the above problem can be avoided. However, this method is not preferable because the heat capacity of the semiconductor jig becomes large and heat hardly reaches the wafer.
【0008】本発明は,かかる従来の問題点に鑑みてな
されたもので,ウエハの処理品質及び処理効率を高める
ことができる,半導体用治具を提供しようとするもので
ある。The present invention has been made in view of such conventional problems, and an object of the present invention is to provide a jig for a semiconductor capable of improving the processing quality and processing efficiency of a wafer.
【0009】[0009]
【課題の解決手段】請求項1に記載の発明は,半導体プ
ロセスにおいて,ウエハの熱処理に用いられる半導体用
治具であって,上記半導体用治具はCVD法により生成
させた炭化珪素より構成されており,上記半導体用治具
の頂面には,ウエハを載置する凹所となるウエハポケッ
トが設けてあり,また,上記半導体用治具の内部には,
少なくとも上記ウエハポケットを覆うように遮光層が設
けてあることを特徴とする半導体用治具にある。According to a first aspect of the present invention, there is provided a semiconductor jig used for heat treatment of a wafer in a semiconductor process, wherein the semiconductor jig is made of silicon carbide generated by a CVD method. On the top surface of the jig, there is provided a wafer pocket serving as a recess for mounting a wafer, and inside the jig,
A semiconductor jig is provided with a light shielding layer so as to cover at least the wafer pocket.
【0010】本発明において,遮光層は少なくともウエ
ハポケットにおけるウエハの載置面と同程度あるいはこ
れより大なる面積を持っている。ウエハの載置面とは,
上記ウエハポケットにおいて,ウエハを載置した際に,
ウエハがウエハポケットにおいて当接した面である(図
1参照)。上記遮光層がウエハポケットを覆うよう設け
てあるとは,遮光層をウエハポケットに対し投影した際
に,ウエハポケットが遮光層の投影面で隠れるような位
置関係にあることををさしている。In the present invention, the light-shielding layer has an area at least as large as or larger than the wafer mounting surface in the wafer pocket. What is the wafer mounting surface?
When a wafer is placed in the wafer pocket,
This is the surface where the wafer abuts in the wafer pocket (see FIG. 1). The phrase “the light-shielding layer is provided so as to cover the wafer pocket” means that when the light-shielding layer is projected onto the wafer pocket, the wafer pocket is hidden by the projection surface of the light-shielding layer.
【0011】次に,本発明の作用効果につき説明する。
後述する図3に示すように半導体用治具にウエハを載置
して,半導体用治具の頂面側,また反対の底面側からラ
ンプ加熱した場合について考える。遮光層により底面側
からのランプ加熱における光は遮断され,熱だけをウエ
ハポケットに伝導させることができる。よって,光によ
るウエハポケットに存在する凹凸による熱的なバラツキ
がウエハに転写されることを防止でき,ウエハの処理品
質を高めて,処理の歩留率を高めることができる。更
に,本発明によれば,急速加熱可能なランプ加熱を利用
できる半導体用治具を得られるため,ウエハに対する処
理効率を高めることもできる。また,CVD−SiCは
高強度なので耐久性に優れ,また高熱伝導性であり,速
やかにウエハを加熱することができる。Next, the operation and effect of the present invention will be described.
Consider a case where a wafer is mounted on a jig for a semiconductor and a lamp is heated from the top side and the opposite bottom side of the jig for a semiconductor as shown in FIG. The light in the lamp heating from the bottom side is blocked by the light shielding layer, and only heat can be conducted to the wafer pocket. Therefore, it is possible to prevent the thermal variation due to the unevenness existing in the wafer pocket due to the light from being transferred to the wafer, thereby improving the processing quality of the wafer and increasing the processing yield. Furthermore, according to the present invention, a jig for a semiconductor that can use lamp heating that can be rapidly heated can be obtained, so that the processing efficiency for a wafer can be improved. In addition, CVD-SiC has high strength and thus has excellent durability and high thermal conductivity, so that the wafer can be quickly heated.
【0012】以上,本発明によれば,ウエハの処理品質
及び処理効率を高めることができる,半導体用治具を提
供することができる。As described above, according to the present invention, it is possible to provide a semiconductor jig capable of improving the processing quality and processing efficiency of a wafer.
【0013】本発明にかかる半導体用治具は,後述する
エピタキシャル成長(実施形態例参照)の他,CVD工
程やアニール工程等のウエハの熱処理工程に用いること
ができる。The semiconductor jig according to the present invention can be used in a wafer heat treatment step such as a CVD step or an annealing step, in addition to the epitaxial growth (see the embodiment) described later.
【0014】次に,請求項2に記載の発明のように,上
記遮光層は波長が400〜800nmの光に対して50
%以上不透化であることが好ましい。急速加熱が可能と
なる熱源は処理時間の短縮に多いに有効であり,このよ
うな熱源としてキセノンランプがある。本請求項にかか
る遮光層は上述の範囲の波長に対して50%以上不透過
であるため,キセノンランプを熱源として用いた際に,
半導体用治具を介して該キセノンランプから発した光が
ウエハポケットまで透過することを防止できる。Next, as in the second aspect of the present invention, the light shielding layer has a wavelength of 400 to 800 nm.
% Or more. A heat source that enables rapid heating is very effective for shortening the processing time, and a xenon lamp is one such heat source. Since the light-shielding layer according to the present invention is opaque to the wavelength in the above-mentioned range by 50% or more, when a xenon lamp is used as a heat source,
The light emitted from the xenon lamp via the semiconductor jig can be prevented from transmitting to the wafer pocket.
【0015】なお,キセノンランプはキセノンの中での
放電発光を利用する放電灯の一種で,分光分布は連続ス
ペクトルの部分が多く,自然昼光に似たスペクトルを示
す光を放つ。更に,点光源に近い明るい光源であり,点
灯と同時に安定に発光する特性を持つ。このため,加熱
のオン/オフ制御が容易で,処理時間の短縮に多いに有
効である。Note that a xenon lamp is a type of discharge lamp that utilizes discharge light emission in xenon, and its spectral distribution has many continuous spectrum parts and emits light showing a spectrum similar to natural daylight. Further, it is a bright light source close to a point light source and has a characteristic of emitting light stably at the same time as lighting. For this reason, the heating on / off control is easy, which is very effective for shortening the processing time.
【0016】波長が400〜800nmの光に対して5
0%未満不透過である場合,ウエハの処理品質が低下す
るおそれがある。もちろん100%不透過,つまり遮光
層によって,キセノンランプの光が全く透過しないこと
が最も好ましい。ランプの光が全く透過しなくとも,ラ
ンプにより半導体用治具が加熱され,熱が半導体用治具
を介してウエハに伝導するため,問題なく熱処理を行な
うことができる。For light having a wavelength of 400 to 800 nm, 5
If the transmittance is less than 0%, the processing quality of the wafer may be degraded. Of course, it is most preferable that the light of the xenon lamp is not transmitted at all by the 100% opacity, that is, by the light shielding layer. Even if the light from the lamp does not transmit at all, the semiconductor jig is heated by the lamp and heat is conducted to the wafer through the semiconductor jig, so that the heat treatment can be performed without any problem.
【0017】更に,上述したごとく,キセノンランプは
自然昼光に近い光を発するため,可視光線領域の波長が
遮断できれば,本発明にかかる遮光層として十分な効果
を得ることができる。Further, as described above, since the xenon lamp emits light close to natural daylight, if the wavelength in the visible light region can be cut off, a sufficient effect can be obtained as the light shielding layer according to the present invention.
【0018】次に,請求項3に記載の発明のように,上
記遮光層は金属シリコンよりなることが好ましい。これ
により,CVD法で半導体用治具を製造する際に,金属
シリコン板をそのまま芯材として用いることができる。Next, it is preferable that the light shielding layer is made of metallic silicon. Thus, when manufacturing a jig for semiconductor by the CVD method, the metal silicon plate can be used as a core material as it is.
【0019】[0019]
【発明の実施の形態】実施形態例 本発明の実施形態例にかかる半導体用治具につき,図1
〜図3を用いて説明する。図3に示すように,本例は,
半導体プロセスにおいて,ウエハ2の熱処理に用いられ
る半導体用治具1である。本例の半導体用治具1はCV
D法により生成させた炭化珪素より構成されており,図
1,図2に示すごとく,半導体用治具1の頂面12に
は,ウエハ2を載置する凹所となるウエハポケット10
が設けてあり,内部には,少なくともウエハポケット1
0を覆うように遮光層13が設けてある。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment A semiconductor jig according to an embodiment of the present invention is shown in FIG.
This will be described with reference to FIG. As shown in FIG.
This is a semiconductor jig 1 used for heat treatment of the wafer 2 in a semiconductor process. The jig 1 for semiconductor of this example is CV
As shown in FIGS. 1 and 2, a wafer pocket 10 serving as a recess for mounting the wafer 2 is formed on the top surface 12 of the jig 1 for a semiconductor.
And at least a wafer pocket 1
The light shielding layer 13 is provided so as to cover 0.
【0020】本例の半導体用治具1について詳細に説明
する。図1に示すごとく,本例の半導体用治具1は円板
体である。頂面12には円形のウエハポケット10が設
けてある。ウエハポケット10における載置面101と
は,ウエハ2をウエハポケット10に載置した際にウエ
ハ1と接触する面をさしている。この載置面101は後
述するごとくウエハポケット10が切削加工で作成され
ているため,平均として1〜10μm程度の凹凸を持っ
ている。The semiconductor jig 1 of this embodiment will be described in detail. As shown in FIG. 1, the semiconductor jig 1 of the present embodiment is a disk. The top surface 12 is provided with a circular wafer pocket 10. The mounting surface 101 of the wafer pocket 10 is a surface that comes into contact with the wafer 1 when the wafer 2 is mounted on the wafer pocket 10. Since the mounting surface 101 is formed by cutting the wafer pocket 10 as described later, the mounting surface 101 has irregularities of about 1 to 10 μm on average.
【0021】頂面12の反対となる底面11と上記ウエ
ハポケット10との間には遮光層13が設けてある。遮
光層13は後述するごとく金属シリコンよりなる。載置
面101と遮光層13とは同形であり,遮光層13をウ
エハポケット10に投影した投影面と載置面101とは
位置も形状も略一致するよう構成されている。A light-shielding layer 13 is provided between the bottom surface 11 opposite to the top surface 12 and the wafer pocket 10. The light shielding layer 13 is made of metal silicon as described later. The mounting surface 101 and the light-shielding layer 13 have the same shape, and the projection surface obtained by projecting the light-shielding layer 13 onto the wafer pocket 10 and the mounting surface 101 are configured to have substantially the same position and shape.
【0022】次に,上記半導体用治具1の製造方法につ
いて説明する。まず,遮光層13となる金属シリコン板
をシリコン単結晶を所定のサイズに機械加工して準備す
る。次いで,上記金属シリコン板の周囲に対しCVD法
を利用して,SiC層を形成する。この時のCVD法
は,原料ガスとしてメチルトリクロロエタン,メチルク
ロロシラン等を用いて,キャリアーガスとして水素を導
入し,1200℃,真空度26664.4Pa(200
Torr)で行なった。Next, a method of manufacturing the semiconductor jig 1 will be described. First, a metal silicon plate serving as the light shielding layer 13 is prepared by machining a silicon single crystal into a predetermined size. Next, an SiC layer is formed around the metal silicon plate by using the CVD method. At this time, in the CVD method, methyltrichloroethane, methylchlorosilane, or the like is used as a source gas, hydrogen is introduced as a carrier gas, and the temperature is set to 1200 ° C. and the degree of vacuum is 26664.4 Pa (200 ° C.).
Torr).
【0023】この結果,金属シリコン板の周囲にCVD
−SiC層が形成され,全体として,金属シリコン板が
芯となったCVD−SiC板を得た。最後にCVD−S
iC板の頂面をダイヤモンド砥石を用いて機械加工し,
ウエハ2のウエハポケット10を設けて,半導体用治具
1を得た。なお,機械加工により形成されたウエハポケ
ット10の全表面にはカッターマーク(加工に用いた刃
の跡)が存在した。As a result, the CVD was performed around the metal silicon plate.
A SiC layer was formed, and a CVD-SiC plate having a metal silicon plate as a core was obtained as a whole. Finally, CVD-S
Machine the top surface of the iC plate using a diamond whetstone,
A wafer jig 1 was obtained by providing a wafer pocket 10 for the wafer 2. Note that cutter marks (traces of blades used for processing) were present on the entire surface of the wafer pocket 10 formed by machining.
【0024】次に,本例の半導体用治具1を使用する際
の加熱方法について説明する。図3に示すごとく,ウエ
ハ2を加熱するために半導体用治具1の頂面12の側,
底面11の側に,半導体用治具1の円周方向に沿って熱
源であるキセノンランプ31を配置する。Next, a heating method when using the semiconductor jig 1 of this embodiment will be described. As shown in FIG. 3, in order to heat the wafer 2, the side of the top surface 12 of the jig 1
On the side of the bottom surface 11, a xenon lamp 31 as a heat source is arranged along the circumferential direction of the jig 1 for semiconductor.
【0025】そして,本例に示した半導体用治具1を上
記加熱方法により加熱して,実際に8インチ(20.3
2cm)径のシリコンウエハ2にエピタキシャル成長処
理を施したところ,シリコンウエハの表面に形成された
単結晶のシリコン膜の厚みバラツキが1%以下となっ
た。また,比較のために遮光層13のない普通の半導体
用治具(図示略)を用いて,同様のエピタキシャル成長
処理を行ったところ,ウエハ2の表面に形成された単結
晶シリコン膜の厚みバラツキが8%となった。Then, the jig 1 for semiconductor shown in this embodiment is heated by the above-mentioned heating method, and is actually 8 inches (20.3 inches).
When an epitaxial growth process was performed on the silicon wafer 2 having a diameter of 2 cm), the thickness variation of the single-crystal silicon film formed on the surface of the silicon wafer became 1% or less. For comparison, when a similar epitaxial growth process was performed using an ordinary semiconductor jig (not shown) without the light-shielding layer 13, the thickness variation of the single-crystal silicon film formed on the surface of the wafer 2 was reduced. 8%.
【0026】次に,本例の作用効果につき説明する。本
例の半導体用治具1は,内部に金属シリコン板よりなる
遮光層13を持つ。そして,金属シリコン板は光を通し
にくい。図3に示す加熱方法で半導体用治具1を用いて
ウエハ2を加熱する際に,頂面12や底面11の方向か
らランプ加熱を施すが,この時,熱は通るが光は金属シ
リコン板よりなる遮光層13を透過することができず,
ウエハポケット10に対し光が達しない。Next, the operation and effect of this embodiment will be described. The jig 1 for a semiconductor of this example has a light shielding layer 13 made of a metal silicon plate inside. And the metal silicon plate is hard to transmit light. When the wafer 2 is heated using the jig 1 for semiconductor by the heating method shown in FIG. Through the light-shielding layer 13 made of
Light does not reach the wafer pocket 10.
【0027】そのため,ランプ加熱時にウエハポケット
10の,特に載置面101にある凹凸をウエハ2に転写
され難くすることができる。よって,ウエハ2の処理品
質を高くすることができる。更に,急速加熱可能なラン
プ加熱を利用できる半導体用治具1を得られるため,ウ
エハ2に対する処理効率を高めることもできる。For this reason, it is possible to make it difficult for the unevenness of the wafer pocket 10, particularly the mounting surface 101, to be transferred to the wafer 2 when the lamp is heated. Therefore, the processing quality of the wafer 2 can be improved. Furthermore, since the jig 1 for semiconductor which can use the lamp heating which can be rapidly heated can be obtained, the processing efficiency for the wafer 2 can be improved.
【0028】以上,本例によれば,ウエハの処理品質及
び処理効率を高めることができる,半導体用治具を提供
することができる。As described above, according to the present embodiment, it is possible to provide a semiconductor jig capable of improving the processing quality and processing efficiency of a wafer.
【0029】[0029]
【発明の効果】上述のごとく,本発明によれば,ウエハ
の処理品質及び処理効率を高めることができる,半導体
用治具を提供することができる。As described above, according to the present invention, it is possible to provide a semiconductor jig capable of improving the processing quality and processing efficiency of a wafer.
【図1】実施形態例における,半導体用治具の断面説明
図。FIG. 1 is a sectional explanatory view of a jig for a semiconductor according to an embodiment.
【図2】実施形態例における,半導体用治具の斜視図。FIG. 2 is a perspective view of a jig for a semiconductor according to the embodiment.
【図3】実施形態例における,加熱方法の説明図。FIG. 3 is an explanatory diagram of a heating method in the embodiment.
1...半導体用治具, 10...ウエハポケット, 12...頂面, 13...遮光層, 2...ウエハ, 1. . . 10. jig for semiconductor, . . 11. wafer pocket, . . Top surface, 13. . . 1. light-shielding layer; . . Wafer,
フロントページの続き Fターム(参考) 4G077 AA03 BA04 DA01 DB01 EG03 EG04 FK02 SA12 TA12 5F045 AB06 AC07 AD16 AE25 AF03 BB02 BB08 BB13 EK14 EK18 EM02 EM09 GH08 Continued on the front page F term (reference) 4G077 AA03 BA04 DA01 DB01 EG03 EG04 FK02 SA12 TA12 5F045 AB06 AC07 AD16 AE25 AF03 BB02 BB08 BB13 EK14 EK18 EM02 EM09 GH08
Claims (3)
理に用いられる半導体用治具であって,上記半導体用治
具はCVD法により生成させた炭化珪素より構成されて
おり,上記半導体用治具の頂面には,ウエハを載置する
凹所となるウエハポケットが設けてあり,また,上記半
導体用治具の内部には,少なくとも上記ウエハポケット
を覆うように遮光層が設けてあることを特徴とする半導
体用治具。1. A semiconductor jig used for heat treatment of a wafer in a semiconductor process, wherein the semiconductor jig is made of silicon carbide generated by a CVD method. The surface is provided with a wafer pocket serving as a recess for mounting a wafer, and a light shielding layer is provided inside the jig for semiconductor so as to cover at least the wafer pocket. Jig for semiconductors.
400〜800nmの光に対して50%以上不透化であ
ることを特徴とする半導体用治具。2. The jig according to claim 1, wherein the light shielding layer is opaque to light having a wavelength of 400 to 800 nm by 50% or more.
金属シリコンよりなることを特徴とする半導体用治具。3. The jig according to claim 1, wherein the light shielding layer is made of metal silicon.
Priority Applications (1)
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JP2001016243A JP2002222768A (en) | 2001-01-24 | 2001-01-24 | Jig for semiconductor |
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JP2002222768A true JP2002222768A (en) | 2002-08-09 |
Family
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Cited By (2)
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JP2018148129A (en) * | 2017-03-08 | 2018-09-20 | 株式会社Screenホールディングス | Thermal treatment equipment |
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JPH0758039A (en) * | 1993-08-20 | 1995-03-03 | Toshiba Ceramics Co Ltd | Susceptor |
JPH08319186A (en) * | 1995-05-23 | 1996-12-03 | Toshiba Ceramics Co Ltd | Cvd-siliconcarbide-coated member |
JPH1083968A (en) * | 1996-09-06 | 1998-03-31 | Toshiba Corp | Semiconductor manufacturing device |
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JPH05152210A (en) * | 1991-11-26 | 1993-06-18 | Toshiba Ceramics Co Ltd | Susceptor |
JPH0758039A (en) * | 1993-08-20 | 1995-03-03 | Toshiba Ceramics Co Ltd | Susceptor |
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WO2005017988A1 (en) * | 2003-08-15 | 2005-02-24 | Hitachi Kokusai Electric Inc. | Substrate processing apparatus and method for manufacturing semiconductor device |
JP2018148129A (en) * | 2017-03-08 | 2018-09-20 | 株式会社Screenホールディングス | Thermal treatment equipment |
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