JP2002203398A - Method for preventing consumption of time to program address in defective column - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for preventing consumption of time to program a defective column in a flash memory to be tested on a memory tester. SOLUTION: This method comprises (a) a step in which a Tag RAM address- specified by the same address 30 as that applied to a memory to be tested is established, (b) a step in which it is discriminated that an applied address is related to a defective column, (c) a step in which display 128, 124 that the column is defective are stored in the applied address in the tag RAM, (d) a step in which an automatic data replacement mechanism (35") is enabled during the next step of the test of the memory to be tested after (a) to (c), (e1) a step in which programming the memory to be tested for the test address is tried applying the test address for the tag RAM, and (e2) a step in which a value of data to be programmed is replaced by informing directly that the memory to be tested is normal when the tag RAM comprises display that the test address belongs to a defective column.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD [0001] The present disclosure is disclosed on September 2, 2000.
US patent application Ser. No. 09 / 672,650, filed on the 8th.
Issue “MEMORY TESTER HAS MEMORY SETS CONFIGURABLE FOR
USE AS ERROR CATCH RAM, TAG RAM's, BUFFER MEMORIE
S AND STIMULUS LOG RAM ". This application discloses aspects of address selection and data selection processing which are related to the present application.
For this reason, reference is made to US application Ser. No. 09 / 672,650, which is incorporated herein by reference. The subject matter of this patent application is discussed in US patent application Ser. No. 09 / 672,650, filed Oct. 2, 2000, entitled “ME
The invention also relates to the invention disclosed in “MORY TESTER TESTS MULTIPLE DUT's PER TEST SITE”.
ttle) device as a single "big" device. Although not required, these techniques are useful and can be used in conjunction with the techniques of the present application and are therefore of interest in the present application. Accordingly, reference is made to this patent application Ser. No. 09 / 672,650, which is hereby incorporated by reference.

[0002]

2. Description of the Related Art In everyday life, electronic devices and functions thereof have become extremely popular. Many people have multiple productive tools with home personal computers and the like for a variety of miscellaneous purposes. Many personalized productive electronic devices include some form of non-volatile memory. Cellular phones use non-volatile memory to retain user programmed phone numbers and settings when the power is turned off. In the case of a PCMCIA card, a non-volatile memory is used so that information can be maintained even when the card is removed from a slot of the computer. Many other common electronic devices also take advantage of the long term storage capabilities of non-volatile memory in unpowered assemblies.

A non-volatile memory manufacturer who sells a non-volatile memory to an electronic device maker must use a tester to check whether the memory manufactured by the non-volatile memory operates properly. Because non-volatile memories are manufactured and sold in large quantities at consistently low cost, it is very important that the time required to test individual components be as short as possible. Non-volatile memory buyers want to integrate the purchased memory elements into more expensive assemblies, requiring only minimal testing or no testing to save cost. Requires a high shipment yield. Therefore, the test procedure for the memory must provide a sufficiently high efficiency that most of the nonconforming products, and preferably all nonconforming products, can be identified in a single test run.

As the size, density, and complexity of non-volatile memories increase, there is a need for a tester that can handle these dimensions and complexity without significantly increasing the test time. Also, testers must be able to easily adapt to these changes made to memory elements as the memory elements evolve and improve. Another characteristic feature of non-volatile memory testing is that repeated writing to a memory cell may degrade the overall lifetime performance of the component. Non-volatile memory manufacturers address many of the testing issues by incorporating special test modes into the memory device.
These test modes are not used by the memory purchaser, but are accessed by the manufacturer to access all of the memory,
Or to test most of them efficiently in the shortest possible time. Some non-volatile memories can be repaired during the test process. Thus, the tester must be able to identify the need for repair, the location of the repair, and the type of repair needed, and be able to perform the appropriate repair. Such a repair process requires a tester that can detect and isolate certain non-conforming parts in the memory. To take advantage of this special test mode in conjunction with the repair function, it is beneficial to use a tester that can execute a test program that supports conditional branching based on the response expected from the device.

The process of testing a memory is an algorithmic process from a conceptual point of view. For example, a common test involves sequentially incrementing or decrementing a memory address while writing a 0 or 1 to a memory cell. The set of 1s and 0s written or read during one memory cycle is generally called a "vector", and a sequence of vectors is called a "pattern". In the test, a pattern such as walking 1's, a butterfly pattern, or a checkerboard is generally written in a memory space. With the help of algorithmic structures, test developers can more easily and efficiently generate programs to create test patterns. Algorithmically consistent test patterns are easy to debug, and logical methods can be used to isolate those portions of the pattern that do not perform the expected processing. Test patterns algorithmically created using instructions and commands that repeat in a programming loop consume less space in the tester memory. Therefore, it is desirable that the memory tester has an algorithmic test pattern creation capability.

The exact placement and detection of signal edges is also a consideration in relation to the efficiency of non-volatile memory testers. To capture components that are non-conforming within the specified margins, but nearly conforming in the median, the non-volatile memory tester must be able to time-correct each signal edge with respect to the other signal edges. Must be able to place Also important is the ability to accurately determine when a signal edge was received. Therefore, the non-volatile memory tester should have sufficient flexibility and control over how the timing of the stimulus is given and the response from the memory that is the device under test (hereinafter referred to as “DUT”). It is.

[0007] It is said that the memory tester generates a transmission vector to be applied (or stimulated) to the DUT and receives the vector as an expected reply (or response). Since memory testers include a mapping mechanism to route signals to and from specific terminals that contact the DUT, the algorithmic logic that generates these vectors is typically Can be performed without considering how a particular bit in the vector is sent to (or from) a particular signal pad in the DUT. A set of mechanisms for algorithm pattern generation, threshold setting, signal condition setting, comparison, and a probe that connects these to the DUT are called test sites. In a simple example, one DUT corresponds to each test site.

[0008] The memory tester has an internal test memory that is used to aid the testing process. This internal test memory can be used for several purposes, such as pre-storage of transmit vectors and storage of receive vectors instead of real-time generation, and various error indications regarding DUT behavior obtained during the test. And storage of other information. (Furthermore, there is housekeeping processing etc. inside the memory tester processing using RAM, which is called "internal memory (interior memory
y) ". But,
These are dedicated to the internal processing of the tester, are not visible at the algorithm level, and correspond to an executable instruction storage mechanism and internal control registers. This memory,
As the "internal control memory", the "internal test memory" (inte
rior test memory). This "internal test memory" is used to store bit patterns that are directly related to stimuli or responses to or from the DUT. It is easy to see that this internal test memory must operate at least as fast as the test to be performed. A very common approach is to address the internal test memory (or a portion thereof) with the same address (or a derivative thereof) that applies to the DUT. In this case, what is stored at the address specified in the internal test memory is some information indicating the behavior of the DUT at that address during the test processing performed on the DUT. If there were algorithmic considerations in the test program, it would be that the address sequence associated with the continuous transmission vector was arbitrary. Therefore, the internal memory needs to have two characteristics: high speed and random addressability. What comes to mind immediately is an SRAM that is fast, easy to control, and capable of completely random addressing. In practice, conventional memory testers have used SRAM as their internal test memory.

[0009]

Unfortunately, SRAM
Is very expensive, so the capacity of the internal test memory used for the memory tester is limited. As a result, the functionality of the memory tester is limited due to lack of memory. DRAM
Is less expensive, but cannot operate at high speed with random addressing.

A DRAM can be used as an internal test memory of the memory tester instead of the SRAM. Although briefly described below, the problem of increasing the processing speed of a DRAM for use as an internal test memory can be solved by increasing the capacity of the DRAM to be used instead of trying to increase the processing speed. A plurality of similar "banks" of DRAM are treated as "groups". By combining the interleaving of signals for different banks of memory in a group with the multiplexing between several groups of banks, memory traffic can be handled by any bank, even for any bank. Slow down to the speed you can.

[0011]

SUMMARY OF THE INVENTION At the top level of the internal test memory organization, there are four sets of memories, each having its own separate address space and performing the required memory transactions. Two of them are the aforementioned DRAMs, and the other two are SRAMs.
Each of the memory sets has its own controller, and memory transactions are directed to that controller.
In terms of externally visible processing power, all four memory sets are basically the same. They differ only in the size of the memory space and how it is implemented internally. The SRAM memory set is inherently fast enough that neither multiplexing nor interleaving is performed. Memory sets of the same type (SRAM or DRAM) are independent of each other, but can be "stacked", that is, treated as one larger address space.

Thus, the tester's internal test memory is divided into four memory sets, two of which are "internal" SRAMs and the other two are "external (e
xternal) "DRAM. For the sake of simplicity, all of these memories are inside the memory tester.
The terms "internal" and "external" refer to the level of integration. SRAM is an integrated component of VLSI (ultra large scale integrated circuit) related to the core functional circuit of the tester,
The AM is a component that is separately packaged and mounted adjacent to the VLSI. SRAM capacity is fairly small (eg 1 megabit per memory set)
However, the capacity of the DRAM can be chosen quite large (eg, 128-1024 Mbits per memory set). The SRAM memory set always exists and can be used for a purpose suitable for them, such as storing contents expected of a DUT which is a ROM. The DRAM memory set is optional in nature, and is generally used to create a record for subsequent analysis to perform a repair, but has a variety of other uses. The tester decides which memory to use for which purpose, SRAM and DRAM
There is no forcible distinction between The selection of the application is mainly determined by its size. While the SRAM memory set is small, the DRAM memory set is potentially large. The decision on how to use the various memory sets is made by the engineer who creates the test program. However, there are some distinctions, such as the need to utilize a particular set of memories for particular processing functions of the memory tester. This results from economic or performance considerations that require a dedicated hardware path to the memory set. It is possible to generalize such a mechanism, but choose the one that looks appropriate,
It would be a shortcut to try it,

The large internal test memory (DR)
The next thing that will be considered after the emergence of them (in the form of an AM memory set) is to help the desired function of the memory tester,
How to use these additional memory capacities. In the tester of interest in this application, the subsystem of the internal test memory is very flexible and has an effective word length of any power of 2 (up to 2 ⁵ = 32), and the address space for narrower words can be correspondingly increased. Extensive address mapping capabilities, both for DUT addressing and internal test memory addressing, with multiple tag RAMs (TagRAMs) and other mechanisms for significant data sorting and address sorting to aid error analysis tools and These are all easily realized by increasing the capacity of the internal test memory. Furthermore, these improvements made possible by more memories are not inexistent, but are very useful for testing certain types of memory components.

[0014] Recent technological innovations have led to the realization of true large capacities (512 MB) and wide data paths (32 bits) in memory components, but nevertheless still exist in current communication services. 4
Bit, 8-bit and 16-bit components are still widely used. Not only that, but at the cost of serializing or supporting multiple cycles of partitioning to transmit the entire data of its wide unique word length, the ability of large components in address and data transmission is achieved. In some cases, it is suppressed to fit a narrow path. There are various reasons for this situation.
The required components are limited to small-capacity components, or applications where large-capacity components can have narrow paths (video applications that are always addressed sequentially). . In short, there are good economic reasons for memory components with narrow paths to be accepted in the market, which means that these smaller components also need to be tested.

Sometimes it is desired to test an 8-bit component with a memory tester with 64 channels per test head. In this case, the power and ground, the I / O bus, the clock and various control lines, perhaps 12-16
A channel is required. Here, for example, it is assumed that 14 channels are used. However, this does not mean that when the part is placed under the test head, the remaining 50 channels are not used.

Sixty-four channels is a sufficient number to perform four tests of sixteen channels. A collection of four undivided DUTs on a wafer, or four packaged components, can be viewed as a single large component that happens to be a combination of four small components. . Logically, these four small volume components can be tested simultaneously by the same test head. The problem here is that this is difficult and cannot be easily implemented. A single-thread-of-control test program emulates a four-thread-of-control test program, and each of these four threads (implemented on an individual DUT) , The test program must be rewritten to include conditional branches and other result-dependent actions. This is very cumbersome, and it may seem desirable to use four separate execution mechanisms with four simple programs that can independently branch the internal execution path as needed. However, a problem arises in the other extreme case where all 64 channels must be controlled by one program for actually testing a single large-capacity component. The combination of four small processors does not make up one large processor.

The internal structure of a memory tester can be extended to allow testing of multiple DUTs of the same type at a single test site, making significant changes to the original test program normally used to test a single DUT. There is no need to add. The plurality of DUTs are electrically isolated from each other, but at least initially the same stimulus that is expected to have the same response is applied. To do this, the DUT is coupled to the set of channels used for each of those tests. The tester will instruct one DU on those channels
The segments of the test vector needed to test T can be duplicated for another DUT. As a result, "DUT
A pattern (or sequence) of transmit (or stimulus) and receive (or response) vectors with "n-many DUT's wide" is generated. The conditional branch in the test program corresponding to the condition (DUT failure) in the reception vector is based on the discrimination ability of a plurality of types of error indications and one or more DUs.
Supported by the ability to selectively disable T-tests while continuing with one or more DUT tests that are not disabled. The error display includes a function error flag for each channel, a function error flag for each DUT, and a parameter error flag for each DUT. The function error flag for each DUT is
-It is created from the logical OR operation of the function error flags for each channel performed based on the channel relationship. These flags are communicated to the test program so that the test program can perform various appropriate actions that alter the program flow to invoke special tests or other processing to be performed on the suspected DUT. Error conditions are also detected by a pre-programmed mechanism in the circuit that applies the transmit vector and compares the receive vector. These pre-programming mechanisms result in operations that include the ability to change the drive and receive format for the DUT signal for that channel on a channel-by-channel basis. Furthermore,
This includes removing or limiting the stimulus to a particular DUT, while at the same time making all comparisons for a particular DUT appear "good" regardless of the truth.

As described above, the test program includes a plurality of (up to four in the embodiment) D unless an error is notified.
UTs can be tested simultaneously and in parallel. Upon notification of the error, the test program branches to an error investigation routine to continue operation of the suspected DUT while temporarily disabling operation of the problem-free DUT. If this defective DUT has an irreparable defect,
Or, if it is not safe to continue to supply power to it, the bad DUT is disabled while another good DUT is re-enabled and normal testing resumes. Thus, execution of one thread (single DU)
In the T-test, this basically exists in the same format), and can be selectively switched between different DUTs as necessary depending on which DUT has failed. During these selective switching periods, the specific target DUT
In order to carry out the test, the simultaneous test of all DUTs is suspended. Switching and jumping to execute a branch also
It can also be defined programmatically to occur when an incident is recognized during a test. Part of this programmatic definition is a change that can be easily implemented for a one-thread test program (the test program remains one thread), and another part is the advance of various hardware assists. Settings.

Certain memory technologies, such as FLASH memory, have certain characteristics that affect the way these memories are used and tested. For example, taking a flash memory as an example, an erase function is typically used to store a 1 in the entire device (or a part thereof called a block), and to write a 0,
“Programming” is performed by repeating the write operation to the address where 0 should be stored. Erasing is a batch operation that affects a large number of addresses (whole device or block containing a given address), but when "programming" a certain address with a zero, the erased memory cell is The write operation is repeated until sufficient charge transfer occurs. In today's flash memory, the device itself reads the contents of the cell internally while the automated internal programming process is repeatedly performed until the programming (writing) is performed. For example, in an 8-bit device, the 8 bits at that address are internally verified and the programming process (write process) will write each of them properly no matter how many 0s to write in these 8 bits Continues internally. Some cells may be easier to write in some memories than others, but writing a zero may require hundreds of programming cycles.

Recent flash devices receive such processing in the form of commands and notify on an output line whether their final result, driven by the status register, was successful or unsuccessful. Thus, for example, address and data are provided to the device, and program lines or commands act. The status register is, for example,
When all become 0, it indicates that it is in a "busy state", and when it becomes all 1, it indicates that it has become a "state in which work has been properly completed". If another bit pattern occurs in the process of this processing, this is an error code and indicates some kind of defect.

Although the process of storing 1 by reprogramming (rewriting) at an address where 0 has been previously written is an allowable process, it is a process that cannot be performed by a flash device for structural reasons. If this must be done, the entire device (or the entire block containing its address) must be erased and the programming must be restarted from the beginning. However, a processing mode in which a command for programming 1 is received, a success notification is immediately made, and this is ignored is ignored in flash devices.

Therefore, the flash component testing method appears to be a process that generally comprises three steps. First, an erasure operation is performed on the part, secondly, the part is programmed, and thirdly, it is excused. Properly programming that part is just performing device testing.
However, test technicians want to operate this while changing the supply voltage after programming is complete, to check timing relationships and to ensure that addressing order and patterns in stored data do not adversely affect processing. In some cases. In a series of tests on a flash component, these three procedures may be performed a plurality of times. In each process, a different set of programming data is processed, and perhaps each performs a separate operation. In general, the time required for operation processing on a component occupies a small part of the test time, and the time for erasing and programming (writing operation) is more important.

The internal concept of some memories, including flash memories, uses the concept of columns. 1
Many addresses belong to one column, and if a failure occurs in decoding a column, many addresses will be affected. Only one bad cell (for example,
Even if only a single bit defect at a single address) was present in the column, the column would be considered defective. Either way, at some point during the programming phase, there will be addresses that are not programmed correctly. At this point, the column containing the address is considered bad.

A row of flash component defects can be found during the programming process or during the operation process.
In the latter case, it is difficult to characterize in advance and it is unlikely that the status information is notified by the device itself, so that it is necessary to detect this by a suitable algorithm mechanism in the test program.

[0025] Another question is whether a bad row is repairable or not, perhaps at a different point in time. Most desirably, the soluble link (fu) in the device in any DUT
The number of alternative circuits that can be switched by "zapping" a sible link is limited to a fixed number). At the present time, if the configuration is made so that time is not used for writing to other addresses in the row in order to maintain the balance of the component test, the time of the tester can be saved somewhat.

Whether a bad row is found in a multi-DUT test on a single test head or in a single DUT test on a single test head is processed later (perhaps by trying to repair). It is desirable to record this fact on the premise of performing the test (particularly in the case of a multi-DUT test). However, it is desirable that the test be continued during this time, while attempting to perform further programming (write operation) on the bad column is suppressed (for other columns). Without this mechanism, extra time would be wasted trying to program the address in the bad column. While it makes sense to have the test program determine if a column is bad during operation (in a sense, that is why the test exists), it will tell the test program that it is bad. It is not desirable to bear the additional task (during the programming or operation process) of changing the subsequent program flow to avoid further programming to other addresses in the known columns. This is especially true for multi-DUT testing. What should I do?

The test program generates a transmission vector (stimulus) and a reception vector (expected response). The transmission vector is D
Applied to the UT, the received vector is treated as a comparison value for determining whether the response from the DUT was as expected. In writing flash components, the test program uses the tag RAM technology to create a defective column table (BA
D COLUMN table) in one of its memory sets.
The bad column table is specified by the same address as that applied to the DUT. Mode to omit bad columns (OMIT B
When in AD COLUMN mode, the entries in this table are obtained and used by the automatic operation of the memory tester hardware, and all 1's which generate a programming success indication automatically and immediately returned from the DUT ( Or other pattern). As a result, there is no need to change the internal functions of the test program, and it is not necessary to spend time programming a column determined to be defective. Finding the bad column and recording the bad column in the table can be performed at the first programming stage of the test program or each time it is found in the operation process of the programmed flash DUT.

These functions are performed by a special bad block table (BAD BLOCK tab) created in the internal test memory.
Combined with the automatic read-out of le), testing of memory components with an internal block structure is facilitated by automatically disabling operations related to bad blocks and eliminating them from further influence on the test program. It is to make. The bad block may or may not be included in the DUT being tested by the multi-DUT test method.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring first to FIG. 1, there is depicted a schematic block diagram 1 of a non-volatile memory test system constructed in accordance with the principles of the present invention. In particular, the system shown allows up to 36 individual DUTs to be tested simultaneously at each of up to 64 test locations at a time, with D tests having more than 64 test locations.
A reset function is provided so that components of a set of test resources can be combined to test the UT. These test locations may be locations on a portion of the integrated circuit wafer that has not yet been split and packaged, or may be terminals of packaged components.
The term "test point" refers to applying a signal (eg, power supply, clock input, data input)
Or an electrical site where signals can be measured (eg, data output). In the present application, in accordance with customs in the industrial field, a test point is referred to as a “channel”. As mentioned earlier, the collection of test resources to be combined (collection of test resources)
es to be bonded together) "can be understood to mean up to 36 test sites, and each test site
Test site controller 4 and (64 channel) DUT
Make the actual electrical connection to tester 6 and DUT 14 (6
4 channel) terminal electronic component set 9. A DUT
If less than 64 channels are required in this test, a single test site will suffice for testing this DUT; for example, test site # 1 (shown in FIG. 1) single site test station) "
Or operate as a "single site test station" to represent this case. On the other hand, if the reconfiguration described above occurs in any way, the two (or more) test sites are "bonded" to operate as a larger, equivalent test site with 128 channels.
Thus, referring again to FIG. 1 as an example, for example, test sites # 35 and # 36 may have a "two-site test station (two
-site test station) "expresses this case.

Next, the reverse case will be briefly considered.
Note that it is not necessary to test one DUT across one test site, or that one test site can only test one DUT. Suppose a wafer contains two, three, or four dies (possibly, but not necessarily, adjacent) and the sum of their test channel conditions is less than or equal to 64. Then, these four DUTs
(15a-d) can be tested at a single test site (eg, test site # 2 shown in FIG. 2). This is possible because each test site has general programmability (ge
neral purpose programmability). Other parts of the test site resources will be used to test one DUT and the other
You can write a test program that the test site runs to be used for the test. In short, the third DUT, which is a logical combination of the two DUTs described above,
Assuming that there is a UT, if this third DUT can be tested at a single test site, its “component DUT's” should be able to be tested as it is. That's what it means. The only difference is that instead of giving an integrated answer to the third DUT, a record is made of whether the two "component DUTs" passed or failed. That is, there is a problem as to which part of the third DUT has failed. Further, removing or restricting a drive signal to a defective DUT, branching a test program based on which DUT has indicated a defect, and not simultaneously increasing the number of branches to an unrealistic number, etc. , There are other problems. Certain aspects of multi-DUT test station capabilities at a single test site are very simple, while others are complex. This multi-DUT test station should not be confused with the concept of combining two or more test sites.

Without the concept of resetting, there is no difference between the test site and the test station, and either one of the words may be used.
However, it is clear that according to this concept the number of test stations is not always the same as the number of test sites. In the past, splitting one test site to create more test stations (such as when the DUT is not as complex as using up one test site)
In some cases, the numbers were different. However, the difference in numbers here is due to the fact that multiple test sites combine to form a multi-site test station (if the DUT is too complex to test at a single test site).

To proceed with the description, the test system controller 2 transmits up to 36 test site controllers (# 1 to # 36) 4a to 4z (the last symbols a to z are 1 to 26) via the system bus 3. It does not correspond to 36 characters, but does not correspond to 36 characters, but as a suffix added after the numeral code, it was considered more preferable to use confusing numbers). The test system controller 2 is a computer (for example, a PC that starts NT) that executes a suitable test system control program related to a test task of a nonvolatile memory. The test system control program represents the highest level of abstraction in the hierarchy (and complexity) of the job to perform the desired test.
The test system controller determines which programs are running at different test sites and supervises the robot system (not shown) that moves the test probes and DUTs as needed. To support the concept that some test sites are programmed to operate as single-site test stations and other test sites are programmed to be combined to form a multi-site test station, The controller 2 can fulfill the function. In such a situation, it is clear that different parts are being tested, but most preferably, different tests are used for different parts. Similarly, there is no requirement that all single-site test stations must test the same style of part, and a multi-site test station does not. Thus, the test system controller 2 is programmed to issue commands to perform the required test site coupling and to cause the various test stations used to execute the appropriate test program. The test system controller 2
It also receives information about the results obtained from the test,
It is possible to take an appropriate action for discarding a defective product, and manage logs of various analysis results that can be used for, for example, control of a manufacturing process in setting of a factory facility.

The test system itself is a correspondingly large and complex system. Generally includes a robot subsystem,
This places the wafer on the stage, and then one or more future dies to be tested (the wafer is not diced at this time) at the test location under the probe that connects to the pin electronics 9 ) Is arranged. The test system can also be used to test packaged components mounted on a suitable carrier. As explained below, regardless of how many test sites are used to form a test station, or how many test stations are formed at a test site, each of the test stations used There is at least one corresponding test site controller (described below). The test site controller includes, for example, a combination of a program memory and a data memory of 36 MB to 64 MB, and has a VOS (VersaTes).
t O / S) is an embedded device such as Intel's i960 processor that starts up a proprietary OS called VOS. It is used. For now, for the moment we will only consider the single site test station. As a specific example, test site # 1 is used as a test station # 1 by WHIZCO
It is assumed that operation is performed to test the part number 0013. To perform the test, about 100 kinds of different types of tests (not only a large amount of simple storage but also monitoring by changing the voltage level, pulse width, edge position and delay, and reading out information of the selected pattern) And each type of test performs millions of memory cycles on the DUT. At the highest level, the test system operator commands the test system controller 2 to begin testing the WHIZCO0013 using test station # 1. The test system controller 2 uses the test site controller # 1 during the process.
(4a) [embedd (computer) system (embedd
ed computer system)] to start a related test program (eg, TEST_WHIZ_13). If this program is already in the environment of Test Site Controller # 1, this program is simply executed. If not, the program will be supplied from the test system controller 2.

Here, basically, the program TEST_
WHIZ_13 may be completely independent.
However, in that case, the program is arguably large, and the processor of the embedded system of the test site controller 4a activates it at a sufficiently high speed to generate the test results at the desired speed, or for each DUT memory cycle. Even at a uniform rate of production becomes difficult. Therefore, lower-level subroutine-type operations that generate a sequence of addresses and associated data to be written or expected in a read operation may require D
It is executed by a programmable algorithmic mechanism in the UT tester 6, which operates in synchronism with the program executed by the embedded system in the test site controller 4. Think of this process, such as a low-level subroutine operation and a task to initiate a DUT memory cycle, as exporting to a mechanism (DUT tester) that is closer to the hardware environment of the DUT 14. And, generally speaking, each time the test system controller 2 supplies a test program to the test site controller 2, the appropriate low level required to perform the overall operation described or required by the programming for the test site controller. A level execution routine (perhaps specific to the memory under test) will also be provided to the corresponding DUT tester. The low-level execution routines are called "patterns" and are given generic names, just as functions and variables in high-level programming languages are named.

Each test site controller #n (4) is connected to a corresponding DUT tester # by a site test bus #n (5).
n (6). The test site controller uses the site test bus 5 to control the operation of the DUT tester and obtain test results therefrom. The DUT tester can quickly generate various DUT memory cycles involved in performing the test and determine whether the results of the read memory cycle were as expected. Basically, this is the corresponding useful read and write D
A command or processing code ("named pattern") sent from the test site controller by initiating a sequence of UT memory cycles.
n) ") (for example, executing the corresponding pattern). Conceptually speaking, the DUT tester 6 is a DUT
It outputs stimulus information to be applied to the UT and receives response information returned therefrom. The stimulus or response information 7a includes the DUT tester 6a and the terminal electronic component # 1.
With the assembly part 9a. The pin electric assembly 9 a supports up to 64 probes that can be connected to the DUT 14.

The above-mentioned stimulus information is represented by a parallel bit pattern sequence (for example, a “transmit vector” and an expected bit rate) expressed based on the voltage level of any of the logic element series used in the DUT tester. A “receive vector” sequence). There is a configurable mapping mechanism between the bit position in the stimulus or response and the probe on the die, and this mapping information is known by the DUT tester 6. The individual bits are correct in their timing and edge placement, but they are
A voltage level shift may be required before being applied to the UT. Similarly, the response output from the DUT following a stimulus may require buffering and (reverse) level shifting before it can be sent back to the DUT tester. These level shift tasks are performed by the terminal electronic component 9a.
In the category. The setting of the terminal electronic components required for the test of WHIZCO-0013 is unlikely to be diverted to AMCE components or perhaps even to WHIZ components. Therefore, it is understood that the terminal electronics assembly configuration also needs to be configurable. Providing such setting capability is a function of the PE setting line 8a.

Thus, a structural overview has been given of how a single test site is constructed to test one DUT. Next, the problems that arise when operating a large number of test sites will be described. As a premise, first, a recommended embodiment for constructing a test system having a plurality of test sites will be described. The information described here will in many ways be a matter of choice based on market research and cost-benefit analysis of customer preferences. Thus, in order to build any one of these items, a clear choice must be made, and once this choice is made, certain results will be apparent throughout the system. It may be useful here to provide, at least in a general form, a broader overview of the hardware characteristics of the test system.
While these properties will vary depending on the conditions, knowing them nonetheless helps in understanding the various examples presented in describing the invention.

First, assume four relatively large card cages. Each card cage has a power and water cooling mechanism (fans can be a source of contamination in a clean room environment, and the number of emissions from a fully populated system using cooling water is lower than air cooling. 10 KW of heat can be removed), as well as a motherboard, a front plane and a back plane. Up to nine assemblies can be inserted into each card cage. Each assembly includes a test site controller, a DUT tester, and terminal electronics. A general overview of how the test site controllers are coupled includes creating a daisy chain connection using several buses.

Although slightly deviating from the main subject, first, this "daisy chain connection" will be briefly described. Assume that there are system components A, B, C and D. It is assumed that these are connected in this order by daisy chain connection. Then, there is an information or control path out of A to B, B can selectively send out traffic from B to C, and C can select traffic to D. Can be sent in a targeted manner. Similar configurations may exist for traffic in the other direction. Daisy-chaining is often used to create a priority mechanism, and is used here to create a master-slave relationship between various test site controllers. After the symbol indicating the communication configuration by the daisy chain method, "BU"
"DSY" was added instead of "S". Therefore, for example, instead of “command / data BUS”, “command / data BUS”
Data DSY ”. Second, the concept of "entering B and being selectively sent out" may imply that the traffic is reproduced on another set of conductors before it is delivered. . It could be so, but for performance reasons this is a normal bus with rather addressable entities. The programmable address mapping configuration and a portion of the downstream test site controller are "sleep
The ability to "p)" state allows a single bus to appear (or function) as if it were a logical daisy chain. Finally, it goes without saying that a daisy chain is a high performance path for command and control information, otherwise the master-slave combination (multi-site test station) would have the same speed as a single test site. It cannot be expected that the processing will be performed. In order not to impair the daisy chain performance, the various DSYs do not go outside their respective card cages. To do this, some restrictions are placed on which (and thus how many) test sites are combined. Basically, there is no fundamental need to impose a limit, nor is there a decisive lack of technical practicality (ie, workable). This is simply because the idea of extending DSY would be to pay a great deal of money and get a small additional benefit, as there are already nine test sites in the card cage.

Returning to the description of FIG. 1, consider the test site controllers 4a-4z, each of which is distributed in a total of four card cages, nine each.
These are 4a-4f, 4g-4m, 4n-4t,
4u to 4z (as described above, the alphabet originally has only 26 characters, but it is assumed that another 10 characters exist somewhere in it). CMD / DAT
DSY (command / data daisy chain) 17a is a test site controller 4 in one card cage.
a-4f are interconnected and another CMD / DATA DSY
17b interconnects the test site controllers 4g-4m in other card cages. Test site controllers 4n to 4t and 4u to
4z have similar configurations. As described above, when "DSY does not exit the card cage", the tail end (tail e) of the bus that actually constitutes the DSY is referred to.
nd) does not leave the card cage and is the beginning of the next section in the other card cage. Instead, the system bus 3 from the test system controller 2 reaches all the test site controllers, and each of the test site controllers can operate as a master at the head of the corresponding “DSY section that does not leave the card cage”. You can.

CMD / DAT D described so far
SY17a to 17d are test site controllers
Exist between the lines 4a to 4z. SYNC / ERR DS
Y18a-18d and DUT testers 6a-6z
Configuration. Luck by SYNC / ERR DSY18
DUT testers harmonize with synchronization and error information
Can work. These two types of daisy
(17 and 18) carry slightly different types of information
But each combine one or more test sites
Of the same overall mechanism to configure the test station
It exists as a department.

Next, proceeding to the description of FIG. 2, an enlarged block diagram schematically showing the DUT tester 6 of FIG. 1 is drawn. There are a maximum of 36 of them, one of which will be described here. As can be seen at a glance in FIG. 2, a substantial number of components are depicted in the schematic block diagram. Some of the elements included in the DUT tester 6 and depicted in this block diagram are functionally very complex and are not readily available as commercial products. Here, two points are specified. First, the main purpose of FIG. 2 is to explain the basic characteristics of the important operating environment of the entire nonvolatile memory test system 1. The present invention, which will be described in detail with reference to the figures after FIG. 3, is an extension of the mechanism described below with reference to FIG.
Or, it is a new mechanism whose grounds of existence can be found in FIG. In any case, it is not clear at this writing which of these mechanisms the reader will face. The goal at this time is to explain each of the mechanisms in a concise and proper manner by providing a concise but sufficient information as a starting point for a number of different details of the various embodiments (different inventions). Contrary to the long specification, which discloses everything for each). Second, some of the expanded, or expanded, examples include information that conforms to the general rules shown in FIG. 2, but is inconsistent with this simple case. However, this is not an error or a definitive contradiction, but it is sometimes difficult or impossible to show things in a simplified way so that the whole picture is represented in a completely reduced version. This situation is similar to a road map. For example, a standard size map of Colorado has an Interstate I
If you go east on the -70, you will find that you can go north on the I-25 in Denver. This looks like a left turn. In fact, it used to be a left turn in the past, but now it is different. A map detailing the interchange shows a series of partial diversions and interrupted lanes. However, no one has said that the standard size road map is wrong. It is right at this level of abstraction. Similarly, although FIG. 2 appears to be drawn in considerable detail, it is actually a simplified diagram drawn with medium abstraction,
At first glance it looks like a "left turn", but it is actually a simple "left turn"
In some cases, this is not the case.

As shown in FIG. 1, the primary input to the DUT tester 6 is an instance of the test site bus 5 originating from the test site controller 4 that couples to the DUT tester 6 instance of interest. is there. The test site bus 5 is coupled to a multi-bus controller 88 that converts traffic on the test site bus into ring bus 85 or VT bus 89 traffic. It is also possible to convert ring bus traffic to VT bus traffic and VT bus traffic to ring bus traffic. Almost everything shown in FIG. 2 is part of a large scale integrated circuit. Although shown as a single entity for convenience, the timing / formatting & comparing circuit 52 (described below) is actually comprised of eight such ICs. Various external DRAM
With the exception of some of these (also included in internal test memory 87 of FIG. 3), most of the components shown in FIG.
It is a part of another large-sized IC called G (Automatic pattern generator: hereinafter, referred to as “APG”). The ring bus 85 is the AP of the DUT tester 6.
This is a general-purpose inter-mechanism communication path for setting main components in the G section, setting operation modes, and the like. There are also various dedicated wide high-speed paths between the various elements of the APG. The VT bus 89 is a bus between ICs used in the DUT tester itself.

The ring bus 85 is a mechanism used by the test site controller to communicate with the APG section of the DUT tester 6. Ring bus 85 is coupled to microcontroller sequencer 19, which can be linked to a special purpose microprocessor. This fetches a program stored in a program memory using an address created by a next address calculator 102. This program memory is stored in the microcontroller sequencer 19. (The program SRAM 20) or an external device (the external DRAM 21). These two memories basically look as if they are addressed by an address 63 acting as a logically common program counter (or instruction fetch address), and both are the source of the program to be executed. However, it should be noted that (1) only one of the memories is performing an instruction fetch memory cycle at any given time, and (2) in fact, they are addressed by electrically different signals. That is. S
Although the RAM is fast and allows true random access, the microsequence controller 19 (large AP)
Due to the use of valuable space inside the GIC), its size is limited. The external DRAM can be flexibly set to a considerable capacity, but cannot operate at high speed unless a continuous area is accessed without branching by linear execution.
Although programming in the SRAM 20 is often highly algorithmic, the external DRAM 21 is suitable for those which cannot be easily generated by algorithm processing such as an initialization routine or random or irregular data.

The next address calculator 102 executes an unconditional jump or a conditional jump instruction, or various program control flags 25 and other flags.
(other flag) 55 and other specific signals provided for multi-DUT processing (for convenience, DFE 0: 3 103 and D
In response to a conditional subroutine instruction conditioned on PE0: 3 104), a branch can be made to the test program being executed.

The instruction word fetched and executed by the microcontroller sequencer 19 is as long as 208 bits. It consists of 13 16-bit fields. These fields often represent instruction information fetched for an external mechanism of the microcontroller sequencer 19. Such fields are dedicated to the mechanism associated with them. One set of ALU instructions 22 is applied to a set of eight 16-bit ALUs 24, and the other set is distributed to various other mechanisms distributed within the DUT tester. The latter state is represented by a line labeled "various control value &instruction" 42.

The eight 16-bit ALUs 24 each have a well-known repertoire of arithmetic instructions built around its associated 16-bit result register (each ALU also contains some other registers). . Three of the result registers and their associated ALU are X and Y
And Z to generate the address component 27. The address components are variously combined to form a DUT.
Will be the complete address supplied to. 8 ALUs /
Two of the registers (DH & DL) help to algorithmically create a 32-bit data parameter 28, where the 32-bit data parameter 28 has a maximum valid portion (DH) and a minimum valid portion (DL). Divided between The last three ALUs / registers (A,
B, C) are used as counters and contribute to the generation of various program control flags 25. These program control flags assist program control and branching that is performed when the number of repetitions or other numerical conditions specified in the program are completed. These are sent back to the microcontroller sequencer 19, which will act on the value of the instruction fetch address (created by the next address calculator 102) in a manner well known to those familiar with microprocessors. There are also various "other flags" 55, which can also be used to cause program branching. These each originate from another mechanism in the DUT tester 6 controlled by another field included in the fetched instruction word. VEC_ as one specific additional flag
FIFO_FULL 26 is explicitly and individually indicated. In another more simplified diagram, this is also the other flag 5
5 is included. This is shown separately here:
This is to help explain one aspect of the processing of the microcontroller sequencer 19.

The function of VEC_FIFO_FULL is to (temporarily) halt further execution of the program by the microcontroller sequencer 19. A multi-stage pipeline exists between the instruction fetched by the microcontroller sequencer 19 and the mechanism that finally sends out the test vector to be applied to the DUT. In addition, the baggage to which the vectors are added in the process of being transported for application to the DUT contains, in part, information about the final vector application speed or the duration of each vector. Therefore, the vector application speed to the DUT does not need to be constant, and specifically, the application time of a certain vector group may be longer than the time required for generation. The microcontroller sequencer simply runs the program at its full speed. However, the “vector consumption” rate is “vector generation”
production) "speed, it is clear that pipelines must have almost infinite flexibility. At the output of the address mapper 29 described below is a vector FIFO 45, which acts as a flexible capacity in the pipeline. Signal VEC_
FIFO_FULL acts to temporarily suspend the generation of a new vector at the beginning of the pipeline so that the limit number of stages in the pipeline is not exceeded.

Continuing with the description, the X, Y and Z address components 27 (of 3 × 16 = 48 bits) are applied to the address mapper 29. The output of the address mapper 29 has been rearranged into address values in a 48-bit address space ordered in an almost arbitrarily preselected configuration. To help understand this, we will leave the subject, but assume that this address mapper 29 is a memory with a 48-bit address space completely filled, and that each address holds a 48-bit value. If it were to be realized, it would be a large refrigerator, but ignore it temporarily.) Whatever address is provided with such a memory, a look-up table that can be arbitrarily selected and mapped into a 48-bit value that can later be used as a replacement address Is realized. Such address mapping is desirable because the X, Y, and Z address components generally have useful meanings that are difficult to implement with a single large linear decoder in the context of a particular DUT internal structure. It is. queue,
The notion of layers, blocks or pages is very useful for test engineers, and failures that occur in physically close locations have corresponding proximity in these X, Y and Z addresses. ing. Such patterns in the test results evaluate what is wrong and repair it, such as by reprogramming at the design or manufacturing level, so that the processing of the defective part branches to the processing of the spare part. Is invaluable above.
From this point of view, two problems arise. The first problem is that 48 bits are paired and reduced to the actual number of bits to apply to the DUT (eg, 32 or 16). To briefly explain how this pairing works, it gets some bits from X,
Take some bits from Y and get the remaining bits from Z. But not all. This is the second problem because a particular address may be located in a circuit that is a left-right (or left-right and up-down) mirror image of another part of the circuit. In this case, as long as the continuous address values are arranged in the physical order in the circuit, the meaning of the bits changes. This chip layout characteristic can occur many times, and what a certain group of bits (for example, Y) means may depend on the value of another bit group (for example, Z) associated therewith. The address mapper 29 allows this type of situation to be reflected by "repackaging" the addresses of the raw X, Y, and Z, and has such an internal structure. It is for the convenience of those testing memory with configuration. Explain how this is actually done. Address mapper 29 is composed of a number of interconnected multiplexers. This does not enable a perfect arbitrary look-up table function in a completely filled memory decoding scheme, as mentioned above for the sake of convenience as a temporary hypothetical example. However,
In particular, since there are other mechanisms that can be reduced by pairing from 48 bits to the actual required number, the subfields of the X, Y and Z address components can be reordered as needed. The address mapper 29 has three 1
It further has a 6-bit (address) look-up table, which allows arbitrary limited mapping to be performed in the local area.

The post-map address output 30 of the address mapper 29 is used as an address for various buffer memories,
This is applied to the tag RAMs 31A to 31C and the error capturing RAM 32. Although these memories have separate functions, they can be implemented as selectable partitions in four memory sets that collectively constitute the internal test memory 87. The mapped address output 30 is further applied as one input to an address bit selection circuit 37 (its multiplexing function will be described later). The internal test memory is
It can be configured to include many different RAM-based memory structures used for different functions. This is achieved by declaring that certain parts of the different memory sets are used for their attendant purposes. One such configuration is shown in FIG. 2, and the configuration can be changed as the test progresses, and the entire processing related to this memory set application is performed very dynamically. It can be said.
Any part present in the internal test memory (eg, error capture RAM 32) is not permanent fixed hardware. Only the four memory sets are immutable. However, at any point in time, what part of which memory set is the error capture RAM (if it is actually defined) depends on the currently established settings.

The buffer memories 31A and 31C will be described. Its function is to hold data patterns 33 and addresses 34 that can be applied to the DUT. In fact, these are separate outputs of the respective buffer memories (buffer memory 31 is not a dual "port memory", but
Preferably consisting of parts of two different memory sets). In this case, it is desirable that the storage data 33 be held in one memory set and the storage address 34 be held in the other memory set. Also, although a mechanism for writing to the buffer memory is not explicitly shown, one way to do this is to use the test site controller 4
The method is performed by processing the bus specified by the address that is activated. "Underfloor (un
der the floorboards) | Utility Services
There is a "utility service" bus (most of its paths have been omitted to make the figure very difficult to see), which leads to almost all of the elements shown in FIG. Another faster method for writing information to a memory set is described in connection with FIG.

The error capturing RAM 32 is a buffer memory 3
One is addressed by the same address applied to one. These are for storing or acquiring information on errors, and the processing is performed by a post-decoding circuit (po) described later.
st decode circuit). Similarly to the paths 33 and 34 from the buffer memories 31A and 31C,
Paths 62A to 62D from the error trapping RAM 32 are multiplexed outputs from a memory set part (part set to function as an error trapping RAM) based on setting information distributed from a ring bus (not shown). It is desirable that

It should be noted that the data multiplexer 35
Is that at the same time as receiving the data 28 from the registers DH and DL in the ALU set 24, it also receives the stored data output 33 from the buffer memory 31A. The data multiplexer 35 supplies these inputs (2
8, 32), the first selection is made based on the value 36 stored in the program SRAM 20. Its output 38 is
Unless the changes described below are made, the transmission vector mapper / serializer / reception vector comparison data circuit 40 is used as one of the two vector components (the other component is the output 39 of the address bit selection circuit 37).
Applied to The data multiplexer 35 further converts the initial selection value into a column jamming mode signal (column jamming).
mode signal) (not shown in the preceding figures) and the "column jamming process" described below based on values obtained from the tag RAM operating as a BAD COLUMN table.
(column jamming) ". The entire mechanism will be described later in detail.

The circuit 40 is capable of performing three vector-related functions, the function of which is to order completed vectors which can be applied (transmitted) to the DUT by combining vector components (38, 39). The physical bits of the terminal electronics that contact the DUT on behalf of its signals (the bits in the vector) instead of its bits (the bits in the vector). Performing a dynamic arbitrary mapping between channel numbers and dividing the entire logical vector so as to be applied in order (serialized) to the DUT receiving it. In this case, it works independently in cooperation with the compiler. Which of these functions is executed is determined by a control signal from the SRAM 41. This control signal is also used for addressing based on one field in a 208-bit instruction fetched by the microcontroller sequencer 19. Is what is done.

The circuit 40 further includes a DUT
This is a disable logic unit (DUT disable logic) 90. This is because of the up to four DUTs
This is to indicate which one or more DUTs are to be disabled, and to accommodate various situations defined programmatically, which may be static or variable depending on test results. These indications consist of four signals DD0: 3444b
(DUT disable for DUT0, DUT1, etc.). This is a multi-DU at the test site
It supports the T-test, the details of which are set forth in the related patent application, which is incorporated herein by reference. The output of circuit 40 is a vector 4 of up to 64 bits.
4a, and this vector is the DUT disable signal 4
4b together with the vector FIFO 45. Vector F
When the FIFO 45 is completely filled, the signal VEC_FIFO_
FULL 26 is generated, the meaning and use of this signal has been described above. Period generator 49
Signal VEC_FIFO_U (which will be briefly mentioned later)
Upon receiving NLOAD 47, the vector at the top of vector FIFO 45 is retrieved therefrom. The vector 46 extracted in this way is connected to the DUT via the corresponding terminal electronic component 9 at the timing / formatting &
This is applied to the comparison circuit 52. That is, each of the terminal electronic components 9 receives the transmission / reception vector 7 and the terminal electronic component setting information 8 from the corresponding timing / formatting & comparing circuit 52.

The timing / formatting & comparing circuit 52 is connected to the VT bus 89 for receiving setting / control information. As described above, the timing / formatting & comparing circuit 52 actually has eight ICs.
However, in this specification, it is assumed to be treated as one entity for convenience.

The timing / formatting & comparing circuit 52 includes an internal SRAM 54 addressed by the same instruction address (A surrounded by a small circle) as the program SRAM 20 of the microcontroller sequencer 19.
(The external DRAM 53 may be used in place of the internal SRAM 54, but this is locally addressed by an increment counter not shown). Internal SRA
M54 (or external DRAM 53) assists in generating a drive cycle and a comparison cycle having respective formats. The drive cycle applies the transmit vector to the DUT using a preselected format provided by one of the RAMs 54 or 53. The comparison cycle receives a vector supplied from the DUT and tests whether it matches the previously supplied comparison data, and this test is also performed based on a preselected format supplied from the RAM. . The drive cycle and the compare cycle both have their duration, whether to apply the load, and when to apply, when to latch or strobe data, and when the signal returns.
It is possible to set whether or not -To-Zero, whether to surround the drive signal with its complement signal, and the like (these options are in the various formats described above).

The timing / formatting & comparing circuit 52 determines whether the channel has become defective due to an incorrect logical value (functional error) and / or has failed because its electrical characteristics have exceeded an allowable range. Information (parameter error) for each channel. Further, when multiple DUT tests are performed, as described in the patent application incorporated by reference, which channel is connected to which DUT is known. It is. Thereby, four signals D
FE0: 3 (DUT # function error) 103 and four signals DPE0: 3 (DUT # parameter error) 104 can be generated.

The comparison process performed by the timing / formatting & comparison circuit 52 produces an additional 64-bit value, which is a logical inverse of the circuit 40 and is a receive vector inverse mapper / deserializer 5 that can be considered.
7. (The processing of the circuit 57 is controlled by the SRAM 58.
). The output 59 of the circuit 57
Is the post-decoding circuit 60 and the error capturing RAM 13
Applies to 2A. Although not described in detail here, the post-decoding circuit 60 receives the input error information 5
9 and the previously stored error information 60 (error capture RA
M) can be checked on a programmatic basis to generate condensed and more easily interpretable error information. This generated error information
The data can be returned to the error capturing RAM 32 via the path 61 and stored. One example is to create a count of the number of times an error has occurred in a particular address range. Useful.

Next, the period generator 49 and the corresponding timing SRAM 51 will be described. These are in response to an 8-bit signal T_SEL 43 that defines the duration of the associated timing / formatting & comparison circuit 52 processing for each of the 208-bit instructions fetched by the microcontroller sequencer 19. T_SEL 43 is part of various control values & instructions 42 each represented by a different field in the fetched instruction. This signal can represent or encode 256 different things as 8-bit values. The “thing” in this case is a 28-bit value stored in the timing SRAM 51 and addressed by T_SEL. Each of the addressed 28-bit values 23 specifies a desired duration with a resolution of 19.5 picoseconds. The sequence of accessed 28-bit duration values 23 is the duration FI
The individual elements of the sequence are stored in the FO 50, from which they are adapted to be synchronized with the acquisition of their intended corresponding vectors, which are stored in the vector FIFO 45.

The coarse timing value field in the oldest entry of the FIFO 50 contains duration information with a resolution of 5 nanoseconds, from which the next transmission vector is sent from the vector FIFO 45 to the timing / formatting & comparing circuit 52. VEC_FIF to send
O_UNLOAD 47 is generated. Companion signal (compan
ion signal) Timing reminder
48 also applies to the circuit 52. At this point 1
A final resolution of 9.5 picoseconds is reached.

Reference is now made to FIG. 3, which is a schematic block diagram 6 of the internal test memory 87 shown in the block diagram of FIG.
4. It receives a 48-bit mapped address 30 to be applied from the address mapper 29 to a plurality of address selectors 77, 78, 79. The address selector is coupled to memory sets 73-76. Each of these memory sets is a complete memory mechanism that can individually perform functions such as, for example, acting as an ECR 32.
Two of the memory sets (73, 74) are external DRAM
And the other two belong to the internal SRAM. The two external DRAM memory sets always perform the same address selection function, and therefore share the same address selection unit 77. On the other hand, the internal SRAM memory sets 75 and 76 have address selecting sections 78 and 79 corresponding to each. These address selectors do not change the address,
Alternatively, it outputs the changed address, and certain details of the processing are described in the patent application which is incorporated herein by reference.

Each memory set includes a memory set controller. The external DRAM memory sets 73 and 74 respectively include DRAM memory set controllers 65 and 66, and the internal SRAM memory sets 75 and 76 include SRAM memory set controllers 67 and 68, respectively. During testing of the DUT, addresses for memory transactions directed to any of these memory sets reach the memory set controllers included in that memory set from the corresponding address selector. During testing of the DUT, the error data 61 supplied from the post decode circuit 60 and to be written to the error capture RAM is first applied to the data selectors 80-83 which are respectively coupled to each memory set. . The data selection unit may or may not change the supply data depending on the setting and the function being executed. The address and data selectors are high speed address and data paths, respectively, which are intended to operate at the highest required speed. Other paths for address and data to be carried by a ring bus (not shown) to a memory set will be described later.

At this point, there are four memory set controllers 65-68 to which (selection) addresses and (selection) data are respectively input. Each of these memory aggregation controllers is coupled to a corresponding memory. That is, DRAM memory aggregation controllers 73 and 74 are coupled to external DRAMs 69 and 70, respectively,
RAM memory aggregation controllers 75 and 76 are coupled to internal SRAMs 71 and 72, respectively.
This configuration forms four memory sets 73-76, two of which (75, 76) are high speed SRAMs.
The other two (73, 74) include the larger capacity of the slower DRAM. The most important point here is not only how to make the DRAM memory set equal to the SRAM memory set, but also how to realize a specific alternative configuration of DRAM corresponding to the user's preference and test program policy. Is it possible? Therefore, DRA
The M memory aggregate controllers 65, 66 are configurable and must perform different types of memory transactions, and are not exactly the same as the simple SRAM memory aggregate controllers 67, 68. Although FIG. 3 does not show a structure that provides this flexibility for simplicity, each memory aggregation controller has a ring bus (not shown) that directs a particular mode of operation and desired settings. Just say you are connected. Some of these modes relate to data storage modes, and others relate to data reacquisition.
In conclusion, each memory set has a corresponding data Out (6
2A-D), which are sent to the post-decode mechanism 60 for later processing. Further, memory sets 0 and 2
It should be noted that the data output from is applied to multiplexer 84, the output of which is STORED DATA 33 which is sent to data multiplexer 35. Similarly, the outputs of memory sets 1 and 3 are applied to multiplexer 127, whose output is sent to address bit select multiplexer 37.
RESESS. The reason for the existence of the multiplexers 84 and 86 and how they are controlled is not important here and is described in the patent application which is hereby incorporated by reference.

The memory set 376 includes a bad column mode signal (COL_JAM_MOD) which is not received by another memory set.
E107). Controller 68 of memory set 3
Responds so that the special operation mode is described at an appropriate time using this signal. It should be understood at this point that if COL_JAM_MODE 107 is true and a write memory cycle has not been activated, then when a new address is supplied, an automatic read cycle for that address will occur. That is the point. The four least significant bits of the data obtained by the reading process are sent to the lower part of the data multiplexer 35.
(The special BAD COLUMN table has been read and how this data is obtained and used will be described later.)

Reference is now made to FIG. 4, which is an enlarged block diagram 120 of the data multiplexer 35 shown in FIG.
It is. The purpose of this figure is to split the multiplexer 35 into two parts 35 'and 35 "which are connected by a path 38'. The part 35 'is based on an input control signal 36 from the inputs 28 and 33 (spare). (Or first) in that it performs a selection and outputs 38 ', similar to a conventional multiplexer, the part we really want to address is part 35 ". It receives output 38 'as a data input and BAD_COL [3: 0] (these are the four least significant bits of 62D from memory set 376) as a control input.

Reference is now made to FIG. 5, which is a block diagram 90 of the portion 35 "shown in FIG. 4. It has 32-bit data 38 'as a data input, but this data is related (adjacent). Four 8-bit groups 1 with significance
Partitioned into 12-115. This division into four 8-bit units is a good fit for this multi-DUT test mode. I will go on with the explanation,
Each of these 8-bit groups (112-115)
Is the corresponding eight-pole two-thr
ow) applied as one input to multiplexers 93-96. Another input to these multiplexers is a 32-bit COLUMN configurable via ring bus 85
8-bit group 10 obtained from JAM register 91
8 to 111.

This concept means that, under appropriate circumstances, all or part of the data 38 ′ going to
This is to make it possible to substitute data set in advance in the UMN JAM register 91. When used as a value to program into a flash DUT, the DUT will return an immediate response as if it were programmed properly, even if the requested value was not programmed properly. Use values that are As discussed above, what is required is to avoid spending time programming a column known or suspected to be a defective column.
(Those that instruct current flash components to program a 1 correspond to such values.)

In this embodiment, a general multiple DUT is used.
This replacement can be done with an 8-bit resolution to match the test scheme. This unit is 8, 16, 24, 3
Effective for 2-bit components. Bits are wasted for 4-bit components, 12-bit components, and the like. In order to avoid this, a unit of 8 bits or less, for example, 2 bits which are significantly finely divided, or 1 bit which is further divided may be used. The four multiplexers 93 to 96 have 16 two-pole two-throws when two bits are used.
It becomes a multiplexer, and if it is 1 bit, it becomes 32 single pole double throw multiplexers.

Therefore, for example, in a test of two 16-bit parts, one of the bits is a bit [31: 1] of 38 '/ 38.
6] and the other uses bits [15: 0], and if the component at bits [15: 0] includes a defective column at a certain applied address, that address is applied. Column jamming mode (this is a name given to "fool" the test program / DUT to avoid wasting time programming into known bad columns). Is enabled and bits [15: 0] of data 38 'are
From the least significant bit of the OLUMN JAM register 91,
For example, all are replaced with 1.

For example, if it is known that bit 3 has a defect, it is possible to avoid this bit alone and process other bits as usual. This uses a 1-bit resolution, or with the bit 3 jammed at 1, the actual data (the one originally at 38 ') is
Bits [15: 4] and [2:
0]. If this configuration is implemented by a ring bus, the speed will decrease, but it is possible. The time saved here is the difference between the time required to program the good 15 bits and the timeout associated with programming the bad bit 3.

All of the processing described so far occurs under "right circumstance". The “appropriate situation” indicates a state in which the column jamming mode is selected by setting the column jamming mode latch 92 by appropriate processing via the ring bus 85. When latch 92 is set, one input to the set of AND gates 97 and 98, 105 and 106 will be set. The other inputs to these gates are B
This is instruction data obtained from the AD COLUMN table (126 in FIG. 6). This data is COL_JAM_MO
As long as DE 107 is true, it results from an automatic read at the applicable address. For this purpose, the signal 107 is also supplied to the memory set controller 68 of the memory set 3 as described in the description relating to FIG. The resulting display signal (the four least significant bits of 62D) is represented by BAD_
COL [3: 0].

In the case of a memory tester, since a device failure is generally represented by 0, the signal BAD_COL
[3: 0] are each inverted when applied to the corresponding AND gate. As a result, the multiplexers 93 to 9
6 selects a bit from the COLUMN JAM register as its output whenever COL_JAM_MODE is true and the corresponding BAD_COL bit is 0 (meaning the column to one of the multiplexers is bad). Controlled. When the replacement resolution increases,
Table 1 from which the number of bits in BAD_COL is read
It is also necessary to increase the width of 26.

In each case, the multiplexers 93 to 9
The six outputs 116-119 are collected as data 38 into a 32 bit stream and sent to circuit 40 as described above in connection with FIG.

Reference is now made to FIG. 6, which is a diagram of a BAD COLUMN table 126 that can be maintained in memory set 3 by a test program. Multiple DUs
The T processing uses the same automatic table reading mechanism as that used for the multiple DUT processing in the memory set 2, and the remaining memory sets do not have this class of service. Is a required element. This constraint is governed by the economic trade-offs that are deemed necessary and can be eliminated from a technical point of view.

As will be further described, the test program is as follows.
If a column is determined to be bad, a zero entry is written to a cell in table 126 during either the programming or operation stages. There are four cells in each row of table 126, each of which represents four 8-bit (resolution of the scheme) groups. Whether the 8-bit group represents one DUT in a multi-DUT test or one section of a single DUT depends on the test technician's choice. In the case of a 32-bit single DUT, all four bits in one row of the table 126 are simultaneously set or cleared at the word width resolution. Similarly, the register 91 in FIG. 5 is a unified set of all 1s. If the replacement resolution is one bit, the row in table 126 is BAD_C
OL [31: 0] has a 32-bit length. (And 32 multiplexers and AND gates shown in FIG. 5 are also required.)

Referring to the patent application, which is hereby incorporated by reference, including a description relating to multi-DUT processing, it describes a bad block (DUT) table similar to the BAD COLUMN table 126 described above. I understand. If there is a bad DUT, the bad block table is maintained in both the new and old versions so that incremental additions can be made to the table.
This is again possible, but most of the bad column information is detected and stored during column-to-column movement during the pre-programming stage, and here a copy of such a table is made. Seems to have little or no benefit.

In this embodiment, cell 122 (and most of the other cells) contains a "1" indicating that it is not defective. On the other hand, cells 123 and 124 are “0” indicating that column 1 of DUT2 and column 3 of DUT0 are defective.
Contains.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a significantly reconfigurable nonvolatile memory tester according to the present invention.

FIG. 2 is a schematic block diagram showing the DUT tester 6 of FIG. 1 in an enlarged manner.

FIG. 3 is a schematic diagram of functional blocks of an internal test memory mechanism shown in the block diagram of FIG. 2;

FIG. 4 is an enlarged schematic block diagram of a data multiplexer 35 of FIG. 2;

5 is an actual block diagram of the enlarged view shown in FIG.

FIG. 6 is a functional diagram of a bad column (BADCOLUMN) table held in a memory set located in the internal test memory of FIG. 2;

[Explanation of symbols]

 1 Memory Tester 14, 15a-d Memory Under Test 31B Tag RAM 35 "Automatic Data Replacement Mechanism

 ──────────────────────────────────────────────────続 き Continued on the front page (71) Applicant 399117121 395 Page Mill Road Palo Alto, California U.S.A. S. A. (72) Inventor John M. Freezeman, Gray Fox Road, Fort Collins, 80526, Colorado, United States 4507 (72) Inventor Ken Han Duck Rye 95148, San Jose, Glenn, California, United States of America・ Ferguson Circle 2736 F-term (reference) 2G132 AA08 AB01 AC03 AD06 AG00 AL09 AL12 5B025 AD04 AD16 AE05 5L106 AA10 DD22 DD23 DD24

Claims (2)

[Claims] 1. A method for avoiding wasting time programming a bad column in a flash memory under test on a memory tester, comprising: (a) using the same address applied to the memory under test; Establishing a tag RAM to be addressed; (b) determining that the applied address is associated with the bad column; and (c) determining that the column is located at the applied address in the tag RAM. Storing an indication of failure; (d) after steps (a)-(c), enabling an automatic data replacement mechanism during a next stage of testing the memory under test; (E1) While applying a test address to the tag RAM,
Attempting to program the memory under test with the test address; and (e2) if the tag RAM includes an indication that the test address belongs to a bad column, the memory tester Substituting a data value to be programmed with a "1" to cause the automatic processing of to immediately notify that the memory under test is healthy. 2. In the step (e2), all data values to be programmed to be replaced are “1”.
The method of claim 1, wherein