JP2002185103A - Method for evaluating flatness of electrode pads on mounting surface of mounting substrate - Google Patents
Method for evaluating flatness of electrode pads on mounting surface of mounting substrateInfo
- Publication number
- JP2002185103A JP2002185103A JP2000384400A JP2000384400A JP2002185103A JP 2002185103 A JP2002185103 A JP 2002185103A JP 2000384400 A JP2000384400 A JP 2000384400A JP 2000384400 A JP2000384400 A JP 2000384400A JP 2002185103 A JP2002185103 A JP 2002185103A
- Authority
- JP
- Japan
- Prior art keywords
- mounting
- flatness
- virtual plane
- electrode pads
- mounting surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 78
- 239000000758 substrate Substances 0.000 title claims abstract description 56
- 239000004065 semiconductor Substances 0.000 claims abstract description 73
- 238000011156 evaluation Methods 0.000 claims abstract description 50
- 238000005259 measurement Methods 0.000 claims abstract description 20
- 238000007796 conventional method Methods 0.000 abstract description 3
- 238000012360 testing method Methods 0.000 description 8
- 239000010931 gold Substances 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Landscapes
- Length Measuring Devices With Unspecified Measuring Means (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
(57)【要約】
【課題】 従来の実装用基板の実装面の平坦性評価方法
では、実際の実装プロセスを反映した電極パッドのなす
面の平坦度を得ることが困難であり、実際の平坦度から
乖離して評価してしまうという問題点があった。
【解決手段】 半導体装置1の実装面に複数の電極パッ
ド4を有する実装用基板3に対し、電極パッド4のうち
のn個(ただし、nは4以上の整数)に設定した測定点
について測定したn組の3次元座標データから最小二乗
法を用いて得られる平面を第1仮想平面とし、次いで第
1仮想平面からの高さが最も低い点を除いた(n−1)
組の3次元座標データから最小二乗法を用いて得られる
平面を第2仮想平面とし、以下順次同様にして3次元座
標データが3組になるまで繰り返し、この3組の3次元
座標データによって得られる第(n−2)仮想平面を得
た後、n点について第(n−2)仮想平面から見た距離
を評価高さとして求める。
(57) [Problem] It is difficult to obtain the flatness of the surface formed by the electrode pads reflecting the actual mounting process by the conventional method for evaluating the flatness of the mounting surface of a mounting board, and There was a problem that the evaluation was deviated from the degree. SOLUTION: A mounting substrate 3 having a plurality of electrode pads 4 on a mounting surface of a semiconductor device 1 is measured at n measurement points (where n is an integer of 4 or more) among the electrode pads 4. A plane obtained by using the least squares method from the n sets of three-dimensional coordinate data is set as a first virtual plane, and then the point having the lowest height from the first virtual plane is removed (n-1).
A plane obtained from the set of three-dimensional coordinate data by using the least squares method is defined as a second virtual plane, and the same process is repeated in order until three sets of three-dimensional coordinate data are obtained. After the obtained (n-2) th virtual plane is obtained, the distance of the n points viewed from the (n-2) th virtual plane is obtained as the evaluation height.
Description
【0001】[0001]
【発明の属する技術分野】本発明は情報通信分野や半導
体分野等において半導体素子や半導体素子を半導体素子
収納用パッケージに収容して成る半導体デバイス等の半
導体装置をいわゆるフリップチップ実装法により実装す
る実装面を有する実装用基板について、その実装面の平
坦性を評価するのに好適な平坦性評価方法に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting method for mounting a semiconductor device such as a semiconductor device or a semiconductor device in which a semiconductor device is housed in a package for housing a semiconductor device by a so-called flip-chip mounting method. The present invention relates to a flatness evaluation method suitable for evaluating the flatness of a mounting surface of a mounting board having a surface.
【0002】[0002]
【従来の技術】近年、回路基板や半導体素子収納用パッ
ケージ等の配線基板として用いられる実装用基板に半導
体素子や半導体素子を収容した半導体デバイス等の半導
体装置を実装する方法として、いわゆるフリップチップ
実装法が多用されるようになっている。この実装法は、
例えば、半導体装置の実装面側の電極上に金や半田材料
等から成る突起電極を設け、一方、この半導体装置が実
装される実装用基板の実装面にはこの突起電極に対向す
る位置に電極パッドを設けておき、これら半導体装置の
突起電極と実装用基板の電極パッドとを位置合わせして
半導体装置を載置した後に加熱加圧することにより、ま
たは半導体装置を介して突起電極と電極パッドに超音波
エネルギーを印加することにより突起電極と電極パッド
とを接合して、半導体装置を実装用基板にいわゆるフェ
ースダウンで実装するものである。2. Description of the Related Art In recent years, as a method of mounting a semiconductor device such as a semiconductor device or a semiconductor device containing a semiconductor device on a mounting substrate used as a wiring substrate such as a circuit board or a package for housing a semiconductor device, a so-called flip-chip mounting method is used. The law is becoming heavily used. This technique is
For example, a protruding electrode made of gold, a solder material, or the like is provided on an electrode on a mounting surface side of a semiconductor device, and an electrode is provided at a position facing the protruding electrode on a mounting surface of a mounting substrate on which the semiconductor device is mounted. Pads are provided, and the semiconductor device is mounted after positioning the projecting electrodes of the semiconductor device and the electrode pads of the mounting substrate, and then heating and pressing the semiconductor device. The projection electrode and the electrode pad are joined by applying ultrasonic energy, and the semiconductor device is mounted on the mounting substrate face-down.
【0003】このようなフリップチップ実装において実
装用基板の電極パッドと半導体装置の突起電極とを機械
的に接合し、かつ電気的に接続する方法には、様々な方
法が用いられている。In such flip-chip mounting, various methods are used for mechanically bonding and electrically connecting the electrode pads of the mounting substrate and the protruding electrodes of the semiconductor device.
【0004】例えば、図4(a)に側面図で示すよう
に、半導体装置としての半導体素子1を、その下面に形
成された突起電極2の先端に例えば銀ペースト5を塗布
して実装用基板3の上面の素子実装領域に形成された電
極パッド4と当接させて載置した後、同図(b)に同様
の側面図で示すように、半導体素子1の上からツール
(加圧加熱手段)6により加熱加圧して、突起電極2と
電極パッド4とを銀ペースト5等を介して接続する方法
がある。For example, as shown in a side view of FIG. 4A, a semiconductor element 1 as a semiconductor device is prepared by applying, for example, a silver paste 5 to the tip of a protruding electrode 2 formed on the lower surface thereof. 3 is placed in contact with the electrode pad 4 formed in the element mounting area on the upper surface of the semiconductor element 1, and as shown in the same side view in FIG. Means 6) There is a method in which the projecting electrode 2 and the electrode pad 4 are connected via the silver paste 5 or the like by heating and pressing by 6.
【0005】また、半導体素子の突起電極を金で形成
し、実装用基板の実装面に形成された電極パッドの表面
も金で形成して、銀ペーストや半田材料を用いずに突起
電極と電極パッドを位置合わせし、これに超音波を加え
ることが可能なツールにより超音波を印加して、超音波
と加熱のみで接続する方法もある。Further, the protruding electrodes of the semiconductor element are formed of gold, and the surfaces of the electrode pads formed on the mounting surface of the mounting board are also formed of gold. The protruding electrodes and the electrodes are formed without using a silver paste or a solder material. There is also a method in which the pads are aligned, ultrasonic waves are applied by a tool capable of applying ultrasonic waves to the pads, and the pads are connected only by ultrasonic waves and heating.
【0006】[0006]
【発明が解決しようとする課題】しかしながら、これら
の方法によって半導体装置を信頼性良く実装するために
は、半導体装置の突起電極の高さが一様に揃っているこ
とと、実装用基板の反りが少なく、実装用基板上の電極
パッドの高さが揃っていることが非常に重要となる。そ
のため、実装用基板上の電極パッドの高さがどの程度揃
っているのかを表す指標により、製品の良否を判定する
ことが必要となってきている。However, in order to mount a semiconductor device with high reliability by these methods, it is necessary to ensure that the heights of the projecting electrodes of the semiconductor device are uniform and that the warpage of the mounting substrate is high. It is very important that the height of the electrode pads on the mounting board is uniform. For this reason, it is necessary to determine the quality of a product based on an index indicating how uniform the heights of the electrode pads on the mounting board are.
【0007】そこで、実際の実装プロセスを考慮する
と、半導体装置を実装用基板に押し付けた際に、まず、
半導体装置の実装面側表面が成す平面すなわち下面の突
起電極の先端により形成される平面が実装用基板に近づ
いて行き、実装用基板の実装面の電極パッドのうち、半
導体装置の下面に最も近い、すなわち、最も高い3点の
電極パッドにて半導体装置を支持した後、それらの突起
電極が変形することによってその他の突起電極も電極パ
ッドに接触し接合されることとなる。このとき、最後に
突起電極が接触し接合されるのは実装面における高さが
最も低い電極パッドである。したがって、実装用基板の
平坦性の評価としては、この最も低い電極パッドに対す
る、最も高い3点の電極パッドを共有する仮想平面から
見た高さを指標として用いることが望ましいといえる。Therefore, considering the actual mounting process, when the semiconductor device is pressed against the mounting substrate, first,
The plane formed by the mounting surface side surface of the semiconductor device, that is, the plane formed by the tips of the protruding electrodes on the lower surface approaches the mounting substrate, and among the electrode pads on the mounting surface of the mounting substrate, is the closest to the lower surface of the semiconductor device. In other words, after the semiconductor device is supported by the three highest electrode pads, the other protruding electrodes are brought into contact with and bonded to the electrode pads by deformation of those protruding electrodes. At this time, the last contact between the protruding electrodes and joining is the electrode pad having the lowest height on the mounting surface. Therefore, in evaluating the flatness of the mounting substrate, it can be said that it is desirable to use, as an index, the height of the lowest electrode pad as viewed from a virtual plane sharing the highest three electrode pads.
【0008】これに対し、従来、実装用基板の平坦性の
指標としては、実装用基板の実装面上の特定の電極パッ
ド3点を固定してその3点を共有する仮想平面を設け、
その仮想平面から見た各電極パッドに対応する測定点の
高さのうち、最も低い点の高さを求め、これを指標とす
るものであった。On the other hand, conventionally, as an index of the flatness of the mounting board, a virtual plane is provided which fixes three specific electrode pads on the mounting surface of the mounting board and shares the three points.
The height of the lowest point among the heights of the measurement points corresponding to the respective electrode pads as viewed from the virtual plane was determined, and this was used as an index.
【0009】また、従来の実装用基板の平坦性の他の指
標としては、実装用基板の実装面上の各電極パッド点の
3次元座標測定系における平面座標と高さとを一組とし
て測定し、得られた3次元座標データを用いて最小二乗
法により仮想平面を得た後、その仮想平面から見た各電
極パッドの高さのうち、最も高い点と最も低い点の差分
を平坦度として求め、これを指標とするものであった。As another index of the flatness of the conventional mounting substrate, a plane coordinate and a height in a three-dimensional coordinate measuring system of each electrode pad point on the mounting surface of the mounting substrate are measured as a set. After obtaining a virtual plane by the least square method using the obtained three-dimensional coordinate data, the difference between the highest point and the lowest point among the heights of the electrode pads viewed from the virtual plane is defined as flatness. Was used as an index.
【0010】しかしながら、従来の前者のような実装用
基板の平坦性評価方法においては、平坦性を評価するた
めの仮想平面を決定する3点が実装平面上の予め選定さ
れた特定の位置のものに固定されており、その3点を共
有する仮想平面が必ずしも実際の実装プロセスを反映す
るのに有効な平面として得られるとは限らず、場合によ
っては仮想平面が極端に傾斜してしまうことがあった。
このため、極端に傾斜した仮想平面から見た各点までの
距離は大きくばらついてしまい、それによって得られた
平坦性の指標は大きくばらつくこととなり、その結果、
実装面の平坦性を実際の平坦度から乖離して評価してし
まうことになるという問題点があった。However, in the conventional method for evaluating the flatness of a mounting substrate as in the former, three points for determining a virtual plane for evaluating the flatness are determined at a predetermined position on the mounting plane. And the virtual plane sharing the three points is not always obtained as an effective plane for reflecting the actual mounting process. In some cases, the virtual plane may be extremely inclined. there were.
For this reason, the distance from the extremely inclined virtual plane to each point as viewed from the virtual plane greatly varies, and the flatness index obtained thereby greatly varies. As a result,
There is a problem that the flatness of the mounting surface is evaluated differently from the actual flatness.
【0011】また、従来の後者のような実装用基板の平
坦性評価方法においては、得られる仮想平面が実際の実
装プロセスを反映するものではなく、単に平均的な平面
として求められているために、それによって得られた平
坦度としては平坦度が良好であるような評価結果が得ら
れることとなり、その結果、実際の平坦度から乖離して
評価してしまうことになるという問題点があった。In the conventional method for evaluating the flatness of a mounting substrate as described above, the obtained virtual plane does not reflect the actual mounting process, but is simply obtained as an average plane. However, as the flatness obtained thereby, an evaluation result that the flatness is good is obtained, and as a result, there is a problem that the evaluation is deviated from the actual flatness. .
【0012】本発明は上記従来技術における問題点に鑑
みてなされたものであり、その目的は、実装用基板の実
装面について実際の実装プロセスを反映した平坦性の指
標を求めることができ、この実装面の電極パッドに対し
て半導体装置を実装する際の良否判定、ならびにこの実
装用基板に半導体装置を実装して得られる製品の良否判
定を容易かつ確実に行なうことができる実装用基板の実
装面における電極パッドの平坦性評価方法を提供するこ
とにある。The present invention has been made in view of the above-mentioned problems in the prior art, and an object of the present invention is to obtain an index of flatness which reflects an actual mounting process on a mounting surface of a mounting substrate. The mounting of the mounting substrate, which can easily and reliably determine the quality of the semiconductor device mounted on the electrode pad on the mounting surface and the quality of the product obtained by mounting the semiconductor device on the mounting substrate. An object of the present invention is to provide a method for evaluating flatness of an electrode pad on a surface.
【0013】[0013]
【課題を解決するための手段】本発明の実装用基板の実
装面における電極パッドの平坦性評価方法は、半導体装
置が実装される実装面に前記半導体装置の突起電極が接
続される複数の電極パッドを有する実装用基板に対し、
前記電極パッドのうちの前記実装面上で分散配置される
ように選択したn個(ただし、nは4以上の整数)に設
定した測定点について3次元座標測定系における平面座
標と高さとを一組として測定し、それにより得られるn
組の3次元座標データから最小二乗法を用いて得られる
平面を第1仮想平面として得て、次いで前記n点のうち
前記第1仮想平面からの高さが最も低い点を除いた(n
−1)組の3次元座標データから最小二乗法を用いて得
られる平面を第2仮想平面として得て、以下順次同様に
して直前に得た仮想平面からの高さが最も低い点を除い
た3次元座標データが3組になるまで繰り返し、この3
組の3次元座標データによって得られる第(n−2)仮
想平面を得た後、前記n点について前記第(n−2)仮
想平面から見た距離を評価高さとして求めることを特徴
とするものである。According to the present invention, there is provided a method for evaluating the flatness of an electrode pad on a mounting surface of a mounting substrate, comprising the steps of: mounting a plurality of electrodes on a mounting surface on which a semiconductor device is mounted; For a mounting board with pads,
For n measurement points (where n is an integer of 4 or more) selected so as to be dispersedly arranged on the mounting surface among the electrode pads, the plane coordinates and the height in the three-dimensional coordinate measurement system are set to one. Measured as a set and the resulting n
A plane obtained by using the least squares method from the set of three-dimensional coordinate data is obtained as a first virtual plane, and then the points having the lowest height from the first virtual plane among the n points are removed (n
-1) A plane obtained by using the least squares method from the set of three-dimensional coordinate data is obtained as a second virtual plane, and points having the lowest height from the virtual plane obtained immediately before are sequentially removed in the same manner. This process is repeated until three sets of three-dimensional coordinate data are obtained.
After obtaining the (n-2) th virtual plane obtained from the set of three-dimensional coordinate data, a distance of the n points viewed from the (n-2) th virtual plane is obtained as an evaluation height. Things.
【0014】また、本発明の実装用基板の実装面におけ
る電極パッドの平坦性評価方法は、上記の方法におい
て、前記評価高さのうちの最も低い高さの値を前記複数
の電極パッドにより形成される面の平坦度とすることを
特徴とするものである。In the method for evaluating flatness of an electrode pad on a mounting surface of a mounting board according to the present invention, the lowest value of the evaluation heights is formed by the plurality of electrode pads. The flatness of the surface to be processed is characterized.
【0015】[0015]
【発明の実施の形態】本発明の実装用基板の平坦性評価
方法によれば、実装用基板の実装面に形成された複数の
電極パッドのうちの実装面上で分散配置されるように選
択したn個(ただし、nは4以上の整数)に設定した測
定点について、3次元座標測定系における平面座標と高
さとを一組として測定し、これらn点の測定点の平面座
標と高さとから得られるn組の3次元座標データを用い
て実装面の平坦性を評価するものであって、n組の3次
元座標データから最小二乗法を用いて得られる平面を第
1仮想平面として得て、次いでこれらn点のうち第1仮
想平面からの高さが最も低い点を除いた(n−1)組の
3次元座標データから最小二乗法を用いて得られる平面
を第2仮想平面として得て、以下順次同様にして直前に
得た仮想平面からの高さが最も低い点を除いた3次元座
標データが3組になるまで繰り返し、この3組の3次元
座標データによって得られる第(n−2)仮想平面を得
た後、元のn点について第(n−2)仮想平面から見た
距離を各測定点に対する評価高さとして求めることか
ら、各測定点について最も高い3点の電極パッドを共有
する仮想平面からみた評価高さをそれぞれの実装面にお
ける高さの指標として用いることができるため、実際の
実装プロセスを反映した平坦性評価のための指標を得る
ことができ、より有用な平坦性評価を行なうことができ
る。According to the method for evaluating the flatness of a mounting substrate of the present invention, a plurality of electrode pads formed on a mounting surface of a mounting substrate are selected so as to be distributed on the mounting surface. For the n measurement points (where n is an integer of 4 or more), the plane coordinates and the height in the three-dimensional coordinate measurement system are measured as a set, and the plane coordinates and the height of the n measurement points are measured. Is used to evaluate the flatness of the mounting surface using n sets of three-dimensional coordinate data obtained from a set of three-dimensional coordinate data. A plane obtained by using the least squares method from the n sets of three-dimensional coordinate data is obtained as a first virtual plane. Then, a plane obtained by using the least square method from the (n-1) sets of three-dimensional coordinate data excluding the point having the lowest height from the first virtual plane among these n points is defined as a second virtual plane. From the virtual plane obtained immediately before The three-dimensional coordinate data excluding the point having the lowest height is repeated until there are three sets. After obtaining the (n−2) -th virtual plane obtained by the three sets of three-dimensional coordinate data, Since the distance viewed from the (n-2) th virtual plane is obtained as the evaluation height for each measurement point, the evaluation height viewed from the virtual plane sharing the highest three electrode pads for each measurement point is mounted. Since it can be used as an index of the height on the surface, an index for flatness evaluation reflecting the actual mounting process can be obtained, and more useful flatness evaluation can be performed.
【0016】すなわち、半導体装置を実装用基板の実装
面に押し付けた際に、まず半導体装置の実装面側表面が
成す平面すなわち下面の突起電極の先端により形成され
る平面が実装用基板の実装面に近づいて行き、実装面に
形成された複数の電極パッドのうち、半導体装置の下面
の突起電極の先端により形成される平面に最も近い、す
なわち最も高さが高い3点の電極パッドにて半導体装置
を支持した後、これらの突起電極の変形によってその他
の突起電極も電極パッドに接触し接合され、最後に突起
電極が接触し接合される最も高さが低い電極パッドの高
さを、最も高い3点の電極パッドを共有する仮想平面か
ら見た評価高さとして求めることが可能となるために、
実装面の平坦度を求めるための仮想平面を決定する3点
が実際の実装プロセスを反映するのに十分な平面として
得られるようになり、実際の平坦度から乖離して評価し
てしまうことがなくなって、実際の実装プロセスを反映
した仮想平面を確実に得ることができる。その結果、実
際の実装プロセスを反映した平坦性を評価し、また平坦
度を求めることが可能となり、この実装面の電極パッド
に対して半導体装置を実装する際の良否判定、ならびに
この実装用基板に半導体装置を実装して得られる製品の
良否判定を容易かつ確実に行なうことができる実装用基
板の実装面における電極パッドの平坦性評価方法とな
る。That is, when the semiconductor device is pressed against the mounting surface of the mounting substrate, first, the plane formed by the surface on the mounting surface side of the semiconductor device, that is, the plane formed by the tips of the projecting electrodes on the lower surface becomes the mounting surface of the mounting substrate. Of the plurality of electrode pads formed on the mounting surface, the semiconductor electrode is closest to the plane formed by the tips of the protruding electrodes on the lower surface of the semiconductor device, that is, at the three highest electrode pads. After supporting the device, the deformation of these protruding electrodes causes the other protruding electrodes to also contact and join the electrode pads, and finally, the height of the lowest electrode pad to which the protruding electrodes are contacted and bonded is the highest. In order to obtain the evaluation height from the virtual plane sharing the three electrode pads,
The three points that determine the virtual plane for determining the flatness of the mounting surface can be obtained as a plane sufficient to reflect the actual mounting process, and the evaluation may deviate from the actual flatness. Thus, a virtual plane reflecting the actual mounting process can be reliably obtained. As a result, it is possible to evaluate the flatness reflecting the actual mounting process and to obtain the flatness, and to judge whether or not the semiconductor device is mounted on the electrode pads on the mounting surface, and to determine whether the mounting substrate is good. The present invention provides a method for evaluating the flatness of an electrode pad on a mounting surface of a mounting substrate, which can easily and reliably determine the quality of a product obtained by mounting a semiconductor device on a mounting surface.
【0017】また、本発明の実装用基板の実装面におけ
る電極パッドの平坦性評価方法によれば、評価高さのう
ちの最も低い高さの値を実装面の複数の電極パッドによ
り形成される面の平坦度として求める場合には、実装面
において最も低い電極パッドに対する、最も高い3点の
電極パッドを共有する仮想平面から見た評価高さをその
指標として用いることができ、実際の実装プロセスを反
映した平坦度の指標を得ることができるため、実装面の
平坦度としてより適切な指標を用いてより有用な平坦性
評価を行なうことができる。その結果、この平坦度を指
標として、この実装面の電極パッドに対して半導体装置
を実装する際の良否判定、ならびにこの実装用基板に半
導体装置を実装して得られる製品の良否判定を容易かつ
確実に行なうことができる。According to the method for evaluating flatness of an electrode pad on a mounting surface of a mounting board according to the present invention, the lowest value of the evaluation heights is formed by a plurality of electrode pads on the mounting surface. When it is determined as the flatness of the surface, the evaluation height as viewed from a virtual plane sharing the highest three electrode pads with respect to the lowest electrode pad on the mounting surface can be used as an index, and the actual mounting process can be used. Can be obtained, so that more useful flatness evaluation can be performed using a more appropriate index as the flatness of the mounting surface. As a result, using the flatness as an index, it is easy and easy to determine whether or not a semiconductor device is mounted on the electrode pad on the mounting surface and whether or not a product obtained by mounting the semiconductor device on the mounting board is good. It can be performed reliably.
【0018】なお、本発明の平坦性評価方法において、
電極パッドのうちから実装面上で分散配置されるように
n個を選択する際には、選択された電極パッドの配置が
実装面上の1箇所近傍に集中したり、片側に偏って配置
されたり、あるいは一直線状の配置されたりするような
配置を選択せず、複数の電極パッドの全体の配置に応じ
て、これに半導体装置を実装するときの実際の実装プロ
セスが反映され、平坦性評価に有効な評価高さが得られ
るように適当な分散状態となるように電極パッドを選択
する。In the flatness evaluation method of the present invention,
When selecting n of the electrode pads so as to be dispersedly arranged on the mounting surface, the arrangement of the selected electrode pads is concentrated near one location on the mounting surface or is arranged to be biased to one side. The actual mounting process when mounting the semiconductor device is reflected in the overall arrangement of the plurality of electrode pads without selecting an arrangement such that the semiconductor device is arranged in a straight line. The electrode pads are selected so as to be in an appropriate dispersed state so that an effective evaluation height can be obtained.
【0019】例えば、通常の半導体素子チップにおける
電極パッドの配列としては半導体素子チップの外辺近傍
に配置され、信号の入出力および電源の供給は外辺から
内部の能動素子領域へと引き回しがなされており、ま
た、接地を確実に行なうための接地電極パッドについて
も能動素子領域から外辺へ引き回された位置に設置され
ている。このように外辺に引き出す電極パッドの配置と
しては信号の入出力の経路として入力側と出力側は対向
した配置あるいは能動素子領域を基準に概ね直交した位
置に配置され、また、電源供給の電極パッドは信号入出
力部に干渉しない位置に配置されるものである。このた
め、半導体素子チップあるいは半導体装置の電極パッド
の配列からn個を選択するのに好適な形態としては、半
導体素子チップあるいは半導体装置の外辺を成す少なく
とも3辺の近傍に分散された配置とすることが通常であ
り、最も一般的な配置として好ましいものと言える。For example, the arrangement of electrode pads in a normal semiconductor element chip is arranged near the outer edge of the semiconductor element chip, and signal input / output and power supply are routed from the outer edge to the internal active element region. In addition, a ground electrode pad for ensuring grounding is provided at a position extended from the active element region to the outer side. As described above, the arrangement of the electrode pads extending to the outer side is such that the input side and the output side are arranged facing each other as a signal input / output path or arranged at a position substantially orthogonal to the active element region as a reference. The pads are arranged at positions that do not interfere with the signal input / output unit. For this reason, a preferred form for selecting n from the arrangement of the electrode pads of the semiconductor element chip or the semiconductor device is a dispersed arrangement in the vicinity of at least three sides forming the outer side of the semiconductor element chip or the semiconductor device. This is usually the case, and can be said to be preferable as the most general arrangement.
【0020】また、本発明の実装用基板の実装面におけ
る電極パッドの平坦性評価方法においては、各測定点に
おける平面座標と高さとの組の測定を非接触式測定にて
行なうことにより、実装面における電極パッドの状態を
変化させることなく評価を完了できるので、評価時の状
態が実装時にそのまま維持されることとなり、評価結果
を実装プロセスに反映させることができる点で好ましい
ものとなる。In the method for evaluating flatness of an electrode pad on a mounting surface of a mounting board according to the present invention, a set of plane coordinates and height at each measurement point is measured by non-contact measurement. Since the evaluation can be completed without changing the state of the electrode pads on the surface, the state at the time of evaluation is maintained as it is at the time of mounting, which is preferable in that the evaluation result can be reflected in the mounting process.
【0021】[0021]
【実施例】次に、本発明の実装用基板の実装面における
電極パッドの平坦性評価方法について、図面を参照しつ
つ具体例を詳細に説明する。Next, a method for evaluating the flatness of an electrode pad on a mounting surface of a mounting board according to the present invention will be described in detail with reference to the drawings.
【0022】〔例1〕まず、実装用基板の絶縁基板とし
て厚さ0.4mmで一辺が10mmの正方形の外形を有する
アルミナセラミック基板を用い、この基板上の実装面
に、膜厚が10μmのW/Ni/Au層から成る複数の電
極パッドを設けた。なお、実装面は一辺が2mmの正方
形状であり、電極パッドは中心座標が表1に示す位置と
なるように一辺が80μmの正方形状に形成し、概略の形
状として図1に示すようなものとした。EXAMPLE 1 First, an alumina ceramic substrate having a square outer shape of 0.4 mm in thickness and 10 mm on a side was used as an insulating substrate of a mounting substrate, and a 10 μm-thick W A plurality of electrode pads made of a / Ni / Au layer were provided. The mounting surface has a square shape with a side of 2 mm, and the electrode pad is formed in a square shape with a side of 80 μm so that the center coordinates are at the positions shown in Table 1, and has a schematic shape as shown in FIG. And
【0023】図1は本発明の平坦性評価方法が適用され
る実装用基板の例を示す平面図である。図1において、
3は実装用基板であり、4は実装用基板3の実装面に設
けられた電極パッドである。8は実装用基板3の周辺部
の実装面の外側領域に設けられた導通試験用電極パッド
であり、7の引き出し線路により電極パッド4と接続さ
れた構造となっている。FIG. 1 is a plan view showing an example of a mounting substrate to which the flatness evaluation method of the present invention is applied. In FIG.
Reference numeral 3 denotes a mounting substrate, and reference numeral 4 denotes an electrode pad provided on a mounting surface of the mounting substrate 3. Reference numeral 8 denotes a continuity test electrode pad provided in a region outside the mounting surface in the peripheral portion of the mounting substrate 3, and has a structure connected to the electrode pad 4 by a lead-out line 7.
【0024】一方、半導体装置としての半導体素子に
は、素子材料が厚さ0.1mmのGaAsであり、その下
面の略全面に導体膜を形成し、直径が60μmの金から成
る複数の突起電極を実装用基板の上面の電極パッドに対
応した位置に形成されているものを用いた。On the other hand, in a semiconductor element as a semiconductor device, the element material is GaAs having a thickness of 0.1 mm, a conductor film is formed on substantially the entire lower surface thereof, and a plurality of projecting electrodes made of gold having a diameter of 60 μm are formed. The one formed at a position corresponding to the electrode pad on the upper surface of the mounting substrate was used.
【0025】そして、この実装用基板について各電極パ
ッドの中心位置を非接触式の形状測定機により平面座標
および高さを1組として測定し、24組の3次元座標デー
タを抽出した。Then, the center position of each electrode pad of the mounting substrate was measured by a non-contact type shape measuring instrument with one set of plane coordinates and height, and 24 sets of three-dimensional coordinate data were extracted.
【0026】その後、この実装用基板に、フリップチッ
プ実装機により半導体素子を位置合わせして各突起電極
をそれぞれに対応する電極パッドに当接させ、熱および
圧力を半導体素子に印加することにより突起電極を電極
パッドに接合して半導体素子をフリップチップ実装し、
導通試験用試料を得た。Thereafter, the semiconductor elements are aligned on the mounting substrate by a flip-chip mounting machine, and the respective projecting electrodes are brought into contact with the corresponding electrode pads, and heat and pressure are applied to the semiconductor elements to thereby form the projecting electrodes. The electrodes are bonded to the electrode pads and the semiconductor element is flip-chip mounted,
A continuity test sample was obtained.
【0027】そして、この実装用基板の各電極パッドに
ついて測定した24組の3次元座標データを用いて実装面
における電極パッドの平坦性を評価した。Then, the flatness of the electrode pads on the mounting surface was evaluated using 24 sets of three-dimensional coordinate data measured for each electrode pad of the mounting substrate.
【0028】まず、本発明の平坦性評価方法の例とし
て、前述の全24組の3次元座標データにより最小二乗法
を用いて得られる平面を第1仮想平面として得た後、全
24点のうち第1仮想平面からの高さが最も低い点を除い
た残りの23点の3次元座標データにより最小二乗法を用
いて第2仮想平面を決定し、以下順次同様にして残りの
3次元座標データの数が3組になるまで仮想平面の決定
および最低点の除去の処理を繰り返し、最終的に残され
た3組のデータによって得られる第22仮想平面を決定し
た後、全24点の測定点について第22仮想平面から見た距
離を各測定点についての評価高さとして求め、表1の手
法AのA(最終)欄に示した。なお、各仮想平面をZ=
m1X+m2Y+bとして表したときの各係数m1、m
2、bも同一欄下方に示した。First, as an example of the flatness evaluation method of the present invention, a plane obtained by using the least squares method based on the above-mentioned 24 sets of three-dimensional coordinate data is obtained as a first virtual plane,
The second virtual plane is determined using the least squares method based on the three-dimensional coordinate data of the remaining 23 points excluding the point having the lowest height from the first virtual plane among the 24 points. The process of determining the virtual plane and removing the lowest point is repeated until the number of the three-dimensional coordinate data becomes three sets, and after determining the 22nd virtual plane obtained by the finally left three sets of data, all 24 The distance of the point measurement point as viewed from the 22nd virtual plane was determined as the evaluation height for each measurement point, and is shown in the A (final) column of technique A in Table 1. Note that each virtual plane is Z =
Each coefficient m1, m when expressed as m1X + m2Y + b
2 and b are also shown below the same column.
【0029】また、比較例(従来の評価方法)として、
特定の3点として実装面上の正方形状の頂点に位置する
4点のうち電極パッドNo.1、No.7、No.13を設定し、
この3点を共有する平面を仮想平面として算出し、各電
極パッドのその平面から見た高さを抽出し、表1の手法
B欄に示した。なお、この仮想平面をZ=m1X+m2
Y+bとして表したときの各係数m1、m2、bも同一
欄下方に示した。As a comparative example (conventional evaluation method),
Electrode pads No. 1, No. 7, and No. 13 are set among the four points located at the square vertex on the mounting surface as specific three points,
The plane sharing these three points was calculated as a virtual plane, and the height of each electrode pad as viewed from the plane was extracted, and is shown in the method B column of Table 1. Note that this virtual plane is represented by Z = m1X + m2
Each coefficient m1, m2, and b when represented as Y + b is also shown below the same column.
【0030】また、他の比較例(従来の他の評価方法)
として、前述の全24点の電極パッドの3次元座標データ
の組により最小二乗法を用いて得られる平面を仮想平面
として決定し、全24点の測定点をこの仮想平面から見た
高さとして求め、表1の手法C欄に示した。また、この
仮想平面をZ=m1X+m2Y+bとして表したときの
各係数m1、m2、bも同一欄下方に示した。なお、こ
の例は本発明の平坦性評価方法における評価手法の最初
の段階(手法A1)に相当する。Another comparative example (another conventional evaluation method)
As a virtual plane, a plane obtained by using the least squares method is determined from a set of three-dimensional coordinate data of the electrode pads of all 24 points described above, and the measurement points of all 24 points are defined as heights viewed from this virtual plane. And the results are shown in the column of Method C in Table 1. The coefficients m1, m2, and b when this virtual plane is represented as Z = m1X + m2Y + b are also shown below the same column. This example corresponds to the first stage (method A1) of the evaluation method in the flatness evaluation method of the present invention.
【0031】[0031]
【表1】 [Table 1]
【0032】そして、これら手法AおよびBおよびCに
より得られた実装用基板の高さデータを電極パッドNo.
1〜No.24の順に、実装領域を周回するようにして抽出
した結果を図2に線図で示す。図2において、横軸は電
極パッドNo.1を始点としてNo.1〜No.24へと周回したと
きのNo.1からの周回長(周回したときにその経路をたど
った距離を指す。単位:mm)を、縦軸は各手法により
抽出された平坦性を評価する仮想平面から見た高さ(単
位:μm)を表しており、実線は手法Aにより得られた
結果を、破線は手法Bにより得られた結果を、一点鎖線
は手法Cにより得られた結果を示している。Then, the height data of the mounting board obtained by these methods A, B and C is stored in the electrode pad No.
FIG. 2 is a diagram showing the results of extraction in the order of No. 1 to No. 24 so as to go around the mounting area. In FIG. 2, the horizontal axis represents the circumference length from No. 1 when the electrode pad No. 1 is started to No. 1 to No. 24 as a starting point (indicating the distance followed along the path when the circuit goes around. : Mm), the vertical axis represents the height (unit: μm) viewed from a virtual plane for evaluating the flatness extracted by each method, the solid line represents the result obtained by the method A, and the broken line represents the method. B indicates the result obtained by the method, and the dashed line indicates the result obtained by the method C.
【0033】図2より、手法Aでは電極パッドNo.7が
最も低くなり、手法Bでは電極パッドNo.20が最も低く
なり、手法Cでは電極パッドNo.21が最も低い電極パッ
ドとして評価されることが分かる。As shown in FIG. 2, in the method A, the electrode pad No. 7 is lowest, in the method B, the electrode pad No. 20 is lowest, and in the method C, the electrode pad No. 21 is evaluated as the lowest electrode pad. You can see that.
【0034】一方、導通試験用電極パッドを用いて各電
極パッドと突起電極との導通を確認したところ、電極パ
ッドNo.7において導通不良が生じていることが分かっ
た。On the other hand, when the continuity between each electrode pad and the protruding electrode was confirmed by using the continuity test electrode pad, it was found that a continuity defect occurred in the electrode pad No. 7.
【0035】そして、この導通不良が生じている電極パ
ッドについては、本発明の実装用基板の実装面における
電極パッドの平坦性評価方法である手法Aによって最も
低いと判定された電極パッドであり、実際の実装プロセ
スを反映した評価結果を得るに至った。The electrode pad having the conduction failure is the electrode pad determined to be the lowest by the method A for evaluating the flatness of the electrode pad on the mounting surface of the mounting board of the present invention, An evaluation result reflecting the actual mounting process was obtained.
【0036】これにより、本発明の実装用基板の実装面
における電極パッドの平坦性評価方法によれば、実際の
実装プロセスを反映した平坦性の指標である評価高さお
よび平坦度を得ることができ、実装面の電極パッドに対
して半導体装置を実装する際の良否判定、ならびにこの
実装用基板に半導体装置を実装して得られる製品の良否
判定を容易かつ確実に行なうことができることが確認で
きた。Thus, according to the method for evaluating flatness of an electrode pad on a mounting surface of a mounting board according to the present invention, it is possible to obtain an evaluation height and flatness which are indicators of flatness reflecting an actual mounting process. It can be confirmed that the quality determination when mounting the semiconductor device on the electrode pads on the mounting surface and the quality determination of the product obtained by mounting the semiconductor device on the mounting board can be performed easily and reliably. Was.
【0037】〔例2〕〔例1〕と同様の実装用基板およ
び半導体装置を200個ずつ作製し、各実装用基板を本発
明の実装用基板の実装面における電極パッドの平坦性評
価方法により平坦度を評価した後、実装用基板に、フリ
ップチップ実装機により半導体素子を位置合わせして各
突起電極をそれぞれに対応する電極パッドに当接させ、
熱および圧力を半導体素子に印加することにより突起電
極を電極パッドに接合して半導体素子をフリップチップ
実装し、導通試験用試料を得た。Example 2 The same mounting substrate and 200 semiconductor devices as those in [Example 1] were prepared, and each mounting substrate was evaluated by the method for evaluating the flatness of the electrode pads on the mounting surface of the mounting substrate of the present invention. After evaluating the flatness, the semiconductor element is aligned with the mounting substrate by a flip chip mounting machine, and each protruding electrode is brought into contact with the corresponding electrode pad,
By applying heat and pressure to the semiconductor element, the protruding electrode was bonded to the electrode pad, and the semiconductor element was flip-chip mounted, thereby obtaining a sample for a conduction test.
【0038】そして、各導通試験用試料を用いて導通試
験用電極パッドを利用して電極パッドと突起電極との導
通試験を実施した結果、14個の試料において導通不良が
発生していることが分かった。A continuity test between the electrode pads and the protruding electrodes was performed using the continuity test electrode pads using each continuity test sample. As a result, it was found that continuity failure occurred in 14 samples. Do you get it.
【0039】そして、各実装用基板の平坦度の分布とし
て図3にヒストグラムで示すような結果が得られた。こ
の結果、導通試験において接続不良となった14個の試料
は本発明の実装用基板の平坦性評価方法によって得られ
た平坦度が9μmより大きなものであることが分かり、
電極パッドの高さのばらつきに起因する接続不良の発生
と本発明により得られた評価指標とが良好に一致するこ
とが分かった。As a distribution of flatness of each mounting substrate, a result as shown by a histogram in FIG. 3 was obtained. As a result, it was found that the 14 samples having a connection failure in the continuity test had a flatness greater than 9 μm obtained by the flatness evaluation method of the mounting board of the present invention,
It has been found that the occurrence of connection failure due to the variation in the height of the electrode pad and the evaluation index obtained by the present invention are in good agreement.
【0040】これにより、本発明の実装用基板の実装面
における電極パッドの平坦性評価方法は、実際の実装プ
ロセスを反映した平坦性の評価指標を得ることができ、
実装面の電極パッドに対して半導体装置を実装する際の
良否判定、ならびにこの実装用基板に半導体装置を実装
して得られる製品の良否判定を容易かつ確実に行なうこ
とができる実装面の電極パッドに対して半導体装置を実
装する際の良否判定、ならびにこの実装用基板に半導体
装置を実装して得られる製品の良否判定を容易かつ確実
に行なうことができる評価方法であることが確認でき
た。Thus, the method for evaluating flatness of an electrode pad on the mounting surface of a mounting board according to the present invention can obtain an evaluation index of flatness reflecting an actual mounting process.
A mounting surface electrode pad that can easily and reliably determine the quality of a semiconductor device mounted on the mounting surface electrode pad and the quality of a product obtained by mounting the semiconductor device on the mounting substrate. As a result, it was confirmed that the evaluation method can easily and reliably determine whether or not the semiconductor device is mounted on the mounting substrate and whether or not the product obtained by mounting the semiconductor device on the mounting board is defective.
【0041】なお、以上はあくまで本発明の実施の形態
の例示であって、本発明はこれらに限定されるものでは
なく、本発明の要旨を逸脱しない範囲で種々の変更や改
良を加えることは何ら差し支えない。It should be noted that the above is only an example of the embodiment of the present invention, and the present invention is not limited to the embodiment. No problem.
【0042】例えば、各点の測定において、1組の3次
元座標データを抽出する際に、電極パッドの中心につい
て測定するだけでなく、その周囲を複数点測定して、そ
れらの測定値を平均したものをその電極パッドについて
の1組の3次元座標データとしてもよい。For example, when a set of three-dimensional coordinate data is extracted at each point, not only the center of the electrode pad is measured but also its surroundings are measured at a plurality of points, and the measured values are averaged. The result may be used as a set of three-dimensional coordinate data for the electrode pad.
【0043】また、例えば、実装用基板の形状として、
半導体装置を実装する際に、支持し得る3点の電極パッ
ドがある特定の電極パッドのみに存在し、他の接続用電
極パッドでは支持し得ないことが分かっているときに
は、その支持し得る複数の電極パッドについてのみ本発
明の平坦度評価方法を適用して仮想平面を抽出した後、
全ての電極パッドについてその仮想平面から見た評価高
さにより平坦性を評価するようにしてもよい。Further, for example, as the shape of the mounting substrate,
When mounting a semiconductor device, if it is known that three electrode pads that can be supported are present only on a specific electrode pad and cannot be supported by other connection electrode pads, the plurality of supportable electrode pads cannot be supported. After extracting a virtual plane by applying the flatness evaluation method of the present invention only for the electrode pads,
The flatness of all the electrode pads may be evaluated based on the evaluation height viewed from the virtual plane.
【0044】[0044]
【発明の効果】以上のように、本発明の実装用基板の実
装面における電極パッドの平坦性評価方法によれば、実
装用基板の実装面に形成された複数の電極パッドのうち
の実装面上で分散配置されるように選択したn個(ただ
し、nは4以上の整数)に設定した測定点について、3
次元座標測定系における平面座標と高さとを一組として
測定し、これらn点の測定点の平面座標と高さとから得
られるn組の3次元座標データを用いて実装面の平坦性
を評価するものであって、n組の3次元座標データから
最小二乗法を用いて得られる平面を第1仮想平面として
得て、次いでこれらn点のうち第1仮想平面からの高さ
が最も低い点を除いた(n−1)組の3次元座標データ
から最小二乗法を用いて得られる平面を第2仮想平面と
して得て、以下順次同様にして直前に得た仮想平面から
の高さが最も低い点を除いた3次元座標データが3組に
なるまで繰り返し、この3組の3次元座標データによっ
て得られる第(n−2)仮想平面を得た後、元のn点に
ついて第(n−2)仮想平面から見た距離を各測定点に
対する評価高さとして求めることから、各測定点につい
て最も高い3点の電極パッドを共有する仮想平面からみ
た評価高さをそれぞれの実装面における高さの指標とし
て用いることができるため、実際の実装プロセスを反映
した平坦性評価のための指標を得ることができ、より有
用な平坦性評価を行なうことができる。As described above, according to the method for evaluating the flatness of the electrode pads on the mounting surface of the mounting substrate according to the present invention, the mounting surface of the plurality of electrode pads formed on the mounting surface of the mounting substrate is determined. For n measurement points (where n is an integer of 4 or more) selected so as to be distributed above, 3
The plane coordinates and height in the three-dimensional coordinate measuring system are measured as a set, and the flatness of the mounting surface is evaluated using n sets of three-dimensional coordinate data obtained from the plane coordinates and the height of these n measurement points. A plane obtained from the n sets of three-dimensional coordinate data by using the least squares method as a first virtual plane, and then, of these n points, the point having the lowest height from the first virtual plane is determined. A plane obtained by using the least squares method from the (n-1) sets of the three-dimensional coordinate data that have been removed is obtained as a second virtual plane, and in the same manner as described above, the height from the virtual plane obtained immediately before is the lowest. The process is repeated until three sets of three-dimensional coordinate data excluding points are obtained. After obtaining the (n-2) th virtual plane obtained by the three sets of three-dimensional coordinate data, the (n-2) th virtual plane is obtained for the original n points. ) The distance viewed from the virtual plane is the evaluation height for each measurement point. From the virtual plane sharing the three highest electrode pads for each measurement point, it is possible to use the evaluation height as an index of the height on each mounting surface, thus reflecting the actual mounting process. An index for flatness evaluation can be obtained, and more useful flatness evaluation can be performed.
【0045】その結果、実際の実装プロセスを反映した
平坦性を評価し、また平坦度を求めることが可能とな
り、この実装面の電極パッドに対して半導体装置を実装
する際の良否判定、ならびにこの実装用基板に半導体装
置を実装して得られる製品の良否判定を容易かつ確実に
行なうことができる。As a result, it is possible to evaluate the flatness reflecting the actual mounting process and obtain the flatness, and to judge whether or not the semiconductor device is mounted on the electrode pad on the mounting surface, The quality of a product obtained by mounting a semiconductor device on a mounting substrate can be easily and reliably determined.
【0046】また、本発明の実装用基板の実装面におけ
る電極パッドの平坦性評価方法によれば、評価高さのう
ちの最も低い高さの値を実装面の複数の電極パッドによ
り形成される面の平坦度として求める場合には、実装面
において最も低い電極パッドに対する、最も高い3点の
電極パッドを共有する仮想平面から見た高さをその指標
として用いることができ、実際の実装プロセスを反映し
た平坦度の指標を得ることができるため、実装面の平坦
度としてより適切な指標を用いてより有用な平坦性評価
を行なうことができる。その結果、この平坦度を指標と
して、この実装面の電極パッドに対して半導体装置を実
装する際の良否判定、ならびにこの実装用基板に半導体
装置を実装して得られる製品の良否判定を容易かつ確実
に行なうことができる。According to the method for evaluating flatness of an electrode pad on a mounting surface of a mounting board according to the present invention, the lowest value of the evaluation heights is formed by a plurality of electrode pads on the mounting surface. In the case of obtaining the flatness of the surface, the height as viewed from a virtual plane sharing the highest three electrode pads with respect to the lowest electrode pad on the mounting surface can be used as an index, and the actual mounting process can be reduced. Since the reflected flatness index can be obtained, more useful flatness evaluation can be performed using a more appropriate index as the flatness of the mounting surface. As a result, using the flatness as an index, it is easy and easy to determine whether or not a semiconductor device is mounted on the electrode pad on the mounting surface and whether or not a product obtained by mounting the semiconductor device on the mounting board is good. It can be performed reliably.
【0047】以上により、本発明によれば、実装用基板
の実装面について実際の実装プロセスを反映した平坦性
の指標を求めることができ、この実装面の電極パッドに
対して半導体装置を実装する際の良否判定、ならびにこ
の実装用基板に半導体装置を実装して得られる製品の良
否判定を容易かつ確実に行なうことができる実装用基板
の実装面における電極パッドの平坦性評価方法を提供す
ることができた。As described above, according to the present invention, it is possible to obtain an index of flatness reflecting the actual mounting process on the mounting surface of the mounting substrate, and mount the semiconductor device on the electrode pads on this mounting surface. To provide a method for evaluating the flatness of an electrode pad on a mounting surface of a mounting board, which can easily and surely determine the quality of the product at the time of mounting and the quality of a product obtained by mounting a semiconductor device on the mounting board. Was completed.
【図1】本発明の平坦性評価方法が適用される実装用基
板の一例を示す平面図である。FIG. 1 is a plan view showing an example of a mounting board to which a flatness evaluation method of the present invention is applied.
【図2】本発明の実装用基板の平坦性評価方法および従
来の実装用基板の平坦性評価方法により得られた実装用
基板の実装面における電極パッドの平坦性の評価結果の
比較を示す線図である。FIG. 2 is a line showing a comparison of the evaluation results of the flatness of the electrode pads on the mounting surface of the mounting substrate obtained by the mounting substrate flatness evaluation method of the present invention and the conventional mounting substrate flatness evaluation method. FIG.
【図3】本発明の実装用基板の平坦性評価方法により得
られた実装用基板の平坦度の分布を示すヒストグラムで
ある。FIG. 3 is a histogram showing a distribution of flatness of a mounting board obtained by a method for evaluating flatness of a mounting board of the present invention.
【図4】(a)および(b)は、それぞれ半導体素子の
フリップチップ実装の工程を説明するための側面図であ
る。FIGS. 4A and 4B are side views for explaining a step of flip-chip mounting a semiconductor element.
1・・・・・・半導体装置 2・・・・・・突起電極 3・・・・・・実装用基板 4・・・・・・電極パッド DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 2 ... Protruding electrode 3 ... Mounting substrate 4 ... Electrode pad
Claims (2)
導体装置の突起電極が接続される複数の電極パッドを有
する実装用基板に対し、前記電極パッドのうちの前記実
装面上で分散配置されるように選択したn個(ただし、
nは4以上の整数)に設定した測定点について3次元座
標測定系における平面座標と高さとを一組として測定
し、それにより得られるn組の3次元座標データから最
小二乗法を用いて得られる平面を第1仮想平面として得
て、次いで前記n点のうち前記第1仮想平面からの高さ
が最も低い点を除いた(n−1)組の3次元座標データ
から最小二乗法を用いて得られる平面を第2仮想平面と
して得て、以下順次同様にして直前に得た仮想平面から
の高さが最も低い点を除いた3次元座標データが3組に
なるまで繰り返し、該3組の3次元座標データによって
得られる第(n−2)仮想平面を得た後、前記n点につ
いて前記第(n−2)仮想平面から見た距離を評価高さ
として求めることを特徴とする実装用基板の実装面にお
ける電極パッドの平坦性評価方法。1. A mounting substrate having a plurality of electrode pads on a mounting surface on which a semiconductor device is mounted and to which protruding electrodes of the semiconductor device are connected, the plurality of electrode pads being distributed on the mounting surface of the electrode pads. Selected n (however,
(n is an integer of 4 or more) is measured as a set of the plane coordinates and the height in the three-dimensional coordinate measurement system for the measurement point set to (4) or more, and is obtained from the n sets of three-dimensional coordinate data obtained using the least squares method. Is obtained as a first virtual plane, and then the least squares method is used from (n-1) sets of three-dimensional coordinate data excluding the point having the lowest height from the first virtual plane among the n points. The obtained plane is obtained as a second virtual plane, and the same procedure is sequentially repeated until three sets of three-dimensional coordinate data excluding the point having the lowest height from the immediately preceding virtual plane are obtained. After obtaining the (n-2) th virtual plane obtained by the three-dimensional coordinate data of the above, the distance from the (n-2) th virtual plane to the n point is obtained as an evaluation height. Of the electrode pads on the mounting surface of the Gender evaluation method.
て、前記評価高さのうちの最も低い高さの値を前記複数
の電極パッドにより形成される面の平坦度とすることを
特徴とする実装用基板の実装面における電極パッドの平
坦性評価方法。2. The flatness evaluation method according to claim 1, wherein a value of a lowest height among the evaluation heights is a flatness of a surface formed by the plurality of electrode pads. A method for evaluating flatness of an electrode pad on a mounting surface of a mounting substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000384400A JP2002185103A (en) | 2000-12-18 | 2000-12-18 | Method for evaluating flatness of electrode pads on mounting surface of mounting substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000384400A JP2002185103A (en) | 2000-12-18 | 2000-12-18 | Method for evaluating flatness of electrode pads on mounting surface of mounting substrate |
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Publication Number | Publication Date |
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JP2002185103A true JP2002185103A (en) | 2002-06-28 |
Family
ID=18851866
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007121183A (en) * | 2005-10-31 | 2007-05-17 | Hioki Ee Corp | Circuit board inspection equipment |
KR101046871B1 (en) * | 2003-10-31 | 2011-07-05 | 에스펙 가부시키가이샤 | Mounting member of semiconductor device, package of semiconductor device, and driving device of semiconductor device |
CN102445174A (en) * | 2011-10-14 | 2012-05-09 | 华南理工大学 | Multipoint flatness assessment method based on support vector regression |
CN102506805A (en) * | 2011-10-14 | 2012-06-20 | 华南理工大学 | Multi-measuring-point planeness evaluation method based on support vector classification |
WO2016208019A1 (en) * | 2015-06-24 | 2016-12-29 | 富士機械製造株式会社 | Substrate inspecting apparatus |
-
2000
- 2000-12-18 JP JP2000384400A patent/JP2002185103A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101046871B1 (en) * | 2003-10-31 | 2011-07-05 | 에스펙 가부시키가이샤 | Mounting member of semiconductor device, package of semiconductor device, and driving device of semiconductor device |
JP2007121183A (en) * | 2005-10-31 | 2007-05-17 | Hioki Ee Corp | Circuit board inspection equipment |
CN102445174A (en) * | 2011-10-14 | 2012-05-09 | 华南理工大学 | Multipoint flatness assessment method based on support vector regression |
CN102506805A (en) * | 2011-10-14 | 2012-06-20 | 华南理工大学 | Multi-measuring-point planeness evaluation method based on support vector classification |
WO2016208019A1 (en) * | 2015-06-24 | 2016-12-29 | 富士機械製造株式会社 | Substrate inspecting apparatus |
JPWO2016208019A1 (en) * | 2015-06-24 | 2018-04-19 | 富士機械製造株式会社 | Board inspection machine |
US10551181B2 (en) | 2015-06-24 | 2020-02-04 | Fuji Corporation | Board inspection machine |
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