JP2002169501A - Impedance converter and driving device for display device provided therewith - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an impedance converter capable of surely reducing the power consumption without the need for a special external signal from the outside, and a driving device for a display device provided therewith. SOLUTION: The impedance converter is provided with differential amplifier circuits 11 and 12, which are connected in parallel and perform an impedance conversion to a voltage varying according to the gradation display data 905 and supplies electric power for operation and activates one of the differential amplifiers circuit 11, 12 and also inactivate the other one without supplying the operation power based on the differential amplifiers 11, 12, based on the above gradation display data 905.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an impedance conversion device which is employed in an output circuit of a drive device for driving a display device such as a liquid crystal panel and reduces power consumption, and a drive device for a display device having the same. Things.

[0002]

2. Description of the Related Art As a conventional technique for realizing low power consumption of an output circuit using a differential amplifier circuit, for example, Japanese Patent Laid-Open No.
No. 0736 (hereinafter, referred to as a first prior art).
There is known a liquid crystal display drive power supply circuit (hereinafter referred to as a second prior art) for stopping an operational amplifier disclosed in Japanese Patent Application Laid-Open Publication No. H11-163,036.

[0003] The first prior art disclosed in Japanese Patent Application Laid-Open No. 5-150736 will be described with reference to FIGS.

In FIG. 11, an operational amplifier 101 has an input stage constituted by P-channel MOS transistors.

As shown in FIG. 12, an operational amplifier 101 has a P-channel MOS transistor 110 as an input stage.
6 and 1107 are constituted by differential pairs. The constant voltage VBP is supplied to the gate of the P-channel MOS transistor 1103, whereby a constant current I flows through the P-channel MOS transistor 1103. This constant current I
Is to determine an operating point for the differential pair to perform distortion-free amplification. In a current mirror circuit constituted by N-channel MOS transistors 1108 and 1109, constant current I is divided into current Ia and current Ib.

In the circuit having the above configuration, the input terminal 110
1 and the output voltage Vo of the output terminal 1102.
If the relationship of ut satisfies Vin <Vout, Ia> I
As a result, the potential at the point A decreases and the N-channel MOS transistors 1108 and 1109 turn off. As a result, the potential at the point B rises and the N-channel MO
The direction in which the S transistor 1121 is turned on is turned on, the current flowing through the N-channel MOS transistor 1121 increases, and the output voltage Vout decreases. Thus, V
The state transits to the state of in = Vout.

On the other hand, if the relationship between the input voltage Vin at the input terminal 1101 and the output voltage Vout at the output terminal 1102 is Vin> Vout, then Ia <Ib, the potential at point A rises, and the N-channel MOS transistor 110
8.11109 is turned on. As a result, point B
Of the N channel MOS transistor 11
21 turns off, and the current flowing through the N-channel MOS transistor 1121 decreases. At this time,
The P-channel MOS transistor 1105 includes a P-channel MOS transistor 1104 and an N-channel M
Since a constant current flows based on the relationship with the OS transistor 1120, the output voltage Vout increases as a result. Thus, the state transits to Vin = Vout.

As described above, a voltage equal to the input voltage is output due to the current balance between the currents Ia and Ib flowing through the current mirror circuit. However, the currents Ia and Ib
Is a current flowing through the P-channel MOS transistor, so that when the input voltage (gate voltage) and the power supply voltage (Vdd in this case) approach, a voltage level region where the current cannot flow occurs. Therefore, in the circuit shown in FIG. 12, a voltage (offset) occurs in which the output does not follow the input voltage close to the power supply.

Here, the circuit configuration of the operational amplifier 102 will be described below with reference to FIG. As shown in FIG. 13, the input stage of the operational amplifier 102 is configured by a differential pair of N-channel MOS transistors 1206 and 1207. The constant voltage VBN is supplied to the gate of the N-channel MOS transistor 1203, so that the constant current I
It flows to 03. The constant current I is for determining an operating point for performing distortion-free amplification. In a current mirror circuit composed of P-channel MOS transistors 1208 and 1209, current Ia and current Ib
Flows into the N-channel MOS transistor 1203 as the constant current I.

In the circuit having the above configuration, the input terminal 120
1 and the output voltage Vo of the output terminal 1202.
If the relationship of ut satisfies Vin <Vout, Ib> I
a, the potential at the point C decreases, and the P-channel MOS transistors 1208 and 1209 turn on. As a result, the potential at the point D rises and the P-channel MO
The direction is such that the S transistor 1221 turns off. At this time, N channel MOS transistor 1205 has N
Since a constant current flows based on the relationship between the channel MOS transistor 1204 and the P-channel MOS transistor 1220, the output voltage Vout decreases as a result. Thus, the state transits to Vin = Vout.

On the other hand, if the relationship between the input voltage Vin at the input terminal 1201 and the output voltage Vout at the output terminal 1202 is Vin> Vout, Ib <Ia, the potential at the point C rises, and the P-channel MOS transistor 120
8.1209 turns off. As a result, point D
Of the P-channel MOS transistor 12
21 is turned on, so that the output voltage Vout increases. Thus, the state transits to Vin = Vout.

As described above, the operational amplifier 102 is configured as shown in FIG.
Unlike the configuration of FIG. 2, the control is performed by the current flowing through the N-channel MOS transistors 1206 and 1207 forming the differential pair of the input stage. Therefore, contrary to the case of FIG. 12, a voltage (offset) occurs in which the output does not follow the input voltage close to the GND (ground) side.

When attempting to create an impedance conversion circuit corresponding to all voltages from the GND level to the power supply voltage level, as described above, only one of the operational amplifier 101 and the operational amplifier 102 cannot cope with it. For this reason, as shown in FIG. 11, by combining the circuits of the operational amplifier 101 and the operational amplifier 102 (connected in parallel with each other), a voltage that cannot be output is mutually compensated, and a circuit that does not generate an offset is realized.

Here, with reference to FIG.
A conventional technique (Japanese Patent Application Laid-Open No. H8-313867) will be described.

The circuit shown in FIG. 14 is also used as an output circuit for driving a capacitive load. Using FIG. 14A or FIG. 14B, an impedance conversion circuit as shown in FIG. 14C is created to charge the capacitive load of the liquid crystal panel. After charging is completed, a signal is input to the OFF terminal to prevent a bias current from flowing, thereby reducing current consumption. This relationship is shown in FIG.

At time a, since the OFF terminal is at H (high level) and the / OFF terminal is at L (low level), the N-channel MOS transistors 32 and 34 and the P-channel MOS transistors 31 and 33 are all turned on. Current does not flow through the amplifier section including the bias current.

At time b, the level of the OFF terminal is inverted,
All of the MOS transistors are turned off, and a current flows to the amplifier section so that normal operation can be performed. When the input signal changes at time c, the output changes as well, charging the capacitive load. After the capacity is sufficiently charged, the OFF terminal is inverted again to stop the bias current, so that no current flows to the amplifier section (time d). The suspension of these bias currents is performed simultaneously for the related differential amplifier circuits. The same operation is performed at the time of discharging the capacity (time e, f,
g).

As described above, it is possible to reduce power consumption by setting the output to high impedance after charging the capacitor and stopping the bias current.

[0019]

However, the first and second prior arts have the following problems, respectively.

That is, in the first prior art, since two differential amplifier circuits are always operating, twice the current is consumed as compared with the case of driving by one differential amplifier circuit. become.

Further, in the above-mentioned second prior art in which the bias current of the differential amplifier circuit is stopped to reduce the drive current, a stop command (stop signal) from outside the circuit is required, and all output terminals are connected. After charging the capacitive load connected to the output, these bias currents are stopped all at once. Therefore, the effect of reducing power consumption is reduced.

[0022]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, an impedance converter according to the present invention comprises first and second impedance converters which are connected in parallel to each other and perform impedance conversion on a voltage that changes according to digital input data. A second differential amplifying circuit for supplying operating power based on the digital input data to bring one of the first and second differential amplifying circuits into an operating state, and supplying the operating power to the other without supplying operating power; And control means for controlling the inactive state.

According to the above-described invention, the first and second differential amplifier circuits connected in parallel to each other perform impedance conversion on a voltage that changes according to digital input data.

At the time of the impedance conversion, conventionally,
Since one differential amplifier circuit is always operating,
As compared with the case of driving by two differential amplifier circuits, twice the current was consumed. Conventionally, even when the drive current of the differential amplifier circuit is reduced, a stop signal from the outside of the differential amplifier circuit is required, and all the output terminals are simultaneously charged after the capacitive load connected to the output is charged. Therefore, the effect of reducing the power consumption is small.

Therefore, according to the present invention, control means is provided, and by this control means, based on the digital input data, one of the first and second differential amplifier circuits has an operating power supply. While being supplied and operating,
The other is controlled so that the operation power is not supplied and the operation is not performed.

As a result, only one of the first and second differential amplifier circuits is always in the operating state. In other words, one of the first and second differential amplifier circuits is always in a non-operating state, and no current is consumed in this differential amplifier circuit (at the same time, both the first and second differential amplifier circuits are not operated). Current does not flow through.) Therefore, it is possible to reduce the current consumption of the impedance conversion device to half of the above-mentioned conventional one.

If both of the two differential amplifier circuits are operating at the same time, when the voltage of the operating power supply is as high as several tens of volts, a current may flow between the two differential amplifier circuits. According to the above-described invention, only one of the differential amplifier circuits is in the operating state, so that such a disadvantage can be surely overcome.

In addition, since the above-mentioned control by the control means is performed based on digital input data which is a basis of a voltage to be subjected to impedance conversion, a signal (stop command) from outside the impedance conversion device is not separately required. .
In addition, since the transition to the non-operation state is not performed all at once but based on digital input data, the effect of reducing power consumption can be surely increased.

Preferably, the control means performs the control based on the most significant bit of the digital input data. In this case, in the voltage range in which the offset occurs, the corresponding differential amplifier circuit can be made inoperative, so that
It is possible to significantly improve the reliability.

In order to solve the above problem, another impedance conversion device according to the present invention is connected in parallel with each other, and performs first and second differential conversions on a voltage that changes according to digital input data. An amplification circuit;
Decoding means for decoding the upper two bits of the digital input data; and
A control is performed such that an operating power is supplied so that one of the first and second differential amplifier circuits is in an operating state and the other is not in operation without supplying the operating power.
And control means for supplying an operating power to both the second differential amplifier circuit and controlling the second differential amplifier circuit to be in an operating state.

According to the above invention, the first and second differential amplifier circuits connected in parallel to each other perform impedance conversion on a voltage that changes according to digital input data.

In the above invention, decoding means for decoding the upper two bits of the digital input data is provided, and based on the output of the decoding means, the control means controls the first data based on the digital input data.
One of the second differential amplifier circuit and the second differential amplifier circuit is controlled to be in an operation state when supplied with operation power, and the other is controlled so as not to be supplied with operation power and to be in an inoperative state, or Operation power is supplied to both of the second differential amplifier circuits, and control is performed so that both are in an operation state.

In the above control, in the former case, as described above, the current consumption of the impedance conversion device can be suppressed to half of that in the conventional case. On the other hand, in the case of the latter control, by operating both the first and second differential amplifier circuits, it is possible to reliably increase the output driving capability of the impedance conversion device.

In addition, since the above-mentioned control by the control means is performed based on digital input data which is the basis of a voltage to be subjected to impedance conversion, a signal from outside the impedance conversion device is not required separately. In addition, since the transition to the non-operation state is not performed all at once, the effect of reducing power consumption can be surely increased.

Further, in a voltage range in which an offset occurs, the corresponding differential amplifier circuit can be made inoperative, thereby significantly improving the reliability.
By operating both the first and second differential amplifier circuits in a voltage range in which no offset occurs in both differential amplifier circuits, it is possible to reliably increase the output drive capability of the impedance conversion device.

Incidentally, it is preferable that the output of the differential amplifier circuit in a non-operating state has a high impedance.
In this case, the output of the differential amplifier circuit to which no operating power is supplied is controlled to high impedance by the control means, so that the operation of the differential amplifier circuit in the operating state is not hindered. Therefore, the reliability of the impedance conversion device can be significantly improved.

The digital input data is gray scale display data, and indicates that an analog gray scale display voltage selected according to the gray scale display data is impedance-converted by the impedance converter. Preferably, it is a drive for the device. In this case, by amplifying the gradation display voltage, the level shifter circuit conventionally required becomes unnecessary, and the circuit can be reduced.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. 1 to 4 and FIGS.

As an example of a system configuration using the present invention, FIG. 8 is a schematic diagram showing a case where a liquid crystal driver (liquid crystal driving device) for driving a liquid crystal panel using a TFT (Thin Film Transistor) is used.

The liquid crystal panel has liquid crystal pixels 809 and TFTs 808 arranged in a matrix, and the TFTs are connected to a source line 807, a gate line 806, and the liquid crystal pixels 809. The gate line 806 is sequentially driven by a liquid crystal driver (gate driver side) 802 to turn on the gate of the TFT 808 and to turn on the source line 80.
7 for transmitting the gradation display voltage to the liquid crystal pixels.

The source line 807 is driven by a liquid crystal driver (source driver side) 801. The output voltage of the liquid crystal driver (source driver side) 801 functions to adjust the amount of light transmitted by the liquid crystal pixels, thereby performing gradation display. LCD driver (source driver side)
To 801, gradation display data 905 is input.

FIG. 9 shows a liquid crystal driver (source driver side).
801 indicates the capture of digital gradation display data 905 (hereinafter simply referred to as gradation display data 905). As the gradation display data 905 (for example, 6-bit data in the case of 64 gradation display), one line of the liquid crystal panel is input as serial data. The grayscale display data 905 input in this manner is the driving clock 8
The data is sampled by the data sampling circuit 906 by the data clock circuit 04 and sent to the internal data bus 907 in synchronization with the drive clock 804.

On the other hand, the shift register 902 is operated by the drive clock 804, and the start pulse 803
Are transmitted, the signals (SD1, SD2, SD3, SD
4, SD5,...). The head of the data is indicated by a start pulse 803.

The gradation display data 905 sent out to the internal data bus 907 includes signals (SD1, SD2, SD
, SD4, SD5,...) And the hold memory circuit 9
08 _1, 908 _2, 908 _3, 908 _4, 908 _5, ...
And latched for one horizontal scanning period. These signals are supplied to the hold memory circuits 908 ₁ , 9
After level conversion in each level shifter circuit (not shown) in 08 ₂ , 908 ₃ , 908 ₄ , 908 ₅ ,..., Hold memory circuits 908 ₁ , 908 ₂ , 90
In each of the DA conversion circuits (not shown) in 8 ₃ , 908 ₄ , 908 ₅ ,..., A gradation display voltage corresponding to the gradation display data 905 is selected from the output voltage from the reference voltage generation circuit 930. Output.

The output circuit (first output circuit 91)
0 ₁ , second output circuit 910 ₂ , third output circuit 910 ₃ ,
After the impedance conversion (described later) of the fourth output circuit 910 ₄ , the fifth output circuit 910 ₅ ,...), The source line 807 ₁ , source line 807 ₂ , source line 807 ₃ , source line 807 ₄ , Are output to the source lines 807 ₅ ,.

Gate lines (GA1, G2) in the liquid crystal panel
A2, GA3, ...), the liquid crystal driver (driven by the gate driver side) 802, a source line 807 (807 ₁ to a line of the liquid crystal pixel of interest, 807 _2, 807
₃ ,…)). Since the output timing of the liquid crystal driver (source driver side) 801 and the drive timing of the gate line are not directly related to the present invention, the description is omitted.

FIG. 10 shows the relationship of data fetching from the internal data bus 907. The start pulse 803 is sampled at the falling edge of the drive clock 804, and when the start pulse 803 becomes H, the internal data bus 90
Reference numeral 7 denotes gradation display data 90 from the falling edge of the next drive clock 804 sampled from the start pulse 803.
5 is started.

On the other hand, the sampled start pulse 803 starts the shift register 902 and sequentially sends the H signal in synchronization with the rise of the driving clock 804 to generate signals SD1, SD2, SD3, SD4, SD5,
... is generated. The signal SDx is determined by the number of outputs of the liquid crystal driver.

For example, when data of three pixels of RGB are simultaneously taken in with 240 outputs, a triple shift register of 80 stages is required, and x of the signal SDx needs to be 1 to 80. Each of the signals SDx is connected to the hold memory circuit and holds data immediately before the signal changes from H to L.

In FIG. 10, when the signal SD1 changes from H to L, the signal on the internal data bus 907 is "1" (high level), so that the first output data is "1".
Is held.

Similarly, signals SD2, SD3, SD4, S
Data corresponding to D5,... Are sequentially taken into the output. With this operation, each hold memory circuit takes in data indicating the gray scale voltage to be output and holds the data for one horizontal scanning period of the display panel. The present invention realizes low power consumption of the output circuit by using the held data.Specific implementation methods, such as a data input method and a drive target of the output circuit, are merely examples, and particularly It is not limited.

FIG. 1 shows an example of the configuration of an impedance conversion circuit according to an embodiment of the present invention. This circuit is an output circuit (first output circuit 910 ₁ , first output circuit 910 ₁₎ for performing the impedance conversion described in FIG. Two output circuit 910 ₂ , third output circuit 910 ₃ , fourth output circuit 910 ₄ , fifth output circuit 9
10 ₅ ,...).

The operational amplifier (differential amplifier circuit) 11 is a differential pair of input stages composed of P-channel MOS transistors. When the signal DIS becomes H (high level), the operational amplifier (differential amplifier circuit) 11 is operated. (Circuit) Turns off the current flowing inside the circuit 11 to bring the output into a high impedance state.

The operational amplifier (differential amplifying circuit) 12 is an N-channel MOS transistor forming an input stage differential pair. When the signal DIS becomes L, the operational amplifier (differential amplifying circuit) 12 The current flowing inside is turned off, and the output is set to a high impedance state.

Operational amplifiers (differential amplifier circuits) 11 and 12
The control of turning off the current flowing inside and setting the output to the high impedance state is performed by a signal DIS. The signal DIS is generated by the gradation display data 905 as described later.
Generated from

FIG. 2 is a circuit diagram showing a specific circuit configuration example of an operational amplifier (differential amplifier circuit) 11 in which a differential pair at the input stage is formed by P-channel MOS transistors. FIG. 3 is a circuit diagram showing a specific circuit configuration example of an operational amplifier (differential amplifier circuit) 12 in which an input stage differential pair is formed by N-channel MOS transistors.

Since these circuit configurations are basically the same as those of FIGS. 12 and 13 described above, the description of the overlapping portions will be omitted.

FIG. 1 (an operational amplifier (differential amplifier circuit) in which a differential pair at the input stage is constituted by P-channel MOS transistors)
11) in the operational amplifier 101 of FIG.
Between the power supply voltage Vdd (operating power supply) and the P-channel MOS transistors 1103 and 1104, a P-channel M
The points where the OS transistors 201 and 202 are provided, the point where the P-channel MOS transistor 203 is provided between the power supply voltage Vdd and the gate of the P-channel MOS transistor 1105, and the point where the N-channel M
Between the gate of the OS transistor 1121 and GND,
In that the N-channel MOS transistor 204 is provided,
This is different from FIG.

According to the above configuration, the signal DIS becomes H (Vd
In the case of (d level), the signal DISN is L (GND level) because it is an inverted signal of the signal DIS. Accordingly, P-channel MOS transistors 201 and 202
Is turned off. Therefore, a circuit current including a bias current that determines an operating point does not flow through the operational amplifier (differential amplifier circuit) 11 (is cut off).

Furthermore, since both P-channel MOS transistor 203 and N-channel MOS transistor 204 provided in the output stage are turned on, P-channel MOS transistor 1105 constituting the output stage
And the N-channel MOS transistor 1121 are both turned off. As a result, the output of the operational amplifier (differential amplifier circuit) 11 becomes in a high impedance state, and the current flowing through the output stage is cut off.

On the other hand, when the signal DIS is at L (GND level), the power supply voltage Vdd is applied to the P-channel MO transistor via the P-channel MOS transistors 201 and 202.
Since they are supplied to the S transistors 1103 and 1104, respectively, the P-channel MOS transistor 203 and the N-channel MOS transistor 204 are both turned off, so that they are equivalent to the circuit shown in FIG. Is performed. The operation is not described here because it is the same as that described above.

FIG. 3 (an operational amplifier (differential amplifier circuit) in which an input-stage differential pair is formed by N-channel MOS transistors)
12), in FIG. 13, N is connected between GND and N-channel MOS transistors 1203 and 1204.
Channel MOS transistors 301 and 302 are provided, respectively, and a P-channel MO of an output stage is provided.
A P-channel MOS transistor 304 is provided between the gate of the S transistor 1221 and the power supply voltage Vdd, and an N-channel MOS transistor 303 is inserted between the gate of the N-channel MOS transistor 1205 and GND. Is different.

According to the above configuration, the signal DIS becomes L (GN
In the case of (D level), the signal DISN is H (Vdd level) because it is an inverted signal of the signal DIS. Accordingly, N-channel MOS transistors 301 and 302
Is turned off, the operational amplifier (differential amplifier circuit) 1
No circuit current including a bias current that determines an operating point flows through 2 and is cut off.

At this time, the N-channel MOS transistor 303 and the P-channel MOS transistor 304 provided in the output stage are both turned on, so that the N-channel MOS transistor 1205 constituting the output stage
And the P-channel MOS transistor 1221 are both turned off. As a result, the output of the operational amplifier (differential amplifier circuit) 12 becomes in a high impedance state, and the current flowing through the output stage is cut off.

On the other hand, when the signal DIS is H (Vdd level), the P-channel MOS transistor 301
And 302 via a P-channel MOS transistor 1
203 and 1204 are connected to GND, respectively, and both the N-channel MOS transistor 303 and the P-channel MOS transistor 304 are turned off. Therefore, the circuit is equivalent to the circuit shown in FIG. Is performed. The operation is not described here because it is the same as that described above.

As described above, when the signal DIS is at L level, the operational amplifier (differential amplifier circuit) 12 forming the differential pair of the input stage by N-channel MOS transistors stops operating, while the input stage by P-channel MOS transistors is stopped. The operational amplifier (differential amplifier circuit) 11 constituting the differential pair operates. N-channel MOS stopped operation
Since the output stage of the operational amplifier (differential amplifier circuit) 12 in which a differential pair of input stages is formed by transistors is in a high-impedance state, the operation of the operational amplifier (differential amplifier circuit) 11 is not hindered. This makes it possible to provide a highly reliable impedance conversion device.

On the other hand, when the signal DIS is H, the operational amplifier (differential amplifier circuit) 11 which forms a differential pair of the input stage by the P-channel MOS transistor stops operating, and the input stage of the input stage is N-channel MOS transistor. The operational amplifier (differential amplifier circuit) 12 forming the differential pair operates. Also in this case, since the output stage of the operational amplifier (differential amplifier circuit) 11 whose operation is stopped is in a high impedance state, the operation of the operational amplifier (differential amplifier circuit) 12 is not hindered. This makes it possible to provide a highly reliable impedance conversion device.

As the signal DIS, for example, the most significant bit of the gradation display data 905 (for example, 6 bits) input to the DA conversion circuit added to each output circuit (installed for each output terminal) Bit (MSB).

The gradation display data 905 at this stage has been level-converted through the level shifter circuit.
The signal has a potential between the Vdd-GND level. Table 1 shows the relationship between the gradation (0 to 63), the gradation display data (6 bits), and the signal DIS (MSB of the gradation display data 905), taking the case of 64 gradation display as an example. As shown in Table 1, when the gradation is 0 to 31, the signal DIS is low.
(Low level, “0”), while the signal DIS becomes H (high level, “1”) when the gradation is 32 to 63.

[0070]

[Table 1]

As described above, since the signal DIS uses the most significant bit (MSB), the gray scale display data 90
5 is L (low level, “0”) when 00H to 1FH (hexadecimal notation), and H (high level, 20H to 3FH).
"1"). Therefore, when the gradation display data 905 is 00H to 1FH, the operational amplifier (differential amplifier circuit) 11
Operate, and the operational amplifier (differential amplifier circuit) 12 does not operate. When the gradation display data 905 is 20H to 3FH, the operational amplifier (differential amplifier circuit) 11 stops operating, and
An operational amplifier (differential amplifier circuit) 12 operates. The operational amplifiers (differential amplifier circuits) 11 and 12 are connected as shown in FIG. 1, and the liquid crystal driving output voltage for the gray scale display data 905 of 00H is the lowest voltage, and the gray scale display data 905 is 3
FIG. 4 shows a case where the liquid crystal driving output voltage with respect to FH is set to the highest voltage.

Here, another embodiment of the present invention will be described below with reference to FIG. Note that members having the same functions as those in FIG.
Detailed description is omitted.

In FIG. 5, an operational amplifier (differential amplifier circuit) 11 and an operational amplifier (differential amplifier circuit) 12 are the same as those in FIG. 1 and have the same connection. The difference is that a decoder 45 for generating a signal for controlling the stop of the operation of the operational amplifier (differential amplifier circuit) based on the display data 905 is further provided. In FIG. 5, the signal DISP from the decoder 45 is input instead of the signal DIS of FIG. 2, and the signal DISN from the decoder 45 is input instead of the signal DIS of FIG.

FIG. 6 shows an example of the circuit configuration of the decoder 45.
In this embodiment, the upper two bits (when the number of bits is six) of the grayscale display data 905 input to a DA conversion circuit (not shown) provided for each output terminal
This is an example using bit 5 and bit 4).

In this case, the decoder 45 comprises an OR circuit 45a and an AND circuit 45b, as shown in FIG. One input terminal of the OR circuit 45a has
Bit 5 of the gradation display data 905 is input, and one input terminal of the AND circuit 45b is connected.
The other input terminal of the OR circuit 45a receives the bit 4 of the gradation display data 905 and the other input terminal of the AND circuit 45b. The output of the OR circuit 45a is sent to the operational amplifier (differential amplifier) 12 as a signal DISN, while the output of the AND circuit 45b is sent to the operational amplifier (differential amplifier) as a signal DISP.
11 is sent.

According to the decoder 45 having the above-described configuration, when both the bit 5 and the bit 4 are H (high level, “1”) in the gradation display data 905, the signal DISP becomes H.
(High level, “1”) while bit 5 or bit 4 is L (low level, “0”), the signal DIS
P becomes L (low level, “0”).

On the other hand, in gradation display data 905, at least one of bit 5 and bit 4 is H
In the case of (high level, “1”), the signal DISN becomes H (high level, “1”), and when both the bit 5 and the bit 4 are L (high level, “0”), the signal DISN
Becomes L (low level, “0”).

Taking the case of 64 gradation display as an example, gradation (0 to 6)
3), gradation display data 905 (6 bits), and signal D
Table 2 shows the relationship between ISP and DISN.

[0079]

[Table 2]

The circuit shown in FIG. 6 uses the upper two bits (bit 5 and bit 4) of the gradation display data 905 to convert the signal DISP to the gradation display data 905 between 00H and 2F.
L at H, H at 30H to 3FH, and signal D
The ISN is set to L when the gradation display data 905 is 00H to 0FH and H when the gradation display data 905 is 10H to 3FH.

In other words, an operational amplifier (differential amplifier circuit)
11 is 00H to 2F because the signal DISP stops at H.
It operates at H and stops at 30H-3FH. The operation of the operational amplifier (differential amplifier circuit) 12 is stopped when the signal DISN is L, and the operation is stopped between 00H and 0FH and
３3FH (operating state).

The gradation display data 905 indicates that the liquid crystal drive output voltage for 00H is the lowest voltage, and the gradation display data 9
FIG. 7 shows the relationship when the liquid crystal drive output voltage 05 is set to the highest voltage of the liquid crystal drive output voltage for 3FH.

As described above, as shown in FIG. 5, depending on the configuration of the decoder 45, the operational amplifier (differential amplifier circuit) 1
The range of operations 1 and 12 and the range of stopping the operations can be freely set. From this, the following can be said.

That is, in this embodiment, when the gradation display data 905 is in the range of 00H to 0FH, the operation of the operational amplifier (differential amplifier circuit) 12 is stopped and only the operational amplifier (differential amplifier circuit) 11 operates. Let it. In the range of the gradation display data 30H to 2FH, the operation of the operational amplifier (differential amplifier circuit) 11 is stopped and only the operational amplifier (differential amplifier circuit) 12 is operated. As a result, in the voltage range where the offset occurs, the circuit current including the bias current is cut off to stop the operation of the corresponding operational amplifier, while in the region where no offset occurs in both, the operational amplifiers (differential amplifier circuits) 11 and 12 are provided. By operating both of them, the driving capability for driving the pixel capacitance of a display device such as a liquid crystal display device is increased.

Although the configuration of FIG. 5 is a step down in reducing the power consumption, the power supply voltage Vdd is relatively low, and the display device has a large screen and a large number of pixels (the number of source lines is large). This is effective when, for example, high-speed driving or driving capability of a pixel capacitor is more strongly required than power consumption consumed by an output circuit.

On the other hand, by setting the operation of the operational amplifiers (differential amplifier circuits) 11 and 12 and the range of stopping the operation by the most significant bit (MSB) as in the above-described embodiment, the operational amplifier (differential amplification circuit) is set. Circuits) 11 and 12
Since one of the circuit currents is cut off and the circuit current does not flow at the same time, an operational amplifier (differential amplifier circuit) 11 that occurs when the power supply voltage Vdd is higher than 10 V and as high as several tens of V (for example, 80 V). When the driving device of the display device includes these operational amplifiers (differential amplifier circuits) 11 and 12, it is possible to greatly contribute to lower power consumption.

The operation and stop operation of each operational amplifier at each signal level of the signal DISP and the signal DISN generated by the decoder 45 are basically the same as those of the above-described embodiment, and will not be described here. Is omitted.

In the description of the above example, the output
The differential amplifier circuit as a path
Although the lower case has been described as an example, the present invention is not limited to this.
For example, non-inverting amplifier circuits or inverting amplifiers
A configuration in which amplification is performed as a width circuit may be employed. In this case, the output
Since the gradation display voltage can be amplified in the circuit,
In FIG. 9, the hold memory circuit 908₁, 908_Two, 908
_Three, 908_Four, 908 _FiveEach level needed within ...
A shifter circuit (not shown) becomes unnecessary, and
Reduction is possible.

As described above, a drive device (particularly, a source driver) for a liquid crystal display device has been described as an example of an output circuit that performs impedance conversion to a low impedance output. However, the present invention is not limited to this. A drive device of a display device having pixels arranged in a matrix, the pixel having a load capacitance including a parasitic capacitance, and realizing grayscale display by changing a voltage applied to the pixel, for example, a liquid crystal display device, It is also effective for an EL (electroluminescence) display device and the like, and particularly when the voltage applied to the pixel is high, the effect is exhibited.

As described above, the impedance conversion device according to the present invention includes a means for selecting one of a plurality of voltage values according to digital input data, and a high voltage for converting the selected voltage value to low impedance output. Impedance conversion means for converting the input stage and the output stage of the low impedance output conversion means for converting the low side to low impedance and the low impedance output conversion means for converting the low voltage side to low impedance. The two types of low-impedance output conversion means have control means for operating or stopping the conversion operation, and the control means is controlled based on data extracted from the digital input data.

The digital input data for controlling the control means is preferably the most significant bit. The digital input data for controlling the control means may be upper two bits.

The low-impedance output conversion means for converting the high-voltage side to low impedance and the low-impedance output conversion means for converting the low-voltage side to low impedance, when one is in operation, the other is always in a stop state. Is preferred.

In the stop state, it is preferable to have a control means for interrupting a current flowing in the low impedance output conversion means and setting the output stage to a high impedance state.

It is preferable to constitute a display device driving device including the above-described low impedance output converter. The display device driving device is preferably a liquid crystal display device driving device. It is preferable that the display device driving device is a source driver.

According to the above invention, the operational amplifier that does not affect the output voltage of each output circuit is stopped by the gradation display data 905 set for each output, thereby reducing the current consumption of the output drive circuit. It is possible to reduce it by almost half. Further, by decoding the gradation display data, it becomes possible to select which operational amplifier is used within the range of the output voltage. This makes it possible to reduce the driving current of the output circuit very effectively.

In the above description, the differential amplifying circuit as the output circuit has been described by exemplifying the voltage follower system which does not amplify. However, the present invention is not limited to this. A configuration in which amplification is performed as an inverting amplifier circuit or an inverting amplifier circuit may be employed. In this case, the output circuit can amplify the gray scale display voltage.
The level shifter circuit shown in (1) becomes unnecessary, and the circuit can be reduced.

The output circuit for performing impedance conversion to a low impedance output has been described above with reference to a driving device (particularly, a source driver) of a liquid crystal display device. However, the present invention is not limited to this. Drive device for a display device having pixels arranged in a matrix, the pixel having a load capacitance including a parasitic capacitance, and realizing gradation display by changing a voltage applied to the pixel, for example, a liquid crystal display device or an EL device (Electroluminescence) This is effective for a display device or the like, and particularly when the applied voltage to a pixel is high, the effect is exhibited.

[0098]

As described above, the impedance conversion device according to the present invention includes the first and second differential amplifier circuits connected in parallel with each other and performing impedance conversion on a voltage that changes according to digital input data. In accordance with the digital input data, operating power is supplied to set one of the first and second differential amplifier circuits to an operating state, and the other is set to a non-operating state without supplying operating power. And control means for performing control.

According to the present invention, the control means is provided, and the control means supplies one of the first and second differential amplifier circuits with operating power based on the digital input data. And the other is controlled so as not to be supplied with the operation power and to be in the non-operation state.

As a result, only one of the first and second differential amplifier circuits is always in the operating state. In other words, one of the first and second differential amplifier circuits is always in a non-operating state, and no current is consumed in this differential amplifier circuit (at the same time, the first and second differential amplifier circuits are not operated). No current flows to both sides.) Therefore, it is possible to reduce the current consumption of the impedance conversion device to half of the above-mentioned conventional one.

If both of the two differential amplifier circuits are operating at the same time, if the voltage of the operating power supply is as high as several tens of volts, a problem occurs in that a current flows between the two differential amplifier circuits. According to the above-described invention, only one of the differential amplifier circuits is in the operating state, so that such a disadvantage can be surely overcome.

In addition, since the above-mentioned control by the control means is performed based on digital input data which is the basis of a voltage to be subjected to impedance conversion, a signal from outside the impedance conversion device is not required separately. In addition, since the transition to the non-operating state is not performed all at once but based on digital input data, the effect of reducing power consumption can be surely increased.

It is preferable that the control means performs the control based on the most significant bit of the digital input data. In this case, in the voltage range in which the offset occurs, the corresponding differential amplifier circuit can be made inoperative, so that
It also has an effect that the reliability can be significantly improved.

In order to solve the above-mentioned problems, another impedance conversion device according to the present invention is connected in parallel with each other, and performs a first and second differential operation for impedance-converting a voltage that changes according to digital input data. An amplification circuit;
Decoding means for decoding the upper two bits of the digital input data; and
A control is performed such that an operating power is supplied so that one of the first and second differential amplifier circuits is in an operating state and the other is not in operation without supplying the operating power.
And control means for supplying an operating power to both the second differential amplifier circuit and controlling the second differential amplifier circuit to be in an operating state.

In the above invention, decoding means for decoding the upper two bits of the digital input data is provided, and based on the output of the decoding means, the control means controls the first and second bits based on the digital input data. Either one of the second differential amplifier circuits is supplied with an operation power supply to be in an operation state, and the other is controlled so as not to be supplied with the operation power supply so as to be in a non-operation state.
Operation power is supplied to both the second differential amplifier circuit and the second differential amplifier circuit, and both are controlled to be in an operation state.

In the above control, in the former case, as described above, the current consumption of the impedance conversion device can be suppressed to half of that in the conventional case. On the other hand, in the case of the latter control, by operating both the first and second differential amplifier circuits, it is possible to reliably increase the output driving capability of the impedance conversion device.

In addition, since the above-described control by the control means is performed based on digital input data which is a basis of a voltage to be subjected to impedance conversion, a signal from outside the impedance conversion device is not required separately. In addition, since the transition to the non-operation state is not performed all at once, the effect of reducing power consumption can be surely increased.

Further, in the voltage range in which the offset occurs, the corresponding differential amplifier circuit can be made inoperative, thereby significantly improving the reliability.
By operating both the first and second differential amplifier circuits within a voltage range in which no offset occurs in both differential amplifier circuits, it is possible to reliably increase the output drive capability of the impedance conversion device. It also has an effect.

In the above impedance converter, it is preferable that the output of the differential amplifier circuit in a non-operating state has a high impedance. In this case, the output of the differential amplifier circuit to which no operating power is supplied is controlled to high impedance by the control means, so that the operation of the differential amplifier circuit in the operating state is not hindered. therefore,
This also has the effect that the reliability of the impedance conversion device can be significantly improved.

The digital input data is gray scale display data, and indicates that the analog gray scale display voltage selected according to the gray scale display data is impedance-converted by the impedance converter. Preferably, it is a drive for the device. In this case, by amplifying the gradation display voltage, the level shifter circuit which has been required conventionally becomes unnecessary, and the circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration example of an impedance conversion circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of a circuit configuration of an operational amplifier (differential amplifier circuit) in which a differential pair at an input stage is configured by P-channel MOS transistors;

FIG. 3 is a circuit diagram showing a specific circuit configuration example of an operational amplifier (differential amplifier circuit) 12 in which an input-stage differential pair is formed by N-channel MOS transistors;

FIG. 4 is an explanatory diagram showing a case where a liquid crystal drive output voltage is set to a lowest voltage and a highest voltage.

FIG. 5 is a circuit diagram showing a configuration example of an impedance conversion circuit according to another embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating a configuration example of a decoder in FIG. 5;

FIG. 7 is an explanatory diagram showing another case where the liquid crystal drive output voltage is set to the lowest voltage and the highest voltage.

FIG. 8 is a schematic diagram showing a case where a liquid crystal driver for driving a liquid crystal panel using a TFT is used.

FIG. 9 is an explanatory diagram for explaining how a liquid crystal driver (source driver side) captures gradation display data.

FIG. 10 is an explanatory diagram for explaining a relationship of taking in data from an internal data bus.

FIG. 11 is a circuit diagram showing a configuration example of a conventional impedance conversion device.

FIG. 12 shows the impedance conversion device of FIG.
FIG. 3 is a circuit diagram showing that an input stage is configured by a differential pair of P-channel MOS transistors.

FIG. 13 shows the impedance conversion device of FIG.
FIG. 9 is a circuit diagram showing that an input stage is configured by a differential pair of N-channel MOS transistors.

FIGS. 14A to 14C are circuit diagrams illustrating another example of a conventional impedance conversion circuit.

FIG. 15 shows the impedance conversion device of FIG.
FIG. 9 is an explanatory diagram showing that current consumption is reduced.

[Explanation of symbols]

 Reference Signs List 11 operational amplifier (differential amplifier circuit) 12 operational amplifier (differential amplifier circuit) 45 decoder (decoding means) 45a OR circuit (decoding means) 45b AND circuit (decoding means) 201 P-channel MOS transistor (control means) 202 P-channel MOS transistor (control means) 203 P-channel MOS transistor (control means) 204 N-channel MOS transistor (control means)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03F 3/68 H03F 3/68 BF Term (Reference) 5C006 AC21 AF69 BB16 BC06 BC12 BC13 BF25 BF26 BF33 BF34 FA43 FA47 FA56 5C080 AA10 BB05 DD22 DD26 EE29 JJ02 JJ03 JJ04 JJ05 5J069 AA01 AA12 AA21 AA45 AA47 CA36 FA10 FA18 HA10 HA17 HA29 KA02 KA09 KA33 KA67 MA21 SA08 TA01 TA02 TA06 5J092 AA10 SAA17A18A17A18A18 TA01 TA02 TA06

Claims (5)

[Claims] A first and a second differential amplifier circuit, which are connected in parallel to each other and perform impedance conversion with respect to a voltage that changes in accordance with digital input data, and supply an operating power supply based on the digital input data. And a control means for controlling one of the first and second differential amplifier circuits to be in an operating state, and to control the other to be in a non-operating state without supplying operating power. 2. The impedance conversion device according to claim 1, wherein said control means performs said control based on the most significant bit of said digital input data. 3. A first and a second differential amplifier circuit, which are connected in parallel with each other and perform impedance conversion on a voltage that changes according to digital input data, and decoding means for decoding upper two bits of the digital input data. And based on the output of the decoding means, supplying an operating power supply to make one of the first and second differential amplifier circuits into an operating state and not supplying the operating power supply to bring the other into a non-operating state. Or a control means for controlling the first and second differential amplifier circuits to supply an operation power supply to make the operation state. 4. The output of the differential amplifier circuit in a non-operating state has a high impedance.
4. The impedance conversion device according to 2 or 3. 5. The digital input data is gray scale display data, and an analog gray scale display voltage selected according to the gray scale display data is an analog gray scale display voltage.
A driving device for a display device, wherein impedance conversion is performed by the impedance conversion device according to claim 1.