JP2002141353A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) Abstract: A gate electrode or a wiring can be formed with high precision using a dummy gate electrode or a dummy wiring while preventing an increase in circuit area. A gate electrode is formed on a semiconductor substrate.
And the dummy gate electrode 105 are formed at the same time. Thereafter, after removing the dummy gate electrode 105, an interlayer insulating film 107 is formed.
08 is formed so as to overlap at least a part of the region where the dummy gate electrode 105 is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device in which a gate electrode or a wiring is formed using a dummy gate electrode or a dummy wiring.

[0002]

2. Description of the Related Art In recent years, as process miniaturization has progressed, dummy gate electrodes or dummy wirings have been used in order to improve the formation accuracy of gate electrodes or wirings.

A conventional method for manufacturing a semiconductor device using a dummy gate electrode and a dummy wiring will be described below with reference to the drawings.

FIGS. 26A to 26D are cross-sectional views showing steps of a conventional method for manufacturing a semiconductor device.

First, as shown in FIG. 26A, a gate electrode 12 is formed on a semiconductor substrate 10 on which a plurality of pairs of impurity diffusion layers 11 to be a source region or a drain region are selectively provided on the surface. Form. The gate electrode 12 is formed between the pair of impurity diffusion layers 11 on the semiconductor substrate 10. At this time, the first region R of the semiconductor substrate 10
1, the gate electrodes 12 are densely arranged, while in the second region R2 of the semiconductor substrate 10, the gate electrodes 12
Are sparsely arranged. Therefore, at the same time as the formation of the gate electrode 12, the dummy gate electrode 13 is formed on the second region R2 of the semiconductor substrate 10 in a region where the impurity diffusion layer 11 and the gate electrode 12 are not provided according to the design rule of the gate electrode 12. I do. Thereby, the gate electrode 12 and the dummy gate electrode 13 can be uniformly arranged as a whole on the semiconductor substrate 10, so that photolithography and etching for forming the gate electrode 12 and the dummy gate electrode 13 can be performed. Since it is performed uniformly, the gate electrode 12 and the dummy gate electrode 13 can be formed with high accuracy.

Next, as shown in FIG. 26B, after a first interlayer insulating film 14 is formed on the entire surface of the semiconductor substrate 10, an impurity diffusion layer is formed on the first interlayer insulating film 14. 11
A first layer contact 15 for selectively connecting the upper layer wiring (the metal wiring 16 in FIG. 26C) is formed.

Next, as shown in FIG. 26C, a metal wiring (hereinafter referred to as a metal wiring) selectively connected to the first layer contact 15 on the first interlayer insulating film 14. ) 16 is formed. At this time, the metal wirings 16 are densely arranged in the third region R3 of the semiconductor substrate 10, while the metal wirings 16 are sparsely arranged in the fourth region R4 of the semiconductor substrate 10. Therefore, the metal wiring 16
At the same time, the dummy metal wiring 17 is placed on the fourth region R4 of the semiconductor substrate 10 and in a region where the first layer contact 15 and the metal wiring 16 are not provided.
6 according to the design rule. Thereby, the metal wiring 16 and the dummy metal wiring 17 can be uniformly arranged as a whole on the semiconductor substrate 10, so that photolithography and etching for forming the metal wiring 16 and the dummy metal wiring 17 can be performed. Since it is performed uniformly, the metal wiring 16 and the dummy metal wiring 17 can be formed with high accuracy.

Next, as shown in FIG. 26D, after a second interlayer insulating film 18 is formed over the entire surface of the semiconductor substrate 10, a metal wiring 16 is formed on the second interlayer insulating film 18. And a second-layer contact 19 for selectively connecting to the upper layer wiring (not shown).

[0009]

However, in the above-mentioned conventional method for manufacturing a semiconductor device, the gate electrode 1
It is necessary to dispose the dummy gate electrode 13 in consideration of the design rule for the second or impurity diffusion layer 11 and the dummy metal wiring in consideration of the design rule for the metal wiring 16, the first layer contact 15 or the second layer contact 19. 17 needs to be arranged. As a result, there arises a problem that a circuit area in the semiconductor device increases.

In view of the foregoing, it is an object of the present invention to enable a gate electrode or a wiring to be formed with high precision using a dummy gate electrode or a dummy wiring while preventing an increase in circuit area.

[0011]

To achieve the above object, a first method of manufacturing a semiconductor device according to the present invention comprises the steps of simultaneously forming a gate electrode and a dummy gate electrode on a semiconductor substrate; Removing the dummy gate electrode;
Forming an interlayer insulating film on the semiconductor substrate from which the dummy gate electrode has been removed, and forming a plug in the interlayer insulating film so as to overlap at least a part of the region where the dummy gate electrode was provided. ing.

According to the first method of manufacturing a semiconductor device, a gate electrode and a dummy gate electrode are simultaneously formed, then, after removing the dummy gate electrode, an interlayer insulating film is formed, and thereafter, a dummy gate electrode is provided. A plug is formed in the interlayer insulating film so as to overlap with the region that has been set. Therefore, while improving the accuracy of forming the gate electrode by using the dummy gate electrode, a plug for selectively connecting a region where the dummy gate electrode is provided by removing the dummy gate electrode to an upper layer wiring is formed. It can be used as a forming area. That is, an increase in the circuit area due to the use of the dummy gate electrode can be prevented. In other words, the circuit area can be reduced to the same extent as when the dummy gate electrode is not used. Can be realized.

In the first method of manufacturing a semiconductor device, it is preferable to use a photomask used for forming the dummy gate electrode when removing the dummy gate electrode.

With this configuration, the dummy gate electrode can be removed accurately, and the reliability of the semiconductor device is improved.

In a second method of manufacturing a semiconductor device according to the present invention, a step of forming a pair of impurity diffusion layers serving as a source region or a drain region on a surface portion of a semiconductor substrate; Forming a gate electrode between them and simultaneously forming a dummy gate electrode on at least one of the pair of impurity diffusion layers;
Removing the dummy gate electrode.

According to the second method of manufacturing a semiconductor device, simultaneously with forming the gate electrode, a dummy gate electrode is formed on the impurity diffusion layer provided on both sides of the gate electrode in the semiconductor substrate, and thereafter, the dummy gate electrode is formed. Is removed. Therefore, while the accuracy of forming the gate electrode is improved by using the dummy gate electrode, the area where the dummy gate electrode is provided by removing the dummy gate electrode is selectively connected to, for example, the impurity diffusion layer and the upper layer wiring. Can be used as a plug formation region or the like. That is, the circuit area can be prevented from increasing due to the use of the dummy gate electrode. In other words, the circuit area can be reduced to the same extent as when the dummy gate electrode is not used.
A semiconductor device with high integration and excellent performance can be realized.

In the second method for manufacturing a semiconductor device, it is preferable to use a photomask used for forming the dummy gate electrode when removing the dummy gate electrode.

In this case, the removal of the dummy gate electrode can be accurately performed, so that the reliability of the semiconductor device is improved.

In the second method of manufacturing a semiconductor device, an interlayer insulating film is formed on a semiconductor substrate after the step of removing the dummy gate electrode, and thereafter, a plug is provided in the interlayer insulating film, and the dummy gate electrode is provided. It may be formed so as to overlap at least a part of the region that has been set.

According to a third method of manufacturing a semiconductor device according to the present invention, there is provided a step of simultaneously forming a wiring and a dummy wiring on a semiconductor substrate, a step of removing the dummy wiring, and a step of removing the dummy wiring from the semiconductor substrate. The method includes a step of forming an interlayer insulating film thereon, and a step of forming a plug in the interlayer insulating film so as to overlap at least a part of a region where the dummy wiring is provided.

According to the third method of manufacturing a semiconductor device, a wiring and a dummy wiring are formed at the same time, then, the dummy wiring is removed, an interlayer insulating film is formed, and then the region where the dummy wiring is provided is formed. A plug is formed in the interlayer insulating film so as to overlap. For this reason, the area where the dummy wiring is provided by removing the dummy wiring is used as a plug formation area for performing selective wiring connection with the upper wiring, while improving the wiring formation accuracy by using the dummy wiring. it can. That is, it is possible to prevent an increase in the circuit area due to the use of the dummy wirings.
Since the size can be reduced to the same extent as when no dummy wiring is used, a semiconductor device with high integration and excellent performance can be realized.

In the third method of manufacturing a semiconductor device, when removing the dummy wiring, it is preferable to use a photomask used for forming the dummy wiring.

With this configuration, the dummy wiring can be accurately removed, and the reliability of the semiconductor device is improved.

A fourth method of manufacturing a semiconductor device according to the present invention comprises the steps of forming an interlayer insulating film provided with a plug on a semiconductor substrate, forming a wiring on the interlayer insulating film, The method includes a step of forming a dummy wiring thereon and a step of removing the dummy wiring.

According to the fourth method of manufacturing a semiconductor device, a wiring is formed on an interlayer insulating film, and at the same time, a dummy wiring is formed on a plug provided in the interlayer insulating film, and then the dummy wiring is removed. For this reason, the area where the dummy wiring is provided by removing the dummy wiring is replaced with, for example, a plug forming area for performing selective wiring connection with the upper wiring, while improving the wiring formation accuracy by using the dummy wiring. Can be used as That is, it is possible to prevent an increase in the circuit area due to the use of the dummy wiring.
Since the circuit area can be reduced to the same extent as when no dummy wiring is used, a semiconductor device with high integration and excellent performance can be realized.

In the fourth method of manufacturing a semiconductor device, when removing the dummy wiring, it is preferable to use a photomask used for forming the dummy wiring.

With this configuration, the dummy wiring can be accurately removed, thereby improving the reliability of the semiconductor device.

In the fourth method of manufacturing a semiconductor device, another interlayer insulating film is formed on the interlayer insulating film after the step of removing the dummy wiring, and then another plug is formed in the other interlayer insulating film. Alternatively, the dummy wiring may be formed so as to overlap at least a part of the area where the dummy wiring is provided.

A fifth method of manufacturing a semiconductor device according to the present invention comprises the steps of simultaneously forming a temporary electrode for forming a gate electrode and a dummy gate electrode on a semiconductor substrate; A step of forming a first resist film in a region where the dummy gate electrode is not provided, a step of removing the temporary electrode for forming a gate electrode and the dummy gate electrode, and a step of forming a second resist film in a concave portion where the dummy gate electrode is removed. The method includes a step of forming a resist film and a step of forming a gate electrode in a concave portion from which the gate electrode forming temporary electrode has been removed.

According to the fifth method of manufacturing a semiconductor device, after the provisional electrode for forming the gate electrode and the dummy gate electrode are simultaneously formed on the semiconductor substrate, the provisional electrode for forming the gate electrode and the dummy gate electrode are not provided. A first resist film is formed in the region, and then the gate electrode forming temporary electrode and the dummy gate electrode are removed. Then, after forming a second resist film in the concave portion from which the dummy gate electrode has been removed, a gate electrode is formed in the concave portion from which the gate electrode forming temporary electrode has been removed. For this reason, the area in which the dummy gate electrode is provided by removing the dummy gate electrode is removed, for example, by using the dummy gate electrode to improve the formation accuracy of the provisional electrode for forming the gate electrode, that is, the formation accuracy of the gate electrode. Can be used as a plug formation region or the like for performing selective wiring connection. That is, an increase in the circuit area due to the use of the dummy gate electrode can be prevented. In other words, the circuit area can be reduced to the same extent as when the dummy gate electrode is not used. Can be realized.

In the fifth method of manufacturing a semiconductor device, it is preferable to use a photomask used for forming a dummy gate electrode when forming the second resist film.

With this configuration, the second resist film can be accurately formed in the concave portion where the dummy gate electrode has been removed, so that the reliability of the semiconductor device is improved.

In a sixth method of manufacturing a semiconductor device according to the present invention, a step of simultaneously forming a temporary wiring for forming a wiring and a dummy wiring on a semiconductor substrate; First in the area not provided
Forming a second resist film in the recess where the dummy wiring is removed, removing the temporary wiring for forming the wiring, removing the temporary wiring for forming the wiring, and removing the temporary wiring for forming the wiring. Forming a wiring in the formed concave portion.

According to the sixth method of manufacturing a semiconductor device, after the temporary wiring for forming the wiring and the dummy wiring are simultaneously formed on the semiconductor substrate, the first wiring is formed in a region where the temporary wiring for forming the wiring and the dummy wiring are not provided. After forming a resist film,
The temporary wiring for wiring formation and the dummy wiring are removed. afterwards,
After forming a second resist film in the concave portion from which the temporary wiring for wiring formation has been removed, a wiring is formed in the concave portion from which the dummy wiring has been removed. For this reason, the area where the dummy wiring is provided by removing the dummy wiring is selectively connected to the upper wiring, for example, while improving the formation accuracy of the wiring forming temporary wiring, that is, the wiring formation accuracy by using the dummy wiring. It can be used as a plug formation area for making connections.
That is, an increase in the circuit area due to the use of the dummy wiring can be prevented. In other words, the circuit area can be reduced to about the same level as when the dummy wiring is not used, thereby realizing a semiconductor device with high integration and excellent performance. it can.

In the sixth method of manufacturing a semiconductor device, it is preferable to use a photomask used for forming a dummy wiring when forming the second resist film.

With this configuration, the second resist film can be accurately formed in the concave portion from which the dummy wiring has been removed, so that the reliability of the semiconductor device is improved.

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) Hereinafter, a method for manufacturing a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings.

FIGS. 1A to 1D and FIGS.
FIG. 4D is a cross-sectional view illustrating each step of the method for manufacturing the semiconductor device according to the first embodiment.

First, as shown in FIG. 1A, a plurality of impurity diffusion layers 1 serving as a source region or a drain region are formed.
The conductive film 102 and the positive type first resist film 10
3 are sequentially formed. After that, the first exposure light 151 is applied to the first resist film 103 via the first photomask 150. Thereby, the first resist film 10
Exposure is performed on portions other than the upper side of the gate electrode formation region and the upper side of the dummy gate electrode formation region in 3.

Next, as shown in FIG. 1B, by developing the first resist film 103, a first resist pattern 103A covering the gate electrode formation region and the dummy gate electrode formation region is formed. Then, dry etching is performed on the conductive film 102 using the first resist pattern 103A as a mask to selectively form the gate electrode 104 and the dummy gate electrode 105. Gate electrode 1
04 is formed between the pair of impurity diffusion layers 101 on the semiconductor substrate 100. At this time, although not shown, the gate electrodes 104 are densely arranged in one region of the semiconductor substrate 100, but are sparsely arranged in other regions of the semiconductor substrate 100. The dummy gate electrode 105 is formed on the gate electrode 10 on the semiconductor substrate 100.
4 is formed in the area where the sparsely arranged area is provided (the other area described above). Further, the dummy gate electrode 105 may be formed on the impurity diffusion layer 101.

Next, as shown in FIG. 1C, after removing the first resist pattern 103A, as shown in FIG. 1D, a positive type A second resist film 106 is formed. After that, the second resist film 106 is irradiated with the second exposure light 153 via the second photomask 152. As a result, the dummy gate electrode 105 in the second resist film 106
Exposure is performed on the upper region of.

Next, by developing the second resist film 106, as shown in FIG. 2A, a second resist pattern 106A covering other areas than the upper side of the dummy gate electrode 105 was formed. Thereafter, the dummy gate electrode 105 is dry-etched using the second resist pattern 106A as a mask to remove the dummy gate electrode 105 as shown in FIG. 2B.

Next, as shown in FIG. 2C, after removing the second resist pattern 106A, as shown in FIG. 2D, the first resist pattern 106A is formed over the entire surface of the semiconductor substrate 100. After the interlayer insulating film 107 is formed, the impurity diffusion layer 101 and the upper wiring (not shown) are formed on the first interlayer insulating film 107.
Layer contact plug 1 for selectively connecting
08 is formed. At this time, the first layer contact plug 1
08 may be formed so as to overlap the region where the dummy gate electrode 105 is provided.

As described above, according to the first embodiment, the gate electrode 104 and the dummy gate electrode 105 are formed on the semiconductor substrate 100 provided with the impurity diffusion layer 101 serving as a source region or a drain region. At the same time, after the dummy gate electrode 105 is removed, a first interlayer insulating film 107 is formed. A layer contact plug 108 is formed. Therefore, the first-layer contact plug 108 is formed so as to overlap at least a part of the region where the dummy gate electrode 105 is provided, or the dummy gate electrode 105 is formed on at least a part of the impurity diffusion layer 101. , The following effects can be obtained. That is, while the formation accuracy of the gate electrode 104 is improved by using the dummy gate electrode 105, the region where the dummy gate electrode 105 is provided by the removal of the dummy gate electrode 105 is changed to the first layer contact plug 108.
Can be used as a formation region. Therefore, an increase in the circuit area due to the use of the dummy gate electrode 105 can be prevented.
5 can be made as small as the case where the semiconductor device 5 is not used, so that a semiconductor device with high integration and excellent performance can be realized.

In the first embodiment, the area where the dummy gate electrode 105 is provided is used as the area for forming the first-layer contact plug 108. However, the dummy gate electrode 105 is provided instead. The region which has been used may be used as a region for forming other components such as a gate electrode (another gate electrode having a different design rule from the gate electrode 104).

In the first embodiment, it is not always necessary to remove the dummy gate electrode which does not affect the circuit area.

(Modification of First Embodiment) A method of manufacturing a semiconductor device according to a modification of the first embodiment of the present invention will be described below with reference to the drawings.

FIGS. 3 (a) to 3 (c), FIGS. 4 (a) to 4 (c)
FIGS. 5A to 5C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a modification of the first embodiment.

First, as shown in FIG. 3A, a plurality of impurity diffusion layers 1 serving as a source region or a drain region are formed.
A conductive film 102 and a negative type first resist film 10 are formed on a semiconductor substrate 100 on which a surface 01 is selectively provided.
3 are sequentially formed. After that, the first resist film 103 is irradiated with the first exposure light 161 via the first photomask 160. Thereby, the first resist film 10
Exposure is performed on the upper side of the dummy gate electrode formation region in FIG.

Next, as shown in FIG. 3B, the first resist film 103 is irradiated with a second exposure light 163 via a second photomask 162. Thereby, the first
Exposure is performed on the upper side of the gate electrode formation region in the resist film 103 of FIG.

Next, as shown in FIG. 3C, a first resist pattern 103A covering the gate electrode formation region and the dummy gate electrode formation region is formed by developing the first resist film 103. Then, dry etching is performed on the conductive film 102 using the first resist pattern 103A as a mask to selectively form the gate electrode 104 and the dummy gate electrode 105. Gate electrode 1
04 is formed between the pair of impurity diffusion layers 101 on the semiconductor substrate 100. At this time, although not shown, the gate electrodes 104 are densely arranged in one region of the semiconductor substrate 100, but are sparsely arranged in other regions of the semiconductor substrate 100. The dummy gate electrode 105 is formed on the gate electrode 10 on the semiconductor substrate 100.
4 is formed in the area where the sparsely arranged area is provided (the other area described above). Further, the dummy gate electrode 105 may be formed on the impurity diffusion layer 101.

Next, as shown in FIG. 4A, after removing the first resist pattern 103A, as shown in FIG. 4B, a positive type A second resist film 106 is formed. Then, FIG.
The third exposure light 164 is applied to the third exposure light 164 via the first photomask 160 used to expose the upper side of the dummy gate electrode formation region in the first resist film 103 in the step shown in FIG. Irradiation is performed on the second resist film 106.

Next, by developing the second resist film 106, as shown in FIG. 4C, a second resist pattern 106A covering other regions than the upper side of the dummy gate electrode 105 was formed. Thereafter, the dummy gate electrode 105 is dry-etched using the second resist pattern 106A as a mask to remove the dummy gate electrode 105 as shown in FIG.

Next, as shown in FIG. 5B, after removing the second resist pattern 106A, as shown in FIG. 5C, the first resist pattern 106A is formed over the entire surface of the semiconductor substrate 100. After forming the interlayer insulating film 107, the first interlayer insulating film 10
7, a first layer contact plug 108 for selectively connecting the impurity diffusion layer 101 and an upper layer wiring (not shown).
To form At this time, the first layer contact plug 108
May be formed so as to overlap with the region where the dummy gate electrode 105 was provided.

According to the modification of the first embodiment described above, the following effect can be obtained in addition to the same effect as the first embodiment. That is, the dummy gate electrode 105
Is removed, the first photomask 160 used to form the dummy gate electrode 105 is used, so that the dummy gate electrode 105 can be removed accurately, thereby reducing the reliability of the semiconductor device. Can be improved.

In the modification of the first embodiment, the area where the dummy gate electrode 105 is provided is used as the area where the first layer contact plug 108 is formed.
Instead, the region where the dummy gate electrode 105 is provided may be used as a region for forming other components such as a gate electrode (another gate electrode having a different design rule from the gate electrode 104).

In a modification of the first embodiment,
After exposing (see FIG. 3A) the first photomask 160 to the upper side of the dummy gate electrode formation region in the first resist film 103, the gate electrode formation in the first resist film 103 is performed. The upper side of the region was exposed using the second photomask 162 (see FIG. 3B), but instead of this, the first resist film 1 was used.
Exposure is performed using the second photomask 162 on the upper side of the gate electrode formation region in the third resist film 103, and then the first photomask 160 is formed on the upper side of the dummy gate electrode formation region in the first resist film 103. May be used for exposure.

In a modification of the first embodiment,
It is not always necessary to remove the dummy gate electrode that does not affect the circuit area.

(Second Embodiment) Hereinafter, a method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings.

FIGS. 6A to 6C and FIGS. 7A to 7C.
FIGS. 8A and 8B are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to the second embodiment.

In the second embodiment, for example, the method of manufacturing the semiconductor device according to the first embodiment or its modification (FIGS. 1A to 1D and FIGS.
(D), or FIGS. 3 (a) to (c), and FIGS.
(C) and FIGS. 5 (a) to 5 (c)), the semiconductor substrate 10 in which a plurality of pairs of impurity diffusion layers 101 serving as a source region or a drain region are selectively provided on a surface portion.
The first contact plug 10 connected to the impurity diffusion layer 101 is formed on the gate electrode 104 on the semiconductor substrate 100 and on the gate electrode 104.
It is assumed that the first interlayer insulating film 107 provided with the layer 8 is formed.

First, as shown in FIG. 6A, a conductive film 201 and a positive first resist film 202 are sequentially formed on the entire surface of the first interlayer insulating film 107. After that, the first resist film 202 is irradiated with the first exposure light 251 via the first photomask 250. As a result, exposure is performed on other portions of the first resist film 202 except the upper side of the wiring formation region and the upper side of the dummy wiring formation region.

Next, as shown in FIG. 6B, by developing the first resist film 202, a first resist pattern 202A covering the wiring formation region and the dummy wiring formation region is formed. 1 resist pattern 202
Dry etching is performed on the conductive film 201 using A as a mask to selectively form the wiring 203 and the dummy wiring 204. At this time, although not shown, the wirings 203 are densely arranged in one region of the semiconductor substrate 100, but are sparsely arranged in another region of the semiconductor substrate 100. Further, the dummy wiring 204 is formed in a region on the semiconductor substrate 100 where the wiring 203 is sparsely arranged (the other region described above). The wiring 203 is formed so as to be connected to the first layer contact plug 108. Further, the dummy wiring 204 may be formed on the first layer contact plug 108.

Next, as shown in FIG. 6C, after removing the first resist pattern 202A, as shown in FIG. 7A, over the entire surface of the first interlayer insulating film 107, as shown in FIG. Then, a positive second resist film 205 is formed. afterwards,
Second photomask 2 for second resist film 205
The second exposure light 253 is irradiated via the light 52. As a result, the dummy wiring 204 in the second resist film 205
Exposure is performed on the upper region of.

Next, by developing the second resist film 205, as shown in FIG.
After forming a second resist pattern 205A covering other regions except the upper side of the second resist pattern 20
Dry etching is performed on the dummy wiring 204 using 5A as a mask, and the dummy wiring 204 is removed as shown in FIG.

Next, as shown in FIG. 8A, after removing the second resist pattern 205A, over the entire surface of the first interlayer insulating film 107 as shown in FIG. 8B. After the formation of the second interlayer insulating film 206, the wiring 203 or the first-layer contact plug 108 and the upper wiring (not shown) are formed.
Layer contact plug 2 for selectively connecting
07 is formed. At this time, the second-layer contact plug 2
07 may be formed so as to overlap the region where the dummy wiring 204 was provided.

As described above, according to the second embodiment, the wiring 203 and the dummy wiring 204 are simultaneously formed on the first interlayer insulating film 107 on which the first-layer contact plug 108 is provided. After that, after the dummy wiring 204 is removed, a second interlayer insulating film 206 is formed. A two-layer contact plug 207 is formed. Therefore, the second-layer contact plug 207 is formed so as to overlap at least a part of the region where the dummy wiring 204 is provided, or the dummy wiring 204 is formed on at least a part of the first-layer contact plug 108. , The following effects can be obtained. That is, the area where the dummy wiring 204 is provided by removing the dummy wiring 204 can be used as the formation area of the second-layer contact plug 207 while improving the formation accuracy of the wiring 203 by using the dummy wiring 204. Therefore, an increase in the circuit area due to the use of the dummy wiring 204 can be prevented. In other words, the circuit area can be reduced to the same extent as when the dummy wiring 204 is not used.
A semiconductor device with high integration and excellent performance can be realized.

In the second embodiment, the area where the dummy wiring 204 is provided is used as the area where the second-layer contact plug 207 is formed.
The region where the dummy wiring 204 is provided may be used as a region for forming other components such as a capacitor, a diode, or a resistor.

In the second embodiment, it is not always necessary to remove the dummy wiring which does not affect the circuit area.

(Modification of Second Embodiment) A method of manufacturing a semiconductor device according to a modification of the second embodiment of the present invention will be described below with reference to the drawings.

FIGS. 9 (a) to 9 (c) and FIGS.
11C and FIGS. 11A to 11C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a modification of the second embodiment.

Incidentally, in a modification of the second embodiment,
For example, a method of manufacturing a semiconductor device according to the first embodiment or its modification (FIGS. 1A to 1D and 2A)
-(D), or FIGS. 3 (a)-(c), FIGS. 4 (a)-
(C) and FIGS. 5 (a) to 5 (c)), the semiconductor substrate 10 in which a plurality of pairs of impurity diffusion layers 101 serving as a source region or a drain region are selectively provided on a surface portion.
The first contact plug 10 connected to the impurity diffusion layer 101 is formed on the gate electrode 104 on the semiconductor substrate 100 and on the gate electrode 104.
It is assumed that the first interlayer insulating film 107 provided with the layer 8 is formed.

First, as shown in FIG. 9A, a conductive film 201 and a negative type first resist film 202 are sequentially formed on the entire surface of the first interlayer insulating film 107. After that, the first resist film 202 is irradiated with first exposure light 261 via the first photomask 260. Thus, exposure is performed on the first resist film 202 above the dummy wiring formation region.

Next, as shown in FIG. 9B, the first resist film 202 is irradiated with the second exposure light 263 via the second photomask 262. Thereby, the first
Exposure is performed on the upper side of the wiring formation region in the resist film 202 of FIG.

Next, as shown in FIG. 9C, by developing the first resist film 202, a first resist pattern 202A covering the wiring formation region and the dummy wiring formation region is formed. 1 resist pattern 202
Dry etching is performed on the conductive film 201 using A as a mask to selectively form the wiring 203 and the dummy wiring 204. At this time, although not shown, the wirings 203 are densely arranged in one region of the semiconductor substrate 100, but are sparsely arranged in another region of the semiconductor substrate 100. Further, the dummy wiring 204 is formed in a region on the semiconductor substrate 100 where the wiring 203 is sparsely arranged (the other region described above). The wiring 203 is formed so as to be connected to the first layer contact plug 108. Further, the dummy wiring 204 may be formed on the first layer contact plug 108.

Next, as shown in FIG. 10A, after the first resist pattern 202A is removed, FIG.
As shown in (1), a positive second resist film 205 is formed over the entire surface of the first interlayer insulating film 107. Thereafter, a third exposure is performed through a first photomask 260 used to expose the upper side of the dummy gate electrode formation region in the first resist film 202 in the step shown in FIG. 9A. Light 264 is applied to the second resist film 205.

Next, by developing the second resist film 205, as shown in FIG. 10C, after forming a second resist pattern 205A covering other regions than the upper side of the dummy wiring 204, , Second resist pattern 2
Dry etching is performed on the dummy wiring 204 using the mask 05A as a mask, and the dummy wiring 204 is removed as shown in FIG.

Next, as shown in FIG. 11B, after the second resist pattern 205A is removed, FIG.
After forming a second interlayer insulating film 206 over the entire surface of the first interlayer insulating film 107 as shown in FIG.
Alternatively, a second-layer contact plug 207 for selectively connecting the first-layer contact plug 108 and an upper-layer wiring (not shown) is formed. At this time, the second layer contact plug 207 may be formed so as to overlap the region where the dummy wiring 204 is provided.

According to the modified example of the second embodiment described above, the following effect can be obtained in addition to the same effect as the second embodiment. That is, when removing the dummy wiring 204, the first photomask 260 used for forming the dummy wiring 204 is used, so that the dummy wiring 204 can be accurately removed. Reliability can be improved.

In the modification of the second embodiment, the area where the dummy wiring 204 is provided is used as the formation area of the second-layer contact plug 207. Instead, the dummy wiring 204 is provided. The region that has been set may be used as a region for forming other components such as a capacitor, a diode, or a resistor.

In a modification of the second embodiment,
After exposing (see FIG. 9A) the first resist film 202 above the dummy wiring formation region using the first photomask 260, the first resist film 2 is exposed.
Exposure was performed using the second photomask 262 (see FIG. 9B) on the upper side of the wiring formation region in the first resist film 202 instead of the upper side of the wiring formation region in the first resist film 202. The second photomask 262
After the exposure using the first photomask 260, the exposure may be performed on the upper side of the dummy wiring formation region in the first resist film 202 using the first photomask 260.

In a modification of the second embodiment,
It is not always necessary to remove dummy wirings that do not affect the circuit area.

(Third Embodiment) Hereinafter, a method for manufacturing a semiconductor device according to a third embodiment of the present invention will be described with reference to the drawings.

FIGS. 12 (a) to 12 (d) and FIGS.
FIGS. 14D and 14A and 14B are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to the third embodiment.

First, as shown in FIG. 12A, a semiconductor substrate 300 in which a plurality of pairs of impurity diffusion layers 301 to be a source region or a drain region are selectively provided on a surface portion.
Conductive film 302 and positive type first resist film 3
03 are sequentially formed. After that, the first resist film 303
Is irradiated with first exposure light 351 through a first photomask 350. Thereby, the first resist film 3
Exposure is performed on portions other than the upper side of the gate electrode formation region and the upper side of the dummy gate electrode formation region in 03.

Next, as shown in FIG. 12B, by developing the first resist film 303, a first resist pattern 303A covering the gate electrode formation region and the dummy gate electrode formation region is formed. Then, dry etching is performed on the conductive film 302 using the first resist pattern 303A as a mask to selectively form the temporary electrode 304 for forming a gate electrode and the dummy gate electrode 305. The temporary electrode 304 for forming a gate electrode is formed on the semiconductor substrate 30.
It is formed between a pair of impurity diffusion layers 301 on zero. At this time, although not shown, the gate electrode forming provisional electrodes 304 are densely arranged in one region of the semiconductor substrate 300, but are sparsely arranged in another region of the semiconductor substrate 300. Further, the dummy gate electrode 305 is
Temporary electrode 3 for forming gate electrode on semiconductor substrate 300
04 is formed in a sparsely arranged region (the other region described above). Further, the dummy gate electrode 305 may be formed on the impurity diffusion layer 301.

Next, as shown in FIG. 12C, after the first resist pattern 303A is removed, FIG.
As shown in FIG. 3, on the semiconductor substrate 300 (impurity diffusion layer 30
1) (including the upper electrode 1).
Then, a second resist film 306 (corresponding to the first resist film of claim 9) is formed in a region where the dummy gate electrode 305 is not provided.

Next, as shown in FIG. 13A, the temporary electrode 304 for forming a gate electrode and the dummy gate electrode 305 are removed, and then, as shown in FIG.
Negative third resist film 30 over the entire surface
7 is formed. Thereafter, the second exposure light 35 is applied to the third resist film 307 through the second photomask 352.
Irradiate 3. Thus, exposure is performed on a region of the third resist film 307 where the dummy gate electrode 305 is provided.

Next, by developing the third resist film 307, as shown in FIG. 13C, the second resist pattern 307A is formed in the concave portion where the dummy gate electrode 305 is removed. (Corresponds to the second resist film)
To form In other words, the third resist film 307 is left only in the concave portion where the dummy gate electrode 305 has been removed.

Next, as shown in FIG. 13D, a gate electrode 308 is formed in the concave portion where the gate electrode forming temporary electrode 304 is removed, and then, as shown in FIG.
Second resist film 306 and second resist pattern 3
07A (that is, the third resist film 307) is removed.

Next, as shown in FIG. 14B, a first interlayer insulating film 309 is formed over the entire surface of the semiconductor substrate 300.
Thereafter, a first-layer contact plug 310 for selectively connecting the impurity diffusion layer 301 and an upper-layer wiring (not shown) is formed in the first interlayer insulating film 309.
At this time, the first layer contact plug 310 may be formed so as to overlap the region where the dummy gate electrode 305 is provided.

As described above, according to the third embodiment, after the gate electrode forming temporary electrode 304 and the dummy gate electrode 305 are simultaneously formed on the semiconductor substrate 300, the gate electrode forming temporary electrode 304 and the dummy electrode 305 are formed. The second resist film 3 is formed in a region where the dummy gate electrode 305 is not provided.
06, and then a gate electrode forming temporary electrode 304 is formed.
And the dummy gate electrode 305 is removed. Thereafter, a second resist pattern 307A is formed in the concave portion where the dummy gate electrode 305 has been removed, and then the gate electrode 308 has been formed in the concave portion where the gate electrode forming temporary electrode 304 has been removed.
To form Therefore, the dummy gate electrode 305 is removed to remove the dummy gate electrode 305 while using the dummy gate electrode 305 to improve the formation accuracy of the provisional electrode 304 for forming the gate electrode, that is, the formation accuracy of the gate electrode 308.
Can be used, for example, as a formation region of a first-layer contact plug 310 that connects the impurity diffusion layer 301 and the upper wiring. Therefore, an increase in the circuit area due to the use of the dummy gate electrode 305 can be prevented.
5 can be made as small as the case where the semiconductor device 5 is not used, so that a semiconductor device with high integration and excellent performance can be realized.

In the third embodiment, the area where the dummy gate electrode 305 is provided is used as the area for forming the first-layer contact plug 310. However, the dummy gate electrode 305 is provided instead. The region which has been used may be used as a region for forming other components such as a gate electrode (another gate electrode having a different design rule from the gate electrode 308).

In the third embodiment, it is not always necessary to remove the dummy gate electrode which does not affect the circuit area.

(Modification of Third Embodiment) A method of manufacturing a semiconductor device according to a modification of the third embodiment of the present invention will be described below with reference to the drawings.

FIGS. 15A to 15D and FIGS.
(D) and FIGS. 17A to 17C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a modification of the third embodiment.

First, as shown in FIG. 15A, a semiconductor substrate 300 in which a plurality of pairs of impurity diffusion layers 301 to be a source region or a drain region are selectively provided on a surface portion.
Conductive film 302 and negative type first resist film 3
03 are sequentially formed. After that, the first resist film 303
Is irradiated with first exposure light 361 through a first photomask 360. Thereby, the first resist film 3
Exposure is performed on the upper side of the dummy gate electrode formation region at 03.

Next, as shown in FIG. 15B, the first resist film 303 is irradiated with the second exposure light 363 via the second photomask 362. Thus, exposure is performed on the first resist film 303 above the gate electrode formation region.

Next, as shown in FIG. 15C, by developing the first resist film 303, a first resist pattern 303A covering the gate electrode formation region and the dummy gate electrode formation region is formed. Then, dry etching is performed on the conductive film 302 using the first resist pattern 303A as a mask to selectively form the temporary electrode 304 for forming a gate electrode and the dummy gate electrode 305. The temporary electrode 304 for forming a gate electrode is formed on the semiconductor substrate 30.
It is formed between a pair of impurity diffusion layers 301 on zero. At this time, although not shown, the gate electrode forming provisional electrodes 304 are densely arranged in one region of the semiconductor substrate 300, but are sparsely arranged in another region of the semiconductor substrate 300. Further, the dummy gate electrode 305 is
Temporary electrode 3 for forming gate electrode on semiconductor substrate 300
04 is formed in a sparsely arranged region (the other region described above). Further, the dummy gate electrode 305 may be formed on the impurity diffusion layer 301.

Next, as shown in FIG. 15D, after the first resist pattern 303A is removed, FIG.
As shown in FIG. 3, on the semiconductor substrate 300 (impurity diffusion layer 30
1) (including the upper electrode 1).
Then, a second resist film 306 (corresponding to the first resist film of claim 9) is formed in a region where the dummy gate electrode 305 is not provided.

Next, as shown in FIG. 16B, after removing the gate electrode forming temporary electrode 304 and the dummy gate electrode 305, as shown in FIG.
Negative third resist film 30 over the entire surface
7 is formed. After that, in the step shown in FIG.
The third exposure light 364 is applied to the third exposure light 364 through the first photomask 360 used to expose the upper side of the dummy gate electrode formation region in the resist film 303 of FIG.
The resist film 307 is irradiated. Thereby, the dummy gate electrode 305 on the third resist film 307 is formed.
Exposure is performed on the region where is provided.

Next, by developing the third resist film 307, as shown in FIG. 16D, the second resist pattern 307A is formed in the concave portion where the dummy gate electrode 305 is removed. (Corresponds to the second resist film)
To form In other words, the third resist film 307 is left only in the concave portion where the dummy gate electrode 305 has been removed.

Next, as shown in FIG. 17A, a gate electrode 308 is formed in the concave portion where the gate electrode forming temporary electrode 304 has been removed, and then, as shown in FIG.
Second resist film 306 and second resist pattern 3
07A is removed.

Next, as shown in FIG. 17C, a first interlayer insulating film 309 is formed over the entire surface of the semiconductor substrate 300.
Thereafter, a first-layer contact plug 310 for selectively connecting the impurity diffusion layer 301 and an upper-layer wiring (not shown) is formed in the first interlayer insulating film 309.
At this time, the first layer contact plug 310 may be formed so as to overlap the region where the dummy gate electrode 305 is provided.

According to the modified example of the third embodiment described above, the following effect can be obtained in addition to the same effect as the third embodiment. That is, the dummy gate electrode 305
The second resist pattern 307 is formed in the concave portion formed by removing
Since the first photomask 360 used to form the dummy gate electrode 305 is used when forming A, the second resist pattern 307A can be formed accurately, thereby improving the reliability of the semiconductor device. Can be done.

In the modification of the third embodiment, the region where the dummy gate electrode 305 is provided is used as the region where the first-layer contact plug 310 is formed.
Instead, the region where the dummy gate electrode 305 is provided may be used as a region for forming other components such as a gate electrode (another gate electrode having a different design rule from the gate electrode 308).

In a modification of the third embodiment,
After exposing the upper side of the dummy gate electrode formation region in the first resist film 303 using the first photomask 360 (see FIG. 15A), the gate electrode formation in the first resist film 303 is performed. Exposure is performed on the upper side of the region using the second photomask 362 (FIG. 15B).
) Was performed, but instead of this, the second resist was placed on the first resist film 303 above the gate electrode formation region.
After exposure using the photomask 362 of FIG.
Exposure may be performed using the first photomask 360 on the upper side of the dummy gate electrode formation region in the resist film 303.

In a modification of the third embodiment,
It is not always necessary to remove the dummy gate electrode that does not affect the circuit area.

(Fourth Embodiment) Hereinafter, a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention will be described with reference to the drawings.

FIGS. 18A to 18C and FIGS. 19A to 19 C
(C), FIG. 20 (a), (b) and FIG. 21 (a),
(B) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on 4th Embodiment.

In the fourth embodiment, for example, a method of manufacturing a semiconductor device according to the third embodiment or its modification (FIGS. 12A to 12D, 13A to
(D) and FIG. 14 (a), (b) or FIG. 15 (a)
-(D), FIGS. 16 (a)-(d) and 17 (a)-
(C), the gate electrode 30 is formed on the semiconductor substrate 300 on which a plurality of pairs of impurity diffusion layers 301 to be a source region or a drain region are selectively provided on the surface.
8, and a first interlayer insulating film 309 provided with a first layer contact plug 310 connected to the impurity diffusion layer 301 is formed on the semiconductor substrate 300 and the gate electrode 308. Shall be.

First, as shown in FIG. 18A, a conductive film 401 and a positive first resist film 402 are sequentially formed over the entire surface of a first interlayer insulating film 309. After that, the first resist film 402 is irradiated with first exposure light 451 through a first photomask 450. As a result, exposure is performed on other portions of the first resist film 402 except the upper side of the wiring formation region and the upper side of the dummy wiring formation region.

Next, by developing the first resist film 402, as shown in FIG. 18B, a first resist pattern 402A covering the wiring formation region and the dummy wiring formation region is formed. 1 resist pattern 40
Dry etching is performed on the conductive film 401 using the mask 2A as a mask, so that the temporary wiring 403 for forming wiring and the dummy wiring 404 are selectively formed. At this time, although not shown, the wiring forming temporary wiring 403 is
0, while the semiconductor substrate 30 is densely arranged.
0 is sparsely arranged in other areas. Also, the dummy wiring 4
04 is formed in a region (the above-mentioned other region) where the wiring forming temporary wiring 403 is sparsely arranged on the semiconductor substrate 300. The temporary wiring 403 for wiring formation is formed so as to be connected to the first-layer contact plug 310. Further, the dummy wiring 404 may be formed on the first-layer contact plug 310.

Next, as shown in FIG. 18C, after the first resist pattern 402A is removed, FIG.
As shown in FIG. 5, the second resist film 405 (in the region where the wiring forming temporary wiring 403 and the dummy wiring 404 are not provided on the first interlayer insulating film 309 (including the first layer contact plug 310)). (Corresponding to the first resist film of claim 11).

Next, as shown in FIG. 19B, after the provisional wiring 403 for forming wiring and the dummy wiring 404 are removed,
As shown in FIG. 19C, a negative third resist film 406 is formed on the entire surface of the first interlayer insulating film 309. Then, the second resist is applied to the third resist film 406.
The second exposure light 453 is irradiated through the photomask 452 of FIG. Thus, exposure is performed on a region of the third resist film 406 where the dummy wiring 404 is provided.

Next, by developing the third resist film 406, as shown in FIG. 20A, the second resist pattern 406A is formed in the concave portion where the dummy wiring 404 is removed. 2) (corresponding to the second resist film). In other words, the third resist film 406 is left only in the concave portion where the dummy wiring 404 has been removed.

Next, as shown in FIG. 20B, a wiring 407 is formed in the recess where the wiring forming temporary wiring 403 has been removed, and then the second resist is formed as shown in FIG. The film 405 and the second resist pattern 406A (that is, the third resist film 406) are removed.

Next, as shown in FIG. 21B, after forming a second interlayer insulating film 408 over the entire surface of the first interlayer insulating film 309, the wiring 407 or the first layer contact plug is formed. A second layer contact plug 409 for selectively connecting 310 to an upper layer wiring (not shown) is formed.
At this time, the second-layer contact plug 409 may be formed so as to overlap a region where the dummy wiring 404 is provided.

As described above, according to the fourth embodiment, the provisional wiring 403 for forming the wiring is formed on the semiconductor substrate 300.
And the dummy wiring 404 are simultaneously formed, a second resist film 405 is formed in a region where the wiring forming temporary wiring 403 and the dummy wiring 404 are not provided, and then the wiring forming temporary wiring 403 and the dummy wiring 404 are formed. Is removed.
Then, the second portion is formed in the concave portion where the dummy wiring 404 is removed.
After the formation of the resist pattern 406A, the wiring 407 is formed in the concave portion where the wiring forming temporary wiring 403 is removed. For this reason, the area where the dummy wiring 404 is provided by removing the dummy wiring 404 is changed to, for example, the first layer while improving the formation accuracy of the wiring forming temporary wiring 403, that is, the formation accuracy of the wiring 407, by using the dummy wiring 404. It can be used as a formation region of a second-layer contact plug 409 for connecting the contact plug 310 and the upper layer wiring. Therefore, it is possible to prevent an increase in the circuit area due to the use of the dummy wiring 404. In other words, the circuit area can be reduced to the same extent as when the dummy wiring 404 is not used. Can be realized.

In the fourth embodiment, the area where the dummy wiring 404 is provided is used as the area where the second-layer contact plug 409 is formed.
The region where the dummy wiring 404 is provided may be used as a region for forming other components such as a capacitor, a diode, or a resistor.

In the fourth embodiment, it is not always necessary to remove the dummy wiring which does not affect the circuit area.

(Modification of Fourth Embodiment) Hereinafter, a method of manufacturing a semiconductor device according to a modification of the fourth embodiment of the present invention will be described with reference to the drawings.

FIGS. 22 (a) to 22 (c) and FIGS.
(C), FIGS. 24 (a) to (c) and FIG. 25 (a),
(B) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the modification of 4th Embodiment.

Note that in a modification of the fourth embodiment,
For example, a method of manufacturing the semiconductor device according to the third embodiment or its modification (FIGS. 12A to 12D, FIG.
(A)-(d) and FIG. 14 (a), (b), or FIG.
5 (a) to (d), FIGS. 16 (a) to (d) and FIG.
According to (a) to (c)) and the like, a gate electrode 308 is formed on a semiconductor substrate 300 on which a plurality of pairs of impurity diffusion layers 301 to be a source region or a drain region are selectively provided on a surface portion. And the semiconductor substrate 300
And the gate electrode 308, the impurity diffusion layer 301
It is assumed that a first interlayer insulating film 309 provided with a first-layer contact plug 310 connected to the first layer is formed.

First, as shown in FIG. 22A, a conductive film 401 and a negative type first resist film 402 are sequentially formed over the first interlayer insulating film 309 over the entire surface. After that, the first resist film 402 is irradiated with first exposure light 461 through a first photomask 460. Thus, exposure is performed on the first resist film 402 above the dummy wiring formation region.

Next, as shown in FIG. 22B, the first resist film 402 is irradiated with the second exposure light 463 via the second photomask 462. Thus, exposure is performed on the first resist film 402 above the wiring formation region.

Next, by developing the first resist film 402, as shown in FIG. 22C, a first resist pattern 402A covering the wiring formation region and the dummy wiring formation region is formed. 1 resist pattern 40
Dry etching is performed on the conductive film 401 using the mask 2A as a mask, so that the temporary wiring 403 for forming wiring and the dummy wiring 404 are selectively formed. At this time, although not shown, the wiring forming temporary wiring 403 is
0, while the semiconductor substrate 30 is densely arranged.
0 is sparsely arranged in other areas. Also, the dummy wiring 4
04 is formed in a region (the other region described above) on the semiconductor substrate 300 where the wiring forming temporary wiring 403 is sparsely arranged. Further, the temporary wiring 403 for wiring formation is formed so as to be connected to the first-layer contact plug 310. Further, the dummy wiring 404 may be formed on the first-layer contact plug 310.

Next, as shown in FIG. 23A, after the first resist pattern 402A is removed, FIG.
As shown in FIG. 5, the second resist film 405 (in the region where the wiring forming temporary wiring 403 and the dummy wiring 404 are not provided on the first interlayer insulating film 309 (including the first layer contact plug 310)). (Corresponding to the first resist film of claim 11).

Next, as shown in FIG. 23 (c), after removing the wiring forming temporary wiring 403 and the dummy wiring 404,
As shown in FIG. 24A, a negative third resist film 406 is formed on the entire surface of the first interlayer insulating film 309. Thereafter, a third exposure is performed through a first photomask 460 used for exposing the upper side of the dummy gate electrode formation region in the first resist film 402 in the step shown in FIG. Light 364 is applied to the third resist film 406. Thus, exposure is performed on a region of the third resist film 406 where the dummy wiring 404 is provided.

Next, by developing the third resist film 406, as shown in FIG. 24B, the second resist pattern 406A is formed in the concave portion where the dummy wiring 404 is removed. 2) (corresponding to the second resist film). In other words, the third resist film 406 is left only in the concave portion where the dummy wiring 404 has been removed.

Next, as shown in FIG. 24C, the wiring 407 is formed in the concave portion where the wiring forming temporary wiring 403 is removed, and then the second resist is formed as shown in FIG. The film 405 and the second resist pattern 406A (that is, the third resist film 406) are removed.

Next, as shown in FIG. 25B, after forming a second interlayer insulating film 408 over the entire surface of the first interlayer insulating film 309, the wiring 407 or the first layer contact plug is formed. A second layer contact plug 409 for selectively connecting 310 to an upper layer wiring (not shown) is formed.
At this time, the second-layer contact plug 409 may be formed so as to overlap a region where the dummy wiring 404 is provided.

According to the modified example of the fourth embodiment described above, the following effect can be obtained in addition to the same effect as the fourth embodiment. That is, since the first photomask 460 used to form the dummy wiring 404 is used when forming the second resist pattern 406A in the concave portion from which the dummy wiring 404 has been removed, the second resist pattern 406A can be formed accurately, whereby the reliability of the semiconductor device can be improved.

In the modification of the fourth embodiment, the area where the dummy wiring 404 is provided is used as the formation area of the second-layer contact plug 409, but the dummy wiring 404 is provided instead. The region that has been set may be used as a region for forming other components such as a capacitor, a diode, or a resistor.

In the modification of the fourth embodiment,
After exposing (see FIG. 22A) the first photomask 460 to the upper side of the dummy wiring formation region in the first resist film 402, the upper surface of the wiring formation region in the first resist film 402 is exposed. Although the upper side was exposed using the second photomask 462 (see FIG. 22B), instead of this, the second resist was applied to the upper side of the wiring formation region in the first resist film 402. Photo mask 4
After the exposure using the first resist film 40,
Exposure may be performed using the first photomask 460 on the upper side of the dummy wiring formation region in FIG.

In the modification of the fourth embodiment,
It is not always necessary to remove dummy wirings that do not affect the circuit area.

[0137]

According to the present invention, while the accuracy of forming a gate electrode or a wiring is improved by using a dummy gate electrode or a dummy wiring, the area where each of the dummy gate electrode or the dummy wiring is provided is removed, for example. It can be used as a plug formation region or the like for performing selective wiring connection with an upper wiring. Therefore, an increase in circuit area due to the use of the dummy gate electrode or the dummy wiring can be prevented. In other words, the circuit area can be reduced to the same extent as when the dummy gate electrode or the dummy wiring is not used. A semiconductor device with excellent performance can be realized.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views showing each step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIGS. 2A to 2D are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIGS. 3A to 3C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a modification of the first embodiment of the present invention.

FIGS. 4A to 4C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a modification of the first embodiment of the present invention.

FIGS. 5A to 5C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a modification of the first embodiment of the present invention.

FIGS. 6A to 6C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIGS. 7A to 7C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIGS. 8A and 8B are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIGS. 9A to 9C are cross-sectional views illustrating each step of a method for manufacturing a semiconductor device according to a modification of the second embodiment of the present invention.

FIGS. 10A to 10C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a modification of the second embodiment of the present invention.

FIGS. 11A to 11C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a modification of the second embodiment of the present invention. FIGS.

FIGS. 12A to 12D are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIGS. 13A to 13D are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIGS. 14A and 14B are cross-sectional views showing each step of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIGS. 15A to 15D are cross-sectional views illustrating each step of a method for manufacturing a semiconductor device according to a modification of the third embodiment of the present invention.

FIGS. 16A to 16D are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a modification of the third embodiment of the present invention.

FIGS. 17A to 17C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a modification of the third embodiment of the present invention. FIGS.

FIGS. 18A to 18C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIGS. 19A to 19C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIGS. 20A and 20B are cross-sectional views showing steps of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIGS. 21A and 21B are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIGS. 22A to 22C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a modification of the fourth embodiment of the present invention.

FIGS. 23A to 23C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to a modification of the fourth embodiment of the present invention.

FIGS. 24A to 24C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a modification of the fourth embodiment of the present invention.

FIGS. 25A and 25B are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to a modification of the fourth embodiment of the present invention.

FIGS. 26A to 26D are cross-sectional views showing steps of a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 Reference Signs List 100 semiconductor substrate 101 impurity diffusion layer 102 conductive film 103 first resist film 103A first resist pattern 104 gate electrode 105 dummy gate electrode 106 second resist film 106A second resist pattern 107 first interlayer insulating film 108 first Single-layer contact plug 150 First photomask 151 First exposure light 152 Second photomask 153 Second exposure light 160 First photomask 161 First exposure light 162 Second photomask 163 Second Exposure light 164 Third exposure light 201 Conductive film 202 First resist film 202A First resist pattern 203 Wiring 204 Dummy wiring 205 Second resist film 205A Second resist pattern 206 Second interlayer insulating film 207 Second Layer contact plug 250 first Photomask 251 First exposure light 252 Second photomask 253 Second exposure light 260 First photomask 261 First exposure light 262 Second photomask 263 Second exposure light 264 Third exposure light Reference Signs List 300 semiconductor substrate 301 impurity diffusion layer 302 conductive film 303 first resist film 303A first resist pattern 304 provisional electrode for gate formation 305 dummy gate electrode 306 second resist film 307 third resist film 307A second resist pattern 308 Gate electrode 309 First interlayer insulating film 310 First layer contact plug 350 First photomask 351 First exposure light 352 Second photomask 353 Second exposure light 360 First photomask 361 First Exposure light 362 Second photomask 363 Second exposure light 64 Third exposure light 401 Conductive film 402 First resist film 402A First resist pattern 403 Wiring forming temporary wiring 404 Dummy wiring 405 Second resist film 406 Third resist film 406A Second resist pattern 407 Wiring 408 Second interlayer insulating film 409 Second layer contact plug 450 First photomask 451 First exposure light 452 Second photomask 453 Second exposure light 460 First photomask 461 First exposure light 462 Second photomask 463 Second exposure light 464 Third exposure light

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/088 29/78 F term (Reference) 4M104 CC01 CC05 DD03 DD62 DD65 DD91 FF26 FF31 GG09 GG10 GG14 HH14 5F033 HH00 JJ00 KK01 QQ01 QQ08 QQ11 QQ58 UU04 VV06 XX03 5F048 AA01 AA07 AC01 BA01 BB05 BC01 BF03 BF11 BF15 BF16 5F140 AA39 BG01 BG36 BG38 BJ27 CE13 CE14

Claims (14)

[Claims] A step of simultaneously forming a gate electrode and a dummy gate electrode on a semiconductor substrate; a step of removing the dummy gate electrode; and an interlayer insulating film on the semiconductor substrate from which the dummy gate electrode has been removed. And a step of forming a plug in the interlayer insulating film so as to overlap at least a part of a region where the dummy gate electrode is provided. 2. The method according to claim 1, wherein a photomask used for forming the dummy gate electrode is used when removing the dummy gate electrode. A step of forming a pair of impurity diffusion layers serving as a source region or a drain region on a surface portion of the semiconductor substrate; and forming a gate electrode between the pair of impurity diffusion layers on the semiconductor substrate. A method of forming a dummy gate electrode on at least one of the pair of impurity diffusion layers; and a step of removing the dummy gate electrode. 4. The method according to claim 3, wherein when removing the dummy gate electrode, a photomask used for forming the dummy gate electrode is used. 5. A step of forming an interlayer insulating film on the semiconductor substrate after the step of removing the dummy gate electrode, a step of forming a plug in the interlayer insulating film and a region in which the dummy gate electrode is provided. Forming the semiconductor device so as to overlap at least a part of the semiconductor device. 6. A step of simultaneously forming a wiring and a dummy wiring on a semiconductor substrate; a step of removing the dummy wiring; and a step of forming an interlayer insulating film on the semiconductor substrate from which the dummy wiring has been removed. And a step of forming a plug in the interlayer insulating film so as to overlap at least a part of a region where the dummy wiring is provided. 7. The method according to claim 6, wherein a photomask used for forming the dummy wiring is used when removing the dummy wiring. 8. A step of forming an interlayer insulating film provided with a plug on a semiconductor substrate; a step of forming a wiring on the interlayer insulating film and simultaneously forming a dummy wiring on the plug; Removing the dummy wirings. 9. The method according to claim 8, wherein a photomask used for forming the dummy wiring is used when removing the dummy wiring. 10. A step of forming another interlayer insulating film on the interlayer insulating film after the step of removing the dummy wiring; and forming another plug in the other interlayer insulating film; Forming a region so as to overlap at least a part of the provided region.
13. The method for manufacturing a semiconductor device according to item 5. 11. A step of simultaneously forming a gate electrode forming temporary electrode and a dummy gate electrode on a semiconductor substrate; and forming a gate electrode forming temporary electrode and a dummy gate electrode in a region on the semiconductor substrate where the gate electrode forming temporary electrode and dummy gate electrode are not provided. A step of forming a first resist film, a step of removing the temporary electrode for forming a gate electrode and a dummy gate electrode, and a step of forming a second resist film in a concave portion where the dummy gate electrode has been removed. Forming a gate electrode in a recess from which the temporary electrode for forming a gate electrode has been removed. 12. The method according to claim 11, wherein a photomask used to form the dummy gate electrode is used when forming the second resist film. 13. A step of simultaneously forming a wiring formation temporary wiring and a dummy wiring on a semiconductor substrate, and a first resist in a region on the semiconductor substrate where the wiring formation temporary wiring and the dummy wiring are not provided. A step of forming a film, a step of removing the wiring forming temporary wiring and the dummy wiring, a step of forming a second resist film in a concave portion where the dummy wiring is removed, and a step of forming the wiring forming temporary wiring. Forming a wiring in the removed concave portion. A method for manufacturing a semiconductor device, comprising: 14. The method according to claim 13, wherein a photomask used for forming the dummy wiring is used when forming the second resist film.